JP2013110908A - Charge pump circuit and power supply unit using the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To achieve easy and appropriate FET on-off control.SOLUTION: A charge pump circuit 1 includes: a FET 103 (104) used as a charging/discharging switch of a capacitor C1; a detection section 109 (110) that generates a detection signal S11 (S12) on the basis of a current passing through the FET 103 (104) or a voltage across the FET 103 (104); and a drive section 107 (108) that generates a drive signal G11 (G12) of the FET 103 (104) according to the detection signal S11 (S12).

Description

  The present invention relates to a charge pump circuit and a power supply device using the same.

  The charge pump circuit is capable of positive voltage boosting and negative voltage boosting (inversion), and is mainly used in situations where current supply capability is not required. In a general charge pump circuit, a diode is used as a charge / discharge switch for a flying capacitor. However, since the diode has a large forward drop voltage, the output voltage range is narrowed. For this reason, when it is necessary to widen the output voltage range, a synchronous rectification method using an FET [field effect transistor] having a smaller voltage drop has been adopted instead of a diode having a large forward voltage drop.

  As an example of the prior art related to the present invention, Patent Document 1 can be cited.

International Publication No. 2008/065941

  In a synchronous rectification type charge pump circuit, if FETs that should not be turned on at the same time among a plurality of FETs are turned on at the same time, there is a risk of malfunction or a reduction in efficiency. Therefore, it is important to appropriately control the on / off of the FET. However, it is difficult to optimize the on / off control of the FET in consideration of circuit constants (particularly the capacitance value of the flying capacitor), element layout, and the like.

  In view of the above-described problems found by the inventors of the present application, the present invention provides a charge pump circuit capable of easily and appropriately performing on / off control of an FET, and a power supply device using the same The purpose is to provide.

  To achieve the above object, a charge pump circuit according to the present invention includes an FET used as a charge / discharge switch for a capacitor, and a detection unit that generates a detection signal according to a current flowing through the FET or a voltage across the FET. And a drive unit that generates a drive signal for the FET in response to the detection signal (first configuration).

  The charge pump circuit having the first configuration includes a first FET connected between the first terminal of the capacitor and a first voltage application terminal, a first terminal of the capacitor and a ground voltage application terminal. A second FET connected between the capacitor, a third FET connected between the second terminal of the capacitor and the application terminal of the second voltage, and between the second terminal of the capacitor and the application terminal of the output voltage. A fourth FET connected to the first FET, an oscillator that generates a clock signal, a first drive unit that generates a drive signal for the first FET and the second FET according to the clock signal, and a current flowing through the third FET or the first FET A first detection unit that generates a first detection signal according to a voltage across the 3FET; a second detection unit that generates a second detection signal according to the current flowing through the fourth FET or the voltage across the fourth FET; A second drive unit that generates a drive signal for the third FET in response to one detection signal; and a third drive unit that generates a drive signal for the fourth FET in response to the second detection signal (second (Configuration).

  In the charge pump circuit having the second configuration, the second driving unit generates a driving signal for the third FET in accordance with both the first detection signal and the clock signal, and the third driving unit. May be configured to generate a drive signal for the fourth FET in accordance with both the second detection signal and the clock signal (third configuration).

  The charge pump circuit having the third configuration includes a first off detection unit that generates a first off detection signal in response to the drive signal of the third FET, and a second off in response to the drive signal of the fourth FET. A configuration (fourth configuration) including a second off detection unit that generates a detection signal, and a delay unit that delays the clock signal according to the first off detection signal and the second off detection signal. Good.

  In the charge pump circuit having any one of the second to fourth configurations, the first voltage and the second voltage may be positive (fifth configuration).

  In the charge pump circuit having the fifth configuration, the first FET, the third FET, and the fourth FET are all P-channel type, and the second FET is N-channel type (sixth Configuration).

  In the charge pump circuit having any one of the second to fourth configurations, the first voltage may be a positive voltage and the second voltage may be a negative voltage (seventh configuration).

  In the charge pump circuit having the seventh configuration, the first FET is a P-channel type, and the second FET, the third FET, and the fourth FET are all N-channel types (eighth). Configuration).

  In the charge pump circuit having the eighth configuration, the first FET, the second FET, the first driving unit, and the oscillator are integrated in a first semiconductor device in which a ground voltage is applied to a substrate. The third FET, the fourth FET, the first detection unit, the second detection unit, the second drive unit, and the third drive unit have a negative voltage applied to the substrate. A configuration integrated with the second semiconductor device (a ninth configuration) is preferable.

  Further, the power supply device according to the present invention has a configuration (tenth configuration) including a charge pump circuit having any one of the first to ninth configurations.

  According to the present invention, it is possible to provide a charge pump circuit capable of easily and appropriately performing on / off control of an FET, and a power supply device using the same.

The figure which shows 1st Embodiment (positive output type) of a charge pump circuit Timing chart showing an operation example of the charge pump circuit 1X The figure which shows 2nd Embodiment (positive output type) of a charge pump circuit Timing chart showing one example of operation of charge pump circuit 1Y The figure which shows 3rd Embodiment (positive output type) of a charge pump circuit Timing chart showing an operation example of the charge pump circuit 1Z The figure which shows 4th Embodiment (negative output type) of a charge pump circuit Timing chart showing one operation example of charge pump circuit 2X The figure which shows 5th Embodiment (negative output type) of a charge pump circuit. Timing chart showing an operation example of the charge pump circuit 2Y The figure which shows 6th Embodiment (negative output type) of a charge pump circuit Timing chart showing an operation example of the charge pump circuit 2Z

<First Embodiment>
FIG. 1 is a diagram showing a first embodiment (positive output type) of a charge pump circuit. The charge pump circuit 1X of the first embodiment includes a semiconductor device 100, a flying capacitor C1, and an output capacitor C2. The power supply device using the charge pump circuit 1X can be used as a power source for various applications such as LCD-TV, PDP-TV, DVD recorder, BD recorder, and the like.

  The semiconductor device 100 includes a PMOSFET [P channel type metal oxide semiconductor field effect transitor] 101, an NMOSFET [N channel type MOSFET] 102, PMOSFETs 103 and 104, an oscillator 105, inverters 106 to 108, and comparators 109 and 110. And are integrated. A ground voltage GND (= 0 V) is applied to the substrate of the semiconductor device 100.

  The source of the FET 101 is connected to the application terminal of the positive voltage V1 (> 0V). Each of the drains of the FETs 101 and 102 is connected to the first terminal (application terminal of the switch voltage SW11) of the flying capacitor C1. The source of the FET 102 is connected to the application terminal of the ground voltage GND. Each of the gates of the FETs 101 and 102 is connected to the output terminal of the inverter 106 (application terminal of the drive signal G10). The input terminal of the inverter 106 is connected to the output terminal (the application terminal of the clock signal CLK) of the oscillator 105.

  The drain of the FET 103 is connected to the application terminal of the positive voltage V2 (> 0V). The source of the FET 103 and the drain of the FET 104 are both connected to the second end (the application end of the switch voltage SW12) of the flying capacitor C1. The source of the FET 104 is connected to the application terminal for the output voltage OUT. The FETs 103 and 104 are accompanied by body diodes 103D and 104D each having a drain as an anode and each source as a cathode. An output capacitor C2 is connected between the application terminal of the output voltage OUT and the application terminal of the ground voltage GND.

  The non-inverting input terminal (+) of the comparator 109 is connected to the drain of the FET 103. On the other hand, the inverting input terminal (−) of the comparator 109 is connected to the source of the FET 103. The output terminal of the comparator 109 (the application terminal of the detection signal S11) is connected to the input terminal of the inverter 107. The output terminal of the inverter 107 (the application terminal of the drive signal G11) is connected to the gate of the FET 103.

  The non-inverting input terminal (+) of the comparator 110 is connected to the drain of the FET 104. On the other hand, the inverting input terminal (−) of the comparator 110 is connected to the source of the FET 104. The output terminal of the comparator 110 (the application terminal of the detection signal S12) is connected to the input terminal of the inverter 108. The output terminal of the inverter 108 (application terminal of the drive signal G12) is connected to the gate of the FET 104.

  The FETs 101 to 104 are all used as charging / discharging switches for the flying capacitor C1. The FET 101 corresponds to a first FET connected between the first end of the flying capacitor C1 and the application end of the positive voltage V1. The FET 102 corresponds to a second FET connected between the first end of the flying capacitor C1 and the application end of the ground voltage GND. The FET 103 corresponds to a third FET connected between the second end of the flying capacitor C1 and the application end of the positive voltage V2. The FET 104 corresponds to a fourth FET connected between the second end of the flying capacitor C1 and the application end of the output voltage OUT.

  The oscillator 105 generates a clock signal CLK having a constant frequency.

  The inverter 106 corresponds to a first drive unit that generates a drive signal G10 for the FETs 101 and 102 in response to the clock signal CLK. The drive signal G10 is a logic inversion signal of the clock signal CLK.

  The inverter 107 corresponds to a second drive unit that generates the drive signal G11 of the FET 103 according to the detection signal S11 input from the comparator 109. The drive signal G11 is a logical inversion signal of the detection signal S11.

  The inverter 108 corresponds to a third drive unit that generates the drive signal G12 of the FET 104 according to the detection signal S12 input from the comparator 110. The drive signal G12 is a logic inversion signal of the detection signal S12.

  The comparator 109 corresponds to a first detection unit that generates the detection signal S11 according to the voltage V11 across the FET 103 (= V2−SW12). The detection signal S11 is at a high level when the voltage V11 across the FET 103 is above the threshold voltage, and is at a low level when the voltage is below the threshold voltage. That is, the detection signal S11 is at a high level when a current flows from the application terminal of the positive voltage V2 toward the application terminal of the switch voltage SW12 (or when the current can flow in the same direction). When the current flows from the application end of the switch voltage SW12 toward the application end of the positive voltage V2 (or when the current can flow in the same direction), the low level is reached. Note that the method for detecting the direction of the current flowing through the FET 103 or the body diode 103D is not limited to the configuration for monitoring the voltage V11 across the FET 103, but other configurations (for example, monitoring the voltage across the sense resistor). Configuration) may be adopted.

  The comparator 110 corresponds to a second detection unit that generates the detection signal S12 according to the voltage V12 across the FET 104 (= SW12−OUT). The detection signal S12 is at a high level when the voltage V12 across the FET 104 is above the threshold voltage, and is at a low level when it is below the threshold voltage. That is, the detection signal S12 becomes high level when a current flows from the application terminal of the switch voltage SW12 toward the application terminal of the output voltage OUT (or when the current can flow in the same direction), and conversely When the current flows from the application terminal of the output voltage OUT toward the application terminal of the switch voltage SW12 (or when the current can flow in the same direction), the output voltage OUT becomes the low level. Note that the method for detecting the direction of the current flowing through the FET 104 or the body diode 104D is not limited to the configuration for monitoring the voltage V12 across the FET 104, but other configurations (for example, monitoring the voltage across the sense resistor). Configuration) may be adopted.

  First, the basic operation of the charge pump circuit 1X will be schematically described. In the first phase (charging phase) in which the FETs 101 and 104 are turned off and the FETs 102 and 103 are turned on, the application terminal for the ground voltage GND is applied from the application terminal for the positive voltage V2 through the FET 103, the flying capacitor C1, and the FET 102. The flying capacitor C1 is charged by the current flowing through the path leading to. At this time, the switch voltage SW11 is substantially the ground voltage GND (more precisely, the voltage obtained by adding the drop voltage of the FET 102 to the ground voltage GND), and the switch voltage SW12 is substantially the positive voltage V2 (more precisely, the positive voltage). Voltage obtained by subtracting the voltage drop of the FET 103 from the voltage V2. Therefore, the charge corresponding to the differential voltage (almost positive voltage V2) between the switch voltage SW11 and the switch voltage SW12 is stored in the flying capacitor C1.

  Thereafter, in the second phase (discharge phase / charge transfer phase) in which the FETs 101 and 104 are turned on and the FETs 102 and 103 are turned off, from the application terminal of the positive voltage V1, via the FET 101, the flying capacitor C1, and the FET 104, The path leading to the application terminal of the output voltage OUT is conducted, and the flying capacitor C1 is discharged (charge transfer to the output capacitor C2). At this time, the switch voltage SW11 is substantially the positive voltage V1 (more precisely, the voltage obtained by adding the drop voltage of the FET 101 to the positive voltage V1), and the switch voltage SW12 is the voltage across the flying capacitor C1 added to the switch voltage SW11. The added voltage (approximately V1 + V2) is obtained.

  Therefore, in the charge pump circuit 1X, the FETs 101 to 104 are turned on / off to repeatedly charge and discharge the flying capacitor C1, thereby generating a positive output voltage OUT (= V1 + V2) obtained by adding the positive voltages V1 and V2. Can do.

  Next, on / off control of the FETs 101 to 104 will be described in detail. FIG. 2 is a timing chart showing an operation example of the charge pump circuit 1X. In order from the top, the clock signal CLK, the drive signal G10, the switch voltages SW11 and SW12, the detection signals S11 and S12, and the drive signals G11 and G12. Is depicted.

  In the example of FIG. 2, the FETs 101 and 104 are on and the FETs 102 and 103 are off until time t11. This state corresponds to the second phase described above, and a current flows from the application end of the switch voltage SW12 to the application end of the output voltage OUT through a path via the FET 104. At this time, the switch voltage SW12 is a voltage obtained by adding the drop voltage of the FET 104 to the output voltage OUT.

  At time t11, when the clock signal CLK falls from the high level to the low level, the drive signal G10 rises from the low level to the high level, so that the FET 101 is turned off and the FET 102 is turned on. As a result, the first terminal of the flying capacitor C1 is conducted to the application terminal of the ground voltage GND through the FET 102, and the switch voltage SW11 starts to decrease. Also, the switch voltage SW12 starts to decrease in the same behavior as the switch voltage SW11 in accordance with the charge conservation law of the flying capacitor C1.

  As the switch voltage SW12 decreases, when the voltage V12 across the FET 104 (= SW12−OUT) falls below the threshold voltage of the comparator 110 at time t12, the detection signal S12 switches from the high level to the low level. That is, when the current starts to flow backward from the application terminal of the output voltage OUT toward the application terminal of the switch voltage SW12 through the path via the FET 104 (or when the current can be reversed), the detection signal S12 is high. Switch from level to low level. As a result, the drive signal G12 of the FET 104 is switched from the low level to the high level, and the FET 104 is turned off. Therefore, the backflow current flowing through the FET 104 can be interrupted without delay.

  When the switch voltage SW12 further decreases and the voltage V11 across the FET 103 (= V2−SW12) exceeds the threshold voltage of the comparator 109 at time t13, the detection signal S11 switches from the low level to the high level. That is, when the current starts to flow from the application terminal of the positive voltage V2 toward the application terminal of the switch voltage SW12 through the path via the body diode 103D (or when the current can flow in the same direction), the detection signal S11 switches from the low level to the high level. As a result, the drive signal G11 of the FET 103 is switched from the high level to the low level, and the FET 103 is turned on. This state corresponds to the first phase described above, and current starts to flow in a path from the application terminal of the positive voltage V2 to the application terminal of the ground voltage GND through the FET 103, the flying capacitor C1, and the FET 102. At this time, the switch voltage SW12 is a voltage obtained by subtracting the voltage drop of the FET 103 from the positive voltage V2.

  Note that since the current flows through the body diode 103D having a larger forward voltage than the FET 103 until the FET 103 is sufficiently turned on, an undershoot occurs in the switch voltage SW12 (and SW11). However, since this state is a short period, the conversion efficiency of the charge pump circuit 1X and the output voltage range are not greatly affected.

  Thereafter, when the clock signal CLK rises from the low level to the high level at time t14, the drive signal G10 falls from the high level to the low level, so that the FET 101 is turned on and the FET 102 is turned off. As a result, the first end of the flying capacitor C1 is conducted to the application terminal of the positive voltage V1 via the FET 101, and thus the switch voltage SW11 starts to rise. Also, the switch voltage SW12 starts to rise with the same behavior as the switch voltage SW11 in accordance with the charge conservation law of the flying capacitor C1.

  As the switch voltage SW12 increases, when the voltage V11 across the FET 103 (= V2−SW12) falls below the threshold voltage of the comparator 109 at time t15, the detection signal S11 switches from the high level to the low level. In other words, when the current starts to flow backward from the application terminal of the switch voltage SW12 toward the application terminal of the positive voltage V2 through the path via the FET 103 (or when the current can flow backward), the detection signal S11 is high. Switch from level to low level. As a result, the drive signal G11 of the FET 103 is switched from the low level to the high level, and the FET 103 is turned off. Therefore, the reverse current flowing through the FET 103 can be interrupted without delay.

  When the switch voltage SW12 further increases and the voltage V12 across the FET 104 (= SW12−OUT) exceeds the threshold voltage of the comparator 110 at time t16, the detection signal S12 is switched from the low level to the high level. That is, when the current starts to flow from the application terminal of the switch voltage SW12 toward the application terminal of the output voltage OUT through the path via the body diode 104D (or when the current can flow in the same direction), the detection signal S12 switches from the low level to the high level. As a result, the drive signal G12 of the FET 104 is switched from the high level to the low level, and the FET 104 is turned on. This state corresponds to the previous second phase, and current starts to flow from the application end of the switch voltage SW12 to the application end of the output voltage OUT through a path via the FET 104. At this time, the switch voltage SW12 is a voltage obtained by adding the drop voltage of the FET 104 to the output voltage OUT.

  Note that since the current flows through the body diode 104D having a larger forward voltage than the FET 104 until the FET 104 is sufficiently turned on, an overshoot occurs in the switch voltage SW12 (and SW11). However, since this state is a short period, the conversion efficiency of the charge pump circuit 1X and the output voltage range are not greatly affected.

  As described above, in the charge pump circuit 1X of the first embodiment, the FET 103 and 104 are turned on when the current flows in the intended direction, and the current flows in the direction opposite to the intended direction. The person who becomes becomes off. Accordingly, since the FETs 103 and 104 are not turned on during the switching of the FETs 101 and 102, it is possible to reliably prevent the FET 101 and the FET 103 from being simultaneously turned on and the FET 102 and the FET 104 from being simultaneously turned on. In the charge pump circuit 1X of the first embodiment, since one of the FETs 103 and 104 is always turned on and then the other is turned on, the simultaneous turning-on of the FET 103 and the FET 104 can be reliably prevented.

  As described above, in the charge pump circuit 1X of the first embodiment, the delay generation method in which a certain delay is given in advance to the on / off timing of each FET, or the gate voltage of one FET is switched to the off level. Compared with the gate voltage monitoring method that confirms that the gate voltage of the other FET is switched to the on level, the FET can be turned on and off easily and appropriately without depending on the parasitic capacitance of the wiring and the delay variation of the drive circuit. Control can be performed.

  In particular, in order to eliminate malfunction and efficiency reduction of the positive output type charge pump circuit in which the behavior of the switch voltage varies greatly according to the capacitance value of the flying capacitor, the first implementation is not performed by the delay generation method or the gate voltage monitoring method. It is desirable to adopt the configuration of the form.

Second Embodiment
FIG. 3 is a diagram showing a second embodiment (positive output type) of the charge pump circuit. The charge pump circuit 1Y of the second embodiment has basically the same configuration as that of the first embodiment, and is characterized in that an OR gate 111 and a NAND gate 112 are provided in place of the inverters 107 and 108. Therefore, the same components as those in the first embodiment are denoted by the same reference numerals as those in FIG. 1, and redundant description is omitted. In the following, only the characteristic portions of the second embodiment will be described. To.

  The first inverting input terminal of the OR gate 111 is connected to the output terminal of the comparator 109 (application terminal of the detection signal S11). The second input terminal of the OR gate 111 is connected to the output terminal (the application terminal for the clock signal CLK) of the oscillator 105. The output terminal of the OR gate 111 (the application terminal of the drive signal G11) is connected to the gate of the FET 103. The OR gate 111 corresponds to a second drive unit that generates the drive signal G11 of the FET 103 according to both the detection signal S11 input from the comparator 109 and the clock signal CLK input from the oscillator 105. The drive signal G11 is low level when the detection signal S11 is high level and the clock signal CLK is low level, and is high level in other cases.

  A first input terminal of the NAND gate 112 is connected to an output terminal (application terminal of the detection signal S12) of the comparator 110. The second input terminal of the NAND gate 112 is connected to the output terminal (the application terminal of the clock signal CLK) of the oscillator 105. The output terminal of the NAND gate 112 (application terminal of the drive signal G12) is connected to the gate of the FET 104. The NAND gate 112 corresponds to a third drive unit that generates the drive signal G12 of the FET 104 according to both the detection signal S12 input from the comparator 110 and the clock signal CLK input from the oscillator 105. The drive signal G12 is at a low level when both the detection signal S12 and the clock signal CLK are at a high level, and is at a high level in other cases.

  FIG. 4 is a timing chart showing an operation example of the charge pump circuit 1Y. In order from the top, the clock signal CLK, the drive signal G10, the switch voltages SW11 and SW12, the detection signals S11 and S12, and the drive signals G11 and G12. Is depicted.

  Regarding the operation of the charge pump circuit 1Y, the point to be particularly noted is the rising timing of the drive signals G11 and G12, that is, the off timing of the FETs 103 and 104. As shown in FIG. 4, in the charge pump circuit 1Y, the drive signal G12 rises with the falling edge (time t11, etc.) of the clock signal CLK as a trigger, and the drive signal with the rising edge (time t14, etc.) of the clock signal CLK as a trigger. G11 stands up.

  As described above, the charge pump circuit 1Y according to the second embodiment employs a configuration in which the FETs 103 and 104 are turned off before the reverse current starts to flow through the FETs 103 and 104. Accordingly, since no backflow current flows through the FETs 103 and 104, it is possible to more reliably prevent malfunction and efficiency reduction of the charge pump circuit 1Y.

  In the charge pump circuit 1Y, the FET 103 is turned off while the voltage V11 across the FET 103 is higher than the threshold voltage of the comparator 109. Therefore, a current flows through the body diode 103D and the switch voltage SW12 (and SW11) Undershoot may occur. Similarly, in the charge pump circuit 1Y, the FET 104 is turned off while the voltage V12 across the FET 104 exceeds the threshold voltage of the comparator 110, so that a current flows through the body diode 104D and the switch voltage SW12 (and SW11). Overshoot may occur. However, since all such states are short-lived, the conversion efficiency of the charge pump circuit 1Y and the output voltage range are not greatly affected.

<Third Embodiment>
FIG. 5 is a diagram showing a third embodiment (positive output type) of the charge pump circuit. The charge pump circuit 1Z of the third embodiment has basically the same configuration as that of the second embodiment, and is characterized in that off detectors 113 and 114 and a delay unit 115 are added. Therefore, the same components as those in the second embodiment are denoted by the same reference numerals as those in FIG. 3, thereby omitting redundant descriptions. In the following, only the characteristic portions of the third embodiment will be described. To.

  The off detection unit 113 generates an off detection signal D11 according to the drive signal G11 of the FET 103. The off detection signal D11 is at a high level if the drive signal G11 is above the threshold voltage for off detection, and is at a low level if it is below.

  The off detection unit 114 generates an off detection signal D12 according to the drive signal G12 of the FET 104. The off detection signal D12 is at a high level if the drive signal G12 is above the threshold voltage for off detection, and is at a low level if it is below.

  The delay unit 115 delays the clock signal CLK according to the off detection signals D11 and D12. Specifically, the delay unit 115 delays the rising edge of the clock signal CLK until the OFF detection signal D11 switches to a high level, and delays the falling edge of the clock signal CLK until the OFF detection signal D12 switches to a high level. Note that the clock signal CLK provided with the delay by the delay unit 115 is sent to the inverter 106.

  FIG. 6 is a timing chart showing an operation example of the charge pump circuit 1Z, in which the clock signal CLK and the drive signals G10 to G12 are depicted in order from the top. In the charge pump circuit 1Z according to the third embodiment, the FET 103 is first used when shifting from the first phase (PHASE 1) to the second phase (PHASE 2) without depending on the parasitic capacitance of the wiring and the delay variation of the driving circuit. Is turned off, then the FET 101 is turned on, the FET 102 is turned off, and finally the FET 104 is turned on. Conversely, the second phase (PHASE2) is shifted to the first phase (PHASE1). In this case, it is possible to realize a series of sequences in which the FET 104 is first turned off, the FET 101 is turned off, the FET 102 is turned on, and the FET 103 is finally turned on.

<Fourth embodiment>
FIG. 7 is a diagram showing a fourth embodiment (negative output type) of the charge pump circuit. The charge pump circuit 2X of the fourth embodiment includes a semiconductor device 200A, a semiconductor device 200B, a flying capacitor C1, and an output capacitor C2. The power supply device using the charge pump circuit 2X can be used as a power supply for various applications such as LCD-TV, PDP-TV, DVD recorder, BD recorder, and the like.

  In the semiconductor device 200A, a PMOSFET 201, an NMOSFET 202, an oscillator 205, and an inverter 206 are integrated. A ground voltage GND (= 0 V) is applied to the substrate of the semiconductor device 200A.

  In the semiconductor device 200B, NMOSFETs 203 and 204, drivers 207 and 208, and comparators 209 and 210 are integrated. A negative voltage NV (<0 V) is applied to the substrate of the semiconductor device 200B.

  The source of the FET 201 is connected to the application terminal of the positive voltage V1 (> 0V). Each of the drains of the FETs 201 and 202 is connected to the first terminal (application terminal of the switch voltage SW21) of the flying capacitor C1. The source of the FET 202 is connected to the application terminal of the ground voltage GND. Each of the gates of the FETs 201 and 202 is connected to the output terminal of the inverter 206 (application terminal of the drive signal G20). The input end of the inverter 206 is connected to the output end (the application end of the clock signal CLK) of the oscillator 205.

  The drain of the FET 203 is connected to the application terminal of the negative voltage V2 (<0V). The source of the FET 203 and the drain of the FET 204 are both connected to the second end (the application end of the switch voltage SW22) of the flying capacitor C1. The source of the FET 204 is connected to the application terminal for the output voltage OUT. The FETs 203 and 204 are accompanied by body diodes 203D and 204D each having a source as an anode and each drain as a cathode. An output capacitor C2 is connected between the application terminal of the output voltage OUT and the application terminal of the ground voltage GND.

  The non-inverting input terminal (+) of the comparator 209 is connected to the source of the FET 203. On the other hand, the inverting input terminal (−) of the comparator 209 is connected to the drain of the FET 103. An output terminal of the comparator 209 (application terminal of the detection signal S21) is connected to an input terminal of the driver 207. The output terminal of the inverter 207 (the application terminal of the drive signal G21) is connected to the gate of the FET 203.

  The non-inverting input terminal (+) of the comparator 210 is connected to the source of the FET 204. On the other hand, the inverting input terminal (−) of the comparator 210 is connected to the drain of the FET 204. The output end of the comparator 210 (the application end of the detection signal S22) is connected to the input end of the driver 208. The output end of the driver 208 (the application end of the drive signal G22) is connected to the gate of the FET 204.

  The FETs 201 to 204 are all used as charging / discharging switches for the flying capacitor C1. The FET 201 corresponds to the first FET connected between the first end of the flying capacitor C1 and the application end of the positive voltage V1. The FET 202 corresponds to a second FET connected between the first end of the flying capacitor C1 and the application end of the ground voltage GND. The FET 203 corresponds to a third FET connected between the second end of the flying capacitor C1 and the application end of the negative voltage V2. The FET 204 corresponds to a fourth FET connected between the second end of the flying capacitor C1 and the application end of the output voltage OUT.

  The oscillator 205 generates a clock signal CLK having a constant frequency.

  The inverter 206 corresponds to a first drive unit that generates a drive signal G20 for the FETs 201 and 202 in accordance with the clock signal CLK. The drive signal G20 is a logic inversion signal of the clock signal CLK.

  The driver 207 corresponds to a second drive unit that generates the drive signal G21 of the FET 203 in accordance with the detection signal S21 input from the comparator 209. The drive signal G21 is the same logic signal as the detection signal S21.

  The driver 208 corresponds to a third drive unit that generates the drive signal G22 of the FET 204 according to the detection signal S22 input from the comparator 210. The drive signal G22 is the same logic signal as the detection signal S22.

  The comparator 209 corresponds to a first detection unit that generates the detection signal S21 according to the both-ends voltage V21 (= SW22−V2) of the FET 203. The detection signal S21 is at a high level when the voltage V21 across the FET 203 is above the threshold voltage, and is at a low level when it is below the threshold voltage. That is, the detection signal S21 is at a high level when a current flows from the application terminal of the switch voltage SW22 toward the application terminal of the negative voltage V2 (or when the current can flow in the same direction). When the current flows from the application terminal of the negative voltage V2 toward the application terminal of the switch voltage SW22 (or when the current can flow in the same direction), the low level is reached. Note that the method for detecting the direction of the current flowing through the FET 203 or the body diode 203D is not limited to the configuration for monitoring the voltage V21 across the FET 203, but other configurations (for example, the voltage across the sense resistor is monitored). Configuration) may be adopted.

  The comparator 210 corresponds to a second detection unit that generates the detection signal S22 according to the voltage V22 (= OUT−SW22) across the FET 204. The detection signal S22 is at a high level when the voltage V22 across the FET 204 is above the threshold voltage, and is at a low level when it is below the threshold voltage. That is, the detection signal S22 is at a high level when a current flows from the application terminal of the output voltage OUT toward the application terminal of the switch voltage SW22 (or when the current can flow in the same direction). When the current flows from the application terminal of the switch voltage SW22 toward the application terminal of the output voltage OUT (or when the current can flow in the same direction), the low level is reached. Note that the method for detecting the direction of the current flowing through the FET 204 or the body diode 204D is not limited to the configuration for monitoring the voltage V22 across the FET 204, but other configurations (for example, monitoring the voltage across the sense resistor). Configuration) may be adopted.

  First, the basic operation of the charge pump circuit 2X will be schematically described. In the first phase (charging phase) in which the FETs 202 and 204 are turned off and the FETs 201 and 203 are turned on, the application terminal for the negative voltage V2 is applied from the application terminal for the positive voltage V1 through the FET 201, the flying capacitor C1, and the FET 203. The flying capacitor C1 is charged by the current flowing through the path leading to. At this time, the switch voltage SW21 is substantially the positive voltage V1 (more precisely, the voltage obtained by subtracting the voltage drop of the FET 201 from the positive voltage V1), and the switch voltage SW22 is substantially the negative voltage V2 (more precisely, the negative voltage). V2 plus the voltage drop of FET 203). Therefore, the charge corresponding to the differential voltage (approximately V1−V2) between the switch voltage SW21 and the switch voltage SW22 is stored in the flying capacitor C1.

  Thereafter, in the second phase (discharge phase / charge transfer phase) in which the FETs 202 and 204 are turned on and the FETs 201 and 203 are turned off, from the application terminal of the ground voltage GND through the FET 202, the flying capacitor C1, and the FET 204. The path leading to the application terminal of the output voltage OUT is conducted, and the flying capacitor C1 is discharged (charge transfer to the output capacitor C2). At this time, the switch voltage SW21 is substantially the ground voltage GND (more precisely, the voltage obtained by adding the drop voltage of the FET 202 to the ground voltage GND), and the switch voltage SW22 is obtained by changing the voltage across the flying capacitor C1 from the switch voltage SW21. The subtracted voltage (approximately V2-V1) is obtained.

  Accordingly, in the charge pump circuit 2X, the negative output voltage OUT (= V2−V1) obtained by subtracting the positive voltage V1 from the negative voltage V2 is obtained by repeatedly turning on and off the FETs 201 to 204 and repeatedly charging and discharging the flying capacitor C1. Can be generated.

  Next, on / off control of the FETs 201 to 204 will be described in detail. FIG. 8 is a timing chart showing an operation example of the charge pump circuit 2X. In order from the top, the clock signal CLK, the drive signal G20, the switch voltages SW21 and SW22, the detection signals S21 and S22, and the drive signals G21 and G22. Is depicted.

  In the example of FIG. 8, the FETs 202 and 204 are on and the FETs 201 and 203 are off until time t21. This state corresponds to the second phase described above, and a current flows from the application terminal of the output voltage OUT to the application terminal of the switch voltage SW22 through a path via the FET 204. At this time, the switch voltage SW22 is a voltage obtained by subtracting the voltage drop of the FET 204 from the output voltage OUT.

  At time t21, when the clock signal CLK rises from the low level to the high level, the drive signal G20 falls from the high level to the low level, so that the FET 201 is turned on and the FET 202 is turned off. As a result, the first end of the flying capacitor C1 is conducted to the application end of the positive voltage V1 via the FET 201, so that the switch voltage SW21 starts to rise. Also, the switch voltage SW22 starts to rise with the same behavior as the switch voltage SW21 in accordance with the charge conservation law of the flying capacitor C1.

  As the switch voltage SW22 rises, when the voltage V22 across the FET 204 (= OUT−SW22) falls below the threshold voltage of the comparator 210 at time t22, the detection signal S22 switches from the high level to the low level. That is, when the current starts to flow backward from the application terminal of the switch voltage SW22 to the application terminal of the output voltage OUT through the path via the FET 204 (or when the current can be reversely flowed), the detection signal S22 is high. Switch from level to low level. As a result, the drive signal G22 of the FET 204 is switched from the high level to the low level, and the FET 204 is turned off. Therefore, the reverse current flowing through the FET 204 can be interrupted without delay.

  When the switch voltage SW22 further decreases and the voltage V21 across the FET 203 (= SW22−V2) exceeds the threshold voltage of the comparator 209 at time t23, the detection signal S21 switches from the low level to the high level. That is, when the current starts to flow from the application end of the switch voltage SW22 toward the application end of the negative voltage V2 through the path via the body diode 203D (or when the current can flow in the same direction), the detection signal S21 switches from low level to high level. As a result, the drive signal G21 of the FET 203 is switched from the low level to the high level, and the FET 203 is turned on. This state corresponds to the first phase described above, and current starts to flow in a path from the application terminal of the positive voltage V1 to the application terminal of the negative voltage V2 via the FET 201, the flying capacitor C1, and the FET 203. At this time, the switch voltage SW22 is a voltage obtained by adding the drop voltage of the FET 203 to the negative voltage V2.

  Note that since the current flows through the body diode 203D having a larger forward voltage than the FET 203 until the FET 203 is sufficiently turned on, an overshoot occurs in the switch voltage SW22 (and SW21). However, since this state is a short period, it does not significantly affect the conversion efficiency and output voltage range of the charge pump circuit 2X.

  Thereafter, when the clock signal CLK falls from the high level to the low level at time t24, the drive signal G20 falls from the low level to the high level, so that the FET 201 is turned off and the FET 202 is turned on. As a result, the first terminal of the flying capacitor C1 is conducted to the application terminal of the ground voltage GND through the FET 202, so that the switch voltage SW21 starts to decrease. Also, the switch voltage SW22 starts to decrease in the same manner as the switch voltage SW21 in accordance with the charge conservation law of the flying capacitor C1.

  As the switch voltage SW22 decreases, when the voltage V21 across the FET 203 (= SW22−V2) falls below the threshold voltage of the comparator 209 at time t25, the detection signal S21 switches from the high level to the low level. That is, the detection signal S21 is high when the current starts to flow backward from the application terminal of the negative voltage V2 toward the application terminal of the switch voltage SW22 through the path through the FET 203 (or when the current can be reversed). Switch from level to low level. As a result, the drive signal G21 of the FET 203 is switched from the high level to the low level, and the FET 203 is turned off. Therefore, the backflow current flowing through the FET 203 can be interrupted without delay.

  When the switch voltage SW22 further decreases and the voltage V22 (= OUT−SW22) across the FET 204 exceeds the threshold voltage of the comparator 210 at time t26, the detection signal S22 is switched from the low level to the high level. That is, when the current starts to flow from the application terminal of the output voltage OUT to the application terminal of the switch voltage SW22 through the path via the body diode 204D (or when the current can flow in the same direction), the detection signal S22 switches from the low level to the high level. As a result, the drive signal G22 of the FET 204 is switched from the low level to the high level, and the FET 204 is turned on. This state corresponds to the previous second phase, and current starts to flow from the application end of the output voltage OUT toward the application end of the switch voltage SW22 through a path via the FET 204. At this time, the switch voltage SW22 is a voltage obtained by subtracting the voltage drop of the FET 204 from the output voltage OUT.

  Until the FET 204 is sufficiently turned on, an electric current flows through the body diode 204D having a larger forward voltage than the FET 204, so that an undershoot occurs in the switch voltage SW22 (and SW21). However, since this state is a short period, it does not significantly affect the conversion efficiency and output voltage range of the charge pump circuit 2X.

  As described above, in the charge pump circuit 2X of the fourth embodiment, the FET 203 and 204 are turned on when the current flows in the intended direction, and the current flows in the direction opposite to the intended direction. The person who becomes becomes off. Accordingly, since the FETs 203 and 204 are not turned on during the switching of the FETs 201 and 202, the simultaneous turn-on of the FET 201 and the FET 203 and the simultaneous turn-on of the FET 202 and the FET 204 can be reliably prevented. In the charge pump circuit 2X of the fourth embodiment, since one of the FETs 203 and 204 is always turned off and then the other is turned on, the simultaneous turning-on of the FET 203 and the FET 204 can be reliably prevented.

  As described above, in the charge pump circuit 2X of the fourth embodiment, a delay generation method in which a certain delay is given in advance to the on / off timing of each FET, or the gate voltage of one FET is switched to an off level. Compared with the gate voltage monitoring method that confirms that the gate voltage of the other FET is switched to the on level, the FET can be turned on and off easily and appropriately without depending on the parasitic capacitance of the wiring and the delay variation of the drive circuit. Control can be performed.

  In particular, in order to eliminate malfunction and efficiency reduction of the negative output type charge pump circuit in which the behavior of the switch voltage greatly fluctuates according to the capacitance value of the flying capacitor, the fourth embodiment is used instead of the delay generation method and the gate voltage monitoring method. It is desirable to adopt the configuration of the form.

<Fifth Embodiment>
FIG. 9 is a diagram showing a fifth embodiment (negative output type) of the charge pump circuit. The charge pump circuit 2Y of the fifth embodiment has basically the same configuration as that of the fourth embodiment, and is characterized in that AND gates 211 and 212 are provided in place of the drivers 207 and 208. Therefore, the same components as those in the fourth embodiment are denoted by the same reference numerals as those in FIG. 7, and redundant descriptions are omitted. In the following, only the characteristic portions of the fifth embodiment will be described. To.

  The first input terminal of the AND gate 211 is connected to the output terminal of the comparator 209 (application terminal of the detection signal S21). The second input terminal of the AND gate 211 is connected to the output terminal (the application terminal of the clock signal CLK) of the oscillator 205. The output terminal of the AND gate 211 (the application terminal of the drive signal G21) is connected to the gate of the FET 203. The AND gate 211 corresponds to a second drive unit that generates the drive signal G21 of the FET 203 in accordance with both the detection signal S21 input from the comparator 209 and the clock signal CLK input from the oscillator 205. The drive signal G21 is at a high level when both the detection signal S21 and the clock signal CLK are at a high level, and is at a low level in other cases.

  The first input terminal of the AND gate 212 is connected to the output terminal (application terminal of the detection signal S22) of the comparator 210. The second inverting input terminal of the AND gate 212 is connected to the output terminal (the application terminal of the clock signal CLK) of the oscillator 205. An output terminal of the AND gate 212 (application terminal of the drive signal G22) is connected to the gate of the FET 204. The AND gate 212 corresponds to a third drive unit that generates the drive signal G22 of the FET 204 in accordance with both the detection signal S22 input from the comparator 210 and the clock signal CLK input from the oscillator 205. The drive signal G22 is at a high level when the detection signal S22 is at a high level and the clock signal CLK is at a low level, and is at a low level in other cases.

  FIG. 10 is a timing chart showing an operation example of the charge pump circuit 2Y. In order from the top, the clock signal CLK, the drive signal G20, the switch voltages SW21 and SW22, the detection signals S21 and S22, and the drive signals G21 and G22. Is depicted.

  Regarding the operation of the charge pump circuit 2Y, a particularly notable point is the falling timing of the drive signals G21 and G22, that is, the off timing of the FETs 203 and 204. As shown in FIG. 10, in the charge pump circuit 2Y, the drive signal G22 falls with the rising edge (time t21, etc.) of the clock signal CLK as a trigger, and is driven with the falling edge (time t24, etc.) of the clock signal CLK as a trigger. The signal G21 falls.

  Thus, in the charge pump circuit 2Y of the fifth embodiment, a configuration is employed in which the FETs 203 and 204 are turned off before the reverse current starts to flow through the FETs 203 and 204. Therefore, no reverse current flows through the FETs 203 and 204, so that it is possible to more reliably prevent malfunction and efficiency reduction of the charge pump circuit 2Y.

  In the charge pump circuit 2Y, the FET 203 is turned off while the voltage V21 across the FET 203 exceeds the threshold voltage of the comparator 209, so that a current flows through the body diode 203D and the switch voltage SW22 (and SW21) Overshoot may occur. Similarly, in the charge pump circuit 2Y, the FET 204 is turned off while the voltage V22 across the FET 204 exceeds the threshold voltage of the comparator 210, so that a current flows through the body diode 204D and the switch voltage SW22 (and SW21). May cause undershoot. However, since all such states are short-lived, the conversion efficiency of the charge pump circuit 2Y and the output voltage range are not greatly affected.

<Sixth Embodiment>
FIG. 11 is a diagram showing a sixth embodiment (negative output type) of the charge pump circuit. The charge pump circuit 2Z of the sixth embodiment has basically the same configuration as that of the fifth embodiment, and is characterized in that off detection units 213 and 214 and a delay unit 215 are added. Therefore, the same components as those in the sixth embodiment are denoted by the same reference numerals as those in FIG. 9, and redundant descriptions are omitted. In the following, only the characteristic portions of the sixth embodiment will be described. To.

  The off detection unit 213 generates an off detection signal D21 according to the drive signal G21 of the FET 203. The off detection signal D21 is at a high level when the drive signal G21 is below the threshold voltage for off detection, and is at a low level when the drive signal G21 is above.

  The off detection unit 214 generates an off detection signal D22 according to the drive signal G22 of the FET 204. The off detection signal D22 is at a high level if the drive signal G22 is below the threshold voltage for off detection, and is at a low level if it is above.

  The delay unit 215 delays the clock signal CLK according to the off detection signals D21 and D22. Specifically, the delay unit 215 delays the fall of the clock signal CLK until the off detection signal D21 switches to the low level, and delays the rise of the clock signal CLK until the off detection signal D22 switches to the low level. Note that the clock signal CLK to which the delay is given by the delay unit 215 is sent to the inverter 206.

  FIG. 12 is a timing chart showing an operation example of the charge pump circuit 2Z, in which the clock signal CLK and the drive signals G20 to G22 are depicted in order from the top. In the case of the charge pump circuit 2Z of the sixth embodiment, the FET 203 is first used when shifting from the first phase (PHASE 1) to the second phase (PHASE 2) without depending on the parasitic capacitance of the wiring and the delay variation of the drive circuit. Is turned off, then the FET 201 is turned off, the FET 202 is turned on, and finally the FET 204 is turned on. Conversely, the second phase (PHASE2) is shifted to the first phase (PHASE1). In this case, it is possible to realize a series of sequences in which the FET 204 is first turned off, then the FET 201 is turned on, the FET 202 is turned off, and finally the FET 203 is turned on.

  In particular, in the negative output type charge pump circuit for exchanging clock signals between a plurality of semiconductor devices, it is desirable to employ the configuration of the sixth embodiment described above.

<Other variations>
The various technical features disclosed in the present specification can be variously modified within the scope of the technical creation in addition to the above-described embodiment. For example, the logic level inversion of various signals is arbitrary. That is, the above-described embodiment is an example in all respects and should not be considered as limiting, and the technical scope of the present invention is not the description of the above-described embodiment, but the claims. It should be understood that all modifications that come within the meaning and range of equivalents of the claims are included.

  The power supply apparatus according to the present invention can be used as a power supply for various applications such as LCD-TV, PDP-TV, DVD recorder, and BD recorder.

1X, 1Y, 1Z Charge pump circuit (positive output type)
100 Semiconductor device 101, 103, 104 PMOSFET
102 NMOSFET
103D, 104D Body diode 105 Oscillator 106-108 Inverter 109, 110 Comparator 111 OR gate 112 NAND gate 113, 114 Off detection unit 115 Delay unit 2X, 2Y, 2Z Charge pump circuit (negative output type)
200A, 200B Semiconductor device 201 PMOSFET
202-204 NMOSFET
203D, 204D Body diode 205 Oscillator 206 Inverter 207, 208 Driver 209, 210 Comparator 211, 212 AND gate 213, 214 Off detector 215 Delay unit C1 Flying capacitor C2 Output capacitor

Claims (10)

FET used as a charge / discharge switch for a capacitor;
A detection unit that generates a detection signal according to a current flowing through the FET or a voltage across the FET;
A drive unit that generates a drive signal of the FET in response to the detection signal;
A charge pump circuit comprising: A first FET connected between a first end of the capacitor and a first voltage application end;
A second FET connected between the first end of the capacitor and a ground voltage application end;
A third FET connected between the second end of the capacitor and a second voltage application end;
A fourth FET connected between the second end of the capacitor and an output voltage application end;
An oscillator that generates a clock signal;
A first driving unit that generates driving signals for the first FET and the second FET in response to the clock signal;
A first detection unit that generates a first detection signal according to a current flowing through the third FET or a voltage across the third FET;
A second detection unit that generates a second detection signal according to a current flowing through the fourth FET or a voltage across the fourth FET;
A second driving unit for generating a driving signal for the third FET in response to the first detection signal;
A third driving unit for generating a driving signal for the fourth FET in response to the second detection signal;
The charge pump circuit according to claim 1, further comprising: The second driving unit generates a driving signal for the third FET according to both the first detection signal and the clock signal,
The third driving unit generates a driving signal for the fourth FET in accordance with both the second detection signal and the clock signal;
The charge pump circuit according to claim 2. A first off detection unit that generates a first off detection signal in response to a driving signal of the third FET;
A second off detection unit for generating a second off detection signal in response to the drive signal of the fourth FET;
A delay unit that delays the clock signal according to the first off detection signal and the second off detection signal;
The charge pump circuit according to claim 3, further comprising:   5. The charge pump circuit according to claim 2, wherein each of the first voltage and the second voltage is a positive voltage. 6.   6. The charge pump circuit according to claim 5, wherein each of the first FET, the third FET, and the fourth FET is a P-channel type, and the second FET is an N-channel type.   5. The charge pump circuit according to claim 2, wherein the first voltage is a positive voltage and the second voltage is a negative voltage. 6.   8. The charge pump circuit according to claim 7, wherein the first FET is a P-channel type, and the second FET, the third FET, and the fourth FET are all N-channel type. The first FET, the second FET, the first driver, and the oscillator are all integrated in a first semiconductor device in which a ground voltage is applied to the substrate,
The third FET, the fourth FET, the first detection unit, the second detection unit, the second drive unit, and the third drive unit are all applied with a negative voltage applied to the substrate. Integrated in a semiconductor device,
The charge pump circuit according to claim 8.   A power supply apparatus comprising the charge pump circuit according to claim 1.