JP2013107341A - Head substrate, inkjet recording head using the head substrate, and recording device using the recording head - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a head substrate capable of maintaining reliability equivalent to that of a conventional ones while achieving a reduction in the number of terminals even when the number of recording elements is increased with the increase in image quality of a recording head, and to provide a long recording head in which the head substrate is turned into multiple chips.SOLUTION: A high capacity high frequency data is transferred by LVDS for reducing the number of terminals, and is stored in a shift register by using an internal clock having a double period or more generated by a clock generation part provided inside a head substrate. A recording data signal thus held is sequentially supplied to a plurality of recording elements driven by time division driving, and the plurality of recording elements are driven. In this way, in addition to the capability of applying EMI measures as compared with the cases in which the clock is separately supplied, the recording data signal is developed with the clock having a lower frequency inside the head substrate. Accordingly, the reliability of recording is improved.

Description

  The present invention relates to a head substrate, a recording head using the head substrate, and a recording apparatus using the recording head. In particular, the present invention relates to, for example, a head substrate in which about several thousand recording elements are arranged, a recording head that performs recording by an ink jet method using the head substrate, and a recording apparatus that uses the recording head. is there.

  For example, as information output devices in word processors, personal computers, facsimiles, and the like, recording devices that record information such as desired characters and images on a sheet-like recording medium such as paper or film are widely used. These recording devices are used in modern business offices and other paper processing departments. Furthermore, it is used as a recording device for personal use. In addition, high-density and high-speed recording is strongly desired for these recording apparatuses, and further cost reduction is required. Therefore, development and improvement have been attempted to meet these requirements.

  Among the recording apparatuses described above, an ink jet recording apparatus (hereinafter referred to as a recording apparatus) that performs recording by discharging ink from an ejection port disposed in a recording element is known as low-noise non-impact recording. The recording apparatus is capable of high-density and high-speed recording due to its structural characteristics, and is widely used as a low-cost color printer. The recording apparatus uses a recording head including a recording element (nozzle) having an ejection port and an electrothermal conversion element that generates ejection energy for ejecting ink from the ejection port, and according to desired recording information. Recording is performed by discharging ink.

  As a configuration of the recording head, a recording head in which a plurality of recording elements are arranged in a single row or a plurality of rows is conventionally known. In such a recording head, several or several tens of driving integrated circuits that can be driven simultaneously with N recording elements as one block are mounted on the same substrate. Arbitrary recording can be performed on a recording medium such as recording paper by aligning image data corresponding to each recording element and driving the recording element based on the image data.

  The performance of recording heads has been greatly improved with the recent increase in recording resolution and image quality. On the other hand, the number of recording elements increases with the increase in definition and image quality, or the number of simultaneous driving of the recording elements increases for the purpose of achieving high-speed recording. The performance of the recording element has also advanced, and it is possible to eject several picoliters of ink with a pulse width of about 1 μsec. This is achieved by a functional element (such as a MOS-FET driver) that switches a large current at high speed.

  In addition to this, the image data transfer for selectively energizing the recording elements is also improved. Already, the transfer frequency of image data exceeds 10 MHz, and in order to achieve higher-speed data transfer, it has been devised that image data can be shifted not only at the rising edge but also at the falling edge of the image data transfer clock. Nevertheless, if the transfer of image data is not completed within the ink ejection period from the printing element, the transfer of the image data lines is made parallel and parallel processing at the same clock frequency is performed.

  In addition to the image data, various data and control information need to be transferred at high speed. For example, there are various types of printheads according to the performance of the printing apparatus main body, and some printheads have information for identifying the type. Further, in the case of an ink jet recording head, there is a wide variety of information regarding the recording head required by the recording apparatus main body, such as the amount of ink used by an ink cartridge that is a consumable item.

  In the recording head, as the number of simultaneously driven recording elements increases, the energy required for driving increases. For this reason, a recording element driving method that matches the capacity of the power supply circuit, which is one of the performances of the recording apparatus main body, is required. Further, in the case of a recording element that performs recording using thermal energy, if one recording element is continuously driven, heat is accumulated, which may change the recording density or destroy the recording element itself. There is. In particular, when there is a factor such as manufacturing variation, the energy applied to the recording element is not appropriate, and the durability of the recording head is reduced.

  The recording element is also affected by the recording element adjacent thereto. For example, in an ink jet recording head (hereinafter referred to as a recording head), when adjacent recording elements are simultaneously driven, each nozzle is subjected to interference due to mutual pressure due to the pressure generated during ink ejection. This pressure interference (crosstalk) may cause a change in recording density. For this reason, it is desirable to perform control so as to provide a pause time to avoid heat radiation to some extent or crosstalk after driving the recording element.

  In addition, there is an increasing demand for drive control in accordance with the usage amount of cartridges that contain ink and processing liquid, particularly the usage amount of ink cartridges that supply ink to the recording head. This requirement is diverse, such as differences depending on ink color information and manufacturing date, differences due to ink viscosity, and differences depending on usage.

Japanese Patent Application Laid-Open No. 7-241992 Japanese Patent Laid-Open No. 10-166583 JP 2002-326348 A Japanese Patent Laid-Open No. 2005-199665

  In order to cope with the above problems and requirements, the recording head includes means for detecting the head temperature, means for arbitrarily changing the driving method with an external input signal, and means for detecting the recording head difference due to manufacturing variations. There is something. And it is proposed to take out and control such information as needed (for example, refer patent document 1). Also, a circuit configuration in which the recording element group is divided into a plurality of blocks composed of a predetermined number of recording elements and time-division driving is performed for each block has been put into practical use. As described above, the control of the periphery of the head unit is under the present situation that various control methods have been adopted and the processing system has become complicated as the recording apparatus has become highly functional.

  In the recording apparatus using the recording head as described above, the number of recording elements provided in the recording head tends to increase in order to increase the recording speed and the recording density. For this reason, the number of blocks for the time-division driving described above increases, and the number of control signal lines increases even when a decoder circuit or the like is used. For example, when a clock signal having a logic level of 5V or 3.3V is transferred at several tens of MHz, the influence of the radiation noise on peripheral devices and the control signal line of the recording apparatus increase.

  Furthermore, the recording apparatus must perform high-speed switching of a large current passing through the recording element. Switching noise (inductive electromotive force) due to the functional element is generated beyond the logic level from the power supply terminal, and affects nearby logic signal series wiring. This has become apparent in the form of abnormal recording due to malfunction of the logic circuit in image data, clock signals, and control data lines, and has become a problem in the configuration of the recording apparatus. As a configuration for taking measures against such noise, there is a method in which the ground terminal of the logic circuit and the ground terminal of the power supply line are separated as much as possible and short-circuited at the power supply terminal of the recording apparatus. However, coupled with the downsizing of the recording apparatus, the influence of jumping noise has increased. The carriage on which the recording head is mounted is moved at high speed by a carriage motor in the recording apparatus, and the noise level that jumps in is changed with the movement of the flexible cable wiring board connecting the carriage and the recording apparatus main body. The higher the image quality and function, the more complicated the configuration of such a recording head and the control of its peripheral devices. Since the control unit of the recording apparatus main body is complicated to control malfunctions due to noise and the like, a large load is generated on the control unit of the recording apparatus main body on which the recording head is mounted.

  For example, it is necessary to manage / execute a control sequence such as changing the drive pattern according to the operation mode of the recording head. If there is a large manufacturing variation or lot difference between recording heads, the difference in the recording state may be reflected in the image remarkably, so it is necessary to manage and calibrate them. Furthermore, it is also necessary to always perform data communication between the recording apparatus and the recording head, such as determining the type of the recording head and monitoring the driving status sequentially. Such noise jumping into the control data line is a fatal malfunction factor for the recording apparatus. Furthermore, there is a need for a mutual EMI (electromagnetic interference) countermeasure that affects peripheral devices due to noise radiated from the entire recording apparatus.

  In order to deal with the above problem, there is a method of providing two input terminals for each terminal differential as described in Patent Document 2. In this case, the common mode dive noise is canceled out. According to this method, a two-terminal transmission line is passed at a signal level equivalent to the control logic level of the logic circuit in the printing apparatus main body, carriage, or printing head. In this case, it is inevitable that the data rate is lowered due to the deterioration of the signal waveform due to the inductance and impedance of the transmission line. This causes a problem that radiation noise that causes malfunction of not only the recording apparatus but also its peripheral devices occurs, such as the influence of EMI due to high-frequency transfer increases.

  In view of this point, Patent Documents 3 and 4 disclose a configuration of a recording apparatus using a low voltage differential transmission (LVDS) line. The method according to the LVDS technique can be said to be effective from the viewpoint of EMI countermeasures.

  A general configuration when this technique is used for transfer between the recording head and the recording apparatus is as follows.

  FIG. 9 is a circuit diagram of the head substrate and the circuit using the conventional LVDS technology. The head substrate is used by being incorporated in an ink jet recording head, and a control signal and a data signal are transferred from the recording device to the recording head through an LVDS line.

  The head substrate 1 shown in FIG. 9 has a plurality of 640 recording elements (heaters) 16 arranged in a row on both sides along the long side of two rectangular ink supply ports 17. The ink supply port 17 is opened through the semiconductor substrate. Further, a drive circuit 15 for driving these recording elements is provided along these 640 recording elements. Furthermore, 640 AND circuits 14 for inputting drive signals to the drive circuit 15 are provided. Since each drive circuit receives a drive signal corresponding to one bit of the recording data signal, the drive circuit 15 is also called a 640-bit driver.

  The head substrate is provided with two LVDS receivers 2-a and 2-b. Outputs from these LVDS receivers are input to the 4-bit shift register 4, and some of the signals pass through the 4-bit latch circuit 6. 4 → 16 decoder 11 inputs. In the 4 → 16 decoder 11, a division drive signal for driving the recording elements in a time division manner is generated and input to one terminal of the AND circuit 14. The remaining signals are input to the other terminal of the AND circuit 14 through the 160-bit shift register 6 and the 160-bit latch circuit 7.

  Note that the AND circuit 14 receives the heat enable signal input from one of the inverting buffer circuits 12 and 13.

  As can be seen from FIG. 9, the head substrate 1 has two LVDS lines indicated by DATA + and DATA− input to the LVDS receiver 2-a and CLK + and CLK− input to the LVDS receiver 2-b. Exists. A latch signal input terminal (LT) for holding the recording data signal in the latch circuits 6 and 7 and a heat enable signal for separately driving the odd number and even number positions in the same column from the recording apparatus main body side are input. There are two terminals (HE1, HE2).

  The above configuration applies LVDS to terminals that require high-frequency data transfer, and can be said to be a typical configuration of a head substrate employing LVDS.

  FIG. 10 is a timing chart of signals for driving the head substrate shown in FIG. In the configuration in which the LVDS is applied to the recording data signal (DATA) and the clock signal (CLK), the recording data and the clock signal transmitted from the recording apparatus main body side by the LVDS driver are received by the LVDS receiver on the head substrate. Each of these signals is input to the head controller, and drive control of the head substrate is performed. This configuration is an effective configuration as an EMI countermeasure in a transmission path through which high-frequency data transfer is performed. In other words, there is an effect of reducing troubles in the recording head and the recording apparatus due to noise or the like in the LVDS line and other communication lines.

  A problem in applying this configuration to the recording apparatus is the speed of the LVDS signal transmitted from the recording apparatus main body to the recording head. The LVDS signal is characterized in that data can be transferred at a speed 10 times higher than that of a single-ended signal.

  A semiconductor substrate (head substrate) used inside the recording head is provided with switching elements having a high withstand voltage of about several tens of volts corresponding to the number of recording elements. The maximum response frequency of these high breakdown voltage switching elements is about several tens of MHz. In a conventional semiconductor process for manufacturing a recording head, high-speed support such as an LVDS receiver that can support even several hundred MHz is not sufficient.

  For this reason, the transfer speed of the recording data and the clock signal still remains at about 10 MHz, and the substantial correspondence to high frequencies has not progressed. Therefore, when recording data or a clock signal is transferred at a high speed, there is a problem that due to semiconductor characteristics, the data shift of the internal shift register does not operate well due to the rounding of the clock signal waveform and the like, and sufficient performance of LVDS cannot be exhibited.

  Further, this type of head substrate also has a problem that high-frequency noise or noise that lowers the reliability of circuit operation occurs due to energization of the recording element. It is necessary to pay sufficient attention to sneak noise that is not in the common mode even for LVDS signals. Furthermore, when the head substrate is used for a thermal head or a thermal ink jet recording head, there is a temperature variation due to heat generation of the recording element, and reliability corresponding to the temperature change is required. In a situation where the setup and hold times of the recording data signal (DATA) with respect to the clock signal (CLK) are shortened due to high-frequency data transfer, a decrease in reliability due to temperature characteristic changes is unavoidable. These problems are unique to a recording apparatus that controls a recording head that supplies a large current.

  As the number of recording elements increases in the future, recording heads that require high-frequency data are required to solve such problems. In particular, in a recording apparatus, it is important to transfer a recording information amount accompanying an increase in recording elements at a high speed with a small number of terminals such as LVDS. In the recording head, it is important to effectively develop the recording information for recording element driving.

  The present invention has been made in view of the above conventional example, and a head substrate capable of high-speed data transfer and highly reliable signal processing with fewer signal lines by LVDS, an ink jet recording head using the head substrate, and recording thereof An object of the present invention is to provide a recording apparatus using a head.

  In order to achieve the above object, the recording apparatus of the present invention has the following configuration.

  That is, a head substrate that serially receives at least a data signal and a clock signal synchronized with the data signal from the outside as a high-frequency signal through an LVDS line, and drives a plurality of recording elements with the high-frequency signal to perform a recording operation, A first LVDS receiver provided near two input terminals for receiving the data signal; a second LVDS receiver provided near two input terminals for receiving the clock signal; and the second LVDS receiver. A clock generation unit that divides a clock signal received and demodulated by the LVDS receiver to generate a low-frequency internal clock signal, and a data signal received and demodulated by the first LVDS receiver are input according to the internal clock signal. A shift register that performs shift processing and latches the data signal held in the shift register. And having a latch circuit, and a driving circuit for driving the plurality of recording elements in accordance with the latched data signal to the latch circuit.

  In another aspect of the present invention, an ink jet recording head using the head substrate having the above configuration is provided.

  Further, from another aspect of the present invention, a recording apparatus using the recording head is provided.

  Therefore, according to the present invention, even when a large amount of high-frequency data is transferred to the head substrate by LVDS, the head substrate is developed at the same speed as the conventional one, so that a highly reliable head substrate can be provided. There is. Further, since the shift operation to the shift register is performed using a low frequency internal clock, a sufficient EMI measure is taken compared to the case where a high frequency clock is supplied separately. By using LVDS for high-frequency data input, for example, the number of head terminals can be reduced by adopting a serial configuration of a plurality of data signals, and the influence of high-voltage switching elements is small, and reliability is strong against jumping noise. A high-performance recording head can be configured.

  Furthermore, in the case of a multi-chip recording head in which a plurality of such head substrates are arranged, high-capacity high-frequency data transfer is performed by LVDS, so that the number of terminals can be significantly reduced compared to conventional recording heads, and high definition and A low-cost long recording head can be provided.

1 is a perspective view showing a configuration of an ink jet recording apparatus that is a typical embodiment of the present invention. FIG. 2 is a block diagram illustrating a control configuration of the recording apparatus illustrated in FIG. 1. 1 is a perspective view illustrating a configuration of an ink jet recording apparatus including a full line recording head. It is a circuit diagram which shows the structure of the head board | substrate according to Example 1 of this invention. FIG. 5 is a circuit diagram showing a specific internal configuration of a shift register and a latch circuit shown in FIG. 4. 6 is a drive timing chart of a recording head. 7 is a drive timing chart illustrating in detail a signal of a portion A surrounded by a dotted line shown in FIG. FIG. 2 is a block diagram showing a configuration of a full line recording head in which a plurality of head substrates of the present invention are arranged. It is a block diagram which shows the structure of the head board | substrate which applied the conventional LVDS. It is a drive timing chart of the head substrate to which the conventional LVDS is applied.

  Hereinafter, preferred embodiments of the present invention will be described more specifically and in detail with reference to the accompanying drawings. The configurations disclosed in the following embodiments are merely examples, and the present invention is not limited to the illustrated configurations.

  In this specification, “recording” (sometimes referred to as “printing”) is not limited to the case of forming significant information such as characters and graphics, but may be significant. Furthermore, it also represents a case where an image, a pattern, a pattern, or the like is widely formed on a recording medium or a medium is processed regardless of whether or not it is manifested so that a human can perceive it visually.

  “Recording medium” refers not only to paper used in general recording apparatuses but also widely to cloth, plastic film, metal plate, glass, ceramics, wood, leather, and the like that can accept ink. Shall.

  Further, “ink” (sometimes referred to as “liquid”) should be interpreted widely as in the definition of “recording (printing)”. Therefore, by being applied on the recording medium, it is used for formation of images, patterns, patterns, etc., processing of the recording medium, or ink processing (for example, solidification or insolubilization of the colorant in the ink applied to the recording medium). It shall represent a liquid that can be made.

   Further, the “recording element” (sometimes referred to as “nozzle”) is a general term for an ink discharge port, a liquid path communicating with this, and an element that generates energy used for ink discharge unless otherwise specified. Say it.

<Description of Recording Apparatus (FIGS. 1 to 3)>
FIG. 1 is a schematic view of an ink jet recording apparatus which is a typical embodiment of the present invention. In FIG. 1, the lead screw 5004 rotates via driving force transmission gears 5011 and 5009 in conjunction with forward and reverse rotation of the carriage motor 5013. The carriage HC has a pin (not shown) that engages with the spiral groove 5005 of the lead screw 5004 and is reciprocated in the directions of arrows a and b as the lead screw 5004 rotates. An ink jet cartridge IJC is mounted on the carriage HC. The ink jet cartridge IJC includes an ink jet recording head (hereinafter referred to as a recording head) IJH and an ink tank IT for storing recording ink.

  The recording head IJH includes a monochrome recording head and a color recording head, and any of the recording heads can be appropriately selected by the user according to the application and mounted on the carriage HC. When a recording head for monochrome recording is used, an ink tank IT containing monochrome ink (black ink) is mounted. When a recording head for color recording is used, four ink tanks IT each containing four types of inks of yellow, magenta, cyan, and black are mounted.

  The ink jet cartridge IJC may have a configuration in which the ink tank and the recording head are integrated, or may have a configuration in which the ink tank and the recording head can be separated.

  Reference numeral 5002 denotes a paper pressing plate that presses the paper against the platen 5000 in the moving direction of the carriage. The platen 5000 is rotated by a transport motor (not shown) and transports the recording paper P. Reference numeral 5016 denotes a member that supports a cap member 5022 that caps the front surface of the recording head. Reference numeral 5015 denotes suction means for sucking the inside of the cap, and performs suction recovery of the recording head via the opening 5023 in the cap.

  Next, a control configuration for executing the recording control of the above-described apparatus will be described.

  FIG. 2 is a block diagram showing the configuration of the control circuit of the recording apparatus shown in FIG.

  In FIG. 2, 1700 is an interface for inputting a recording signal, 1701 is an MPU, and 1702 is a ROM for storing a control program executed by the MPU 1701. Reference numeral 1703 denotes a DRAM for storing various data (such as the recording data and recording data signals supplied to the recording head). Reference numeral 1704 denotes a gate array (GA) that controls supply of recording data signals to the recording head IJH, and also performs data transfer control among the interface 1700, MPU 1701, and RAM 1703. The above is the configuration of the control circuit 101 on the recording apparatus main body side.

  Reference numeral 1709 denotes a transport motor (not shown in FIG. 1) for transporting the recording paper P. Reference numeral 1706 denotes a motor driver for driving the carry motor 1709, and 1707 denotes a motor driver for driving the carriage motor 5013.

  The operation of the above control configuration will be described. When recording data enters the interface 1700, the recording data is converted into a recording data signal for recording between the gate array 1704 and the MPU 1701. Then, the motor drivers 1706 and 1707 are driven, and the recording head IJH is driven via the control unit 102 on the carriage side in accordance with the recording data signal sent to the carriage HC to record an image on the recording paper P. Is called.

  In order to drive the recording element provided in the recording head IJH under the optimum driving condition, the characteristic information held in the memory 131 of the head substrate 1 in the recording head IJH is referred to and the driving condition of each recording element is referred to. Is determined. The head substrate 1 is mounted with a plurality of recording elements and functional elements (for example, power transistors) for driving the recording elements. In order to selectively drive the functional elements, a logic circuit including a shift register, a latch circuit, an AND circuit, a decoder, and the like are mounted. The recording element may be an electrothermal conversion element that generates thermal energy for ejecting ink or a piezo element.

<Outline of recording apparatus and recording head assembly>
FIG. 3 is a schematic perspective view of a full-line recording apparatus using a recording head assembly 25 described later. In FIG. 3, reference numerals 201A and 201B denote a pair of rollers provided for nipping and conveying the recording medium R such as recording paper in the conveying direction VS. Reference numeral 200 denotes a discharge recovery unit including a cap, an ink absorber, a wiping blade, and the like. In the ejection recovery process, the ejection recovery unit 200 faces the recording head assembly 25 instead of the recording medium R.

  Next, an embodiment of a head substrate used in the recording apparatus and the recording head (or recording head assembly) having the above-described configuration will be described.

  FIG. 4 is a diagram showing a circuit configuration of a head substrate according to a typical embodiment of the present invention. 4, the same reference numerals and symbols are assigned to the same components and signals as those included in the head substrate described with reference to FIG.

  The head substrate 1 is manufactured by a semiconductor manufacturing process. Further, the terminals of the head substrate 1 include a portion that is further extended by a flexible substrate that is formed by inner bonding each terminal on the outer periphery of the head substrate 1 shown in FIG. 4 (not shown in FIG. 4).

  A plurality of VH and GNDH existing on the outer periphery of the head substrate 1 (short side of the rectangular substrate) are a power supply terminal for energizing the recording element and a ground terminal for the feedback current, respectively. The recording current per recording element is several tens of mA, and when several tens or more recording elements are energized simultaneously, the recording current exceeds 1 A. Therefore, two systems are distributed and arranged for each recording element array. VDD is a power supply terminal for driving the semiconductor circuit, and GNDL is a ground terminal thereof. Although one by one is illustrated in this embodiment, it may be added as appropriate in accordance with the configuration of the semiconductor circuit.

  The configuration of this embodiment includes two LVDS lines indicated by DATA + and DATA− and CLK + and CLK−. Here, the data of the LVDS line is set as high-frequency data, and the signal data corresponding to the recording elements after the corresponding stage of the LVDS receivers 2-a and 2-b is set as a recording data signal conventionally used. These LVDS receivers are arranged on the head substrate in the vicinity of two input terminals that receive DATA + and DATA− and CLK + and CLK−. As other signal terminals, a latch signal input terminal LT for holding the recording data signal in the latch circuits 6 to 10 in the head substrate, and a pulse-like heat enable signal for providing energy for driving the recording element from the recording apparatus side are input. There are only terminals HE1 and HE2.

  The input terminals HE1 and HE2 are terminals that can separately drive the odd-numbered and even-numbered recording elements 16 in the same column. Since this terminal is a negative logic signal, it is connected to the AND circuit 14 in the head substrate 1 via the inverting buffers 12 and 13. In the head substrate 1, ink supply ports 17 that can correspond to two colors (or one color) may be opened through the semiconductor substrate.

  The input terminals HE1 and HE2 function in common for a plurality of printing element arrays. In FIG. 4, a printing element group consisting of 640 printing element numbers A1, A3,. Similarly, A2, A4,..., A1280 have one row of recording element groups of 640, B1, B3,..., B1279 have one row of printing element groups, B2, B4,. One row of printing element groups of 640 is formed by B1280. The functional element array (640-bit driver) 15 corresponding to the number (640) of the recording data signal, the divided drive signal input to the AND circuit 14, and the pulse of the heat enable signal input from the input terminals HE1 and HE2 Driven according to the width. The recording data signal is an output from the latch circuits 7, 8, 9, and 10 corresponding to each column. The divided drive signal is input to the latch circuit 6 as a 4-bit signal following the recording data signal, and the 4 → 16 decoder 11 converts it into 16 types of output signals.

  Further, the latch circuits 6, 7, 8, 9, and 10 are provided with shift registers 4 and 5 for inputting the division drive signal and the recording data signal. The control for internally generating the shift clock signal input to the shift registers 4 and 5 and holding the developed recording data signal in the latch circuit is a characteristic configuration of the head substrate of the present invention.

  In a conventional head substrate (not shown), the shift clock used for this shift register is about several tens of MHz, but in the present invention, it is twice or more. Conventionally, input of a clock signal exceeding several tens of MHz has led to an increase in the input buffer size of the semiconductor circuit. For this reason, when transferring a recording data signal of 50 MHz or more, two or more data lines are provided at a reduced frequency. However, in such a conventional method, when the number of recording elements reaches several thousand, the data lines are arranged in parallel, so that the number of terminals on the substrate increases.

  In the present invention, the receiving portion of this data line is an LVDS line, and as shown in FIG. 4, this embodiment includes an LVDS receiver 2-a (first LVDS receiver). The differential input signal by DATA + and DATA− is a low voltage of about several hundred mV. These low voltage signals can reduce power consumption on the cable, contribute to EMI countermeasures, and reduce the differential buffer size of the input stage. After high frequency data is input into the semiconductor circuit, the internal circuit can be made small so that a function corresponding to the high frequency characteristics can be extracted.

  On the other hand, the clock signal demodulated from the LVDS receiver 2-b (second LVDS receiver) to the logic level in the head substrate is frequency-divided by the internal clock generator 3 at a speed less than half. The recording data signal and the divided drive signal similarly demodulated by the LVDS receiver 2-a are inputted to the shift registers 4 and 5 at high speed, but are shifted by the divided clock. In this manner, the data shift is performed by reducing the speed to half or less the frequency of the input clock signal, thereby increasing the reliability of data development inside the head substrate. Further, dividing the recording data signal and the divided drive signal and shifting the data in parallel is one method for improving reliability.

  As an internal configuration of the head substrate, a circuit layout that supplies a signal obtained by demodulating a high-frequency signal input to the LVDS receiver to the shift register most recently is also important for improving reliability. When the recording data signal shifted by the internal clock generated by the clock generation unit 3 and the divided drive signal are held in the latch circuits 6 to 10, the operation speed is reduced to the conventional transfer speed. Can be deployed while maintaining reliability. Thereafter, the process up to the energization of the recording element is performed in the same manner as in the prior art.

  FIG. 5 is a circuit diagram showing an internal configuration and an arrangement configuration of a shift register that shifts high-frequency data using an internal clock and a latch circuit that latches a recording data signal and a divided drive signal. In FIG. 4, latch circuits 6 and 7, shift registers 4 and 5, and a part of the latch circuit 8 are illustrated.

  The data signal DATA, which is a serial signal of the recording data signal and the divided driving signal, is sent to the shift register 4 for the divided driving signal and the shift register 5 for the recording data signal that determines the number of recording elements to be driven simultaneously at the division timing. Align with each other. For this purpose, shift clocks ICLK0-3 are used.

  As described above, in this embodiment, the last 4 bits of the high-frequency data are held in the latch circuit 6 by using the shift register 4, and the output is converted into 16 kinds of timing outputs by the 4 → 16 decoder 11. This sets the division driving order. A configuration having latch circuits 7 to 10 (only 7 and 8 are shown in FIG. 5) corresponding to each printing element array is a characteristic configuration of the head substrate 1. By designating the division driving order every time, it is not necessary to provide shift registers and latch circuits corresponding to all 2560 recording elements of the head substrate 1, so that the scale of the shift registers and latch circuits can be reduced to 1/16. it can. That is, the recording data signal and the divided driving signal of the shift register and the latch circuit are updated 16 times to drive all the recording elements. This configuration has been applied conventionally, and is an important technique that contributes to cost reduction by reducing the area of the semiconductor substrate.

  6 to 7 are timing charts of signals used for the head substrate 1. FIG. 6 shows an outline of the drive, and FIG. 7 is a detailed description of a portion surrounded by a dotted line A in FIG.

  In these timing charts, the recording data signal and the divided drive signal transferred earlier in time are aligned from the end of the shift register 5 shown in FIGS. 4 to 5 and held at the end of the corresponding latch circuit 10. is there. In general, high-frequency data is added with a start bit, an end bit, and the like. However, bits corresponding to these bits are not handled on the shift register, and here, the number of bits corresponding to the printing element will be described.

  According to FIG. 6, the high-frequency data DATA ± has a data length of 160 bits corresponding to a recording data signal for 4 blocks of divided drive signals initially handled by the decoder 11 and 1 block of time-division drive. Serial input. This corresponds to the signal in the area surrounded by the dotted line A. The serially received recording data signal and the division drive signal are latched by the next simultaneous division block period. Update data having the same data length is input at the same timing, and the recording operation of time-division driving for 2560 recording elements is completed by repeating 16 times.

  In each divided drive block, a heat enable signal for driving the recording element is input from the input terminals HE1 and HE2. The reason why the input timing from each of the input terminals HE1 and HE2 is shifted is to allow the adjacent recording elements to act on the ink without crosstalk.

  In this embodiment, the heat enable signal is input from the outside using the input terminals HE1 and HE2, but this is to give a degree of freedom regarding the control from the recording apparatus main body. Accordingly, it goes without saying that the head substrate 1 itself may be configured to internally generate the heat enable signal. In this case, the input signal terminals can be further reduced, which greatly contributes to the cost reduction of the head substrate 1.

  FIG. 7 is a timing chart showing the relationship between the input of the portion A surrounded by the dotted line A in FIG. In this embodiment, as shown in FIG. 7, the high frequency data DATA ± is reproduced by the LVDS receiver, the internal clocks ICLK0 to 3 are sufficient for DATA setup, and the clock rising position at the hold time point (center position). Align. Then, by the latch signal, the 160-bit recording data signal transferred previously is held in the latch circuit together with the divided drive signal. Then, the recording elements are individually driven according to the heat enable signals supplied from the input terminals HE1 and HE2.

  According to the embodiment described above, the clock generator for reproducing the clock signal of the LVDS line input and dividing the clock signal to generate the internal clock signal is provided in the head substrate, and the shift register at the subsequent stage is provided by the internal clock signal. And shift processing in the latch circuit. Therefore, even if a high frequency clock signal is input by LVDS, the shift processing in the shift register and the latch circuit is performed by the low speed clock signal inside the head substrate, so that a highly reliable data signal while contributing to EMI countermeasures. Deployment can be realized inside the head.

  Here, an example of a multi-chip recording head configuration in which a plurality of head substrates 1 described in the first embodiment are arranged will be described.

  FIG. 8 is a functional block diagram showing an example of the peripheral circuit configuration of the multichip recording head assembly and the recording apparatus main body.

  In FIG. 8, the block shown on the left side shows the control circuit 101 and the LVDS transceiver (parallel serial conversion (P / S)) 130 of the printing apparatus. As described above, it goes without saying that there are various other circuits on the recording apparatus main body side, such as a motor driver such as a motor for transporting recording paper and a drive circuit for controlling the ink supply mechanism. . The block shown on the right side is a peripheral circuit configuration including a head controller 110 and an LVDS receiver (serial / parallel conversion (S / P)) 140 (third LVDS receiver). The right block controls the printhead assembly 25, which is the lower right block of FIG. The head controller 110, the recording head assembly 25, and the LVDS receiver 140 may be configured integrally or may be configured separately. The recording head assembly 25 is also provided with a sensor 132 for measuring the internal temperature.

  A power supply 150 is provided on the recording apparatus main body side. Since the configuration of the control circuit 101 has already been described with reference to FIG. 2, the description thereof is omitted here.

  In addition, as can be seen from FIG. 8, the control circuit 101 and the head controller 110 have an LVDS transceiver and an LVDS receiver arranged in front of each other, and transmit and receive signals by LVDS. Each physical connection portion is a cable or a flexible cable (FPC), and an LVDS driver is arranged near the connector to be connected (preferably within 1 inch). Thus, the effect of the LVDS line is maximized by suppressing the routing of the pair wirings as much as possible. A plurality of head substrates 1 described in the above-described embodiments are arranged in the recording head assembly 25, and signals are transmitted to and received from these head substrates and the head controller 110 by LVDS.

  The high frequency data handled by the LVDS driver may include a print head control command in addition to the print data signal. In this case, by providing a command register on the recording head assembly side, it has a control function in accordance with the command protocol. In generating these data, it is necessary to convert the data obtained by the parallel processing into high-frequency data on the recording apparatus side. This function is achieved by a parallel-serial conversion circuit. Since it is necessary to multiplex the clock and the high-frequency data at this stage, the timing control using the PLL is similarly required. It goes without saying that such a circuit including a control circuit 101 on the recording apparatus side is composed of a one-chip gate array in terms of function. In this case, it is essential that the arrangement of the gate array be close to the connector of the transmission line.

  Various configurations including the recording head assembly 25 are conceivable on the LVDS receiver 140 side connected to the head controller 110. Here, a configuration having the LVDS receiver 140 and the head controller 110 that are faster than the recording head assembly 25 will be described as an example.

  Also in this case, the LVDS receiver is arranged near the connector to which the cable is connected (preferably within 1 inch). The configuration of the head substrate is as described with reference to FIG. 4, and the recording head assembly 25 shown in FIG. 8 has a configuration in which four head substrates 1 are arranged in a staggered manner.

  In the vicinity of the LVDS receiver, a clock recovery and edge detection circuit for generating a multiplexed clock is applied. The high-frequency data is developed in the head controller 110 by serial / parallel (S / P) conversion. The clock signal and the latch signal are provided with a clock and latch signal input terminal input from the recording apparatus side for internally generating. It is desirable to have no configuration.

  If the transfer rate of the high-frequency data transferred to the head substrate 1 is not required more than necessary, a clock-synchronized parallel LVDS line may be configured. When such a high-frequency data signal line is arranged in a cable or a flexible cable (FPC), it is arranged away from the power supply line. If possible, there should be a ground conductor (GNDL) partition in between. Originally, the low voltage LVDS line is preferably a shielded line, but it is difficult to use the shielded line in the recording apparatus. Therefore, a configuration using a flexible cable is optimal. A pair of LVDS lines is placed close to each other and separated from other LVDS line pairs and normal signal lines by a ground conductor (GNDL). The wiring corresponding to the end of the flexible substrate is preferably a ground wiring without using a pair of LVDS lines. This is to maintain the balance of the LVDS line pair section.

  LVDS high-frequency data and other signals generated in the head controller 110 and connected to each head substrate are connected by a connector or the like. The head controller 110 has a function of developing data to a low-speed LVDS that can handle a high-speed LVDS high-frequency signal on a head substrate, and a function of performing characteristic data and sensor control on the multi-chip recording head assembly 25. In accordance with a command from the recording apparatus main body, data relating to drive control of the recording head assembly 25 is transmitted / received via the head controller 110. For example, if the head controller 110 is made compatible with a multi-chip including four head substrates, even if the recording head assembly becomes longer, it can be dealt with by adding the head controller 110.

  Therefore, by adopting the configuration as in the above-described embodiment, it is possible to easily cope with a long recording head and a full line recording head having a multichip configuration. In the case of a multi-chip recording head in which a plurality of such head substrates are arranged, the number of terminals of the head substrate can be significantly reduced as compared with the conventional head substrate.

  Needless to say, the effects obtained with the configuration of the embodiment described above are not affected by differences in electrical and mechanical configurations, differences in software sequences, and the like.

  In addition, the head substrate and the recording head are implemented in various modes, and the development process to the shift register performed in the head substrate is P / S conversion (shifting of head driving information including a recording data signal for each recording element array). (Transfer from register to latch circuit).

  Further, the LVDS signal input is applied to a signal that requires high-frequency transmission such as a recording data signal or a clock signal, and may be mixed with a single-ended signal when a high transmission rate is not required.

Claims (9)

A head substrate for serially receiving at least a data signal and a clock signal synchronized with the data signal as a high-frequency signal from the outside through an LVDS line and driving a plurality of recording elements by the high-frequency signal to perform a recording operation;
A first LVDS receiver provided in the vicinity of two input terminals for receiving the data signal;
A second LVDS receiver provided near two input terminals for receiving the clock signal;
A clock generator that divides the clock signal received and demodulated by the second LVDS receiver to generate a low-frequency internal clock signal;
A shift register that receives and demodulates the data signal received and demodulated by the first LVDS receiver according to the internal clock signal;
A latch circuit for latching a data signal held in the shift register;
And a driving circuit for driving the plurality of recording elements in accordance with the data signal latched by the latch circuit. The data signal includes a recording data signal for driving the plurality of recording elements and a division driving signal for time-division driving the plurality of recording elements,
The shift register includes a shift register for holding the recording data signal, and a shift register for holding the divided drive signal,
2. The head substrate according to claim 1, wherein the latch circuit includes a latch circuit for holding the recording data signal and a latch circuit for holding the divided drive signal.   3. The head substrate according to claim 1, wherein the clock generation unit generates an internal clock signal in which a frequency of the clock signal received by the second LVDS receiver is reduced to a half or less.   The head substrate according to claim 1, further comprising an ink supply port that supplies ink supplied from outside to the plurality of recording elements.   An ink jet recording head using the head substrate according to claim 4.   An ink jet recording head comprising a plurality of head substrates according to claim 4.   The inkjet recording head according to claim 6, further comprising a head controller that supplies a recording data signal and a clock signal to the plurality of head substrates.   The head controller further includes a third LVDS receiver that serially receives at least a data signal and a clock signal synchronized with the data signal as an RF signal from the outside through an LVDS line and demodulates the received RF signal. The ink jet recording head according to claim 7.   A recording apparatus using the inkjet recording head according to claim 5.

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