JP2011046160A - Recording head and recording device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a high quality recording head which maintains reliability equivalent to that of a conventional type while reducing the number of terminals even when the number of recording elements are increased to achieve high image quality of the recording head, and to provide a long recording head formed by making the recording head into a multichip-type, and a recording device. <P>SOLUTION: Large volume of high frequency data and synchronized clock are transferred by LVDS (Low-Voltage Differential Signaling) to reduce the number of terminals, and wiring is performed so that the wiring of the data and wiring of the clock have approximately equal length, so as to eliminate a synchronous error of the data and clock. By multi-dropped connection of the clock, the clock can be made common, and reduction in the number of terminals and an EMI (Electro-Magnetic Interference) countermeasure can be promoted, compared with a case where a large number of clocks are supplied. Thus, this is effective as a basic configuration for improving the reliability of the long recording head in the multichip-type and providing the high-definition and inexpensive long recording head. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to a recording head and a recording apparatus. In particular, for example, the present invention relates to a recording head and a recording apparatus that perform recording by an ink jet method, in which a plurality of recording head substrates on which several thousand recording elements are arranged are arranged.

  For example, as information output devices in word processors, personal computers, facsimiles, and the like, recording devices that record information such as desired characters and images on a sheet-like recording medium such as paper or film are widely used. These recording devices are used in modern business offices and other paper processing departments. Furthermore, while it is used as a printer for personal use and high density and high speed recording are strongly desired, development and improvement have been attempted in order to achieve further cost reduction or high definition.

  Among the recording apparatuses described above, there is an ink jet recording apparatus that performs recording by ejecting ink from an ejection port disposed on a recording element as low-noise non-impact recording. Inkjet recording apparatuses are capable of high-density and high-speed recording due to their structural characteristics, and are widely used as low-cost color printers. An ink jet recording apparatus uses a recording head including a recording element (nozzle) having an ejection port and an electrothermal conversion element that generates ejection energy for ejecting ink from the ejection port, and according to desired recording information. Recording is performed by discharging ink.

  As a configuration of the recording head, a recording head in which a plurality of recording elements are arranged in a single row or a plurality of rows is conventionally known. In such a recording head, several or several tens of driving integrated circuits that can be driven simultaneously with N recording elements as one block are mounted on the same substrate. Arbitrary recording can be performed on a recording medium such as recording paper by aligning image data corresponding to each recording element and driving the recording element.

  With recent high definition and high image quality, the performance of the recording head has been greatly improved. On the other hand, the number of printing elements simultaneously increases for the purpose of increasing the number of printing elements with higher definition and higher image quality or increasing the printing speed. The performance of the recording element has also improved, and it is possible to eject several picoliters of ink with a pulse width of about 1 microsecond. This is achieved by a functional element (such as a MOS-FET driver) that switches a large current at high speed.

  In addition to this, the same improvement has been achieved in image data transfer for selectively supplying a recording current to a recording element. The transfer frequency of image data has already exceeded 10 megahertz, and in order to achieve higher-speed data transfer, it has been devised that image data can be shifted not only at the rising edge but also at the falling edge of the image data transfer clock. . Nevertheless, if the transfer of image data is not completed within the ink ejection period from the printing element, the transfer of the image data lines is made parallel and parallel processing at the same clock frequency is performed.

  There is also a need to transfer not only image data but also various data and control information at high speed. For example, there are various types of printheads according to the performance of the printer body, and some printheads have information for identifying the type. Further, in the case of an ink jet recording head, there is a wide variety of information about the recording head required by the printer main body, such as the amount of ink used by an ink cartridge that becomes a consumable item.

  In the recording head, as the number of recording elements driven simultaneously increases, the energy required for driving increases. Therefore, a recording element driving method that matches the capacity of the power supply circuit, which is one of the performances of the printer main body, is required. Furthermore, in the case of a recording element that performs recording using heat, when one recording element is continuously driven, heat is accumulated, which may change the recording density or destroy the recording element itself. There is sex. In particular, when there is a factor such as manufacturing variation, the energy applied to the recording element is not appropriate, and the durability of the recording head is reduced.

  The recording element is also affected by the recording element adjacent thereto. For example, in an ink jet recording apparatus, when adjacent recording elements are driven simultaneously, the pressure generated when ink is ejected causes each nozzle to receive interference due to mutual pressure. This pressure interference (crosstalk) may cause a change in recording density. For this reason, it is desirable to perform control so as to provide a pause time to avoid heat radiation to some extent or crosstalk after driving the recording element.

  In addition, there is an increasing demand for drive control in accordance with the amount of recording agent used in a cartridge containing a recording agent such as ink, particularly the amount of ink cartridge used in an ink jet recording head. This requirement is diverse, such as differences depending on ink color information and manufacturing date, differences due to ink viscosity, and differences depending on usage.

Japanese Patent Application Laid-Open No. 7-241992 Japanese Patent Laid-Open No. 10-166583 JP 2002-326348 A Japanese Patent Laid-Open No. 2005-199665

  In order to deal with the above problems and requirements, the recording head has means for detecting the temperature of the recording head, means for arbitrarily changing the driving method with an external input signal, and means for detecting the recording head difference due to manufacturing variations. There is what I did. It has been proposed to extract and control such information as necessary. (For example, refer to Japanese Patent Application Laid-Open No. 7-241992.) (Patent Document 1) Further, a circuit configuration in which the recording element group is divided into a plurality of blocks composed of a predetermined number of recording elements and time-division driving is performed for each block is practical. It has become. As described above, the present situation is that the periphery of the recording head unit has been complicated by adopting various control methods as the recording apparatus becomes more sophisticated.

  In the recording apparatus using the recording head as described above, the number of recording elements provided in the recording head tends to increase in order to increase the recording speed and the recording density. For this reason, the number of blocks in the above-described time-division driving increases, and the number of control signal lines increases even when a decoder circuit or the like is used. For example, when a clock signal having a logic level of 5 volts or 3.3 volts is transferred at several tens of megahertz, the influence of the radiated noise on the peripheral device and the influence on the control signal line of the recording apparatus increase.

  Furthermore, the recording apparatus must perform high-speed switching of a large current passing through the recording element. Switching noise (inductive electromotive force) due to the functional element is generated beyond the logic level from the power supply terminal, and affects nearby logic signal series wiring. This state has become apparent in the form of abnormal recording due to malfunction of the logic circuit in image data, clock signals, control data lines, and the like, and has become a problem in the configuration of the recording apparatus. As a configuration to take countermeasures against such noise, there is a method of separating the ground terminal of the logic circuit and the ground terminal of the power line as much as possible and short-circuiting at the power supply terminal of the recording device. Coupled with the downsizing of the equipment, the influence of jumping noise has increased. The carriage on which the recording head is mounted is moved at high speed by a carriage motor in the recording apparatus, and the noise level that jumps in is changed with the movement of the flexible cable wiring board connecting the carriage and the recording apparatus main body. The higher the image quality and function, the more complicated the configuration of the recording head and the surrounding control devices. Since the control unit of the recording apparatus main body is complicated to control malfunctions due to noise and the like, a large load is generated on the control unit of the recording apparatus main body on which the recording head is mounted.

  For example, it is necessary to manage / execute a control sequence such as changing the drive pattern according to the operation mode of the recording head. If there is a large manufacturing variation or lot difference between recording heads, the difference in the recording state may be reflected in the image remarkably, so it is necessary to manage and calibrate them. Furthermore, it is also necessary to always perform data communication between the recording apparatus and the recording head, such as discriminating the model of the head and sequentially monitoring the driving status. Such noise jumping into the control data line is a fatal malfunction factor for the recording apparatus. Furthermore, there is a need for a mutual EMI (Electro-Magnetic Interference) countermeasure that affects peripheral devices due to noise radiated from the entire recording apparatus.

  In order to deal with the above problem, there is a method of providing two input terminals for each terminal differential as described in JP-A-10-166583 (Patent Document 2). In this case, common mode dive noise is canceled out. The two-terminal transmission line is passed at a signal level equivalent to the logic level of the logic circuit control in the printing apparatus main body and the carriage or printing head. In this case, it is inevitable that the data rate is lowered due to the waveform deterioration due to the inductance and impedance of the transmission line. This causes a problem that radiation noise that causes malfunction of not only the recording apparatus but also its peripheral devices occurs, such as the influence of EMI due to high-frequency transfer increases.

  In view of this point, Japanese Patent Application Laid-Open No. 2002-326348 (Patent Document 3) and Japanese Patent Application Laid-Open No. 2005-199665 (Patent Document 4) disclose the configuration of a recording apparatus using a low voltage differential transmission (LVDS) line. Has been. This method in conformity with the LVDS technology can be said to be an effective method from the viewpoint of EMI countermeasures.

  When the present technology is used for transfer between a recording head and a recording apparatus, a general configuration of a recording head substrate is shown in FIG. In this case, there are two LVDS lines indicated by 2-a DATA + and DATA- and 2-b CLK + and CLK-. LT input terminal for holding the image data in the latch circuits 6 and 7 in the printhead substrate, and a pulse width input terminal HE1 capable of separately driving the odd number and even number positions in the same column from the printing apparatus side. There are three HE2. The recording head substrate 1 has an ink supply port 17 that can correspond to two colors (may be one color) and is opened through the semiconductor substrate. LVDS is applied to terminals that require high-frequency data transfer, and can be said to be a basic configuration of a future recording head substrate.

  FIG. 6 is a drive timing chart of FIG. 5 showing the recording head substrate. In this configuration in which LVDS is applied to the DATA and CLK terminals, image data, a clock signal, and the like transmitted from the main body side by the LVDS driver are received by the recording head board side LVDS receiver. Each of these signals is input to the head control unit to control the drive of the recording head substrate. This system is an effective configuration as an EMI countermeasure in a transmission path for high-frequency data transfer. It is possible to reduce troubles of the recording head and the recording apparatus due to noise and other problems in the LVDS line and other communication lines.

  FIG. 7 is a timing chart showing the relationship between the input of the head portion A of FIG. 6 and the internal signal. For the high-frequency data DATA ±, CLK ± adjusts the rising position to a sufficient DATA setup and hold time point (center position). By the LT signal, the image data for 160 bits transferred previously is held in the latch circuit together with the divided drive data. The recording elements are individually driven according to the pulse width inputs HE1 and HE2.

  A problem in applying this method to the recording apparatus is a difference in transmission speed between the LVDS clock and the data signal transmitted from the recording apparatus main body to the recording head. The LVDS signal is characterized in that data can be transferred at a speed 10 times higher than that of a single-ended signal. A semiconductor substrate (recording head substrate) used in a conventional recording head is provided with switching elements having a high withstand voltage of about several tens of volts corresponding to the number of recording elements. Since the maximum response frequency of these high-breakdown-voltage switching elements was about a dozen megahertz, the transmission difference between the clock and data was not so much of a problem. However, when a high-speed compatible circuit such as an LVDS receiver capable of handling several hundred megahertz is applied to the recording head substrate, the transmission difference between the LVDS clock and the data becomes conspicuous as the wiring becomes long, and data transfer is not performed correctly. Produced.

  FIG. 8A and FIG. 8B are obtained by observing the LVDS clock wiring length and transmission waveform delay. The top shows the oscillation on the recording apparatus side, and the bottom shows the vicinity of the LVDS clock input terminal of the recording head substrate with a differential probe. FIG. 8A shows the waveform of the recording head substrate mounted at the closest distance on the recording head, and FIG. 8-B shows the waveform of the recording head substrate mounted at the farthest distance. Although the wiring distance between the recording head substrates is about 400 millimeters, the transmission waveform delay is delayed by about 3 nanoseconds. In the conventional recording head, such a delay time is not a big problem. For example, in the case of 10 megahertz transfer, there is a margin of 25 nanoseconds for the clock and data setup and hold times even for both edge shift data. As shown in FIG. 9, when the LVDS data transfer capacity is 100 megabps, the LVDS clock frequency is 50 MHz both-edge shift data, and the clock and data setup (ts) and hold time (th) are 5 nanoseconds each. I can only afford it. However, as shown in FIG. 9, the delay of 3 nanoseconds causes a problem that it is difficult to define the data hold time. If the recording head is driven in this state, clock skew occurs due to factors such as the recording device, connection cable, and recording head substrate characteristics, and data control cannot be performed normally. When image data and clocks are transferred at high speed, due to semiconductor characteristics, the data shift of the internal shift register cannot exhibit sufficient performance of LVDS due to the rounding of the clock waveform. Further, this type of recording head substrate generates high frequency noise and noise that degrades circuit operation reliability due to energization of recording current. It is necessary to pay sufficient attention to sneak noise that is not in the common mode even for LVDS signals. Further, when the recording head substrate is a thermal head or a thermal inkjet head, there is a temperature variation due to heat generation of the recording element, and reliability corresponding to the temperature change is required. In a situation where the setup and hold times for the data clock are shortened due to high-frequency data transfer, a decrease in data transfer reliability due to temperature characteristic changes is unavoidable. These problems are unique to the configuration of a recording apparatus that controls a large amount of image data with a recording head that supplies a large current.

  FIG. 10 is a graph showing the relationship based on the observation results of the LVDS clock wiring pattern length and transmission waveform delay. The measurement point is proportional to the relative permittivity εr of the circuit pattern material on which the recording head substrate is mounted as the slope constant. The relative dielectric constant εr calculated from the graph of FIG. 10 was 4.46. This value is equivalent to the relative dielectric constant of a general glass / epoxy substrate (FR-4). When the conductor of the LVDS pattern wiring exists in the circuit pattern material, the transmission speed can be calculated as follows.

When electromagnetic waves are propagating in a material having a relative dielectric constant εr, the transmission speed is
V = C / √εr (C is the speed of light)
= 3 × 10 ⁸ /√4.46
The time τ required for 1 mm transmission is
^{τ = √4.46 × 10 3/3} × 10 8
≈ 7 picoseconds The ratio of the dielectric constant of the pattern material to the dielectric constant of the vacuum is ε / ε0 = εr. Basically, the transmission speed of the conductor is determined by the relative dielectric constant of the circuit pattern material in which the conductor exists, and increases in proportion to the pattern length. As long as it has LVDS data for which high-speed transmission is essential and LVDS clock to be synchronized, a circuit pattern layout without a transmission speed difference is indispensable.

  As the number of recording elements increases in the future, recording heads that require high-frequency data are required to solve such problems. In particular, in a recording apparatus, it is important to transfer a recording information amount accompanying an increase in recording elements at a high speed with a small number of terminals such as LVDS. In the recording head, it is important to reliably transfer the recording information to the recording head and improve the reliability of driving the recording element.

  In order to increase the number of recording elements accompanying high image quality and to reliably transfer large-capacity image data and control data necessary for recording head high-speed driving to the recording head and improve the reliability of recording element driving, the present invention provides the following: Such means are provided. In other words, the LVDS clock and LVDS data input to the printhead substrate are substantially equal in length, and the setup and hold time for the data clock so that data can be correctly developed within the drive circuit of the printhead substrate in the printhead. It is set as the structure which can fully ensure. Further, by devising the wiring inside the recording head, it is possible to provide a high-function, high-definition long recording head capable of processing a large amount of data while reducing the number of terminals of the recording head.

  The recording head and the recording apparatus according to the present invention can be implemented in various modes, and are particularly suitable for a recording head configuration in which a plurality of recording head substrates having LVDS input terminals are arranged.

  When LVDS clocks individually input to the printhead substrate are multidrop connected in units of several, the corresponding LVDS data wiring is individually made to be approximately equal length wiring according to the clock wiring length. Even when three or more recording head substrates are connected in common, the corresponding LVDS data wiring is configured to have substantially the same length.

  Even in a configuration in which the multi-drop connected LVDS clock is divided into two or more blocks commonly connected across three or more recording head substrates and double-terminated, the corresponding LVDS data wirings are individually substantially equal. The configuration is such that the wiring is long.

  Even in a recording head having a configuration in which at least one row of recording head substrates is continuously arranged or staggered, the LVDS clock wiring is wired in parallel to the recording head substrate row, and the multi-drop connection is made from this wiring to the recording head substrate at the shortest. The configuration.

  Regarding the connection between the recording apparatus and the recording head, the LVDS clock and the LVDS data wiring are wired from the point transmitted from the recording apparatus side to the recording head substrate input terminal at approximately the same length.

  When the LVDS clock wiring of the multi-chip recording head in which a plurality of the recording head substrates are arranged is shared, the number of terminals of the recording head of this configuration can be significantly reduced as compared with the conventional recording head.

  The LVDS input having a transmission capacity more than double that of the conventional one can reduce the number of head terminals and can constitute a high-function, high-definition long recording head capable of processing a large amount of data.

  With the above configuration, in a recording head that requires a large amount of high-frequency data, a high-function, high-definition recording head that can develop data with high reliability by making the LVDS clock wiring synchronized with the LVDS data substantially equal in length. Can provide.

  The effect of the recording head and the recording apparatus according to the present invention is remarkable in a recording head configuration in which a plurality of recording head substrates having LVDS clock wirings synchronized with LVDS data are arranged.

  Further, it goes without saying that the same effect can be obtained even when LVDS clocks individually input to the printhead substrate are multidrop connected in units of several. The same effect can be obtained even in a configuration in which multidrop-connected LVDS clocks are connected in common over three or more recording head substrates and are divided into two or more blocks and double-terminated.

  The present invention can also be applied to a recording head having a configuration in which at least one row of recording head substrates is continuously arranged or staggered. If the LVDS clock wiring is wired in parallel to the plurality of recording head substrate rows, the clock can be supplied from the wiring to the recording head substrate in the shortest time, so that a more reliable recording head can be provided.

  Furthermore, the LVDS clock and the LVDS data wiring are wired from the point transmitted from the recording apparatus side to the recording head substrate input terminal at approximately the same length, so that the recording apparatus has a highly reliable configuration.

  When the LVDS clock wiring of a multi-chip recording head in which a plurality of the recording head substrates are arranged is shared, the number of recording head terminals in this configuration can be remarkably reduced as compared with the conventional recording head.

  The number of head terminals can be reduced with the LVDS input having a transmission capacity more than double that of the conventional one, and a high-function, high-definition long recording head capable of processing a large amount of data can be configured, thereby providing a high-quality recording head at low cost. Is.

FIG. 3 is a block diagram of a recording head configuration in which a plurality of recording head substrates are arranged, showing a typical configuration of the present invention. FIG. 3 is a block diagram of a recording head configuration in which a plurality of recording head substrate arrangements are further expanded. FIG. 3 is a configuration block diagram of a recording apparatus in which a plurality of recording head substrates are arranged. -A The most basic wiring layout of the recording head to which the present invention can be applied, -b Related to FIG. 4-a, wiring layout in which the recording head substrate is a block of three units, and -c related to FIG. 4-a In connection with FIG. 4-a, a wiring layout in which all six printhead substrates are connected in a multi-drop connection, -e. Related to a, the shortest wiring layout in which all six printhead substrates are shared. 1 is a configuration block diagram of a recording head substrate to which the present invention can be applied. 4 is a drive timing chart of a recording head substrate to which the present invention can be applied. FIG. 7 is a drive timing chart illustrating in detail the top portion A of FIG. 6. -A Waveform of the recording head substrate mounted at the closest distance on the recording head, -b Waveform of the recording head substrate mounted at the farthest distance on the recording head. The figure which shows the setup and hold time of a clock and data. Graph based on observation results of wiring pattern length and transmission waveform delay. 1 is a schematic view of an ink jet recording apparatus that is a typical embodiment of the present invention. FIG. 12 is a block diagram illustrating a control configuration of the recording apparatus illustrated in FIG. 11. 1 is a schematic diagram illustrating a configuration of a long recording apparatus to which the present invention is applied.

(Example)
In the embodiments described below, a recording apparatus using a recording head according to an ink jet system will be described as an example.

  In this specification, “record” (sometimes referred to as “print”) not only forms significant information such as characters and graphics, but also forms images, patterns, patterns, etc. on a wide range of recording media. Or a case where the medium is processed.

  “Recording medium” refers not only to paper used in general recording apparatuses but also widely to cloth, plastic film, metal plate, glass, ceramics, wood, leather, and the like that can accept ink. Shall.

  Further, “ink” (sometimes referred to as “liquid”) should be interpreted widely as in the definition of “recording (printing)”. By being applied on the recording medium, an image, a pattern, a pattern, or the like is formed. Alternatively, it represents a liquid that can be used for processing of the recording medium or processing of the ink (for example, solidification or insolubilization of the colorant in the ink applied to the recording medium).

  Furthermore, unless otherwise specified, the “nozzle” collectively refers to an ejection port or a liquid channel communicating with the ejection port and an element that generates energy used for ink ejection.

<First embodiment>
FIG. 1 is a block diagram best illustrating the configuration of the present invention. Assume a recording head on which a plurality of recording head substrates are arranged, a cable connecting the recording apparatus, or a low-cost flexible cable (FFC). The recording apparatus side of this configuration is configured by an LVDS transceiver that transmits the LVDS clock (CLK) and a plurality of LVDS data (DATA 0 to n) in the recording head controller (signal generation to the LVDS transceiver is not shown). A plurality of recording head substrates are mounted on the recording head side. The recording head substrate having the configuration shown in FIG. 5 is applied. It is driven by the timing chart shown in FIGS. When a plurality of these printhead substrates are mounted to form a multichip printhead, DATA ± terminals described in the basic timing chart of FIG. 6 are supplied in parallel for the printhead substrate. A feature of this configuration is that all clock terminals are connected in common (multidrop) in order to reduce the number of terminals of the recording head. A recording head substrate (described as a recording head unit in the figure) includes a terminal for receiving an LVDS clock and LVDS data, and a head driver array that drives a plurality of aligned recording elements for each recording head substrate.

  The differential input signal of the LVDS receiver is about several hundred millivolts at a low voltage. These low voltage signals can reduce power consumption on the line, contribute to EMI countermeasures, and reduce the differential buffer size of the input stage. After high frequency data is input into the semiconductor circuit, the internal circuit can be made small so that a function corresponding to the high frequency characteristics can be extracted.

  The nth LVDS clock of the recording head substrate is terminated before the input of the LVDS receiver. Since the termination resistance is about 100 ohms and is fail-safe, both ends may be pulled up and down. LVDS data is individually terminated for each printhead substrate. As an internal configuration of the recording head substrate, a circuit layout that supplies a signal obtained by demodulating a high-frequency signal input to the LVDS receiver to the shift register most recently is also important for improving reliability. Thereafter, the processing until the recording current is supplied to the recording element is achieved in the same manner as in the prior art.

<Second embodiment>
FIG. 2, which is a second embodiment to which the present invention can be applied, shows a multi-chip recording head configuration in which the plurality of recording head substrate arrangements used in the first embodiment are further expanded.

  The characteristic configuration of FIG. 2 is a configuration in which when 2n recording head substrates are mounted, an LVDS clock is supplied to the center and n recording head substrates are aligned on both sides. The LVDS clock terminals in the recording head substrate that are both ends (each nth) have a double-ended multidrop configuration in which a terminating resistor is added immediately before. The LVDS data is supplied and terminated separately as in the first embodiment. In any recording head configuration, since the LVDS clock is multidrop-connected to a plurality of recording head substrates, the number of terminals is greatly reduced. As for the cable wiring connecting the recording apparatus and the recording head, it is necessary to make the LVDS signal pair close to each other, avoid interference with other pairs, and to arrange a ground potential guard pattern or the like in some cases.

  FIG. 3 is a block diagram showing an example of the configuration of a multi-chip recording head (assembly) and a peripheral circuit of the recording apparatus main body. The block shown on the left side is a print head control circuit including a controller of the printing apparatus. Although not shown, it goes without saying that there are various other circuits on the recording apparatus side, such as a paper driver, a motor driver such as a carriage drive motor, and a drive circuit for controlling the ink supply mechanism. The block shown on the right side is a peripheral circuit configuration including a recording head. The right circuit block is composed of a block on which a controller for controlling the printhead is mounted and a printhead assembly, both of which are integrated or separated.

  The recording apparatus side control circuit on the left side includes a power source, a drive control unit, and an image data control unit, and has a processor that performs overall control of these functions. A connection portion with the block including the recording head assembly on the right side is a cable or a flexible cable (FPC), and an LVDS driver is disposed near the connector to be connected (preferably within 1 inch). The effect of the LVDS line is maximized by suppressing the routing of the pair wiring as much as possible.

  The high frequency data sent to the LVDS driver may include a print head control command and the like in addition to the image data. In this case, by providing a command register on the recording head side, a control function corresponding to the command protocol is provided. In generating these data, it is necessary to convert the data obtained by the parallel processing into high-frequency data on the recording apparatus side. This function is achieved by a parallel-serial conversion circuit. Since it is necessary to multiplex the clock and the high-frequency data at this stage, the timing control using the PLL is similarly required. Needless to say, it is functionally superior to configure such a circuit including a control circuit on the recording apparatus side by a one-chip gate array. In this case, it is essential that the arrangement of the gate array be close to the connector of the transmission line.

  Various configurations including the recording head assembly can be provided on the LVDS receiver side of the right block. Here, a block having an LVDS receiver and a head controller that are faster than the recording head assembly will be described as an example. Also in this case, the LVDS receiver is arranged near the connector to which the cable is connected (preferably within 1 inch). The configuration of the recording head substrate is as described in FIG. 1, and FIG. 5 shows a configuration in which four recording head substrates are arranged in a staggered manner. In the vicinity of the LVDS receiver, a clock recovery and edge detection circuit for generating a multiplexed clock is applied. The high-frequency data is developed in the head controller by serial-parallel conversion, but it is desirable that the clock and latch signal input terminal from the recording apparatus side exist in order to internally generate the clock and latch signal. If the high-frequency data rate sent to the recording head substrate is not required to be higher than necessary, it can be constituted by a clock-synchronized parallel LVDS line. When such a high-frequency data signal line is arranged in a cable or a flexible cable (FPC), it is separated from the power line at a distance. If possible, there should be a ground conductor (GNDL) partition in between. Originally, a shielded wire is desirable for the low voltage LVDS line, but it is difficult to use the shielded wire in the recording apparatus. Therefore, a recording apparatus configuration using a flexible cable is optimal. A pair of LVDS lines is placed close to each other and separated from other LVDS line pairs and normal signal lines by a ground conductor (GNDL). The wiring corresponding to the end of the flexible substrate is preferably a ground wiring without using a pair of LVDS lines. This is to maintain the balance of the LVDS line pair section.

  LVDS high-frequency data and other signals generated in the head controller of the right block and connected to each recording head substrate are connected by a connector or the like. The head controller has a function of developing data to a low-speed LVDS capable of handling a high-speed LVDS with a recording head substrate, and a function of enabling characteristic data relating to a multi-chip recording head assembly and sensor control. In accordance with a command from the recording apparatus main body, data relating to drive control of the recording head assembly is transmitted and received via the head controller. For example, if this head controller is adapted to four multichips, even if the recording head assembly is further lengthened, it can be coped with by adding a head controller. Needless to say, the recording head can be easily adapted to a longer recording head in the future. In the case of FIG. 3, the configuration in which the wiring of the LVDS clock and the LVDS data, which is a feature of the present invention, is applied to the wiring from the head controller to the recording head substrate mounted on the multi-chip recording head assembly is applied. . As a result, it is possible to provide a highly reliable recording head and recording apparatus free from data transfer errors even when the recording head assembly is further lengthened.

  4A to 4E are wiring layout examples of a multichip recording head to which the present invention can be applied. In either case, the LVDS clock and the LVDS data are substantially equal in length.

  FIG. 4A shows a substantially equal length wiring layout of the most basic LVDS clock and LVDS data in the multi-chip recording head. In the drawing, the case where there are six recording head substrates is described as an example, but the configuration is conscious of mounting about one or two. In particular, when the number of printhead substrates mounted is small and the printhead has several LVDS clocks and LVDS data terminals, this configuration is the optimum configuration with the least data transfer error.

  FIG. 4-b shows a multi-chip recording head on which six recording head substrates are mounted. Three recording head substrates are connected by multi-drop connection, and the LVDS clock and LVDS data are wired with approximately the same length. In recent years, the length of the recording head substrate in the direction of the recording element array has increased by about 1 inch. On the other hand, the stub length of the LVDS multidrop connection wiring (branch wiring length from the common connection line) should be 2 inches or less. There is a disclosure. In the case of three or more multi-drop connections, a common LVDS clock line is arranged as a dotted line (the dotted line is an image of the back side wiring of a double-sided board), and the stub length is minimized. In this state, if the LVDS clock and the LVDS data terminal are substantially equal in length, an optimum configuration with few data transfer errors can be obtained.

  FIG. 4-c shows a configuration in which all LVDS clocks are shared in a multi-chip recording head on which six recording head substrates are mounted. When six recording head substrates are mounted, the upper row and the lower row of the staggered arrangement are each multidrop-connected, and both ends (the left end of the staggered arrangement in the figure) are terminated. The LVDS clock is supplied from the right input at the center. In this case as well, the LVDS clock and the LVDS data are wired substantially in the same length, so that the data transfer error is reduced. Since all the LVDS clocks are multidrop connected to a plurality of recording head substrates, the number of terminals is greatly reduced.

  FIG. 4D shows another configuration in which all LVDS clocks are shared in a multi-chip recording head on which six recording head substrates are mounted. When six printhead substrates are mounted, the upper row in the staggered arrangement and the lower row (or the reverse order) are respectively multidrop-connected in order to form the final end (the right end in the staggered arrangement in the figure). In the figure, the LVDS clock is supplied from the upper right input of the staggered arrangement which is the first stage. In this case as well, the LVDS clock and the LVDS data are wired substantially in the same length, so that the data transfer error is reduced. Also in this case, since the LVDS clocks are all multidrop-connected to a plurality of recording head substrates, the number of terminals is greatly reduced.

  FIG. 4E shows another configuration in which the LVDS clock is shared in the multi-chip recording head on which six recording head substrates are mounted. When six recording head substrates are mounted, the LVDS clock wiring for multidrop connection is laid out between the upper and lower rows in a staggered arrangement, and the final end is the left end. The LVDS clock is supplied from the lower right side input of the first staggered arrangement. In this case as well, the LVDS clock and the LVDS data are wired substantially in the same length, so that the data transfer error is reduced. In the case of FIG. 4D, the wiring length to the sixth recording head substrate is the longest, and the equal-length wiring distance of the LVDS data is correspondingly increased. However, in the case of this configuration, the total wiring distance to each recording head substrate. Therefore, the wiring layout area in the recording head can be minimized. Also in this case, since the LVDS clocks are all multidrop-connected to a plurality of recording head substrates, the number of terminals is greatly reduced. In this embodiment, the LVDS clock is arranged between the upper row and the lower row of the staggered arrangement of the recording head substrate, but it goes without saying that the same effect can be obtained even if arranged in either the upper row or the lower row. . Further, even when the LVDS clocks are arranged in parallel rather than in a staggered arrangement, the stub lengths are all uniform and the data transfer error is reduced if the LVDS clocks are arranged in parallel to the arrangement row.

<Description of recording apparatus>
FIG. 11 is a schematic view of an ink jet recording apparatus which is a typical embodiment of the present invention. In the drawing, a lead screw 5005 rotates via driving force transmission gears 5011 and 5009 in conjunction with forward and reverse rotation of a carriage motor 5013. The carriage HC has a pin (not shown) that engages with the spiral groove 5005 of the lead screw 5004 and is reciprocated in the directions of arrows a and b as the lead screw 5004 rotates. An ink jet cartridge IJC is mounted on the carriage HC. The ink jet cartridge IJC includes a recording head IJH and an ink tank IT that stores recording ink.

  The recording head IJH includes a monochrome recording head and a color recording head, and any of the recording heads can be appropriately selected by the user according to the application and mounted on the carriage HC. When a recording head for monochrome recording is used, an ink tank IT containing monochrome ink (black ink) is mounted. When a recording head for color recording is used, four ink tanks IT each containing four types of inks of yellow, magenta, cyan, and black are mounted.

  The ink jet cartridge IJC may have a configuration in which the ink tank and the recording head are integrated, or may have a configuration in which the ink tank and the recording head can be separated.

  Reference numeral 5002 denotes a paper pressing plate that presses the paper against the platen 5000 in the moving direction of the carriage. The platen 5000 is rotated by a conveyance motor (not shown) to convey the recording paper P. Reference numeral 5016 denotes a member that supports a cap member 5022 that caps the front surface of the recording head. Reference numeral 5015 denotes suction means for sucking the inside of the cap, and performs suction recovery of the recording head via the opening 5023 in the cap.

  Next, a control configuration for executing the recording control of the above-described apparatus will be described. 12 is a block diagram showing the configuration of the control circuit of the recording apparatus shown in FIG. 1700 is an interface for inputting a recording signal, 1701 is an MPU, 1702 is a ROM for storing a control program executed by the MPU 1701, and 1703 is for storing various data (such as the recording signal and image data supplied to the recording head). DRAM. Reference numeral 1704 denotes a gate array (GA) that controls the supply of image data to the recording head IJH, and also controls data transfer among the interface 1700, MPU 1701, and RAM 1703. The above is the configuration of the control circuit 101 on the recording apparatus side.

  Reference numeral 1709 denotes a transport motor (not shown in FIG. 11) for transporting the recording paper P. Reference numeral 1706 denotes a motor driver for driving the carry motor 1709, and 1707 denotes a motor driver for driving the carriage motor 5013.

  The operation of the above control configuration will be described. When a recording signal enters the interface 1700, the recording signal is converted into image data for printing between the gate array 1704 and the MPU 1701. Then, the motor drivers 1706 and 1707 are driven, and the recording head IJH is driven via the carriage-side control unit 102 according to the image data sent to the carriage HC, and image recording on the recording paper P is performed.

  In order to drive the recording element provided in the recording head IJH under the optimum driving condition, the characteristic information held in the memory 131 of the recording head substrate 103 in the recording head IJH is referred to, and the driving of each recording element is performed. Conditions are determined. A plurality of recording elements and a functional element (for example, a power transistor) for driving the recording elements are mounted on the recording head substrate 103. In order to selectively drive the functional elements, a logic circuit including a shift register, a latch circuit, an AND circuit, a decoder, and the like are mounted. The recording element may be an electrothermal conversion element that generates thermal energy for ejecting ink or a piezo element.

<Overview of recording device and recording head assembly>
FIG. 13 shows a long recording apparatus using the recording head assembly 25. In FIG. 13, 201A and 201B are a pair of rollers as conveying means provided for nipping and conveying the recording medium R in the sub-scanning direction VS. Reference numeral 200 denotes discharge recovery means. In the ejection recovery process, 200 faces the recording head assembly 25 instead of the recording medium R. Reference numeral 200 includes a cap, an ink absorber, a wiping blade, and the like.

  In addition, regarding the configuration of the embodiment described above, as long as the effects of the present invention are obtained, the configuration is not affected by differences in electrical and mechanical configurations, software sequences, or the like.

DESCRIPTION OF SYMBOLS 1 Recording head board | substrate 2-a, 2-b LVDS receiver 3 Clock control circuit 4 Shift register circuit for divided drive data 5 Shift register circuit for image data 6 Latch circuit for divided drive data 7, 8, 9, 10 Latch for image data Circuit 11 Decoder circuit 12, 13 Inversion buffer circuit for ODD / EVEN terminal 14 AND circuit 15 Functional element array 16 Recording element 17 Ink supply port

Claims (9)

In a recording head for recording on a recording medium by supplying a recording current to a plurality of recording elements based on recording head drive information.
A driving circuit power supply terminal for energizing the recording current and controlling the recording current, a low voltage differential transmission (LVDS) clock input for controlling at least one system of the driving circuit, and an LVDS clock input In the recording head substrate composed of at least one synchronized LVDS data input terminal,
An LVDS clock input to the recording head substrate and the LVDS data wiring are wired at equal lengths. In a recording head having a configuration in which a plurality of recording head substrates for performing recording on a recording medium are provided by supplying a recording current to a plurality of recording elements based on recording head driving information.
An LVDS clock and LVDS data wiring, which are individually input to the recording head substrate, are wired at equal lengths. In a recording head having a configuration in which a plurality of recording head substrates for performing recording on a recording medium are provided by supplying a recording current to a plurality of recording elements based on recording head driving information.
LVDS clocks that are individually input to the recording head substrate are multi-drop connected in units of several, and the corresponding LVDS data wiring is individually equal in length according to the multi-drop connected clock wiring length. A recording head characterized by being made.   The multi-drop connected LVDS clocks are commonly connected across the three or more recording head substrates, and the corresponding LVDS data lines are individually equal in length according to the multi-drop connected clock line lengths. The recording head according to claim 3, wherein the recording head is wired.   The multi-drop connected LVDS clock is divided into a plurality of blocks commonly connected across three or more recording head substrates, and the corresponding LVDS data wiring has a plurality of multi-drop connected clock wiring lengths. 4. The recording head according to claim 3, wherein the recording head is individually wired to have the same length.   The multi-drop connected LVDS clock is divided into two or more blocks commonly connected across three or more recording head substrates and is double-terminated, and the corresponding LVDS data wiring is connected to the multi-drop 4. The recording head according to claim 3, wherein the recording heads are individually wired at equal lengths in accordance with a plurality of connected clock wiring lengths. In a recording head having a configuration in which a recording current is applied to a plurality of recording elements based on recording head drive information and the recording head substrate for recording on a recording medium is continuously arranged in at least one row.
The LVDS clock wiring is wired in parallel to the arrangement row of the recording head substrates and is multidrop-connected to the recording head substrate, and the corresponding LVDS data wiring is individually adapted to the multidrop-connected clock wiring length. A recording head, wherein the recording heads are wired in equal lengths.   8. The recording head according to claim 7, wherein the arrangement of the recording head substrate is a two-row staggered configuration, and the LVDS clock wiring is arranged over the entire area in a two-row staggered central line. In a recording apparatus that supplies a recording current to a plurality of recording elements based on recording head drive information and performs recording on a recording medium.
A driving circuit power supply terminal for energizing the recording current and controlling the recording current, a low voltage differential transmission (LVDS) clock input for controlling at least one system of the driving circuit, and an LVDS clock input For a printhead substrate configured with at least one synchronized LVDS data input terminal,
The recording apparatus, wherein the LVDS clock transmitted from the recording apparatus side and inputted to the recording head substrate and the LVDS data wiring are wired in equal length.

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