JP6948116B2 - Recording element substrate, recording head, and recording device - Google Patents

Description

The present invention relates to a recording element substrate, a recording head, and a recording device.

In recent years, in order to realize high-speed printing, a full-line type recording head in which a plurality of recording element substrates are arranged and has a recording width larger than that of a recording medium has become widespread. The full-line type recording head realizes a recording width larger than that of a recording medium by arranging a plurality of recording element substrates in a row or staggered pattern. The recording element substrate has a plurality of electrode pads for receiving an electric signal, and receives recording data and a driving voltage from the recording apparatus main body via, for example, a flexible substrate. In order to connect the flexible substrate and the recording device main body, it is necessary to invert and arrange the recording element substrate for each substrate.

In the transfer of recording data, the recording data is transmitted so as to correspond to the arrangement direction of the recording element substrate and the transport direction of the recording medium, based on the relative positional relationship between the recording element substrate and the recording medium. Therefore, it is necessary for the transmitting side (head control IC) to rotate the recorded data to be transmitted to the recording element substrate arranged in reverse. Since the rotation processing of the recorded data requires an extra memory in the head control IC, there is a problem that the cost increases.

For example, Patent Document 1 discloses an example of a full-line type recording head that rearranges recorded data by switching the connection relationship between the output of the shift register circuit and the input of the latch circuit in the recording element substrate. As a result, the full-line recording head does not need to change the transmission order of the recorded data, and does not require extra memory.

Japanese Unexamined Patent Publication No. 2004-82396

However, in the above-mentioned conventional example, in order to switch the connection state between the output of the shift register circuit and the input of the latch circuit, a large number of wirings are required and the area of the recording element substrate increases. For example, in the case of a recording element substrate having 2048 shift register circuits, it is necessary to route as many as 2048 wires from one end to the other of the recording element substrate, which causes a problem that the area of the recording element substrate increases. When the area of the recording element substrate is increased, the head width is increased, and the accuracy of the dot landing position is deteriorated due to the unevenness of the transport speed of the recording medium, and the image quality is deteriorated. Further, if the head width is wide, a mechanism for restraining the recording medium such as a pinch roller cannot be placed, and the recording medium comes into contact with the head surface to deteriorate the image quality.

In order to solve the above problems, the present invention has the following configuration. That is, it is a recording element substrate.
Multiple recording elements arranged side by side in a predetermined direction,
The input circuit where the recorded data is input and
A shift register circuit that holds the recorded data from the input circuit and
A latch circuit that latches the recorded data output from the shift register circuit, and
It has a drive circuit that drives the plurality of recording elements based on the recorded data latched by the latch circuit.
The shift register circuit
A plurality of flip-flops arranged corresponding to the plurality of recording elements, and
A plurality of switching units provided on the input unit side and the output unit side of each of the plurality of flip-flops, and of the two flip-flops adjacent to each other, the output unit of one flip-flop and the other flip-flop. A plurality of switching units capable of switching between the connection state between the input unit and the input unit of one of the flip-flops and the output unit of the other flip-flop based on a control signal. ,
Of the two flip-flops adjacent to each other, a wiring connecting a switching portion provided on the input portion side of the one flip-flop and a switching portion provided on the output portion side of the other flip-flop.
A wiring connecting the switching portion provided on the output portion side of the one flip-flop and the switching portion provided on the input portion side of the other flip-flop.
Includes
Based on the control signal, the input circuit may be placed on one of the switching portion on the input portion side of the flip-flop at one end and the switching portion on the input portion side of the flip-flop at the other end among the plurality of flip-flops. Enter the recorded data.

INDUSTRIAL APPLICABILITY According to the present invention, it is possible to provide a recording head having high image quality at low cost.

The schematic diagram of the full-line type recording apparatus which concerns on this invention. The figure which shows the structural example of the control circuit of the recording apparatus which concerns on this invention. The figure for demonstrating the outline of the recording head which concerns on this invention. The figure which shows the cross section of the recording head which concerns on 1st Embodiment. The figure for demonstrating the detail of the recording head which concerns on 1st Embodiment. The figure which shows the structural example of the recording element substrate which concerns on 1st Embodiment. The figure which shows the example of the circuit structure which concerns on 1st Embodiment. The figure which shows the truth table of the data expansion circuit which concerns on 1st Embodiment. The figure which shows the structural example of the data development circuit which concerns on 1st Embodiment. The figure for demonstrating the recorded data held in the latch circuit which concerns on 1st Embodiment. The figure which shows the timing chart of the recording element substrate which concerns on 1st Embodiment The figure which shows the block composition example of the recording element substrate which concerns on 2nd Embodiment. The figure which shows the example of the circuit structure which concerns on 2nd Embodiment. The figure which shows the truth table of the data expansion circuit which concerns on 2nd Embodiment. The figure which shows the structural example of the data development circuit which concerns on 2nd Embodiment. The figure which shows the example of the circuit structure of the time division drive signal processing unit which concerns on 2nd Embodiment. The figure which shows the truth table of the decoding circuit which concerns on 2nd Embodiment. The figure which shows the truth table of the time division drive signal coding circuit which concerns on 2nd Embodiment. The figure for demonstrating the recorded data held in the latch circuit which concerns on 2nd Embodiment. The figure which shows the timing chart of the recording element substrate which concerns on 2nd Embodiment. The figure for demonstrating the outline of the recording head when the shape of a recording element substrate is trapezoidal. The figure for demonstrating the detail of the recording head when the shape of a recording element substrate is trapezoidal. The figure for demonstrating the outline of the recording head when the shape of a recording element substrate is made into a parallelogram.

Hereinafter, preferred embodiments of the present invention will be described in more detail with reference to the accompanying drawings. However, the relative arrangement of the components described in this embodiment is not intended to limit the scope of the present invention to those, unless otherwise specified.

In this specification, "record" (sometimes referred to as "print") is not limited to the case of forming significant information such as characters and figures, and may be significant or involuntary. Furthermore, regardless of whether or not it is manifested so that it can be visually perceived by humans, it also refers to the case where an image, a pattern, a pattern or the like is widely formed on a recording medium, or the medium is processed.

The term "recording medium" refers not only to paper used in general recording devices, but also to a wide range of materials such as cloth, plastic film, metal plate, glass, ceramics, wood, and leather that can accept ink. Shall be.

Furthermore, "ink" (sometimes referred to as "liquid") should be broadly interpreted as in the definition of "print" above. Therefore, by being applied onto the recording medium, it is used for forming images, patterns, patterns, etc., processing the recording medium, or processing ink (for example, coagulation or insolubilization of the colorant in the ink applied to the recording medium). It shall represent a liquid that can be produced.

Furthermore, unless otherwise specified, the "recording element" shall collectively refer to the ejection port, the liquid passage communicating with the ejection port, and the element that generates energy used for ink ejection.

Furthermore, the term "nozzle" is used as a general term for the ejection port, the liquid passage communicating with the ejection port, and the element for generating energy used for ink ejection, unless otherwise specified.

The element substrate (head substrate) for a recording head used below does not indicate a mere substrate made of a silicon semiconductor, but indicates a configuration in which each element, wiring, or the like is provided.

Further, the term “on the substrate” means not only the top of the element substrate but also the surface of the element substrate and the inside side of the element substrate in the vicinity of the surface. Further, the term "build-in" as used in the present invention does not mean that each element of a separate body is simply arranged as a separate body on the surface of a substrate, but that each element is manufactured as a semiconductor circuit. It indicates that it is integrally formed and manufactured on an element plate by a process or the like.

In the inkjet recording head (hereinafter referred to as a recording head), which is the most important feature of the present invention, a plurality of recording elements and a drive circuit for driving these recording elements are mounted on the same substrate on the element substrate of the recording head. As can be seen from the description below, the recording head has a structure in which a plurality of element substrates are built in and these element substrates are cascade-connected. Therefore, this recording head can achieve a relatively long recording width. Therefore, the recording head is used not only for a serial type recording device generally found, but also for a recording device provided with a full-line recording head whose recording width corresponds to the width of a recording medium. Further, the recording head is used in a large format printer using a large size recording medium such as A0 or B0 among serial type recording devices.

Therefore, first, a recording device in which the recording head of the present invention is used will be described.

[Overview of recording device]
FIG. 1 is a perspective view for explaining the structure of a recording device 1 provided with a full-line inkjet recording head (hereinafter, recording head) 100K, 100C, 100M, 100Y and a recovery system unit for guaranteeing stable ink ejection at all times. It is a perspective view.

In the recording device 1, the recording paper 15 is supplied from the feeder unit 17 to the printing position by these recording heads, and is conveyed by the transfer unit 16 provided in the housing 18 of the recording device.

The image is printed on the recording paper 15 from the recording head 100K when the reference position of the recording paper 15 reaches below the recording head 100K that ejects the black (K) ink while conveying the recording paper 15. Is discharged. Similarly, the recording paper 15 reaches each reference position in the order of the recording head 100C for ejecting cyan (C) ink, the recording head 100M for ejecting magenta (M) ink, and the recording head 100Y for ejecting yellow (Y) ink. Then, the ink of each color is ejected to form a color image. The recording paper 15 on which the image is printed in this way is discharged to the stacker tray 20 and deposited.

The recording device 1 further includes an ink cartridge (not shown) that can be replaced for each ink for supplying ink to the transport unit 16, the recording heads 100K, 100C, 100M, and 100Y. Further, it has a pump unit (not shown) for supplying ink to the recording head 100 and a recovery operation, a control board (not shown) for controlling the entire recording device 1, and the like. The front door 19 is an opening / closing door for replacing the ink cartridge.

[Control configuration]
Next, a control configuration for executing the recording control of the recording device described with reference to FIG. 1 will be described.

FIG. 2 is a block diagram showing a configuration of a control circuit of a recording device. In FIG. 2, the controller 30 includes an MPU 31, a ROM 32, a gate array (GA) 33, and a DRAM 34. The interface 40 is an interface for inputting recorded data. The ROM 32 is a non-volatile storage area and stores a control program executed by the MPU 31. The DRAM 34 is a DRAM that stores data such as recording data and a recording signal supplied to the recording head 100. The gate array 33 is a gate array that controls the supply of recording signals to the recording head 100, and also controls data transfer between the interface 40, the MPU 31, and the DRAM 34. The carriage motor 90 is a motor for conveying the recording head 100 (100K, 100C, 100M, 100Y). The transport motor 70 is a motor for transporting recording paper. The head driver 50 drives the recording head 100. The motor drivers 60 and 80 are motor drivers for driving the transport motor 70 and the carriage motor 90, respectively.

In a recording device having a configuration using a full-line recording head as shown in FIG. 1, there is no carriage motor 90 or a motor driver 80 for driving the motor. For this reason, parentheses are added in FIG.

Explaining the operation of the control configuration, when the recorded data enters the interface 40, the recorded data is converted into a recording signal for recording between the gate array 33 and the MPU 31. Then, the motor drivers 60 and 80 are driven, and the recording head 100 is driven according to the recording data sent to the head driver 50 to perform recording.

<First Embodiment>
[Recording head configuration]
FIG. 3 is a diagram showing an outline of the recording head 100 according to the first embodiment of the present invention. In the case of the example shown in FIG. 3, the lateral direction of the recording head 100 is the transport direction of a recording medium such as paper. FIG. 4 is a diagram showing a cross section of the broken line AA'section of FIG. A plurality of recording element substrates 101 are arranged on the support substrate 103. Each of the recording element substrates 101 has an electrode pad 104, and is connected to the flexible substrate 102 by wire bonding 201. The flexible board 102 is also connected to the connector 202 arranged on the head control board 204. The recorded data is transferred from the head control IC 203 to the recording element substrate 101 via the flexible substrate 102. Further, a drive power supply VH for driving the recording element is supplied to each of the recording element substrates 101 from a power supply circuit (not shown) on the head control substrate 204 via the flexible substrate 102. This drive power supply VH requires a large current on the order of A (ampere) in order to perform high-speed recording operation, and needs to supply the large current via the flexible substrate 102.

The recording head 100 shown in FIG. 3 has two rows of recording element substrate rows (first recording element substrate row 105 and second recording element substrate row 106). A plurality of recording element substrates are arranged side by side in each recording element substrate row. The recording element substrate 101 included in the second recording element substrate row 106 is arranged so as to be reversed from the arrangement of the first recording element substrate row 105 in order to connect the flexible substrate 102 to the head control substrate 204. .. With such a configuration, the width W of the flexible substrate 102 can be increased. As a result, the drive power supply wiring width can be increased, so that a large current on the order of A (ampere) can be supplied to each recording element substrate. In the present embodiment, as shown in FIG. 3, each recording element substrate is arranged in a staggered arrangement in the recording head 100. Further, each recording element substrate is arranged so that a part of the end portion of the recording element substrate overlaps in the lateral direction as shown in FIG. 3 in consideration of the position of the nozzle.

FIG. 5 is an enlarged view of the broken line portion B of FIG. FIG. 5 shows an example of a recording element substrate 101 in which nozzles 301 are arranged in four rows. Each of the recording element boards 101 has a control pad 303, and a control signal CONT is supplied from the head control board 204 via the control signal wiring 302 on the flexible board 102. The control signal CONT is a signal for controlling whether or not to rotate the recorded data in the recording element substrate 101. When the control signal CONT is at the High level, the rotation processing of the recorded data is performed, and when the control signal CONT is at the Low level, the rotation processing is not performed. That is, the value of the control signal CONT is set according to the orientation of the recording element substrate. The rotation process here is arranged in a predetermined order so as to correspond to the arrangement direction of the recording element substrate and the transport direction of the recording medium based on the relative positional relationship between the recording element substrate and the recording medium. It is to control the arrangement of recorded data. That is, when the recording operation is performed using the recorded data, it is controlled whether the arrangement of the recorded data is in a predetermined order or in the reverse order of the predetermined order according to the arrangement of the recording element substrate that outputs the data. ..

The control signal CONT of the recording element substrate 101 arranged in the first recording element substrate row 105 is at the Low level. Therefore, on the first recording element substrate row 105 side, the rotation processing of the recorded data is not performed, and the recorded data is handled in the order in which they were input. On the other hand, the control signal CONT of the recording element substrate 101 invertedly arranged in the second recording element substrate row 106 is at the High level. Therefore, on the second recording element substrate row 106 side, the rotation processing of the recorded data is performed, and the recorded data is handled in the reverse order from the order in which they were input.

FIG. 6 shows a configuration example of the recording element substrate 101 according to the first embodiment. In the recording element substrate 101, a shift register circuit 401, a latch circuit 402, and a drive circuit 405 are provided corresponding to the nozzle 301. Since the nozzles 301 are arranged in four rows as shown in FIG. 5, the shift register circuit 401, the latch circuit 402, and the drive circuit 405 are provided in four rows (rows A to D), respectively. Be done. Further, the shift register circuit 401 and the latch circuit 402 show an example in which 512 are arranged in one row. Further, the recording element substrate 101 has a plurality of recording data input pads 404 in the electrode pads 104. Here, it is assumed that the recording data input pads 404 are also four (DATA1, DATA2, DATA3, DATA4) corresponding to the four rows of nozzles 301. The recorded data is serially input from the recorded data input pads 404 (DATA1, DATA2, DATA3, DATA4) and supplied to the shift register circuit 401 of each column via the data expansion circuit 403. The data expansion circuit 403 functions as an input circuit that receives input of recorded data from the outside and outputs it to the shift register circuit 401. The data expansion circuit 403 expands the serially input recorded data into the data wiring connected to the input unit of the shift register circuit 401 of each column according to the control signal CONT. Here, as data wiring, DATA_AL, DATA_BL, DATA_CL, DATA_DL, DATA_AR, DATA_BR, DATA_CR, and DATA_DR are provided. The details of the operation related to the expansion of the data expansion circuit 403 will be described later. The control signal CONT is input to the data development circuit 403 from the control pad 303. Further, the control signal CONT is also supplied from the control pad 303 to each of the shift register circuits 401.

FIG. 11 shows a timing chart of the recording element substrate 101 of this embodiment. As shown in FIG. 11A, when the control signal CONT is at the Low level, the data expansion circuit 403 connects the inputs (DATA1, DATA2, DATA3, DATA4) from the recording data input pad 404 to the data wiring DATA_AL, DATA_BL, respectively. Output to DATA_CL and DATA_DL. The shift register circuit 401 shifts the recorded data input from the data expansion circuit 403 via the data wiring DATA_AL, DATA_BL, DATA_CL, and DATA_DL in the direction from S512 to S1 (left shift). On the other hand, as shown in FIG. 11B, when the control signal CONT is at the high level, the data expansion circuit 403 connects the inputs (DATA1, DATA2, DATA3, DATA4) from the recording data input pad 404 to the data wiring DATA_AR, respectively. Output to DATA_BR, DATA_CR, DATA_DR. The shift register circuit 401 shifts the recorded data input from the data expansion circuit 403 via the data wiring DATA_AR, DATA_BR, DATA_CR, and DATA_DR in the direction of S1 to S512 (right shift).

FIG. 7 shows an example of a detailed circuit configuration of the shift register circuit 401, the latch circuit 402, and the drive circuit 405 of the recording element substrate 101 according to the present embodiment. The recorded data is input to the shift register circuit 401 from the terminal IN_L or the terminal IN_R. The shift register circuit 401 shifts the recorded data in synchronization with the clock signal (CLK). Further, the latch circuit 402 holds the recorded data input from the shift register circuit 401 in synchronization with the latch signal (LT). The latch circuit 402 takes the logical product of the recorded data held in the latch circuit 402 by the AND gate 503 and the heat enable signal HE, and transfers the result to the gate of the transistor 502. When the logical product is high level, the transistor 502 is turned on and the heat generating resistor 501 is driven. On the other hand, when the logical product is at the Low level, the transistor 502 is turned off and the heat generating resistor 501 does not operate.

The shift register circuit 401 in the first embodiment controls the shift direction of the recorded data by switching the connection state between the output of the flip-flop in the previous stage and the input of the flip-flop in the next stage by the switching means 504. The switching means 504 is switched according to the control signal CONT. FIG. 7A is a diagram showing a connection state when the control signal CONT is at the Low level. The recorded data input from the terminal IN_L is transferred in the order of flip-flops S512, S511, S510, ..., S2, S1 (left shift). FIG. 7B is a diagram showing a connection state when the control signal CONT is at the High level. The recorded data input from the terminal IN_R is transferred in the order of flip-flops S1, S2, ..., S510, S511, S512 (right shift). By switching the connection state between the output of the flip-flop in the previous stage and the input of the flip-flop in the next stage as described above, the transfer direction of the recorded data can be controlled by adding only two wires per row. Is possible.

[Data expansion circuit]
Next, the operation of the data expansion circuit 403 according to the present embodiment will be described. The data expansion circuit 403 controls the expansion method of the recorded data according to the control signal CONT. FIG. 8 shows a truth table of the data expansion circuit 403. FIG. 9 shows a configuration example of the data expansion circuit 403 according to the present embodiment. By switching the output of the flip-flop 702 and the connection state between the data wirings DATA_AR to DATA_DR and DATA_AL to DATA_DL by the switching means 701, the method of expanding the recorded data is controlled. That is, the data expansion circuit 403 switches the output destination (data wiring) of the input recorded data according to the control signal CONT. Further, the switching means 701 is switched according to the control signal CONT.

FIG. 9A is a diagram showing a connection state of the data expansion circuit 403 when the control signal CONT is at the Low level. The recorded data input from DATA1 is output to DATA_AL via the flip-flop 702. Similarly, the recorded data input from DATA2 is output to DATA_BL, the recorded data input from DATA3 is output to DATA_CL, and the recorded data input from DATA4 is output to DATA_DL. At this time, the output from DATA_AR to DATA_DR is not performed.

FIG. 9B is a diagram showing a connection state of the data expansion circuit 403 when the control signal CONT is at the High level. The recorded data input from DATA1 is output to DATA_DR via the flip-flop 702. Similarly, the recorded data input from DATA2 is output to DATA_CR, the recorded data input from DATA3 is output to DATA_BR, and the recorded data input from DATA4 is output to DATA_AR. At this time, the output from DATA_AL to DATA_DL is not performed.

By controlling the transfer direction of the recorded data by the shift register circuit 401 and controlling the data expansion method of the data expansion circuit 403, the recording element substrate 101 according to the present embodiment can rotate the recorded data according to its arrangement. It becomes.

FIG. 10A shows the recorded data held in the latch circuit 402 of each row (rows A to D) when the control signal CONT is at the Low level. FIG. 10B shows the recorded data held in the latch circuit 402 of each row (rows A to D) when the control signal CONT is at the high level. Comparing FIG. 10A and FIG. 10B, it can be confirmed that the recorded data is rotated and held in the latch circuit 402 of each row. Specifically, when the control signal CONT = Low, the recorded data D1_1 is held in L1 of the latch circuit A row, and the recorded data D4_512 is held in L512 of the latch circuit D row. On the other hand, when the control signal CONT = High, the recorded data D4_512 is held in L1 of the latch circuit A row, and the recorded data D1-1-1 is held in L512 of the latch circuit D row.

As described above, the recording element substrate 101 according to the present embodiment can control the data shift direction of the shift register circuit 401 and the data expansion method of the data expansion circuit 403 without increasing the area of the recording element substrate. Rotation processing can be performed. This makes it possible to provide a low-cost, high-quality, full-line recording head.

<Second embodiment>
A second embodiment of the present invention will be described. The recording element substrate 101 according to the second embodiment is a recording element substrate that performs time-division driving, and is configured to realize rotation processing of recorded data by using the recording element substrate 101. The description of the configuration overlapping with the configuration described in the first embodiment will be omitted.

FIG. 12 shows a configuration example of the recording element substrate 101 according to the second embodiment of the present invention. In the recording element substrate 101, a shift register circuit 1001, a latch circuit 1002, a drive circuit 1005, and a time division drive signal processing unit 1006 are provided corresponding to the nozzle 301. In FIG. 12, the nozzles 301 are arranged in four rows as shown in FIG. 5, and the shift register circuit 1001, the latch circuit 1002, the drive circuit 1005, and the time-division drive signal processing unit 1006 correspond to each of the nozzles 301. It is provided in 4 rows (rows A to D). Further, 32 shift register circuits 1001 and 32 latch circuits 1002 are arranged in one row. Further, the recording element substrate 101 has a plurality of recording data input pads 404 in the electrode pads 104. Further, in the present embodiment, the number of time divisions is 16, and 512 drive circuits per row are formed by a matrix of 32 bits of recorded data held in the latch circuit 1002 of each row and 16 bits of time division drive signals 1007. A configuration example capable of driving 1005 is shown.

The recorded data and the time-division drive signal are serially input from the recorded data input pads 404 (DATA1, DATA2, DATA3, DATA4) and supplied to the shift register circuit 1001 of each column via the data expansion circuit 1003. The data expansion circuit 1003 expands the serially input recorded data into the data wiring DATA_AL, DATA_BL, DATA_CL, DATA_DL, DATA_AR, DATA_BR, DATA_CR, and DATA_DR according to the control signal CONT. Further, the data expansion circuit 1003 expands the serially input time division drive signal into the wirings BE_D, BE_C, BE_B, and BE_A according to the control signal CONT. The control signal CONT is input to the data development circuit 1003 from the control pad 303. Further, the control signal CONT is also supplied from the control pad 303 to the shift register circuit 1001 and the time division drive signal processing unit 1006, respectively.

FIG. 20 shows a timing chart of the recording element substrate 101 of this embodiment. FIG. 20A shows a case where the control signal CONT is at the Low level. Further, FIG. 20B shows a case where the control signal CONT is at a high level. In addition to the clock signal (CLK), the clock signal for recording data (CLK_D) used in the shift register circuit 1001 and the clock signal (CLE_BE) for the time division signal used in the time division drive signal processing unit 1006. ) Is shown and explained.

FIG. 13 shows an example of a detailed circuit configuration of the shift register circuit 1001, the latch circuit 1002, and the drive circuit 1005 of the recording element substrate 101 according to the second embodiment. The shift register circuit 1001 shifts the recorded data in synchronization with the clock signal (CLK_D). Further, the latch circuit 1002 holds the recorded data input from the shift register circuit 1001 in synchronization with the latch signal (LT). The shift register circuit 1001 controls the transfer direction of the recorded data according to the control signal CONT, as in the first embodiment. The AND gate 503 takes the logical product of the recorded data held by the latch circuit 1002, the time-division drive signal 1007, and the heat enable signal HE, and transfers the result to the gate of the transistor 502. When the logical product is high level, the transistor 502 is turned on and the heat generating resistor 501 is driven. On the other hand, when the logical product is at the Low level, the transistor 502 is turned off and the heat generating resistor 501 does not operate.

The shift register circuit 1001 in the second embodiment switches the connection state between the output of the flip-flop in the previous stage and the input of the flip-flop in the next stage by the switching means 504. The switching means 504 is switched according to the control signal CONT.

[Data expansion circuit]
Next, the operation of the data expansion circuit 1003 according to the second embodiment will be described. The data expansion circuit 1003 controls the expansion method of the recorded data according to the control signal CONT. FIG. 14 shows a truth table of the data expansion circuit 1003 according to the second embodiment. FIG. 15 shows a detailed configuration example of the data expansion circuit 1003 of the invention according to the present embodiment. By switching the output of the flip-flop 702 and the connection state of the data wirings DATA_AR to DATA_DR, DATA_AL to DATA_DL, and BE_D to BE_A by the switching means 701, the development method of the recorded data and the time division drive signal is controlled. In the present embodiment, the switching means 701 is switched according to the control signal CONT.

FIG. 15A is a diagram showing a connection state of the data expansion circuit 1003 when the control signal CONT is at the Low level. The time division drive signal input from DATA1 is output to BE_A via the flip-flop 702. Similarly, the time-division drive signal input from DATA2 is output to BE_B, the time-division drive signal input from DATA3 is output to BE_C, and the time-division drive signal input from DATA4 is output to BE_D. Further, the recorded data input from DATA1 is output to DATA_AL via the flip-flop 702. Similarly, the recorded data input from DATA2 is output to DATA_BL, the recorded data input from DATA3 is output to DATA_CL, and the recorded data input from DATA4 is output to DATA_DL. At this time, the output from DATA_AR to DATA_DR is not performed.

FIG. 15B is a diagram showing a connection state of the data development circuit 1003 when the control signal CONT is at the High level. The time division drive signal input from DATA1 is output to BE_D via the flip-flop 702. Similarly, the time-division drive signal input from DATA2 is output to BE_C, the time-division drive signal input from DATA3 is output to BE_B, and the time-division drive signal input from DATA4 is output to BE_A. Further, the recorded data input from DATA1 is output to DATA_DR via the flip-flop 702. Similarly, the recorded data input from DATA2 is output to DATA_CR, the recorded data input from DATA3 is output to DATA_BR, and the recorded data input from DATA4 is output to DATA_AR. At this time, the output from DATA_AL to DATA_DL is not performed.

[Time division drive signal processing unit]
FIG. 16 shows an example of a detailed circuit configuration of the time division drive signal processing unit 1006. The time-division drive signal processing unit 1006 includes a shift register circuit 1404, a latch circuit 1403, a decoding circuit 1402, and a time-division drive signal coding circuit 1401. The shift register circuit 1404 shifts the time division signals (BE_A to BE_D) in synchronization with the clock signal (CLK_BE). Further, the latch circuit 1403 holds a time division signal input from the shift register circuit 1404 in synchronization with the latch signal (LT). The time-division drive signal coding circuit 1401 converts the 4-bit time-division drive signals BE_1 to BE_4 held in the latch circuit 1403 into 4-bit time-division drive signals xBE_1 to xBE_4 according to the control signal CONT. The decoding circuit 1402 decodes the 4-bit time-division drive signals xBE1 to xBE4 into 16-bit time-division drive signals BLE0 to BLE15. FIG. 17 shows a truth table of the decoding circuit 1402. Based on FIG. 17, the decoding circuit 1402 converts the input 4-bit time-division drive signals xBE1 to xBE4 into the values of the output 16-bit time-division drive signals BLE0 to BLE15.

FIG. 18 shows a truth table of the time division drive signal coding circuit 1401. Based on FIG. 18, the time-division drive signal coding circuit 1401 converts the input 4-bit time-division drive signals BE_1 to BE_4 into the values of the output 4-bit time-division drive signals xBE_1 to xBE_4. Specifically, when the control signal CONT is at the Low level, the values of BE1 to BE4 are output as they are as the values of xBE1 to xBE4 without being encoded. On the other hand, when the control signal CONT is at High level, the logic of BE1 to BE4 is inverted and output as xBE1 to xBE4. For example, when BE1 to BE4 are all 0 and the control signal CONT is at the Low level, xBE1 to xBE4 are all 0. As a result, the time-division drive signal BLE0 after decoding becomes the High level (1), and BLE1 to BLE15 become the Low level (0). When BE1 to BE4 are all 0 and the control signal CONT is high level, xBE1 to xBE4 are all 1. As a result, the time-division drive signal BLE15 after decoding becomes the High level (1), and BLE0 to BLE14 become the Low level (0).

By controlling the transfer direction of the recorded data by the shift register circuit 1001 described above and encoding the time-divided drive signal of the time-divided drive signal coding circuit 1401, the recording element substrate 101 according to the present embodiment rotates the recorded data. Is possible.

FIG. 19A shows the recorded data held in the latch circuit 1002 of each row (rows A to D) when the control signal CONT is at the Low level. FIG. 19B shows the recorded data held in the latch circuit 1002 of each row (rows A to D) when the control signal CONT is at the high level. Comparing FIG. 19A and FIG. 19B, it can be confirmed that the recorded data is rotated and held in the latch circuit 1002 of each row.

As described above, the recording element substrate 101 according to the present embodiment can rotate the recorded data without increasing the area of the recording element substrate by the configuration different from that of the first embodiment. This makes it possible to provide a low-cost, high-quality, full-line recording head.

<Third embodiment>
In the first and second embodiments, the description has been made using the configuration of a recording head made of a recording element substrate having a rectangular shape as shown in FIG. As a third embodiment according to the present invention, a configuration example of another recording head will be described with reference to FIGS. 21 to 23.

FIG. 21 is a configuration example in which the shape of the recording element substrate 101 is changed to a trapezoid, the distance from the nozzle of the adjacent recording element substrate 101 is shortened, and the nozzles can be arranged without a gap. With this configuration, it is possible to reduce the length of the recording element substrate row in the transport direction (short direction) of the recording medium. FIG. 22 is an enlarged view of the broken line portion B of FIG. Since the contents are the same as those described with reference to FIGS. 3 and 5 except for the shape of the recording element substrate 101, the details will be omitted.

FIG. 23 is a configuration example in which the shape of the recording element substrate 101 is changed to a parallelogram and a plurality of them are arranged. In the configuration of FIG. 23, the recording element substrates 101 are arranged in one row with their orientations reversed alternately. In this configuration, the row of recording element substrates is one row, unlike the configuration of FIG. Further, as shown in FIG. 23, by changing the shape of the flexible substrate 102 as the shape of the recording element substrate 101 is changed, the width W of the flexible substrate 102 is maintained thick as in the configuration of FIG. be able to. As a result, the drive power supply wiring width can be increased, so that a large current on the order of A (ampere) can be supplied to each recording element substrate.

As described above, by applying the configurations of the first and second embodiments using the shape of the recording element substrate described above, in addition to the effects of the first and second embodiments, a more compact recording head can be configured. Can be done.

In the above embodiment, a full-line type recording device has been described as an example. However, the recording head having the arrangement of the recording element substrate as described above is not limited to the full-line type recording device, and may be applied to a scanning type recording device using a carriage.

100 ... Recording head, 101 ... Recording element board, 102 ... Flexible board, 103 ... Support board, 104 ... Electrode pad, 204 ... Head control board, 301 ... Nozzle, 401 ... Shift register circuit, 402 ... Latch circuit, 403 ... Data Deployment circuit, 405 ... Drive circuit

Claims (10)

It is a recording element substrate,
Multiple recording elements arranged side by side in a predetermined direction,
The input circuit where the recorded data is input and
A shift register circuit that holds the recorded data from the input circuit and
A latch circuit that latches the recorded data output from the shift register circuit, and
It has a drive circuit that drives the plurality of recording elements based on the recorded data latched by the latch circuit.
The shift register circuit
A plurality of flip-flops arranged corresponding to the plurality of recording elements, and
A plurality of switching units provided on the input unit side and the output unit side of each of the plurality of flip-flops, and of the two flip-flops adjacent to each other, the output unit of one flip-flop and the other flip-flop. A plurality of switching units capable of switching between the connection state between the input unit and the input unit of one of the flip-flops and the output unit of the other flip-flop based on a control signal. ,
Of the two flip-flops adjacent to each other, a wiring connecting a switching portion provided on the input portion side of the one flip-flop and a switching portion provided on the output portion side of the other flip-flop.
A wiring connecting the switching portion provided on the output portion side of the one flip-flop and the switching portion provided on the input portion side of the other flip-flop.
Includes
Based on the control signal, the input circuit may be placed on one of the switching portion on the input portion side of the flip-flop at one end and the switching portion on the input portion side of the flip-flop at the other end among the plurality of flip-flops. A recording element substrate characterized in that recording data is input. The shift register circuit
A wiring connecting the switching portion provided on the input portion side of the flip-flop at the other end and the switching portion provided on the output portion side of the flip-flop next to the switching portion.
A wiring connecting the switching portion provided on the output portion side of the flip-flop at the other end and the switching portion provided on the input portion side of the flip-flop next to the switching portion.
The recording element substrate according to claim 1, further comprising. The shift register circuit
A wiring connecting the switching portion provided on the output portion side of the flip-flop at one end and the switching portion provided on the input portion side of the flip-flop next to the switching portion.
A wiring connecting the switching portion provided on the input portion side of the flip-flop at one end and the switching portion provided on the output portion side of the flip-flop next to the switching portion.
The recording element substrate according to claim 1, further comprising. The first pad to which the control signal is input and
The recording element substrate according to any one of claims 1 to 3 , further comprising a second pad into which the recording data is input. A recording head including the recording element substrate according to any one of claims 1 to 4.
A plurality of the recording element substrates are arranged in the first row and the second row, respectively.
A recording head characterized in that the plurality of recording element substrates arranged in the second row are arranged in reverse with respect to the plurality of recording element substrates arranged in the first row. The recording head according to claim 5 , wherein the first row and the plurality of recording element substrates arranged in the second row are arranged in a staggered arrangement. A recording head including the recording element substrate according to any one of claims 1 to 4.
Multiple recording element substrates are arranged in a row,
A recording head characterized in that the plurality of recording element substrates are alternately arranged in opposite directions. The recording head according to any one of claims 5 to 7 , wherein the control signal is set according to the orientation of the recording element substrate. The recording head according to any one of claims 5 to 8 , wherein the recording head is a full-line type recording head. A recording device including one or more recording heads according to any one of claims 5 to 9.

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