JP2013105978A - High-frequency semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a high-frequency semiconductor device that allows increasing an inductance value without lengthening the length of bonding wires.SOLUTION: A high-frequency semiconductor device 1 includes a semiconductor chip 24 of a multi-cell configuration, a matching circuit, and a plurality of bonding wires 12 and 14 connected in parallel between the semiconductor chip 24 and the matching circuit. The plurality of bonding wires 12 and 14 have a predetermined angle lower than or equal to 90° on a plane with respect to the semiconductor chip 24.

Description

  Embodiments described herein relate generally to a high-frequency semiconductor device.

  In a conventional high-frequency semiconductor device, active elements arranged in parallel are connected to a common input matching circuit via an input bonding wire, and are connected to a common output matching circuit via an output bonding wire.

  In the discrete semiconductor of the microwave band, the inductance of the bonding wire connecting the semiconductor chip and the circuit board is a part of the components of the matching circuit, and when a large inductance is required, the bonding wire is lengthened.

Japanese Patent Laid-Open No. 02-154501

  When the wire becomes long, it becomes difficult to dissipate heat, the current capacity decreases, and the circuit configuration increases.

  The present embodiment provides a high frequency semiconductor device capable of increasing the inductance value without increasing the length of the bonding wire.

  The high-frequency semiconductor device according to the present embodiment includes a multi-cell semiconductor chip, a matching circuit, and a plurality of bonding wires connected in parallel between the semiconductor chip and the matching circuit. The plurality of bonding wires have a predetermined angle of 90 ° or less on the plane with respect to the semiconductor chip.

The typical plane pattern block diagram of the high frequency semiconductor device which concerns on 1st Embodiment. The typical plane pattern block diagram of the high frequency semiconductor device which concerns on a comparative example. The typical plane pattern block diagram of the high frequency semiconductor device which concerns on the modification 1 of 1st Embodiment. The typical plane pattern block diagram of the high frequency semiconductor device which concerns on the modification 2 of 1st Embodiment. It is a typical bird's-eye view of a package which stores a high frequency semiconductor device concerning modification 1 or modification 2 of a 1st embodiment, and (a) metal cap 10, (b) metal seal ring 10a, (c) metal Schematic configuration diagram of strip lines 19a and 19b arranged on the wall 16, (d) the conductor base plate 200, the feedthrough lower layer 20, the feedthrough upper layer 22 and the feedthrough lower layer 20. FIG. 5 is a schematic cross-sectional configuration diagram of the high-frequency semiconductor device according to the first embodiment and Modification 1 or Modification 2 thereof, taken along line II in FIGS. 1 and 3 to 4. The enlarged view of the typical plane pattern structure of the semiconductor chip which comprises the high frequency semiconductor device which concerns on a comparative example. (A) The enlarged view of the typical plane pattern structure of the semiconductor chip which comprises the high frequency semiconductor device which concerns on 1st Embodiment, (b) The enlarged view of J part of Fig.8 (a). It is a structural example of the semiconductor chip mounted in the high frequency semiconductor device which concerns on 1st Embodiment, Comprising: The typical cross-section figure which follows the II-II line | wire of FIG.8 (b). The schematic diagram explaining a mode that wire bonding was implemented to the drain connection terminal on the semiconductor chip which comprises the high frequency semiconductor device which concerns on a comparative example. The schematic diagram explaining a mode that wire bonding was implemented to the drain connection terminal on the semiconductor chip which comprises the high frequency semiconductor device which concerns on 1st Embodiment. The enlarged schematic diagram explaining a mode that wire bonding was implemented to the drain connection terminal on the semiconductor chip which comprises the high frequency semiconductor device which concerns on a comparative example. The schematic diagram explaining a mode that the wire bonding was implemented to the gate connection terminal on the semiconductor chip which comprises the high frequency semiconductor device which concerns on a comparative example. The schematic diagram explaining a mode that the wire bonding was implemented to the gate connection terminal on the semiconductor chip which comprises the high frequency semiconductor device which concerns on 1st Embodiment. (A) On the semiconductor chip constituting the high-frequency semiconductor device according to the first embodiment, the inductance between terminals bonded by bonding eight bonding wires having a length of 1 mm in parallel and with an interval between the wire ends of 0.2 mm. (B) shows a state in which eight bonding wires W11, W21, W31,..., W81 are bonded in parallel at the wiring angle θ to the drain terminal electrode D1. Pattern diagram. On the semiconductor chip constituting the high-frequency semiconductor device according to the first embodiment, a plurality of bonding wires are connected in parallel to the drain terminal electrode D1, and the wire end interval DE and the wire are bonded at a wiring angle θ. The space | interval DW of this and the figure which shows wiring angle (theta). The typical plane pattern block diagram of the high frequency semiconductor device which concerns on 2nd Embodiment. The typical plane pattern block diagram of the high frequency semiconductor device which concerns on the modification 1 of 2nd Embodiment. The typical plane pattern block diagram of the high frequency semiconductor device which concerns on the modification 2 of 2nd Embodiment. The typical plane pattern block diagram of the high frequency semiconductor device which concerns on the modification 3 of 2nd Embodiment. The typical cross-section figure which follows the III-III line of FIG. The typical cross-section figure which follows the IV-IV line of FIG. FIG. 21 is a schematic sectional view taken along line VV in FIG. 20. FIG. 21 is a schematic cross-sectional structure diagram taken along line VI-VI in FIG. 20. It is a typical bird's-eye view of the package which accommodates the high frequency semiconductor device concerning modification 3 of a 2nd embodiment, and (a) metal cap 10, (b) metal seal ring 10a, (c) metal wall 16, ( d) A schematic configuration diagram of the strip lines 19a and 19b disposed on the conductor base plate 200, the feedthrough lower layer 20, the feedthrough upper layer 22, and the feedthrough lower layer 20. The typical plane pattern block diagram of the high frequency semiconductor device which concerns on 3rd Embodiment. The typical plane pattern block diagram of the high frequency semiconductor device which concerns on the modification 1 of 3rd Embodiment. The typical plane pattern block diagram of the high frequency semiconductor device which concerns on the modification 2 of 3rd Embodiment.

  Next, embodiments will be described with reference to the drawings. In the following, the same elements are denoted by the same reference numerals to avoid duplication of explanation and to simplify the explanation. It should be noted that the drawings are schematic and different from the actual ones. Moreover, it is a matter of course that portions having different dimensional relationships and ratios are included between the drawings.

  The embodiment described below exemplifies an apparatus and a method for embodying the technical idea, and the embodiment does not specify the arrangement of each component as described below. This embodiment can be modified in various ways within the scope of the claims.

[First embodiment]
(High-frequency semiconductor device)
A schematic planar pattern configuration of the high-frequency semiconductor device 1 according to the first embodiment is expressed as shown in FIG. 1 is a schematic cross-sectional configuration of the high-frequency semiconductor device 1 according to the first embodiment, and a schematic cross-sectional structure taken along line II in FIG. 1 is expressed as shown in FIG.

  As shown in FIGS. 1 and 6, the high-frequency semiconductor device 1 according to the first embodiment includes a multi-cell semiconductor chip 24, an input distribution matching circuit 17, an output synthesis matching circuit 18, a semiconductor chip 24, and an input. A plurality of bonding wires 12 and 14 connected in parallel between the distribution matching circuit 17 and the output synthesis matching circuit 18 are provided. Here, the plurality of bonding wires 12 and 14 have a predetermined angle of 90 ° or less on the plane with respect to the semiconductor chip 24.

  In the high-frequency semiconductor device 1 according to the first embodiment, each cell of the semiconductor chip 24 includes a drain terminal electrode, and the drain terminal electrode includes a parallelogram parallel to the plurality of output bonding wires 14. May be.

  In the high-frequency semiconductor device 1 according to the first embodiment, each cell of the semiconductor chip 24 includes a gate terminal electrode, and the gate terminal electrode includes a parallelogram parallel to the plurality of input bonding wires 12. May be.

(Comparative example)
On the other hand, a schematic planar pattern configuration of the high-frequency semiconductor device 1a according to the comparative example is expressed as shown in FIG. In the high-frequency semiconductor device 1a according to the comparative example, as shown in FIG. 2, between the semiconductor chip 24 and the input distribution matching circuit 17 and the output synthesis matching circuit 18, each cell of the semiconductor chip 24 arranged in parallel is connected. They are connected via an input bonding wire 12 and an output bonding wire 14 connected at right angles. Further, also in the high-frequency semiconductor device 1a according to the comparative example, the schematic cross-sectional structure taken along the line I-I in FIG. Other configurations are the same as those in FIG.

  In the high-frequency semiconductor device 1 according to the first embodiment, a plurality of bonding wires 12 and 14 that are connected at right angles to the semiconductor chip 24 are connected to the semiconductor chip 24 at a predetermined angle. By doing so, the distance between the plurality of bonding wires is reduced, and the mutual inductance value can be increased. As a result, the inductance value can be increased without increasing the length of the bonding wire.

  More specifically, as shown in FIGS. 1 and 6, the high-frequency semiconductor device 1 according to the embodiment includes a conductor base plate 200, a multi-cell semiconductor chip 24 disposed on the conductor base plate 200, and the semiconductor chip 24. An internal metal wall 16 disposed on the conductor base plate 200, and an input distribution matching circuit 17 and an output synthesis matching circuit 18 disposed adjacent to the semiconductor chip 24 on the conductor base plate 200 surrounded by the metal wall 16. The semiconductor chip 24 includes a plurality of input bonding wires 12 and a plurality of output bonding wires 14 that connect the input distribution matching circuit 17 and the output synthesis matching circuit 18, and the input bonding wires 12 and the output bonding wires 14 are semiconductors. A predetermined angle of 90 ° or less on the plane with respect to the chip 24 Having.

  In addition, as shown in FIGS. 1 and 6, the high-frequency semiconductor device 1 according to the first embodiment is fitted into the through hole 34 provided in the input / output portion of the metal wall 16, and the through hole 34. Feedthrough lower layer 20 disposed on conductor base plate 200, feedthrough upper layer 22 fitted in through hole 34 and disposed on feedthrough lower layer 20, feedthrough lower layer 20 and feedthrough upper layer 22, the input strip line 19a and the output strip line 19b disposed between the input strip line 19a and the input terminal electrode 21a and the output terminal electrode 21b disposed on the output strip line strip line 19b, respectively. good.

  The high-frequency semiconductor device 1 according to the first embodiment includes an input circuit board 26 and an output circuit board 28 disposed adjacent to the semiconductor chip 24 on the conductor base plate 200 surrounded by the metal wall 16. The input distribution matching circuit 17 is disposed on the input circuit board 26 and connected to the input strip line 19a, and the output synthesis matching circuit 18 is disposed on the output circuit board 28 and connected to the output strip line 19b. good.

  Further, as shown in FIGS. 1 and 6, the high-frequency semiconductor device 1 according to the embodiment includes a metal seal ring 10a disposed on the metal wall 16 and a metal cap 10 disposed on the metal seal ring 10a. May be provided.

  The conductor base plate 200 of the high-frequency semiconductor device 1 according to the embodiment is formed of a conductive metal such as molybdenum or a copper molybdenum alloy, for example. Furthermore, a plated conductor such as Au, Ni, Ag, Ag—Pt alloy, or Ag—Pd alloy may be formed on the surface of the conductor base plate 200.

  The package outer wall can be formed of metal or ceramic. In the case of the metal wall 16, for example, the metal wall 16 is formed of a conductive metal such as aluminum, molybdenum, or copper molybdenum alloy.

  A solder metal layer (not shown) for soldering is formed on the upper surface of the metal wall 16 via a metal seal ring 10a. The solder metal layer can be formed from, for example, a gold germanium alloy, a gold tin alloy, or the like.

  In the high-frequency semiconductor device 1 according to the embodiment, the metal wall 16 is disposed on the conductor base plate 200 via an insulating or conductive adhesive. The insulating adhesive can be formed from, for example, an epoxy resin or glass, and the conductive adhesive can be formed from, for example, a gold germanium alloy or a gold-tin alloy.

  The metal cap 10 has a flat plate shape. The metal cap 10 is formed of, for example, a conductive metal such as aluminum, molybdenum, or copper molybdenum alloy.

Further, the feedthrough lower layer portion 20 and the feedthrough upper layer portion 22 may be formed of ceramic, for example. The ceramic material can be formed from, for example, alumina (Al ₂ O ₃ ), aluminum nitride (AlN), beryllium oxide (BeO), or the like.

(Modification)
A schematic planar pattern configuration of the high-frequency semiconductor device 1 according to the first modification of the first embodiment is expressed as shown in FIG. 3, and a schematic planar pattern configuration of the high-frequency semiconductor device 1 according to the second modification is It is expressed as shown in FIG.

  5 is a schematic bird's-eye view configuration of a package that houses the high-frequency semiconductor device 1 according to Modification 1 and Modification 2 of the first embodiment, and the metal cap 10 is represented as shown in FIG. The metal seal ring 10a is represented as shown in FIG. 5B, and the metal wall 16 is represented as shown in FIG. 5C. The conductor base plate 200, the feedthrough lower layer 20 and the feedthrough upper layer are shown. A schematic configuration of the strip lines 19a and 19b arranged on the portion 22 and the feedthrough lower layer portion 20 is expressed as shown in FIG.

  Moreover, it is a schematic cross-sectional configuration of the high-frequency semiconductor device 1 according to Modification 1 and Modification 2 of the first embodiment, and the schematic cross-sectional structure taken along the line II of FIGS. This is the same as FIG. 6 according to the first embodiment.

  In the high-frequency semiconductor device 1 according to the first modification of the first embodiment, the terminal electrodes 21a and 21b are substantially straight lines by devising the pattern shape of the output synthesis matching circuit 18 disposed on the output circuit board 28. The structure which can be arranged on the top is realized. On the other hand, in the high-frequency semiconductor device 1 according to the second modification of the first embodiment, the pattern shape of the output synthesis matching circuit 18 arranged on the output circuit board 28 is the same as the pattern shape of the first embodiment. By arranging the bonding wires 15 diagonally, the terminal electrodes 21a and 21b can be arranged on a substantially straight line.

  In the high-frequency semiconductor device 1 according to the first embodiment, the input bonding wire 12 and the output bonding wire 14 are arranged to have a predetermined angle of 90 ° or less on the plane with respect to the semiconductor chip 24. The arrangement of the through holes 34 provided in the input / output portion of the metal wall 16 is such that the terminal electrodes 21a and 21b deviate from the straight line as shown in FIG.

  On the other hand, in the high-frequency semiconductor device 1 according to Modification 1 and Modification 2 of the first embodiment, since the terminal electrodes 21a and 21b have a configuration that can be arranged on a substantially straight line, the metal wall 16 As shown in FIGS. 3 and 4, the terminal electrodes 21a and 21b are arranged on a substantially straight line.

  As shown in FIGS. 1 and 3 to 6, in the high-frequency semiconductor device 1 according to the first embodiment and the first and second modifications thereof, the thickness W2 of the feedthrough upper layer portion 22 is set to a metal. The wall 16 may be formed thicker than the thickness W1. That is, in the convex feedthrough 25 composed of the feedthrough lower layer portion 20 and the feedthrough upper layer portion 22, the thickness W2 of the feedthrough upper layer portion 22 is formed to be greater than the thickness W1 of the metal wall 16. The stress concentration point and the stress generation source (metal wall 16) at the connection portion between the portion 20 and the feedthrough upper layer portion 22 can be separated. As a result, the stress is relaxed and the generation of cracks at the stress concentration point can be suppressed.

(Semiconductor element structure)
An enlarged view of a schematic planar pattern configuration of the semiconductor chip 24c mounted on the high-frequency semiconductor device 1a according to the comparative example is expressed as shown in FIG.

  An enlarged view of a schematic planar pattern configuration of the semiconductor chip 24 mounted on the high-frequency semiconductor device 1 according to the embodiment is expressed as shown in FIG. 8A, and an enlarged view of a portion J in FIG. 8A. Is expressed as shown in FIG. 9 is a configuration example of the semiconductor chip 24 mounted on the high-frequency semiconductor device according to the embodiment, and a schematic cross-sectional configuration example along the line II-II in FIG. 8B is shown in FIG. Is done.

  In the semiconductor chip 24 mounted on the high-frequency semiconductor device 1 according to the first embodiment, the plurality of FET cells FET1 to FET8 include a semi-insulating substrate 110 and a semi-insulating substrate 110 as shown in FIG. A gate finger electrode 124, a source finger electrode 120, and a drain finger electrode 122 each having a plurality of fingers disposed on the first surface, and a gate finger electrode 124, a source finger electrode disposed on the first surface of the semi-insulating substrate 110 A plurality of gate terminal electrodes G1, G2,..., G8, a plurality of source terminal electrodes S1, S2,..., S9 and drain terminal electrodes D1, D2, formed by bundling a plurality of fingers for each of 120 and drain finger electrodes 122. ..., D8 and arranged below the source terminal electrodes S1, S2, ..., S9 , SC9 and the second surface opposite to the first surface of the semi-insulating substrate 110, and the VIA holes SC1, SC1, S2,. SC2,..., SC9, and ground electrodes (not shown) connected to each other.

  A bonding wire 12 is connected to the gate terminal electrodes G1, G2,..., G8, and a bonding wire 14 is connected to the drain terminal electrodes D1, D2,.

  In the semiconductor chip 24 mounted on the high-frequency semiconductor device 1 according to the first embodiment, the drain terminal electrodes D1, D2,..., D8 and the gate terminal electrodes G1, G2,. Is different from the semiconductor chip 24c mounted on the high-frequency semiconductor device 1a according to the comparative example.

  The source terminal electrode S1 is formed on the barrier metal layer (not shown) formed on the inner wall of the VIA holes SC1, SC2,..., SC9 and the filling metal layer (not shown) formed on the barrier metal layer and filling the VIA hole. , S2,..., S9 are connected to a ground electrode (not shown).

  The semi-insulating substrate 110 is a GaAs substrate, a SiC substrate, a GaN substrate, a substrate in which a GaN epitaxial layer is formed on a SiC substrate, a substrate in which a heterojunction epitaxial layer made of GaN / AlGaN is formed on a SiC substrate, a sapphire substrate, or One of the diamond substrates.

(Example structure)
The configuration example of the FET cell of the semiconductor chip 24 mounted on the high-frequency semiconductor device 1 according to the embodiment includes a semi-insulating substrate 110 and a nitride disposed on the semi-insulating substrate 110 as shown in FIG. -Based compound semiconductor layer 112, aluminum gallium nitride layer (Al _x Ga _1-x N) (0.1 ≦ x ≦ 1) 118 disposed on nitride-based compound semiconductor layer 112, and aluminum gallium nitride layer (Al a source finger electrode (S) 120, a gate finger electrode (G) 124, and a drain finger electrode (D) 122 disposed on _x Ga _1-x N) (0.1 ≦ x ≦ 1) 118. A two-dimensional electron gas (2DEG) layer is formed at the interface between the nitride-based compound semiconductor layer 112 and the aluminum gallium nitride layer (Al _x Ga _1-x N) (0.1 ≦ x ≦ 1) 118. 116 is formed. In the configuration example shown in FIG. 9, a high electron mobility transistor (HEMT) is shown.

  The source finger electrode 120 and the drain finger electrode 122 are made of, for example, Ti / Al. The gate finger electrode 124 can be formed of, for example, Ni / Au.

  In the semiconductor chip 24 mounted on the high-frequency semiconductor device according to the embodiment, the longitudinal pattern lengths of the gate finger electrode 124, the source finger electrode 120, and the drain finger electrode 122 are microwave / millimeter wave / submillimeter wave. As the operating frequency increases, it is set shorter. For example, in the millimeter wave band, the pattern length is about 25 μm to 50 μm.

  Further, the width of the source finger electrode 120 is, for example, about 40 μm, and the width of the source terminal electrodes S1, S2,..., S9 is, for example, about 100 μm. The formation width of the VIA holes SC1, SC2,..., SC9 is, for example, about 10 μm to 40 μm.

(Wire bonding)
FIG. 10 schematically shows how bonding wires W11, W21, W31, W41, W51,... Are formed on the drain terminal electrode D1 on the semiconductor chip 24c constituting the high-frequency semiconductor device 1a according to the comparative example. expressed. In FIG. 10, bonding connection electrodes BG11, BG21, BG31, BG41, and BG51 are formed on the drain terminal electrode D1 corresponding to the bonding wires W11, W21, W31, W41, and W51. Although not shown for the other drain terminal electrodes D2, D3,..., D8, bonding wires and bonding connection electrodes are similarly formed.

  FIG. 11 schematically shows how bonding wires W11, W21, W31, W41, W51,... Are formed on the drain terminal electrode D1 on the semiconductor chip 24 constituting the high-frequency semiconductor device 1 according to the first embodiment. It is expressed as shown in In FIG. 11, bonding connection electrodes BG11, BG21, BG31, BG41, and BG51 are formed on the drain terminal electrode D1 corresponding to the bonding wires W11, W21, W31, W41, and W51. Although not shown for the other drain terminal electrodes D2, D3,..., D8, bonding wires and bonding connection electrodes are similarly formed.

  In the high-frequency semiconductor device 1 according to the first embodiment, each cell of the semiconductor chip 24 includes drain terminal electrodes D1, D2,... D8, and the drain terminal electrodes D1, D2,. As shown in FIG. 11, a parallelogram parallel to the plurality of bonding wires W11, W21,..., W51 may be provided.

  An enlarged view for explaining a state in which wire bonding is performed obliquely on the drain terminal electrode D1 on the semiconductor chip 24c constituting the high-frequency semiconductor device 1a according to the comparative example is expressed as shown in FIG. In particular, on the semiconductor chip 24c constituting the high-frequency semiconductor device 1a according to the comparative example, when wire bonding is performed obliquely on the drain terminal electrode D1, the drain terminal electrode D1 is rectangular, so that the connection points A11, A21, A31, The lengths between A41 and A51 and the connection points B11, B21, B31, B41, and B51 are likely to vary. In addition, when the length between the connection points A11, A21, A31, A41, A51 and the connection points B11, B21, B31, B41, B51 varies or becomes longer, it melts at the center point M. easy. This is because if the wire becomes long, it becomes difficult to dissipate heat and the current capacity decreases.

  FIG. 13 schematically shows how the bonding wires WG1, WG2,... WG8 are formed on the gate terminal electrodes G1, G2,..., G8 on the semiconductor chip 24c constituting the high-frequency semiconductor device 1a according to the comparative example. Represented as shown. In FIG. 13, bonding connection electrodes BG1, BG2,... BG8 are formed on the gate terminal electrodes G1, G2,..., G8 corresponding to the bonding wires WG1, WG2,.

  The manner in which the bonding wires WG1, WG2,... WG8 are formed on the gate terminal electrodes G1, G2,..., G8 on the semiconductor chip 24 constituting the high-frequency semiconductor device 1 according to the first embodiment is schematically shown. , As shown in FIG. 14, bonding connection electrodes BG1, BG2,... BG8 are formed on the gate terminal electrodes G1, G2,..., G8 corresponding to the bonding wires WG1, WG2,.

  Further, in the high-frequency semiconductor device 1 according to the first embodiment, each cell of the semiconductor chip 24 includes gate terminal electrodes G1, G2,..., G8 as shown in FIG. G8 may include a parallelogram parallel to the plurality of bonding wires WG1, WG2,... WG8.

  In the high-frequency semiconductor device 1 according to the first embodiment, the drain terminal electrodes D1, D2,..., D8 are parallel to the plurality of bonding wires W11, W21,. Since the quadrilateral is provided, it is easy to form a plurality of bonding wires W11, W21,. That is, as shown in FIG. 11, bonding connection electrodes BG1, BG2,..., BG8 that are crushed in an elliptical shape are formed at the tip of the bonded wire, and when the wire is slanted, the tip of the bonding wire is adjacent. Do not contact the drain terminal electrode of the cell. On the other hand, in the high-frequency semiconductor device 1a according to the comparative example, as shown in FIG. 10, the tip of the bonding wire tends to come into contact with the drain terminal electrode of the adjacent cell when the wire is slanted.

  Similarly, in the high-frequency semiconductor device 1 according to the first embodiment, the gate terminal electrodes G1, G2,... G8 are connected to a plurality of bonding wires WG1, WG2,. Since the parallelograms are provided in parallel, it is easy to form a plurality of bonding wires WG1, WG2,.

  On the semiconductor chip 24 constituting the high-frequency semiconductor device 1 according to the first embodiment, eight bonding wires having a length of 1 mm are connected in parallel, and the inductance value between the terminals is bonded with a wire end spacing of 0.2 mm. And the wiring angle θ is expressed as shown in FIG. In addition, a state in which eight bonding wires W11, W21, W31,..., W81 are connected in parallel to the drain terminal electrode D1 at a wiring angle θ is schematically represented as shown in FIG. The Here, as shown in FIG. 15B, the wiring angle θ is set to 0 degree when a plurality of bonding wires W11, W21,..., W81 are arranged perpendicular to the semiconductor chip 24. This is the angle taken from. Here, the wiring angle θ has a predetermined angle of 90 ° or less on the plane.

  On the semiconductor chip 24 constituting the high-frequency semiconductor device 1 according to the first embodiment, a wire end interval DE when bonding-connecting a plurality of bonding wires to the drain terminal electrode D1 in parallel at a wiring angle θ. The wire interval DW and the wiring angle θ are expressed as shown in FIG.

  As shown in FIG. 15A, on the semiconductor chip 24 constituting the high-frequency semiconductor device 1 according to the first embodiment, eight 1 mm long bonding wires are arranged in parallel, and the wire end interval DE is set to 0. When it is desired to form 0.03 nH in parallel by 8 mm bonding, when the wiring angle θ = 0 degree (comparative example), the wire length is 1.2 mm. On the other hand, when the wiring angle θ = 45 degrees, 0.03 nH can be obtained with a 1 mm long wire.

  When the wiring angle θ = 0 degree (comparative example), the bonding wire interval DW remains 0.2 mm, but the wire wire interval DE remains 0.2 mm by making the bonding wire oblique. By reducing the wire spacing DW, the mutual inductance value can be substantially increased, and as a result, the inductance value can be increased.

  Further, the lower limit value of the wiring angle θ is an angle at which bonding wires overlap and appear as one, that is, 0 degree.

  According to the first embodiment and the first and second modifications thereof, it is possible to provide a high-frequency semiconductor device capable of increasing the inductance value without increasing the length of the bonding wire.

[Second Embodiment]
The schematic planar pattern configuration of the high-frequency semiconductor device 1 according to the second embodiment is expressed as shown in FIG. 17, and the schematic planar pattern configuration of the high-frequency semiconductor device 1 according to the first to third modifications is shown in FIG. It is expressed as shown in FIG.

  In the high-frequency semiconductor device 1 according to the second embodiment and the first to third modifications thereof, as shown in FIGS. 17 to 20, a plurality of chips of semiconductor chips 24a and 24b are arranged. Here, in FIGS. 17 to 20, an example of a two-chip configuration is shown, but three or more chips may be used.

  As shown in FIGS. 17 to 20, the high-frequency semiconductor device 1 according to the second embodiment and its modifications 1 to 3 has a conductor base plate 200 and a multi-cell configuration of a plurality of chips arranged on the conductor base plate 200. The semiconductor chip 24a / 24b, the semiconductor chip 24a / 24b, the metal wall 16 disposed on the conductor base plate 200, and the conductor base plate 200 surrounded by the metal wall 16 adjacent to the semiconductor chip 24a / 24b. Input circuit board 26 / output circuit board 28 arranged, input matching circuits 17a, 17b, input distribution circuit 17c and strip line 17d arranged on input circuit board 26, and output arranged on output circuit board 28 Matching circuits 18a and 18b, output synthesis circuit 18c and strip line 18d, and semiconductor chip And a plurality of input bonding wire 12a · 12b and a plurality of output bonding wires 14a · 14b to be connected to the 4a · 24b of the input matching circuit 17a · 17b and the output matching circuit 18a · 18b. Here, the input bonding wires 12a and 12b and the output bonding wires 14a and 14b have a predetermined angle of 90 ° or less on the plane with respect to the semiconductor chips 24a and 24b.

  In the high-frequency semiconductor device 1 according to the second embodiment and the first to third modifications thereof, each cell of the semiconductor chips 24a and 24b includes a drain terminal electrode, and the drain terminal electrode includes a plurality of output bonding wires 14a and 14b. You may provide the parallelogram parallel to.

  In the high-frequency semiconductor device 1 according to the second embodiment and the first to third modifications thereof, each cell of the semiconductor chips 24a and 24b includes a gate terminal electrode, and the gate terminal electrode includes a plurality of input bonding wires 12a. -You may provide the parallelogram parallel to 12b. 18 to 19, the conductor base plate 200 and the metal wall 16 disposed on the conductor base plate 200 are not shown. The other configuration is the same as that of the first embodiment, and a duplicate description is omitted.

  In the high-frequency semiconductor device 1 according to the second embodiment and the modified examples 1 and 2 thereof, both of the semiconductor chips 24a and 24b and the metal wall 16 in which the through-holes 34 are arranged in the longitudinal direction of the semiconductor chips 24a and 24b. The example arrange | positioned in parallel with respect to is shown.

  On the other hand, in the high-frequency semiconductor device 1 according to the third modification of the second embodiment, as shown in FIG. 20, the semiconductor chips 24a and 24b are arranged and the through-holes 34 are arranged in the longitudinal direction of the semiconductor chips 24a and 24b. An example in which the metal wall 16 is disposed at 90 degrees with respect to the metal wall 16 is shown. Further, the semiconductor chips 24a and 24b may be arranged such that the longitudinal direction of the semiconductor chips 24a and 24b is a predetermined angle of 0 degrees or more and 90 degrees or less with respect to the metal wall 16 where the through holes 34 are arranged. .

  In the high-frequency semiconductor device according to Modification 3 of the second embodiment, a schematic cross-sectional structure taken along line III-III in FIG. 20 is represented as shown in FIG. 21, and is taken along line IV-IV in FIG. The schematic cross-sectional structure is represented as shown in FIG. 22, and the schematic cross-sectional structure along the VV line in FIG. 20 is represented as shown in FIG. 23, and the schematic cross-sectional structure along the VI-VI line in FIG. The cross-sectional structure is expressed as shown in FIG.

  Also, a schematic bird's-eye view configuration of a package that houses a high-frequency semiconductor device according to Modification 3 of the second embodiment is expressed as shown in FIG. 25A shows the metal cap 10, FIG. 25B shows the metal seal ring 10a, FIG. 25C shows the metal wall 16, FIG. 25D shows the conductor base plate 200, the feedthrough lower layer 20, the feed. The schematic configurations of the strip lines 19a and 19b arranged on the through upper layer portion 22 and the feedthrough lower layer portion 20 are respectively shown.

  In the package that accommodates the high-frequency semiconductor device according to the third modification of the second embodiment, the feed-through configuration on the input side (20, 19a, 22) and the feed-through configuration on the output side (20, 19b, 22) As shown in FIG. 25, the conductor base plate 200 is shifted and disposed on the sides facing each other.

  The package shown in FIG. 25 can also be applied to the first embodiment shown in FIG. 1 and the second modification of the second embodiment shown in FIG.

  According to the second embodiment and the first to third modifications thereof, it is possible to provide a high-frequency semiconductor device capable of increasing the inductance value without increasing the length of the bonding wire.

[Third embodiment]
A schematic planar pattern configuration of the high-frequency semiconductor device 1 according to the third embodiment is expressed as shown in FIG. 26, and a schematic planar pattern configuration of the high-frequency semiconductor device 1 according to Modifications 1 to 2 is It is expressed as shown in FIGS.

  In the high-frequency semiconductor device 1 according to the third embodiment and the first and second modifications thereof, as shown in FIGS. 26 to 28, semiconductor chips 24a and 24b of a plurality of chips are arranged. Here, in FIGS. 26 to 28, an example of a two-chip configuration is shown, but three or more chips may be used.

  Further, in the high-frequency semiconductor device 1 according to the third embodiment and the first to second modifications thereof, the semiconductor chips 24a and 24b are arranged with respect to the diagonal of the metal wall 16 as shown in FIGS. Are arranged almost in parallel.

  In particular, in the high-frequency semiconductor device 1 according to the third embodiment, as shown in FIG. 26, the semiconductor chips 24a and 24b are arranged so that the longitudinal directions of the semiconductor chips 24a and 24b are two diagonal lines of the metal wall 16, respectively. It arrange | positions so that it may be substantially parallel with respect to.

  The high-frequency semiconductor device 1 according to the third embodiment and its modifications 1 to 2 includes, as shown in FIGS. 26 to 28, a conductor base plate 200 and a multi-cell of a plurality of chips arranged on the conductor base plate 200. The semiconductor chips 24a and 24b, the semiconductor chips 24a and 24b, and the metal wall 16 disposed on the conductor base plate 200 and the conductor base plate 200 surrounded by the metal wall 16 are adjacent to the semiconductor chips 24a and 24b. The input circuit board 26 and the output circuit board 28 arranged in this manner, the input matching circuits 17a and 17b, the input distribution circuit 17c and the strip line 17d arranged on the input circuit board 26, and the output circuit board 28. Output matching circuits 18a, 18b, output synthesis circuit 18c, strip line 18d, and semiconductor Tsu and a plurality of input bonding wire 12a · 12b and a plurality of output bonding wires 14a · 14b for connecting flop 24a · 24b and the input matching circuit 17a · 17b and the output matching circuit 18a · 18b. Here, the input bonding wires 12a and 12b and the output bonding wires 14a and 14b have a predetermined angle of 90 ° or less on the plane with respect to the semiconductor chips 24a and 24b.

  In the high-frequency semiconductor device 1 according to the third embodiment and the first to second modifications thereof, each cell of the semiconductor chips 24a and 24b includes a drain terminal electrode, and the drain terminal electrode includes a plurality of output bonding wires 14a. -You may provide the parallelogram parallel to 14b.

  Further, in the high-frequency semiconductor device 1 according to the third embodiment and the first to second modifications thereof, each cell of the semiconductor chips 24a and 24b includes a gate terminal electrode, and the gate terminal electrode has a plurality of input bondings. A parallelogram parallel to the wires 12a and 12b may be provided. The other configuration is the same as that of the first embodiment, and a duplicate description is omitted.

  In the high-frequency semiconductor device 1 according to the third embodiment and the first and second modifications thereof, the width in which the semiconductor chip can be mounted is increased as compared with the first and second embodiments, and the mounting substrate is mounted on the mounting substrate. A high-frequency semiconductor device that can be used effectively can be provided.

  According to the third embodiment and its modifications 1 to 2, it is possible to provide a high-frequency semiconductor device in which the value of inductance is increased without increasing the length of the bonding wire.

  As described above, according to the present embodiment, the bonding wire connected at a right angle to the semiconductor chip is connected at an angle to the semiconductor chip, so that the distance between the bonding wires is reduced. Shrinkage and mutual inductance can be increased.

  According to the present embodiment, it is possible to provide a high-frequency semiconductor device capable of increasing the inductance value without increasing the length of the bonding wire.

[Other embodiments]
Although this embodiment has been described, this embodiment is presented as an example and is not intended to limit the scope of the invention. The novel embodiment can be implemented in various other forms, and various omissions, replacements, and changes can be made without departing from the scope of the invention. This embodiment and its modifications are included in the scope and gist of the invention, and are included in the invention described in the claims and the equivalents thereof.

  Semiconductor chips mounted on the high-frequency semiconductor device according to the embodiment are not limited to FETs and HEMTs, but are LDMOS (Laterally Diffused Metal-Oxide-Semiconductor Field Effect Transistors) and heterojunction bipolar transistors (HBTs). Needless to say, an amplifying element such as a bipolar transistor is also applicable.

  As described above, various embodiments that are not described herein are included.

DESCRIPTION OF SYMBOLS 1 ... High frequency semiconductor device 10 ... Metal cap 10a ... Metal seal ring 11, 12, 12a, 12b, 14, 14a, 14b, 15 ... Bonding wire 16 ... Package outer wall (metal wall)
17... Input distribution matching circuit 17 a, 17 b... Input matching circuit 17 c... Input distribution circuit 18. Lower layer part 21, 21a, 21b ... Terminal electrode 22 ... Feedthrough upper layer part 24, 24a, 24b, 24c ... Semiconductor chip 25 ... Convex feedthrough 26 ... Input circuit board 28 ... Output circuit board 34 ... Through hole 110 ... Semi-insulating Substrate 112 ... nitride compound semiconductor layer (GaN epitaxial growth layer)
116: Two-dimensional electron gas (2DEG) layer 118: Aluminum gallium nitride layer (Al _x Ga _1-x N) (0.1 ≦ x ≦ 1)
DESCRIPTION OF SYMBOLS 120 ... Source finger electrode 122 ... Drain finger electrode 124 ... Gate finger electrode 200 ... Conductor baseplate G, G1, G2, ..., G8 ... Gate terminal electrode S, S1, S1, ..., S9 ... Source terminal electrode D, D1, D2 , ..., D8 ... Drain terminal electrodes SC1, SC2, ..., SC9 ... VIA holes

Claims (13)

A multi-cell semiconductor chip;
A matching circuit;
A plurality of bonding wires connected in parallel between the semiconductor chip and the matching circuit, and the plurality of bonding wires have a predetermined angle of 90 ° or less on a plane with respect to the semiconductor chip. A high-frequency semiconductor device. Each cell of the semiconductor chip includes a drain terminal electrode,
The high-frequency semiconductor device according to claim 1, wherein the drain terminal electrode has a parallelogram parallel to the plurality of bonding wires. Each cell of the semiconductor chip includes a gate terminal electrode,
The high-frequency semiconductor device according to claim 1, wherein the gate terminal electrode has a parallelogram parallel to the plurality of bonding wires. A conductor base plate;
A semiconductor chip having a multi-cell configuration disposed on the conductor base plate;
A metal wall which is embedded on the semiconductor chip and disposed on the conductor base plate;
A through hole provided in the input / output part of the metal wall;
A feedthrough terminal fitted in the through hole;
An input distribution matching circuit and an output synthesis matching circuit disposed adjacent to the semiconductor chip on the conductor base plate surrounded by the metal wall;
A plurality of input bonding wires and a plurality of output bonding wires that connect the semiconductor chip to the input distribution matching circuit and the output synthesis matching circuit; and the input bonding wires and the output bonding wires are connected to the semiconductor chip. A high-frequency semiconductor device having a predetermined angle of 90 ° or less on a plane. Each cell of the semiconductor chip includes a drain terminal electrode,
The high-frequency semiconductor device according to claim 4, wherein the drain terminal electrode has a parallelogram parallel to the plurality of output bonding wires. Each cell of the semiconductor chip includes a gate terminal electrode,
6. The high-frequency semiconductor device according to claim 4, wherein the gate terminal electrode includes a parallelogram parallel to the plurality of input bonding wires. The high-frequency semiconductor device according to claim 1, wherein a plurality of the semiconductor chips are arranged.   8. The high-frequency semiconductor device according to claim 7, wherein the semiconductor chip is arranged in parallel with the metal wall in which the longitudinal direction of the semiconductor chip is provided with the through hole.   The high frequency according to claim 7, wherein the semiconductor chip is arranged at a predetermined angle of 0 degree or more and 90 degrees or less with respect to the metal wall in which the longitudinal direction of the semiconductor chip is arranged with the through hole. Semiconductor device.   The high-frequency semiconductor device according to claim 7, wherein the semiconductor chip is arranged substantially parallel to one diagonal line of the metal wall.   The high-frequency semiconductor device according to claim 7, wherein the semiconductor chip is arranged so that the longitudinal direction of the semiconductor chip is substantially parallel to two diagonal lines of the metal wall 16. The semiconductor chip is
A semi-insulating substrate;
A gate finger electrode, a source finger electrode and a drain finger electrode disposed on the first surface of the semi-insulating substrate, each having a plurality of fingers;
A plurality of gate terminal electrodes arranged on the first surface of the semi-insulating substrate and formed by bundling a plurality of fingers for each of the gate finger electrode, the source finger electrode and the drain finger electrode; A plurality of the drain terminal electrodes;
A VIA hole disposed under the source terminal electrode;
2. A ground electrode disposed on a second surface opposite to the first surface of the semi-insulating substrate and connected to the source terminal electrode via the VIA hole. 11. The high frequency semiconductor device according to any one of 11 above.   The semi-insulating substrate is a GaAs substrate, a SiC substrate, a GaN substrate, a substrate in which a GaN epitaxial layer is formed on a SiC substrate, a substrate in which a heterojunction epitaxial layer made of GaN / AlGaN is formed on a SiC substrate, a sapphire substrate, or The high-frequency semiconductor device according to claim 12, wherein the high-frequency semiconductor device is any one of a diamond substrate.