JP2013101617A5 - - Google Patents
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- Publication number
- JP2013101617A5 JP2013101617A5 JP2012246051A JP2012246051A JP2013101617A5 JP 2013101617 A5 JP2013101617 A5 JP 2013101617A5 JP 2012246051 A JP2012246051 A JP 2012246051A JP 2012246051 A JP2012246051 A JP 2012246051A JP 2013101617 A5 JP2013101617 A5 JP 2013101617A5
- Authority
- JP
- Japan
- Prior art keywords
- port
- memory
- access
- digital signal
- processing system
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000000034 method Methods 0.000 claims 7
- 239000000872 buffer Substances 0.000 claims 3
- 238000004590 computer program Methods 0.000 claims 3
- 230000002093 peripheral effect Effects 0.000 claims 3
- 238000001914 filtration Methods 0.000 claims 1
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| GB1119327.3A GB2496396B (en) | 2011-11-09 | 2011-11-09 | Memory access for digital signal processing |
| GB1119327.3 | 2011-11-09 |
Publications (3)
| Publication Number | Publication Date |
|---|---|
| JP2013101617A JP2013101617A (ja) | 2013-05-23 |
| JP2013101617A5 true JP2013101617A5 (enExample) | 2014-12-18 |
| JP5752666B2 JP5752666B2 (ja) | 2015-07-22 |
Family
ID=45421495
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2012246051A Expired - Fee Related JP5752666B2 (ja) | 2011-11-09 | 2012-11-08 | デジタル信号処理用のメモリアクセス |
Country Status (6)
| Country | Link |
|---|---|
| US (1) | US8935486B2 (enExample) |
| EP (1) | EP2592562B1 (enExample) |
| JP (1) | JP5752666B2 (enExample) |
| CN (1) | CN103218301B (enExample) |
| GB (1) | GB2496396B (enExample) |
| TW (1) | TWI521352B (enExample) |
Families Citing this family (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US9690494B2 (en) * | 2015-07-21 | 2017-06-27 | Qualcomm Incorporated | Managing concurrent access to multiple storage bank domains by multiple interfaces |
| CN109271333B (zh) * | 2017-07-17 | 2022-03-01 | 深圳市中兴微电子技术有限公司 | 一种sram控制方法及控制器、控制系统 |
| FR3078439A1 (fr) * | 2018-02-27 | 2019-08-30 | Stmicroelectronics (Rousset) Sas | Procede de gestion du routage de transactions entre des equipements sources, au moins un equipement cible, par exemple une memoire multiports, et systeme sur puce correspondant |
| US20220269437A1 (en) * | 2021-02-19 | 2022-08-25 | Western Digital Technologies, Inc. | Data Storage Device and Method for Predetermined Transformations for Faster Retrieval |
| CN116719479B (zh) * | 2023-07-03 | 2024-02-20 | 摩尔线程智能科技(北京)有限责任公司 | 存储器访问电路及存储器访问方法、集成电路和电子设备 |
| CN117555902A (zh) * | 2023-12-06 | 2024-02-13 | 广东人工智能与先进计算研究院 | 数据计算方法、装置及电子设备 |
Family Cites Families (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4051551A (en) * | 1976-05-03 | 1977-09-27 | Burroughs Corporation | Multidimensional parallel access computer memory system |
| JPS6042970B2 (ja) * | 1979-07-11 | 1985-09-26 | 日本電気株式会社 | 並列処理システム |
| US5377340A (en) * | 1991-06-18 | 1994-12-27 | Hewlett-Packard Company | Method and apparatus for memory interleaving using an improved hashing scheme |
| US5479624A (en) * | 1992-10-14 | 1995-12-26 | Lee Research, Inc. | High-performance interleaved memory system comprising a prime number of memory modules |
| JP2003228517A (ja) * | 2002-02-01 | 2003-08-15 | Matsushita Electric Ind Co Ltd | メモリ装置 |
| GB2396031B (en) * | 2002-12-05 | 2005-10-26 | Imagination Tech Ltd | A SIMD processor with multi-port memory unit |
| US7685354B1 (en) | 2004-06-30 | 2010-03-23 | Sun Microsystems, Inc. | Multiple-core processor with flexible mapping of processor cores to cache banks |
| JP2008097572A (ja) * | 2006-09-11 | 2008-04-24 | Matsushita Electric Ind Co Ltd | 演算装置、コンピュータシステム、および携帯機器 |
| US8194481B2 (en) * | 2008-12-18 | 2012-06-05 | Mosaid Technologies Incorporated | Semiconductor device with main memory unit and auxiliary memory unit requiring preset operation |
| US8359421B2 (en) | 2009-08-06 | 2013-01-22 | Qualcomm Incorporated | Partitioning a crossbar interconnect in a multi-channel memory system |
-
2011
- 2011-11-09 GB GB1119327.3A patent/GB2496396B/en active Active
-
2012
- 2012-07-31 US US13/563,204 patent/US8935486B2/en active Active
- 2012-10-12 TW TW101137695A patent/TWI521352B/zh not_active IP Right Cessation
- 2012-11-06 EP EP12191503.7A patent/EP2592562B1/en active Active
- 2012-11-08 JP JP2012246051A patent/JP5752666B2/ja not_active Expired - Fee Related
- 2012-11-08 CN CN201210444130.5A patent/CN103218301B/zh active Active
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