JP2013097715A - Electronic device and program - Google Patents

Abstract

PROBLEM TO BE SOLVED: To shorten the time until starting execution of a program while shortening the execution time of the program.SOLUTION: An electronic device includes: a nonvolatile memory for storing the program; a volatile memory whose read speed is faster than that of the nonvolatile memory; and a processor part for successively reading an instruction included in the program from the nonvolatile memory and executing it when an operation is started. The processor part transfers the program from the nonvolatile memory to the volatile memory in parallel with execution of the instruction read from the nonvolatile memory, and when transfer to the nonvolatile memory is completed, switches a read destination of the instruction to be executed from the nonvolatile memory to the volatile memory.

Description

  The present invention relates to an electronic device and a program.

An information processing apparatus is known in which a part of a hibernated memory image is transferred in advance to the system RAM and then the execution of the operating system is started, and in parallel with the execution of the operating system, the memory image that has not been transferred in advance is transferred. (For example, refer to Patent Document 1).
[Prior art documents]
[Patent Literature]
[Patent Document 1] JP 2007-334383 A

  By executing the program after transferring the program to the RAM, the execution time of the program can be shortened. However, the program transferred to the RAM cannot be executed without waiting for the completion of the transfer to the RAM. Conventionally, there has been a problem that it is not possible to shorten the time until the program execution is started while shortening the program execution time.

  In the first aspect of the present invention, the electronic device transmits a nonvolatile memory storing the program, a volatile memory having a faster reading speed than the nonvolatile memory, and an instruction included in the program when the operation is started. A processor unit that sequentially reads out and executes from the non-volatile memory, and the processor unit transfers the program from the non-volatile memory to the volatile memory in parallel with the execution of the instruction read from the non-volatile memory. When the transfer is completed, the read destination of the instruction to be executed is switched from the nonvolatile memory to the volatile memory.

  In the second aspect of the present invention, when the program starts operation, the program sequentially reads out the instructions included in the computer program stored in the nonvolatile memory from the nonvolatile memory, and executes the instructions. In parallel with the execution of the instruction read from the memory, execute the step of transferring the computer program from the nonvolatile memory to the volatile memory that has a faster reading speed than the nonvolatile memory, and when the transfer to the nonvolatile memory is completed And causing the computer to execute a step of switching from a nonvolatile memory to a volatile memory.

  It should be noted that the above summary of the invention does not enumerate all the necessary features of the present invention. In addition, a sub-combination of these feature groups can also be an invention.

2 shows a schematic cross section of a main part of the imaging apparatus 10. 1 schematically shows a system configuration of an imaging apparatus 10. An example of a block configuration of the control unit 52 is shown. An example of the physical address space mapped to the logical address space is shown. An example of the physical address space mapped to the logical address space is shown. An example of an operation sequence in the control unit 52 is shown. An example of the operation flow of the first processor 310 during execution of the initialization code is shown. 2 shows a processing flow from the start to the end of the imaging apparatus 10. Another example of the operation flow for transferring the OS to the SDRAM 58 is shown.

  Hereinafter, the present invention will be described through embodiments of the invention, but the following embodiments do not limit the invention according to the claims. In addition, not all the combinations of features described in the embodiments are essential for the solving means of the invention.

  FIG. 1 shows a schematic cross section of the main part of the imaging apparatus 10. The imaging device 10 is a single-lens reflex camera as an example of an interchangeable lens camera. The imaging device 10 includes a camera unit 30, a single lens unit 20, and a light emitting unit 60. The single lens unit 20 and the light emitting unit 60 are attached to the camera unit 30.

  A plurality of lens units 20 having different focal lengths, open F values, and the like are attached to the camera unit 30 as interchangeable lenses. The lens unit 20 includes a lens system 21 arranged along the optical axis 11 and supported by the lens barrel 26. The lens system 21 as an example of the imaging lens guides the incident subject light flux to the camera unit 30. In the figure, the lenses constituting the lens system 21 include a front lens 22 and a lens group 23 responsible for focusing and zooming. The lens group 23 is configured such that one or more lenses included in the lens group 23 can move in the optical axis direction in response to instructions for focus adjustment and field angle adjustment. The camera unit 30 can transmit instructions for focus adjustment and angle of view adjustment to the lens unit 20.

  The lens barrel 26 supports the lens circuit board 27. The lens circuit board 27 is mounted with various circuits, electronic elements and the like for controlling the lens unit 20. The lens unit 20 includes a lens mount 29 at a connection portion with the camera unit 30, and engages with a camera mount 31 included in the camera unit 30 to be integrated with the camera unit 30. The lens mount 29 and the camera mount 31 are each provided with a communication terminal, and the communication terminals are connected to each other when the mounts are engaged with each other. Thereby, various circuits, electronic elements, and the like mounted on the lens circuit board 27 are electrically connected to the camera unit 30 side.

  The camera unit 30 includes a main mirror 32 that reflects the subject light beam incident from the lens unit 20 and a focus plate 33 on which the subject light beam reflected by the main mirror 32 forms an image. The main mirror 32 swings around the main mirror rotation axis 34 in the mirror box, and takes an oblique state in which the subject light beam is tilted around the optical axis 11 and a retreat state in which the main mirror 32 is retreated from the subject light beam. obtain. When the main mirror 32 retracts from the subject light beam, the sub mirror 40 retracts from the subject light beam in conjunction with the main mirror 32. The main mirror rotation shaft 34 is supported on the side wall of the mirror box.

  When the live view button is pressed down or when the release button is pressed down to the lowest position, the retracted state indicated by the broken line is taken. For example, when the live view button is pressed down or the release button is pressed down to the lowest position while the main mirror 32 is obliquely installed in the subject light flux, the main mirror 32 moves to the retracted position indicated by the broken line. . When the live view button is depressed, the main mirror 32 remains in the retracted position until the live view button is depressed again. On the other hand, when the release button is pressed down, the main mirror 32 is lowered and returned to the original oblique position when the predetermined imaging operation is finished.

  The focal plane shutter 43 and the image sensor 36 are arranged along the optical axis 11. When the main mirror 32 and the sub mirror 40 are in the retracted state, the subject light flux passes through the lens system 21 and enters the camera unit 30, passes through the inside of the mirror box and the open focal plane shutter 43, and then the image sensor. An image is formed on 36 light receiving surfaces.

  The image sensor 36 has a plurality of photoelectric conversion elements that output the subject image formed on the light receiving surface as an electrical signal. Examples of the photoelectric conversion element include a CMOS sensor and a CCD sensor. The image sensor 36 is connected to the camera processing unit 50. The camera processing unit 50 is equipped with electrical elements such as an ASIC that processes electrical signals photoelectrically converted by the image sensor 36 and a processor that controls the entire camera unit 30.

  A display unit 53 such as a liquid crystal monitor is disposed on the back of the camera unit 30. The display unit 53 displays an image generated from the image signal output from the photoelectric conversion element included in the image sensor 36. The display unit 53 displays the subject image using the display image data generated from the electrical signal of the subject image by the ASIC in the camera processing unit 50. The display unit 53 displays various menu information, imaging information, notification information, and the like as well as a still image after imaging. During live view, display image data is generated by the ASIC in the camera processing unit 50 from the electrical signal of the subject image formed on the light receiving surface of the image sensor 36 while adjusting the focus on the subject. The display unit 53 displays the subject image using the image data for work.

  The focus plate 33 is disposed at a position conjugate with the light receiving surface of the image sensor 36. The subject image formed on the focus plate 33 is converted into an erect image by the pentaprism 37 and observed by the user via the eyepiece optical system 38. A photometric element 39 is disposed above the exit surface of the pentaprism 37. The photometric element 39 is a photoelectric conversion element for detecting the luminance distribution of the subject image via the photometric optical system 35. The luminance distribution of the subject image detected by the photometric element 39 is used in the camera processing unit 50 to determine the shutter speed, aperture value, and the like. The luminance distribution of the subject image detected by the photometric element 39 is used in an ASIC or the like in the camera processing unit 50 in order to detect a person's face or the like.

  A region near the optical axis 11 of the main mirror 32 in the oblique state is formed as a half mirror, and a part of the incident subject light flux is transmitted therethrough. The transmitted subject luminous flux is reflected by the sub-mirror 40 that swings in conjunction with the main mirror 32 and guided to the focusing unit 42. The subject luminous flux guided to the focusing unit 42 is incident on the focusing sensor through the focusing optical system. The focus sensor outputs a phase difference detection signal indicating the focus state, the front pin state, and the rear pin state in each of the plurality of focus adjustment regions. In the case of the front pin state and the rear pin state, the phase difference detection signal also indicates a deviation amount from the focused state. The camera processing unit 50 adjusts the focus of the lens unit 20 by phase difference AF (automatic focus) using a phase difference detection method.

  The camera unit 30 houses a detachable secondary battery 54. The secondary battery 54 supplies power not only to the camera unit 30 but also to the lens unit 20. When the power is turned on, power is supplied from the secondary battery 54 to the camera processing unit 50 and the like.

  The light emitting unit 60 emits illumination light that illuminates the subject. The light emitting unit 60 and the camera unit 30 are connected via a mount portion 69 included in the light emitting unit 60 and a mount portion 41 included in the camera unit 30. The light emitting unit 60 includes a light emitting unit 61 such as a xenon lamp, a reflecting plate 62, a Fresnel lens 63, a battery 65 such as a battery, and a light emitting unit control unit 66. The light emitting unit control unit 66 supplies electric power from the battery 65 to cause the light emitting unit 61 to emit light, thereby flashing illumination light through the reflecting plate 62 and the Fresnel lens 63. The light emitting unit controller 66 controls light emission and the like based on the light emission instruction signal from the camera processing unit 50.

  FIG. 2 is a block diagram schematically showing the system configuration of the imaging apparatus 10. The system in the imaging apparatus 10 corresponds to each of the lens unit 20, the camera unit 30, and the light emitting unit 60, and includes a lens control system centered on the lens system control unit 71 and a camera control system centered on the control unit 52. And a light emission control system centering on the light emission unit controller 66. The lens control system and the camera control system exchange various data and control signals with each other via a communication terminal connected by the lens mount 29 and the camera mount 31. The light emission control system and the camera control system exchange various data and control signals with each other via a communication terminal connected by the mount unit 69 and the mount unit 41.

  The image processing unit 51 included in the camera control system is realized by, for example, an ASIC. The image processing unit 51 processes the electrical signal of the subject image output from the image sensor 36 in accordance with a command from the control unit 52 to generate image data. The generated image data is sent to the display control unit 55 and displayed on the display unit 53 for a certain time after imaging, for example. In parallel with this, the image processing unit 51 processes the generated image data into a predetermined image format. For example, the image processing unit 51 processes the image data into a JPEG file as an image format for still images, an MPEG file as an image format for moving images, or the like.

  The external connection IF 56 includes a recording medium IF that is responsible for data transmission with the recording medium, and an external device IF that is responsible for communication with an external device of the external connection IF 56. The image data generated in the image processing unit 51 is recorded on the recording medium via the recording medium IF. Also, the image data is transmitted to the external device via the external device IF, and is recorded or processed in the external device. Examples of the external device include a personal computer and a digital photo stand. When the external device is a video device, the image data as the video data is transmitted as a video signal via the external device IF.

  Further, the image processing unit 51 processes the electrical signal of the subject image output from the image sensor 36 in accordance with a command from the control unit 52, and generates a contrast evaluation value indicating the contrast amount of the subject image. The control unit 52 generates a focus adjustment control signal based on at least one of the contrast evaluation value and the phase difference detection signal output from the focusing unit 42, and supplies it to the lens system control unit 71.

  The system memory 57 is a flash memory, for example. The system memory 57 may be a NOR type flash memory. The system memory 57 is an example of a non-volatile memory, and plays a role of storing a program for controlling the imaging apparatus 10, various parameters, and the like. The program includes an operating system (OS). The OS may include software components such as various basic applications in addition to the kernel image.

  The SDRAM 58 is an example of a volatile memory. The SDRAM 58 is a memory that can be accessed at a higher speed than the system memory 57. For example, the SDRAM 58 has a faster reading speed than the system memory 57. The control unit 52 can access the information stored in the SDRAM 58 in a shorter time than the information stored in the system memory 57. The SDRAM 58 stores the OS transferred from the system memory 57. The SDRAM 58 also serves as a work memory that temporarily stores image data being processed by the image processing unit 51.

  The drive control unit 59 drives the main mirror 32, the sub mirror 40, the focal plane shutter 43, and the like according to instructions from the control unit 52. The operation input unit 47 includes a release button, a live view button, an imaging mode switch, a moving image shooting button, a power button, and the like. The control unit 52 acquires a signal indicating a user operation on the operation input unit 47.

  The lens system control unit 71 receives various control signals from the control unit 52 and controls various operations in the lens unit 20. The lens memory 72 stores lens unique information, a program executed by the lens system control unit 71, and the like. The lens driving unit 73 drives the focus lens, the zoom lens, the diaphragm 28 and the like according to the control signal received from the control unit 52 by the lens system control unit 71. In addition, the lens system control unit 71 transmits lens specific information to the control unit 52 in response to a request from the control unit 52.

  The light emitting unit control unit 66 receives the control signal from the control unit 52 and controls the entire light emitting unit 60. The light emitting unit control unit 66 drives the light emitting unit 61 according to the control signal received from the control unit 52. In 66, the lens system control unit 71 transmits specific information of the light emitting unit 60 to the control unit 52 in response to a request from the control unit 52.

  FIG. 3 shows an example of a block configuration of the control unit 52. In this example, the control unit 52 has a memory management unit that maps the logical address space of the processor to the physical memory address space. Examples of the physical address include an address of the system memory 57 and an address of the SDRAM 58.

  In this example, the control unit 52 is a multiprocessor unit. The control unit 52 includes a first processor 310 and a second processor 320. The first processor 310 and the second processor 320 interrupt each other through the interrupt line 330. The first processor 310 and the second processor 320 share at least a part of the memory area of the SDRAM 58.

  The first processor 310 includes an execution unit 314 that executes instructions, a memory management unit 312, and a cache 316. The memory management unit 312 maps the logical address space of the first processor 310 to the physical memory space. The memory management unit 312 converts the logical address of the first processor 310 into a physical address. The execution unit 314 can access the address of the system memory 57 or the SDRAM 58 mapped by the memory management unit 312 through the logical address. Cache 316 caches instructions and data transferred from system memory 57 or SDRAM 58. The cache 316 caches the data transferred from the execution unit 314. When the instruction and data corresponding to the logical address requested by the execution unit 314 exist in the cache 316, the execution unit 314 accesses the cache 316.

  The second processor 320 includes an execution unit 324, a memory management unit 322, and a cache 326. The execution unit 324, the memory management unit 322, and the cache 326 have the same functions and configurations as the execution unit 314, the memory management unit 312, and the cache 316, respectively, and thus detailed description of the operation is omitted.

  When the first processor 310 starts its operation, the instructions included in the OS stored in the system memory 57 are sequentially read from the system memory 57 and executed. Specifically, when a power button as a part of the operation input unit 47 is turned on, instructions are sequentially read from the system memory 57 and executed. Specifically, the execution unit 314 executes an instruction read from the system memory 57. When the power button is turned on, the execution unit 314 reads the command from the system memory 57 and executes it, so that the operation for controlling the imaging device 10 can be started quickly.

  Note that “reading and executing instructions sequentially from the system memory 57” indicates that the execution unit 314 performs reading by designating an address of the system memory 57. Therefore, when the instruction requested by the execution unit 314 exists in the cache 316, the execution unit 314 also executes the instruction provided from the cache 316, which corresponds to executing the instruction sequentially read from the system memory 57. To do. The same applies to the sequential reading of instructions from the SDRAM 58.

The second processor 320 transfers the OS from the system memory 57 to the SDRAM 58 in parallel with the execution of the instruction in the first processor 310. The first processor 310 switches the read destination of the instruction to be executed from the system memory 57 to the SDRAM 58 when the transfer to the system memory 57 by the second processor 320 is completed. Specifically, when the transfer of the OS to the SDRAM 58 is completed, the first processor 310 allocates a memory space corresponding to the system memory 57 in which the OS is stored among the memory spaces of the first processor 310 to the SDRAM 58. The OS is switched to the transferred memory space. More specifically, when the transfer of the OS to the SDRAM 58 is completed, the memory management unit 312 has an address corresponding to the system memory 57 in which the OS is stored in the logical address space mapped to the processor. The space is converted into an address space to which the OS in the SDRAM 58 is transferred.
As described above, when the operation starts, the control unit 52 sequentially reads out the instructions included in the OS stored in the system memory 57 from the system memory 57 and executes them. The control unit 52 transfers the OS from the system memory 57 to the SDRAM 58 in parallel with the execution of the instruction read from the system memory 57, and when the transfer to the system memory 57 is completed, the control unit 52 determines the instruction read destination to be executed. The system memory 57 is switched to the SDRAM 58. Specifically, when the transfer to the SDRAM 58 is completed, the control unit 52 allocates a memory space corresponding to the system memory 57 in which the OS is stored, among the memory spaces of the control unit 52, by the OS in the SDRAM 58. Switch to the transferred memory space. More specifically, the memory management unit corresponds to the system memory 57 in which the OS is stored in the logical address space mapped to the control unit 52 when the transfer of the OS to the SDRAM 58 is completed. The address space is converted into an address space to which the OS in the SDRAM 58 has been transferred.

  With the control described above, the first processor 310 starts the execution of the OS on the system memory 57 when the imaging device 10 is activated, so that the control of the imaging device 10 can be started promptly. The second processor 320 can transfer the OS to the SDRAM 58 in the background while the first processor 310 executes the OS instruction on the system memory 57. Then, when the transfer to the SDRAM 58 is completed, the logical address space of the first processor 310 is switched from the system memory 57 to the address space in which the OS of the SDRAM 58 is loaded. Therefore, the first processor 310 can read the instruction to be executed next to the instruction from the SDRAM 58 and execute it following the instruction executed before switching. For example, the first processor 310 may simply restart the operation without changing the value of the program counter before and after switching. Therefore, the first processor 310 can seamlessly switch from execution on the system memory 57 to execution on the SDRAM 58.

  FIG. 4 schematically shows an example of a physical address space mapped to the logical address space. In this example, the logical address space 400 is a logical address space of the first processor 310. This example is a mapping example when the first processor 310 is executing an OS on the system memory 57.

  The physical address space 450 of the system memory 57 stores an initialization code executed by the first processor 310 and the second processor 320, an OS image, and the like. The logical address space 410 of the first processor 310 is mapped to the physical address space 450 of the system memory 57. Therefore, when the first processor 310 accesses a page included in the logical address space 410, the corresponding page in the physical address space 450 of the system memory 57 is accessed. The logical address space 420 of the first processor 310 is mapped to the physical address space 460 of the SDRAM 58. Therefore, when the first processor 310 accesses a page included in the logical address space 420, the corresponding page in the physical address space 460 of the SDRAM 58 is accessed.

  The OS image includes a text section for storing machine language instructions, a data section for storing variables having initial values, a BSS section for storing information on variables having no initial values, and the like. The text section is stored in the physical address space 452 in the system memory 57. The first processor 310 can read an OS instruction from the physical address space 452 by accessing the logical address space 412 corresponding to the physical address space 452.

  The data section is transferred from the system memory 57 to the SDRAM 58 at startup. Further, variables used by the OS are expanded in the SDRAM 58 based on the information of the BSS section. The variable section of the SDRAM 58 stores a variable whose value may be changed by execution of the OS. The variable section is stored in the physical address space 462 of the SDRAM 58. The first processor 310 can access the variable by accessing the page of the logical address space 422 corresponding to the physical address space 462.

  The first processor 310 sequentially reads and executes machine language instructions from the logical address space 412. The first processor 310 reads / writes the physical address space 462 of the SDRAM 58 via the logical address 422 when reading / writing data such as variables during execution of the kernel.

  FIG. 5 schematically shows an example of a physical address space mapped to the logical address space. This example is a mapping example when the first processor 310 is executing the OS on the SDRAM 58.

  The text section transferred from the system memory 57 to the SDRAM 58 by the second processor 320 is stored in the physical address space 464 of the SDRAM 58. The logical address space 412 of the first processor 310 is mapped to the physical address space 464 by the address conversion by the memory management unit 312. Accordingly, the first processor 310 can read an instruction from a corresponding page in the physical address space 464 of the SDRAM 58 via a page in the logical address space 412.

  For this reason, even when the first processor 310 is executing the OS on the SDRAM 58, the first processor 310 can read the instruction by designating the logical address space 412. For this reason, the memory management unit 312 switches the mapping so that the instruction read destination can be seamlessly switched from the system memory 57 to the SDRAM 58.

  The physical address space 464 and the physical address space 462 are address spaces shared by the first processor 310 and the second processor 320. Therefore, the second processor 320 can also execute the same OS as the first processor 310. When the OS is an SMP (Symmetric Multiprocessing) type OS, the control unit 52 can execute the OS in parallel.

  FIG. 6 shows an example of an operation sequence in the control unit 52. This flow is started when a power button as a part of the operation input unit 47 is turned on.

  The first processor 310 reads the initialization code from the system memory 57 and executes it (step S602). Specifically, the first processor 310 is hardware reset when the power is turned on, and when the reset is released, a predetermined address of the system memory 57, for example, the initial address of the initialization code is changed to the first address. Set to the program counter of the processor 310. The first processor 310 starts reading an instruction from the address, and sequentially reads and executes the instruction of the initialization code from the system memory 57. The first processor 310 executes hardware initialization, stack pointer setting, and the like according to the initialization code.

  Further, the first processor 310 generates a variable section in the SDRAM 58 from the data section and the BSS section of the OS image according to the initialization code, and initializes it. The first processor 310 does not transfer a portion whose value is not changed by execution of the OS to the SDRAM 58. For example, text sections are not transferred to SDRAM 58.

  Note that the first processor 310 may maintain the reset state of the second processor 320 by outputting a reset signal to the second processor 320 while performing the above processing. The first processor 310 may release the reset state of the second processor 320 after executing the initialization process. The operation for releasing the reset state of the second processor 320 will be described later.

  Subsequently, the first processor 310 jumps to the address in the system memory 57 where the OS startup routine is stored, and starts the execution of the OS (step S604). Specifically, the first processor 310 sequentially reads OS instructions from the system memory 57 and starts executing the OS.

  When the first processor 310 executes the OS, the units of the camera unit 30, the lens unit 20, and the light emitting unit 60 operate. For example, when the user presses the release button, a still image capturing operation is executed. When the moving image shooting button is operated, a moving image capturing operation is executed. When the user presses the playback button, an operation of playing back still image data or moving image data is executed. When the user presses the setting button, an operation for setting the imaging device 10 is executed.

  The operation of the second processor 320 will be described. When the reset of the second processor 320 is released, the second processor 320 reads the initialization code for the second processor 320 from the system memory 57 and executes it, as with the first processor 310 (step S622). Note that the reset release of the second processor 320 may be controlled by the first processor 310. The second processor 320 executes hardware initialization, stack pointer setting, and the like in accordance with the initialization code for the second processor 320. The operation of reading out and executing an instruction from the system memory 57 is the same as that of the first processor 310, and thus description thereof is omitted.

  Subsequently, the second processor 320 transfers the OS stored in the system memory 57 to the SDRAM 58 according to the OS transfer code included in the initialization code (step S624). Specifically, the second processor 320 transfers the OS stored in the system memory 57 to the SDRAM 58 page by page. More specifically, the second processor 320 transfers the text section to the SDRAM 58 page by page. Here, the second processor 320 transfers the text section to a memory area shared with the first processor 310 in the SDRAM 58.

  As described above, the first processor 310 sequentially reads and executes commands included in the OS from the system memory 57 when the imaging apparatus 10 is activated. On the other hand, the second processor 320 transfers the OS to a memory area shared with the first processor 310 in the SDRAM 58 in parallel with the execution of the instruction by the first processor 310.

  Subsequently, when the transfer of the OS is completed, the second processor 320 notifies the first processor 310 that the transfer has been completed (step S626). For example, the second processor 320 notifies the transfer completion by an interrupt. When the interrupt is completed, the second processor 320 transitions to an idle state (step S628).

  When receiving an interrupt from the second processor 320, the first processor 310 jumps to a predetermined address with respect to the interrupt and executes a switching code for switching mapping to the physical address space (step S606). When the first processor 310 executes the switching code, the address conversion table of the memory management unit 312 is changed, and the OS command is read from the SDRAM 58. As a result, the logical address space 412 of the first processor 310 is mapped to the physical address space 464 of the SDRAM 58.

  Subsequently, the first processor 310 performs control so that the second processor 320 can execute the OS (step S608). Specifically, when the OS is an SMP type OS, the second processor 320 is registered with the OS dispatcher. As a result, the second processor 320 waits for task assignment (step S630).

  Subsequently, the first processor 310 returns to the execution of the OS (step S610). In step S 610, the OS command is read from the physical address space 464 of the SDRAM 58 by the address conversion by the memory management unit 312. Further, when a task is assigned from the OS, the second processor 320 executes the task (step S632). Thereby, the first processor 310 and the second processor 320 can execute instructions of the OS in parallel.

  FIG. 7 shows an example of the operation flow of the first processor 310 when the initialization code is executed. This figure shows a part of the processing flow of step S602. It is assumed that processing such as hardware initialization and generation of a variable section on the SDRAM 58 is completed before this processing flow is executed. This processing flow is executed at the final stage of initialization, for example.

  The first processor 310 releases the reset state of the second processor 320 (step S702). As described with reference to FIG. 6, when the reset state of the second processor 320 is released, the second processor 320 starts execution of the initialization code and subsequently transfers the OS to the SDRAM 58. Start.

  Subsequently, the first processor 310 acquires a value indicating the position of the imaging mode switch for switching the imaging mode (step S704). For example, the first processor 310 accesses an IO address corresponding to the output of the imaging mode switch, and acquires a value indicating the position of the imaging mode switch. Subsequently, the first processor 310 determines the value and determines whether or not interval shooting is instructed (step S706). Interval imaging is an imaging method that repeats imaging at preset intervals.

  If interval shooting is not instructed, the OS startup routine is called (step S712), and the execution of the initialization code is terminated. In this case, in step S604 in FIG. 6, the first processor 310 executes the OS on the system memory 57, so that the imaging apparatus 10 can be started up at high speed. Therefore, for example, the possibility that the user misses a photo opportunity can be reduced.

  If interval shooting is instructed, the first processor 310 waits for the OS to be transferred to the SDRAM 58 without starting the execution of the OS (step S708). When an interrupt is received from the second processor 320, the allocation of the memory space is changed as in step S606 (step S710). When the process of step S710 is completed, the OS startup routine is called (step S712), and the execution of the initialization code is terminated. In this case, in step S604, the first processor 310 executes the OS on the SDRAM 58, so that instructions can be fetched at high speed. Accordingly, the OS can be operated at a higher speed than when operating on the system memory 57, and the imaging apparatus 10 can be operated at a higher speed.

  Note that interval shooting is an imaging method that acquires a group of images having different playback frame rates and display frame rates, unlike normal movie shooting. In interval shooting, for example, one frame of a subject image is shot at intervals of 3 minutes, and moving image data is generated. The generated moving image data is displayed at a normal frame rate such as 30 frames per second. Therefore, when moving image data is played back by default, it is played back in a time shorter than the time from the start to the end of interval shooting.

  Interval shooting can be said to be a shooting method that emphasizes a subject change over a relatively long period rather than a photo opportunity. In interval shooting, the subject is shot for a relatively long period of time, so it is possible to set many shooting parameters in advance, such as the shooting interval, the time until the interval shooting ends, and whether to use automatic exposure. Many. Therefore, there are few cases in which interval shooting starts immediately after the imaging device 10 is activated. On the other hand, it is desirable for the user to be able to set many shooting parameters with good response. According to this control, when the shooting mode is set to interval shooting, the OS is transferred to the SDRAM 58 and then executed. Therefore, it is possible to provide an environment in which the user can set shooting parameters with good response.

  As described above, the control unit 52 transfers the OS to the SDRAM 58 in preference to the execution of the command included in the OS when the imaging mode is an imaging mode that performs interval shooting that repeats imaging at a preset interval. When not in an imaging mode for performing interval shooting, a command included in the OS is executed in preference to the transfer of the program to the SDRAM 58. Note that examples of the imaging mode in which priority should be given to the transfer of the OS to the SDRAM 58 include a landscape mode for capturing a landscape in addition to interval shooting. That is, the control unit 52 acquires information indicating the imaging mode when the imaging apparatus 10 is started up, determines whether or not to prioritize the transfer of the OS to the SDRAM 58, and determines whether to transfer the OS. When priority is to be given, the OS is transferred to the SDRAM 58 in preference to the execution of instructions included in the program.

  Further, whether to give priority to the transfer of the OS to the SDRAM 58 may be determined based on the operation mode. For example, in the playback mode as a part of the operation mode, it is desirable that video data or the like can be played with good response, for example. Accordingly, the first processor 310 may prioritize the transfer of the OS to the SDRAM 58 when the playback button is pressed and the system is started in the playback mode, for example. That is, the control unit 52 acquires information indicating the operation mode of the imaging device 10 when the imaging device 10 is activated, and determines whether to prioritize transfer of the OS to the SDRAM 58 based on the acquired operation mode. When priority is given to the transfer of the OS, the OS may be transferred to the SDRAM 58 in preference to the execution of the instruction included in the OS.

  In this operation flow, the first processor 310 determines whether to prioritize the transfer of the OS to the SDRAM 58 before executing the OS on the system memory 57. However, a code for realizing an operation related to this operation flow may be included in the execution code of the OS. In this case, if the first processor 310 executes the OS and determines that the transfer of the OS to the SDRAM 58 should be prioritized, the execution of the second processor 320 may be prioritized over the first processor 310. Good. For example, execution of instructions in the first processor 310 may be stopped. Further, the second processor 320 may be operated with higher priority than the first processor 310 while continuing execution of instructions in the first processor 310.

  FIG. 8 shows a processing flow from the start to the end of the imaging apparatus 10. This flow is started when a power button as a part of the operation input unit 47 is turned on. This flow is executed by controlling each part of the imaging apparatus 10 mainly by the control unit 52. For example, until the OS is transferred to the SDRAM 58, the first processor 310 mainly controls each part of the imaging device 10, and after the OS is transferred to the SDRAM 58, the first processor 310 and the second processor 320 are Run as the subject. Therefore, unless otherwise specified, the control subject will be collectively referred to as the control unit 52.

  In step S800, the control unit 52 starts the initial setting. For example, the control unit 52 expands various parameters for controlling the imaging device 10 from the system memory 57 to the SDRAM 58. Then, the control unit 52 sets the operating conditions of each unit of the imaging device 10 based on the state of the operation input unit 47 including, for example, the imaging mode switch and the developed various parameters. For example, the imaging mode is set according to the position of the imaging mode switch. In addition, imaging conditions and image processing conditions are set according to the imaging mode. For example, when the imaging mode is a portrait mode, an edge enhancement parameter for applying a slightly weaker edge enhancement in image processing so that a relatively close exposure value is set so that a person stands out and a soft expression is expressed. Is set. In addition, a red-eye processing parameter for performing red-eye processing is set.

  Subsequently, in step S802, display on the display unit 53 is performed. For example, the control unit 52 controls the display control unit 55 to cause the display unit 53 to display setting information for identifying the imaging mode, imaging conditions, image processing conditions, and the like set in step S800. Therefore, the user can understand the currently set imaging mode, imaging conditions, image processing conditions, and the like through the display unit 53 at a glance. Here, since the OS starts up from the system memory 57 when the imaging device 10 is started up, the settings of the imaging device 10 can be presented to the user more quickly than when the OS is transferred to the SDRAM 58 and then started up. it can. For example, when the user turns on the power to simply confirm the current setting, the user can quickly confirm the setting.

  Subsequently, in step S804, the control unit 52 determines a user instruction to the operation input unit 47. When the user instruction is an instruction to execute various settings, the control unit 52 performs the instructed setting process (step S806). Examples of the setting process include a process for setting an imaging mode, a process for setting an imaging condition, a process for setting an image processing condition, and the like.

  Further, the control unit 52 determines whether or not the light emitting unit 60 should emit light based on the output of the photometric element 39 during imaging. In addition, when imaging conditions such as an aperture value and shutter speed are instructed by the user, the imaging conditions are set according to the user instruction.

  If it is determined in step S804 that the user instruction is an instruction relating to shooting execution, processing relating to imaging execution is performed (step S812). Examples of instructions related to shooting execution include operations on a live view button, a moving image shooting button, and a release button. If the user instruction in step S804 is an instruction to execute image reproduction, reproduction processing is executed (step S822). Examples of the reproduction process include a process for displaying an image recorded on a recording medium as a thumbnail, a process for displaying an image instructed by a user, and the like.

  When the processes of step S806, step S812, and step S822 are completed, the process proceeds to step S808, and it is determined whether or not to turn off the power. For example, it is determined that the power is turned off when the power button is switched to the OFF position, or when there is no user instruction for a predetermined period after the power is turned on. If it is determined that the power is to be turned off, the operation is terminated. If it is determined that the power is not to be turned off, the process proceeds to step 804.

  3 to 8, the control unit 52 has been described as having two processors. However, the control unit 52 may have more than two processors. That is, the control unit 52 may have a plurality of processors. When the control unit 52 has three or more processors, one processor is applied as a processor for transferring the OS from the system memory 57 to the SDRAM 58, and the other two or more processors receive the OS command on the system memory 57. May be executed.

  3 to 8, particularly in FIG. 6, the case where the control unit 52 operates the SMP type OS is illustrated. However, the OS may be an AMP type. In this case, the second processor 320 may execute an OS or program different from the OS executed by the first processor 310 after transferring the OS for the first processor 310. For example, the second processor 320 may execute a program for encoding image data and a program for outputting data to a recording medium or an external device through the external connection IF 56.

  On the other hand, the first processor 310 may control the imaging operation in the imaging apparatus 10 by executing the OS. The first processor 310 may control operations related to the user IF, such as controlling display on the display unit 53. Examples of the control of the imaging operation include control of the lens unit 20, control of the drive control unit 59, and the light emitting unit 60. As described above, the first processor 310 that drives the OS from the system memory 57 is in charge of control that requires high-speed response, so that high-speed response can be provided to the user.

  FIG. 9 shows another example of an operation flow for transferring the OS to the SDRAM 58. In this example, the first processor 310 is responsible not only for executing the OS but also for transferring the OS from the system memory 57 to the SDRAM 58. For example, when the OS is a multitask OS, the SDRAM 58 is executed by a task different from the main task. Specifically, the first processor 310 executes a transfer task for transferring the OS from the system memory 57 to the SDRAM 58 while operating the OS on the system memory 57. The first processor 310 switches between the main task responsible for OS execution and the transfer task, and executes both tasks in parallel.

  This operation flow starts when the power button is turned on. First, the first processor 310 reads the initialization code from the system memory 57 and executes it (step S902). Specifically, the operation is the same as the operation in step S602 except for the processing for the second processor 320, such as releasing the reset of the second processor 320. In step S902, the first processor 310 performs initialization such as initialization of hardware, setting of a stack pointer, generation of a variable section on the SDRAM 58, and the like.

  Subsequently, the first processor 310 jumps to an address in the system memory 57 in which the OS startup routine is stored, and starts execution of the OS (step S904). Specifically, the first processor 310 sequentially reads OS instructions from the system memory 57 and starts executing the OS. Here, the task for executing the OS is called a main task.

  Here, as the processing in step S904, the first processor 310 generates a transfer task. Then, the first processor 310 starts the operation of the transfer task (step S922) and executes it in parallel with the processing of step S904 (step S924). Specifically, the first processor 310 executes the transfer task in the background while switching the task with the main task.

  Subsequently, when the transfer of the OS by the transfer task is completed, the first processor 310 notifies the main task that the transfer has been completed (step S926). For example, the transfer completion is notified by inter-task communication. When the notification is completed, the transfer task stops (step S928).

  When receiving a transfer completion notification in the main task, the first processor 310 executes a switching code for switching the mapping of the first processor 310 to the physical address space (step S906). Specifically, as in step S606, the address conversion table of the memory management unit 312 is changed. Then, the first processor 310 proceeds to step S908 and continues execution of the OS. In step S 908, the OS command is read from the physical address space 464 of the SDRAM 58 by address conversion by the memory management unit 312.

  In step S924, the first processor 310 may execute the transfer task with a lower priority than the main task. However, when the imaging mode is set to interval shooting, the transfer task may be executed with a higher priority than the main task. In addition, when the imaging mode is a landscape mode, the transfer task may be executed with a higher priority than the main task. As described above, the transfer task may be executed with the priority according to the imaging mode of the imaging apparatus 10. Note that DMA (Direct Memory Access) may be applied to the OS transfer.

  In the figure, the first processor 310 executes the main task and the transfer task. However, the first processor 310 may execute tasks other than the main task and the transfer task in parallel.

  In addition, the first processor 310 executes the OS and the process of transferring the OS to the SDRAM 58. In this case, the second processor 320 may operate an OS different from the OS executed by the first processor 310. The OS executed by the second processor 320 may provide a function different from the OS executed by the first processor 310.

  In the above description, the control unit 52 is assumed to be a multiprocessor. However, the control unit 52 may be a multi-core processor. The first processor core of the multi-core processor may execute the process of the first processor 310 described above, and the second processor core of the multi-core processor may execute the process of the second processor 320 described above.

  The control unit 52 may be a single processor. For example, when the control unit 52 has one processor that executes an OS, the processor may sequentially switch and execute a task that executes an OS command and a task that transfers the OS to the SDRAM 58.

  In the above description, the memory space of the control unit 52 is switched by address conversion by the memory management unit 312. However, the memory space may be switched by bank switching. That is, when the transfer of the OS to the SDRAM 58 is completed, the memory management unit 312 changes the memory space corresponding to the system memory 57 in which the OS is stored, among the memory spaces of the processor, by switching the bank. May be switched to the transferred memory space.

  Similarly, the system memory 57 is an external memory connected to the external bus. However, the system memory 57 may be an internal memory provided in the control unit 52. Further, a non-volatile memory for storing the OS transferred to the SDRAM 58 may be provided separately from the system memory 57.

  The processing described in relation to the imaging device 10 according to the present embodiment can be realized by causing each unit of the imaging device 10, for example, a processor or the like to operate according to a computer program. That is, the process can be realized by a so-called computer device. The computer device may load a computer program for controlling the execution of the above-described processing, operate according to the read computer program, and execute the processing. The computer device can load the computer program by reading a computer-readable recording medium storing the computer program.

  In the present embodiment, an example of the electronic apparatus has been described by taking up the imaging device 10. As imaging devices, entertainment such as interchangeable lens single-lens reflex cameras, compact digital cameras, mirrorless single-lens cameras, video cameras, mobile phones with imaging functions, portable information terminals with imaging functions, game devices with imaging functions, etc. A device having an imaging function, such as a device, a scanner, or a facsimile, can be applied. Further, the electronic device may be realized as an electronic image device that displays an image, such as an entertainment device such as a television, a video, a digital photo frame, a projector device, or a game device.

  As mentioned above, although this invention was demonstrated using embodiment, the technical scope of this invention is not limited to the range as described in the said embodiment. It will be apparent to those skilled in the art that various modifications or improvements can be added to the above-described embodiment. It is apparent from the scope of the claims that the embodiments added with such changes or improvements can be included in the technical scope of the present invention.

  The order of execution of each process such as operations, procedures, steps, and stages in the apparatus, system, program, and method shown in the claims, the description, and the drawings is particularly “before” or “prior to”. It should be noted that the output can be realized in any order unless the output of the previous process is used in the subsequent process. Regarding the operation flow in the claims, the description, and the drawings, even if it is described using “first”, “next”, etc. for convenience, it means that it is essential to carry out in this order. It is not a thing.

DESCRIPTION OF SYMBOLS 10 Imaging device, 11 Optical axis, 20 Lens unit, 21 Lens system, 22 Front lens, 23 Lens group, 26 Lens barrel, 27 Lens circuit board, 29 Lens mount, 30 Camera unit, 31 Camera mount, 32 Main mirror, 33 Focus plate, 34 Main mirror rotation axis, 35 Photometric optical system, 36 Image sensor, 37 Pentaprism, 38 Eyepiece optical system, 39 Photometric element, 40 Sub mirror, 41 Mount unit, 42 Focus unit, 43 Focal plane shutter, 47 Operation Input unit, 50 Camera processing unit, 51 Image processing unit, 52 Control unit, 53 Display unit, 54 Secondary battery, 55 Display control unit, 56 External connection IF, 57 System memory, 58 SDRAM, 59 Drive control unit, 60 Light emission Unit, 61 Light emitting part, 62 Reflector 63 Fresnel lens, 65 Battery, 66 Light emitting unit controller, 69 Mount unit, 71 Lens system controller, 72 Lens memory, 73 Lens driver, 310 First processor, 320 Second processor, 312, 322 Memory management unit, 314 324 execution unit, 316, 326 cache, 330 interrupt line, 410, 412, 420, 422 logical address space, 450, 452, 460, 462, 464 physical address space

Claims (14)

A non-volatile memory for storing the program;
A volatile memory having a faster reading speed than the nonvolatile memory;
A processor unit that sequentially reads out and executes instructions included in the program from the nonvolatile memory when the operation is started;
The processor unit transfers the program from the nonvolatile memory to the volatile memory in parallel with the execution of the instruction read from the nonvolatile memory, and is executed when the transfer to the nonvolatile memory is completed. An electronic device that switches a read destination of an instruction to be transferred from the nonvolatile memory to the volatile memory. When the transfer to the volatile memory is completed, the processor unit allocates a memory space corresponding to the nonvolatile memory in which the program is stored in the memory space of the processor unit in the volatile memory. The electronic device according to claim 1, wherein the electronic device is switched to a memory space to which the program is transferred. The processor unit is
A processor for executing the instructions;
When the transfer of the program to the volatile memory is completed, out of the logical memory space mapped to the processor, the memory space corresponding to the nonvolatile memory in which the program is stored is changed to the volatile memory. The electronic device according to claim 2, further comprising: a memory management unit that converts an address into a memory space to which the program in the volatile memory is transferred. The program is an operating system;
The electronic device according to any one of claims 1 to 3, wherein the processor unit sequentially reads and executes instructions included in the operating system from the nonvolatile memory when the electronic device is activated. An imaging unit;
The electronic device according to claim 4, wherein the program includes an instruction for the processor unit to control the imaging unit. A lens device;
The electronic apparatus according to claim 5, wherein the program includes an instruction for the processor unit to control one or more lenses included in the lens device. The processor unit acquires information indicating an operation mode of the electronic device when the electronic device is activated, and based on the operation mode acquired whether to prioritize transfer of the program to the volatile memory. The electronic device according to claim 5, wherein when the determination is to give priority to transfer of the program, the program is transferred to the volatile memory in preference to execution of an instruction included in the program. The processor unit acquires information indicating an imaging mode of the imaging unit when the electronic device is activated, and based on the imaging mode acquired whether to prioritize transfer of the program to the volatile memory. The electronic device according to claim 7, wherein when the determination is to give priority to transfer of the program, the program is transferred to the volatile memory in preference to execution of an instruction included in the program. When the imaging mode of the imaging unit is an imaging mode for performing interval shooting in which imaging is repeated at a preset interval, the processor unit prioritizes execution of an instruction included in the program and volatiles the program. The electronic device according to claim 8, wherein the instruction included in the program is executed in preference to the transfer of the program to the volatile memory, when the mode is not an imaging mode in which the interval shooting is performed. The processor unit includes a first processor and a second processor,
The first processor sequentially reads and executes instructions included in the operating system from the non-volatile memory when the electronic device is activated.
The said 2nd processor transfers the said operating system to the memory area shared with the said 1st processor among the said volatile memories in parallel with execution of the said instruction | indication by the said 1st processor. An electronic device according to any one of the above. The electronic device according to claim 10, wherein the processor unit is a multi-core processor, the first processor is a first processor core of the multi-core processor, and the second processor is a second processor core of the multi-core processor. machine. The processor unit has one processor that executes the operating system,
The operating system is a multitasking operating system;
The electronic device according to any one of claims 4 to 9, wherein the processor sequentially switches and executes a task for executing an instruction of the operating system and a task for transferring the operating system to the volatile memory. . The processor unit is
A processor;
When the transfer of the program to the volatile memory is completed, a memory space corresponding to the nonvolatile memory in which the program is stored in the memory space of the processor is changed in the volatile memory by bank switching. The electronic device according to claim 1, further comprising: a memory management unit that switches to a memory space to which the program is transferred. A step of sequentially reading out and executing instructions contained in the computer program stored in the nonvolatile memory from the nonvolatile memory when the operation is started;
Transferring the computer program from the non-volatile memory to a volatile memory having a higher read speed than the non-volatile memory in parallel with the execution of the instructions read from the non-volatile memory;
A program for causing a computer to execute a step of switching a read destination of an instruction to be executed from the nonvolatile memory to the volatile memory when the transfer to the nonvolatile memory is completed.

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