JP2013089616A - Crystalline laminate structure and manufacturing method thereof - Google Patents

Crystalline laminate structure and manufacturing method thereof Download PDF

Info

Publication number
JP2013089616A
JP2013089616A JP2011225629A JP2011225629A JP2013089616A JP 2013089616 A JP2013089616 A JP 2013089616A JP 2011225629 A JP2011225629 A JP 2011225629A JP 2011225629 A JP2011225629 A JP 2011225629A JP 2013089616 A JP2013089616 A JP 2013089616A
Authority
JP
Japan
Prior art keywords
crystal
layer
oxygen concentration
nitride semiconductor
semiconductor layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2011225629A
Other languages
Japanese (ja)
Other versions
JP2013089616A5 (en
Inventor
Kazuyuki Iizuka
和幸 飯塚
Yoshikatsu Morishima
嘉克 森島
Shinkuro Sato
慎九郎 佐藤
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Tamura Corp
Koha Co Ltd
Original Assignee
Tamura Corp
Koha Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Tamura Corp, Koha Co Ltd filed Critical Tamura Corp
Priority to JP2011225629A priority Critical patent/JP2013089616A/en
Priority to KR1020147012854A priority patent/KR20140085508A/en
Priority to CN201280050003.5A priority patent/CN103918061A/en
Priority to US14/351,535 priority patent/US9059077B2/en
Priority to PCT/JP2012/076517 priority patent/WO2013054916A1/en
Priority to EP12839912.8A priority patent/EP2768013A4/en
Priority to TW101137959A priority patent/TW201334221A/en
Publication of JP2013089616A publication Critical patent/JP2013089616A/en
Publication of JP2013089616A5 publication Critical patent/JP2013089616A5/ja
Pending legal-status Critical Current

Links

Images

Abstract

PROBLEM TO BE SOLVED: To provide a crystalline laminate structure in which a dislocation density of a top face of a nitride semiconductor layer on a GaOsubstrate is low, and to provide a manufacturing method thereof.SOLUTION: In one embodiment, a crystalline laminate structure 1 comprises: a GaOsubstrate 2; a buffer layer 3 which is arranged on the GaOsubstrate 2 and is made of an AlGaInN(0≤x≤1, 0≤y≤1, 0≤z≤1, x+y+z=1) crystal; and a nitride semiconductor layer 4 which is arranged on the buffer layer 3 and is made of an AlGaInN(0≤x≤1, 0≤y≤1, 0≤z≤1, x+y+z=1) crystal containing oxygen as an impurity. A region 4a with a thickness of 200 nm or more, which is on the GaOsubstrate 2 side of the nitride semiconductor layer 4, has an oxygen concentration of 1.0×10/cmor more.

Description

本発明は、結晶積層構造体及びその製造方法に関する。   The present invention relates to a crystal multilayer structure and a method for manufacturing the same.

従来、Ga基板、AlNバッファ層、及びGaN層からなる結晶積層構造体を含むLED素子が知られている(例えば、特許文献1参照)。特許文献1によれば、GaN層はAlNバッファ層上に1050℃の温度条件でGaN結晶を成長させることにより形成される。 2. Description of the Related Art Conventionally, an LED element including a crystal laminated structure including a Ga 2 O 3 substrate, an AlN buffer layer, and a GaN layer is known (see, for example, Patent Document 1). According to Patent Document 1, the GaN layer is formed by growing a GaN crystal on the AlN buffer layer under a temperature condition of 1050 ° C.

特開2006−310765号公報JP 2006-310765 A

しかし、特許文献1に記載された方法によれば、GaN結晶を1050℃という高温の条件で成長させるため、GaN層の酸素濃度が低くなる。そのため、GaN層の上面(AlNバッファ層と反対側の面)の転位密度が高くなり、結晶積層構造体を含む素子に縦方向の電圧を印加したときに低電圧領域でのリーク電流が発生する。   However, according to the method described in Patent Document 1, since the GaN crystal is grown at a high temperature of 1050 ° C., the oxygen concentration of the GaN layer is lowered. Therefore, the dislocation density on the upper surface of the GaN layer (the surface opposite to the AlN buffer layer) is increased, and a leakage current is generated in the low voltage region when a vertical voltage is applied to the element including the crystal multilayer structure. .

したがって、本発明の目的は、Ga基板上の窒化物半導体層の上面の転位密度が低い結晶積層構造体、及びその製造方法を提供することにある。 Accordingly, an object of the present invention is to provide a crystal laminated structure having a low dislocation density on the upper surface of a nitride semiconductor layer on a Ga 2 O 3 substrate, and a method for manufacturing the same.

本発明の一態様は、上記目的を達成するために、[1]〜[6]の結晶積層構造体、及び[7]〜[10]の結晶積層構造体の製造方法を提供する。   In order to achieve the above object, one embodiment of the present invention provides a crystal laminate structure according to [1] to [6] and a method for producing a crystal laminate structure according to [7] to [10].

[1]Ga基板と、前記Ga基板上のAlGaInN(0≦x≦1、0≦y≦1、0≦z≦1、x+y+z=1)結晶からなるバッファ層と、前記バッファ層上の、酸素を不純物として含むAlGaInN(0≦x≦1、0≦y≦1、0≦z≦1、x+y+z=1)結晶からなる窒化物半導体層と、を含み、前記窒化物半導体層の前記Ga基板側の200nm以上の厚さの領域の酸素濃度が1.0×1018/cm以上である、結晶積層構造体。 [1] From a Ga 2 O 3 substrate and an Al x Ga y In z N (0 ≦ x ≦ 1, 0 ≦ y ≦ 1, 0 ≦ z ≦ 1, x + y + z = 1) crystal on the Ga 2 O 3 substrate. And a nitride layer made of Al x Ga y In z N (0 ≦ x ≦ 1, 0 ≦ y ≦ 1, 0 ≦ z ≦ 1, x + y + z = 1) containing oxygen as an impurity on the buffer layer. A crystal laminated structure, wherein an oxygen concentration in a region having a thickness of 200 nm or more on the Ga 2 O 3 substrate side of the nitride semiconductor layer is 1.0 × 10 18 / cm 3 or more. .

[2]前記窒化物半導体層の前記Ga基板の反対側の表面における転位密度が1.0×10/cm未満である、前記[1]に記載の結晶積層構造体 [2] The crystal multilayer structure according to [1], wherein a dislocation density on the surface of the nitride semiconductor layer opposite to the Ga 2 O 3 substrate is less than 1.0 × 10 9 / cm 2.

[3]前記窒化物半導体層の前記Ga基板側の500nm以上の厚さの領域の酸素濃度が1.0×1018/cm以上である、前記[1]又は[2]に記載の結晶積層構造体。 [3] In the above [1] or [2], an oxygen concentration of a region having a thickness of 500 nm or more on the Ga 2 O 3 substrate side of the nitride semiconductor layer is 1.0 × 10 18 / cm 3 or more. The crystal laminated structure described.

[4]前記領域の酸素濃度が5.0×1018/cm以上である、前記[1]〜[3]のいずれか1つに記載の結晶積層構造体。 [4] The crystal multilayer structure according to any one of [1] to [3], wherein the oxygen concentration in the region is 5.0 × 10 18 / cm 3 or more.

[5]前記バッファ層の前記AlGaInN結晶はAlN結晶である、前記[1]〜[4]のいずれか1つに記載の結晶積層構造体。 [5] The crystal stacked structure according to any one of [1] to [4], wherein the Al x Ga y In z N crystal of the buffer layer is an AlN crystal.

[6]前記窒化物半導体層の前記AlGaInN結晶はGaN結晶である、前記[1]〜[5]のいずれか1つに記載の結晶積層構造体。 [6] The crystal stacked structure according to any one of [1] to [5], wherein the Al x Ga y In z N crystal of the nitride semiconductor layer is a GaN crystal.

[7]Ga基板上に第1のAlGaInN(0≦x≦1、0≦y≦1、0≦z≦1、x+y+z=1)結晶を成長させてバッファ層を形成する工程と、前記バッファ層上に第2のAlGaInN(0≦x≦1、0≦y≦1、0≦z≦1、x+y+z=1)結晶を成長させて窒化物半導体層を形成する工程と、を含み、前記窒化物半導体層を形成する工程において、初めに1000℃以下の第1の温度で前記第2のAlGaInN結晶を成長させ、その後、前記第1の温度よりも高い第2の温度で前記第2のAlGaInN結晶を成長させ、前記第1の温度で成長する前記第2のAlGaInN結晶の厚さが200nm以上である、結晶積層構造体の製造方法。 [7] A first Al x Ga y In z N (0 ≦ x ≦ 1, 0 ≦ y ≦ 1, 0 ≦ z ≦ 1, x + y + z = 1) crystal is grown on a Ga 2 O 3 substrate to form a buffer layer. And growing a second Al x Ga y In z N (0 ≦ x ≦ 1, 0 ≦ y ≦ 1, 0 ≦ z ≦ 1, x + y + z = 1) crystal on the buffer layer Forming the nitride semiconductor layer, and first growing the second Al x Ga y In z N crystal at a first temperature of 1000 ° C. or lower, Thereafter, the second at a second temperature higher than the first temperature Al x Ga y in z N was grown crystal, the second Al x growing in the first temperature Ga y in z N A method for producing a crystal laminated structure, wherein the crystal thickness is 200 nm or more.

[8]前記第1の温度で成長する前記第2のAlGaInN結晶の厚さが500nm以上である、前記[7]に記載の結晶積層構造体の製造方法。 [8] The method for producing a crystal stacked structure according to [7], wherein the thickness of the second Al x Ga y In z N crystal grown at the first temperature is 500 nm or more.

[9]前記第1のAlGaInN結晶はAlN結晶である、前記[7]又は[8]に記載の結晶積層構造体の製造方法。 [9] The method for producing a crystal stacked structure according to [7] or [8], wherein the first Al x Ga y In z N crystal is an AlN crystal.

[10]前記第2のAlGaInN結晶はGaN結晶である、前記[7]〜[9]のいずれか1つに記載の結晶積層構造体の製造方法。 [10] The method for manufacturing a crystal stacked structure according to any one of [7] to [9], wherein the second Al x Ga y In z N crystal is a GaN crystal.

本発明によれば、Ga基板上の窒化物半導体層の上面の転位密度が低い結晶積層構造体、及びその製造方法を提供することができる。 According to the present invention, it is possible to provide Ga 2 O 3 dislocation density of the upper surface of the nitride semiconductor layer on the substrate is low crystalline layered structure, and a manufacturing method thereof.

図1は、実施の形態に係る結晶積層構造体の断面図である。FIG. 1 is a cross-sectional view of a crystal multilayer structure according to an embodiment. 図2は、実施の形態の結晶積層構造体の製造工程順序の一例を表すグラフである。FIG. 2 is a graph showing an example of a manufacturing process sequence of the crystal laminated structure according to the embodiment. 図3は、実施例1に係る高酸素濃度層の厚さと窒化物半導体層の上面の転位密度との関係、及び高酸素濃度層の酸素濃度と窒化物半導体層の上面の転位密度との関係を示すグラフである。FIG. 3 shows the relationship between the thickness of the high oxygen concentration layer and the dislocation density on the top surface of the nitride semiconductor layer according to Example 1, and the relationship between the oxygen concentration in the high oxygen concentration layer and the dislocation density on the top surface of the nitride semiconductor layer. It is a graph which shows. 図4は、実施例2に係るLED素子の断面図である。FIG. 4 is a cross-sectional view of the LED element according to the second embodiment.

〔実施の形態〕
(結晶積層構造体の構造)
図1は、実施の形態に係る結晶積層構造体1の断面図である。結晶積層構造体1は、Ga基板2と、Ga基板2上のバッファ層3と、バッファ層3上の窒化物半導体層4を含む。
Embodiment
(Structure of crystal laminated structure)
FIG. 1 is a cross-sectional view of a crystal multilayer structure 1 according to an embodiment. The crystal stacked structure 1 includes a Ga 2 O 3 substrate 2, a buffer layer 3 on the Ga 2 O 3 substrate 2, and a nitride semiconductor layer 4 on the buffer layer 3.

Ga基板2は、β−Ga単結晶からなる。 The Ga 2 O 3 substrate 2 is made of a β-Ga 2 O 3 single crystal.

バッファ層3は、AlGaInN(0≦x≦1、0≦y≦1、0≦z≦1、x+y+z=1)結晶からなる。また、後述する窒化物半導体層4の高酸素濃度層4aを首尾よく形成するために、バッファ層3のGa基板2の上面の被覆率は、10〜90%であることが好ましく、例えば、バッファ層3は、図1に示されるように、アイランド状に形成される。 The buffer layer 3 is made of Al x Ga y In z N (0 ≦ x ≦ 1, 0 ≦ y ≦ 1, 0 ≦ z ≦ 1, x + y + z = 1) crystal. Further, in order to successfully form a high oxygen concentration layer 4a of the nitride semiconductor layer 4 to be described later, the coverage of the upper surface of the Ga 2 O 3 substrate 2 of the buffer layer 3 is preferably 10 to 90%, For example, the buffer layer 3 is formed in an island shape as shown in FIG.

また、バッファ層3は、AlGaInN結晶の中でも、特にAlN結晶(x=1、y=z=0)からなることが好ましい。バッファ層3がAlN結晶からなる場合、Ga基板2と窒化物半導体層4との密着性がより高まる。 The buffer layer 3 is preferably made of an AlN crystal (x = 1, y = z = 0), among Al x Ga y In z N crystals. When the buffer layer 3 is made of an AlN crystal, the adhesion between the Ga 2 O 3 substrate 2 and the nitride semiconductor layer 4 is further increased.

窒化物半導体層4は、バッファ層3に接触する高酸素濃度層4aと、高酸素濃度層4a上の低酸素濃度層4bを含む。窒化物半導体層4(高酸素濃度層4a及び低酸素濃度層4b)は、酸素を不純物として含むAlGaInN(0≦x≦1、0≦y≦1、0≦z≦1、x+y+z=1)結晶からなり、特に、結晶品質のよいGaN結晶(y=1、x=z=0)からなることが好ましい。窒化物半導体層4の厚さは、例えば、3μmである。 The nitride semiconductor layer 4 includes a high oxygen concentration layer 4a in contact with the buffer layer 3 and a low oxygen concentration layer 4b on the high oxygen concentration layer 4a. The nitride semiconductor layer 4 (high oxygen concentration layer 4a and low oxygen concentration layer 4b) is made of Al x Ga y In z N (0 ≦ x ≦ 1, 0 ≦ y ≦ 1, 0 ≦ z ≦ 1) containing oxygen as an impurity. , X + y + z = 1) crystal, particularly preferably a GaN crystal (y = 1, x = z = 0) with good crystal quality. The thickness of the nitride semiconductor layer 4 is 3 μm, for example.

窒化物半導体層4の上面(Ga基板2の反対側の表面)、すなわち低酸素濃度層4bの上面における転位密度は低く、結晶積層構造体1を含む素子に縦方向の電圧を印加したときに、低電圧領域におけるリーク電流の発生が抑えられる。特に、低酸素濃度層4bの上面における転位密度が1.0×10/cm未満である場合に、上記のリーク電流を実用可能なレベルに抑えることができる。 The dislocation density on the upper surface of the nitride semiconductor layer 4 (the surface opposite to the Ga 2 O 3 substrate 2), that is, the upper surface of the low oxygen concentration layer 4b is low, and a vertical voltage is applied to the element including the crystal multilayer structure 1 As a result, the occurrence of leakage current in the low voltage region can be suppressed. In particular, when the dislocation density on the upper surface of the low oxygen concentration layer 4b is less than 1.0 × 10 9 / cm 2 , the above leakage current can be suppressed to a practical level.

高酸素濃度層4aは、低酸素濃度層4bよりも酸素濃度が高く、1.0×1018/cm以上の酸素濃度を有する。また、高酸素濃度層4aの厚さは200nm以上である。高酸素濃度層4aを設けることにより、窒化物半導体層4の上面の転位密度が低減される。 The high oxygen concentration layer 4a has an oxygen concentration higher than that of the low oxygen concentration layer 4b and has an oxygen concentration of 1.0 × 10 18 / cm 3 or more. The thickness of the high oxygen concentration layer 4a is 200 nm or more. By providing the high oxygen concentration layer 4a, the dislocation density on the upper surface of the nitride semiconductor layer 4 is reduced.

また、窒化物半導体層4の上面の転位密度をより低減するためには、高酸素濃度層4aの酸素濃度は5.0×1018/cm以上であることが好ましく、高酸素濃度層4aの厚さは500nm以上であることが好ましい。 In order to further reduce the dislocation density on the upper surface of the nitride semiconductor layer 4, the oxygen concentration of the high oxygen concentration layer 4a is preferably 5.0 × 10 18 / cm 3 or more, and the high oxygen concentration layer 4a The thickness is preferably 500 nm or more.

なお、窒化物半導体層4の表面にピット(穴)を形成しないように、半導体結晶を最後に高温で成長させる必要があるため、酸素濃度が比較的低い低酸素濃度層4bが形成される。   Since the semiconductor crystal needs to be finally grown at a high temperature so as not to form pits (holes) on the surface of nitride semiconductor layer 4, low oxygen concentration layer 4b having a relatively low oxygen concentration is formed.

Ga基板2及び窒化物半導体層4(高酸素濃度層4a及び低酸素濃度層4b)は、Si等の導電型不純物を含んでもよい。 The Ga 2 O 3 substrate 2 and the nitride semiconductor layer 4 (the high oxygen concentration layer 4a and the low oxygen concentration layer 4b) may include a conductive impurity such as Si.

(結晶積層構造体の製造方法)
図2は、本実施の形態の結晶積層構造体の製造工程順序の一例を表すグラフである。図2の折れ線は時間の経過に伴う温度条件の変化を表す。
(Method for producing crystal laminated structure)
FIG. 2 is a graph showing an example of the manufacturing process sequence of the crystal laminated structure according to the present embodiment. The broken line in FIG. 2 represents a change in temperature condition with the passage of time.

まず、150℃に加熱した濃度98wt%のリン酸を用いて、Ga基板2に120分間の前処理を施す。この前処理により、Ga基板2の表面が約1000nmエッチングされる。 First, using phosphoric acid heated concentration 98 wt% to 0.99 ° C., subjected to a pretreatment Ga 2 O 3 substrate 2 to 120 minutes. By this pretreatment, the surface of the Ga 2 O 3 substrate 2 is etched by about 1000 nm.

次に、MOCVD(Metal Organic Chemical Vapor Deposition)装置のチャンバー内にGa基板2を搬送した後、チャンバー内の温度をT1まで上げる(ステップS1)。ここで、T1は350〜600℃であり、例えば、450℃である。 Next, after transporting the Ga 2 O 3 substrate 2 into the chamber of a MOCVD (Metal Organic Chemical Vapor Deposition) apparatus, the temperature in the chamber is raised to T1 (step S1). Here, T1 is 350-600 degreeC, for example, is 450 degreeC.

次に、チャンバー内の温度をT1に保持した状態で、Nの原料としてのNHガス、Gaの原料としてのトリメチルガリウム(TMG)、Alの原料としてのトリメチルアルミニウム(TMA)、及びInの原料としてのトリメチルインジウム(TMI)をチャンバー内に供給して、AlGaInN結晶をGa基板2上に成長させ、バッファ層3を形成する(ステップS2)。 Next, NH 3 gas as a raw material of N, trimethyl gallium (TMG) as a raw material of Ga, trimethyl aluminum (TMA) as a raw material of Al, and a raw material of In with the temperature in the chamber maintained at T1 Then, trimethylindium (TMI) is supplied into the chamber, and an Al x Ga y In z N crystal is grown on the Ga 2 O 3 substrate 2 to form the buffer layer 3 (step S2).

次に、チャンバー内の温度をT2まで上げる(ステップS3)。ここで、T2は1000℃以下であり、例えば、950℃である。T2が1000℃を超えた場合、高酸素濃度層4aの酸素濃度が低下するおそれが高い。   Next, the temperature in the chamber is raised to T2 (step S3). Here, T2 is 1000 ° C. or less, for example, 950 ° C. When T2 exceeds 1000 ° C., the oxygen concentration of the high oxygen concentration layer 4a is likely to decrease.

次に、チャンバー内の温度をT2に保持した状態で、NH、TMG、TMA、及びTMIをチャンバー内に供給して、AlGaInN結晶をバッファ層3上に成長させ、窒化物半導体層4の高酸素濃度層4aを形成する(ステップS4)。 Next, with the temperature in the chamber maintained at T2, NH 3 , TMG, TMA, and TMI are supplied into the chamber, and an Al x Ga y In z N crystal is grown on the buffer layer 3 to be nitrided. The high oxygen concentration layer 4a of the physical semiconductor layer 4 is formed (step S4).

次に、各原料ガスの供給を続けたまま、チャンバー内の温度をT3まで上げる(ステップS5)。ここで、T3はT2より高く、また、1000℃より高いことが好ましく、例えば、1050℃である。   Next, the temperature in the chamber is raised to T3 while continuing to supply each source gas (step S5). Here, T3 is higher than T2 and preferably higher than 1000 ° C., for example, 1050 ° C.

次に、チャンバー内の温度をT3に保持した状態でAlGaInN結晶の成長を続け、窒化物半導体層4の低酸素濃度層4bを形成する(ステップS6)。これにより、結晶積層構造体1が得られる。 Next, the growth of the Al x Ga y In z N crystal is continued with the temperature in the chamber kept at T3, and the low oxygen concentration layer 4b of the nitride semiconductor layer 4 is formed (step S6). Thereby, the crystal laminated structure 1 is obtained.

その後、チャンバー内の温度を下げ(ステップS7)、結晶積層構造体1をチャンバー内から取り出す。   Thereafter, the temperature in the chamber is lowered (step S7), and the crystal laminated structure 1 is taken out from the chamber.

(実施の形態の効果)
本実施の形態によれば、窒化物半導体層のGa基板側に酸素濃度の高い領域を設けることにより、窒化物半導体層の上面の転位密度が低い結晶積層構造体を形成することができる。このため、結晶積層構造体を用いてLED素子等の素子を形成する場合、低電圧領域におけるリーク電流の発生を抑えることができる。
(Effect of embodiment)
According to the present embodiment, by providing a region having a high oxygen concentration on the Ga 2 O 3 substrate side of the nitride semiconductor layer, a crystal stacked structure having a low dislocation density on the top surface of the nitride semiconductor layer can be formed. it can. For this reason, when forming elements, such as an LED element, using a crystal | crystallization laminated structure, generation | occurrence | production of the leakage current in a low voltage area | region can be suppressed.

実施例1において、実施の形態の結晶積層構造体1における高酸素濃度層4aの厚さと窒化物半導体層4の上面の転位密度との関係、及び高酸素濃度層4aの酸素濃度と窒化物半導体層4の上面の転位密度との関係を評価した。   In Example 1, the relationship between the thickness of the high oxygen concentration layer 4a and the dislocation density of the upper surface of the nitride semiconductor layer 4 in the crystal multilayer structure 1 of the embodiment, and the oxygen concentration of the high oxygen concentration layer 4a and the nitride semiconductor The relationship with the dislocation density on the upper surface of the layer 4 was evaluated.

高酸素濃度層4aに対応する高酸素濃度層の酸素濃度及び厚さの異なる12個の結晶積層構造体を用意して評価を行った。ここで、高酸素濃度層の酸素濃度は、1.0×1017/cm、1.0×1018/cm、又は5.0×1018/cmであり、厚さは、100nm、200nm、500nm、又は1000nmである。このうち、酸素濃度が1.0×1018/cm以上であり、かつ厚さが200nm以上である高酸素濃度層が、本発明の実施の形態の高酸素濃度層4aに相当する。 Twelve crystal laminated structures having different oxygen concentrations and thicknesses of the high oxygen concentration layer corresponding to the high oxygen concentration layer 4a were prepared and evaluated. Here, the oxygen concentration of the high oxygen concentration layer is 1.0 × 10 17 / cm 3 , 1.0 × 10 18 / cm 3 , or 5.0 × 10 18 / cm 3 , and the thickness is 100 nm. , 200 nm, 500 nm, or 1000 nm. Among these, the high oxygen concentration layer having an oxygen concentration of 1.0 × 10 18 / cm 3 or more and a thickness of 200 nm or more corresponds to the high oxygen concentration layer 4a of the embodiment of the present invention.

なお、酸素濃度が1.0×1017/cm、1.0×1018/cm、及び5.0×1018/cmの高酸素濃度層は、それぞれT2=1050℃、1000℃、及びT2=950℃の温度条件で形成されたものである。 Note that the high oxygen concentration layers having oxygen concentrations of 1.0 × 10 17 / cm 3 , 1.0 × 10 18 / cm 3 , and 5.0 × 10 18 / cm 3 have T2 = 1050 ° C. and 1000 ° C., respectively. , And T2 = 950 ° C.

なお、本実施例のいずれの結晶積層構造体においても、バッファ層3に対応するバッファ層はT1=450℃の温度条件で形成された厚さ5nmのAlN結晶膜であり、高酸素濃度層と低酸素濃度層4bに対応する低酸素濃度層はSiを含むGaN結晶膜であり、窒化物半導体層4に対応する窒化物半導体層の厚さ(高酸素濃度層の厚さと低酸素濃度層の厚さの合計)は3μmであり、低酸素濃度層はT3=1050℃の温度条件で形成された。   In any of the crystal stacked structures of this example, the buffer layer corresponding to the buffer layer 3 is an AlN crystal film having a thickness of 5 nm formed under a temperature condition of T1 = 450 ° C., and a high oxygen concentration layer and The low oxygen concentration layer corresponding to the low oxygen concentration layer 4b is a GaN crystal film containing Si, and the thickness of the nitride semiconductor layer corresponding to the nitride semiconductor layer 4 (the thickness of the high oxygen concentration layer and the low oxygen concentration layer). The total thickness was 3 μm, and the low oxygen concentration layer was formed under the temperature condition of T3 = 1050 ° C.

図3は、高酸素濃度層の厚さと窒化物半導体層の上面の転位密度との関係、及び高酸素濃度層の酸素濃度と窒化物半導体層の上面の転位密度との関係を示すグラフである。図3の縦軸は窒化物半導体層の上面の転位密度[/cm]を表し、横軸は高酸素濃度層の厚さ[nm]を表す。   FIG. 3 is a graph showing the relationship between the thickness of the high oxygen concentration layer and the dislocation density on the top surface of the nitride semiconductor layer, and the relationship between the oxygen concentration in the high oxygen concentration layer and the dislocation density on the top surface of the nitride semiconductor layer. . The vertical axis in FIG. 3 represents the dislocation density [/ cm] on the upper surface of the nitride semiconductor layer, and the horizontal axis represents the thickness [nm] of the high oxygen concentration layer.

図3中の○は、高酸素濃度層の酸素濃度が1.0×1017/cmである結晶積層構造体の測定値を表し、◇は高酸素濃度層の酸素濃度が1.0×1018/cmである結晶積層構造体の測定値を表し、◆は高酸素濃度層の酸素濃度が5.0×1018/cmである結晶積層構造体の測定値を表す。 3 represents the measured value of the crystal laminated structure in which the oxygen concentration of the high oxygen concentration layer is 1.0 × 10 17 / cm 3 , and ◇ indicates the oxygen concentration of the high oxygen concentration layer is 1.0 × is 10 18 / cm 3 represents the measure of the crystal multilayer structure, ◆ represents the measured value of the crystalline layered structure of oxygen concentration in the high oxygen concentration layer is 5.0 × 10 18 / cm 3.

図3に示されるように、高酸素濃度層の酸素濃度が高いほど窒化物半導体層の上面の転位密度が低い。また、高酸素濃度層の厚さが大きいほど窒化物半導体層の上面の転位密度が低い。特に、高酸素濃度層の酸素濃度が1.0×1018/cm以上、かつ厚さが200nm以上である場合、すなわち高酸素濃度層が高酸素濃度層4aに相当する場合に、窒化物半導体層の上面の転位密度が1.0×10/cm未満になり、その結晶積層構造体を含む素子に縦方向の電圧を印加したときにの低電圧領域におけるリーク電流の発生を効果的に抑えることができる。 As shown in FIG. 3, the higher the oxygen concentration in the high oxygen concentration layer, the lower the dislocation density on the upper surface of the nitride semiconductor layer. Further, the greater the thickness of the high oxygen concentration layer, the lower the dislocation density on the upper surface of the nitride semiconductor layer. In particular, when the oxygen concentration of the high oxygen concentration layer is 1.0 × 10 18 / cm 3 or more and the thickness is 200 nm or more, that is, when the high oxygen concentration layer corresponds to the high oxygen concentration layer 4a. Dislocation density on the upper surface of the semiconductor layer is less than 1.0 × 10 9 / cm 2, and it is effective in generating a leakage current in a low voltage region when a vertical voltage is applied to an element including the crystal stacked structure. Can be suppressed.

実施例2においては、実施の形態の結晶積層構造体1を用いて形成したLED素子に縦方向の電圧を印加したときの、低電圧領域におけるリーク電流の大きさを評価した。   In Example 2, the magnitude of the leakage current in the low voltage region when a voltage in the vertical direction was applied to the LED element formed using the crystal multilayer structure 1 of the embodiment was evaluated.

(LED素子の構造)
図4は、実施の形態の結晶積層構造体を用いて形成したLED素子の断面図である。LED素子100は、Ga基板12と、Ga基板12上のバッファ層13と、バッファ層13上のn−GaN層14と、n−GaN層14上の発光層15と、発光層15上のp−GaN層16と、p−GaN層16上のコンタクト層17と、コンタクト層17上のp型電極18と、Ga基板12のバッファ層13と反対側の面上のn型電極19とを有する。
(Structure of LED element)
FIG. 4 is a cross-sectional view of an LED element formed using the crystal laminated structure according to the embodiment. The LED element 100 includes a Ga 2 O 3 substrate 12, a buffer layer 13 on the Ga 2 O 3 substrate 12, an n-GaN layer 14 on the buffer layer 13, a light emitting layer 15 on the n-GaN layer 14, The p-GaN layer 16 on the light emitting layer 15, the contact layer 17 on the p-GaN layer 16, the p-type electrode 18 on the contact layer 17, and the surface of the Ga 2 O 3 substrate 12 opposite to the buffer layer 13. And the upper n-type electrode 19.

LED素子100は、Ga基板12側を光取り出し面とする発光素子である。n−GaN層14、発光層15、p−GaN層16、及びコンタクト層17から構成される積層体はメサ形状を有し、その側面はSiO膜20に覆われる。 The LED element 100 is a light emitting element having a light extraction surface on the Ga 2 O 3 substrate 12 side. The laminate composed of the n-GaN layer 14, the light emitting layer 15, the p-GaN layer 16, and the contact layer 17 has a mesa shape, and its side surface is covered with the SiO 2 film 20.

ここで、Ga基板12、バッファ層13、及びn−GaN層14は、実施の形態のGa基板2、バッファ層3、及び窒化物半導体層4に相当し、Ga基板2、バッファ層13、及びn−GaN層14の積層体が実施の形態の結晶積層構造体1に相当する。 Here, the Ga 2 O 3 substrate 12, the buffer layer 13, and the n-GaN layer 14 correspond to the Ga 2 O 3 substrate 2, the buffer layer 3, and the nitride semiconductor layer 4 of the embodiment, and Ga 2 O A stacked body of the three substrates 2, the buffer layer 13, and the n-GaN layer 14 corresponds to the crystal stacked structure 1 of the embodiment.

n−GaN層14は、高酸素濃度層14aと低酸素濃度層14bを含む。高酸素濃度層14a及び低酸素濃度層14bは、それぞれ実施の形態の高酸素濃度層4a及び低酸素濃度層4bに相当する。   The n-GaN layer 14 includes a high oxygen concentration layer 14a and a low oxygen concentration layer 14b. The high oxygen concentration layer 14a and the low oxygen concentration layer 14b correspond to the high oxygen concentration layer 4a and the low oxygen concentration layer 4b of the embodiment, respectively.

Ga基板12は、Siを含むn型のβ−Ga基板である。また、Ga基板12の厚さは400μmであり、主面の面方位は(101)である。 The Ga 2 O 3 substrate 12 is an n-type β-Ga 2 O 3 substrate containing Si. The thickness of the Ga 2 O 3 substrate 12 is 400 μm, and the plane orientation of the main surface is (101).

バッファ層13は、成長温度450℃で形成された厚さ5nmのAlN結晶膜である。   The buffer layer 13 is an AlN crystal film having a thickness of 5 nm formed at a growth temperature of 450 ° C.

高酸素濃度層14aは、成長温度950℃で形成されたSiを含むn型のGaN結晶膜である。高酸素濃度層14aは、Si濃度が2.0×1019/cmの厚さ10nmの下部領域と、Si濃度が5.0×1018/cmの厚さ1000nmの上部領域を含む。なお、Siの原料として、モノメチルシランガスガスを用いた。 The high oxygen concentration layer 14a is an n-type GaN crystal film containing Si formed at a growth temperature of 950 ° C. The high oxygen concentration layer 14a includes a lower region having a Si concentration of 2.0 × 10 19 / cm 3 and a thickness of 10 nm, and an upper region having a Si concentration of 5.0 × 10 18 / cm 3 and a thickness of 1000 nm. Note that monomethylsilane gas gas was used as a raw material for Si.

低酸素濃度層14bは、成長温度1050℃で形成された厚さ3μmのn型のGaN結晶膜である。低酸素濃度層14bは、濃度1.0×1018/cmのSiを含む。 The low oxygen concentration layer 14b is an n-type GaN crystal film having a thickness of 3 μm and formed at a growth temperature of 1050 ° C. The low oxygen concentration layer 14b contains Si having a concentration of 1.0 × 10 18 / cm 3 .

発光層15は、成長温度750℃で形成された3層の多重量子井戸構造と、その上の厚さ10nmのGaN結晶膜からなる。各多重量子井戸構造は、8nmのGaN結晶膜と厚さ2nmのInGaN結晶膜からなる。   The light emitting layer 15 is composed of a three-layer multiple quantum well structure formed at a growth temperature of 750 ° C. and a GaN crystal film having a thickness of 10 nm thereon. Each multiple quantum well structure is composed of an 8 nm GaN crystal film and a 2 nm thick InGaN crystal film.

p−GaN層16は、成長温度1000℃で形成された厚さ150nmのp型のGaN結晶膜である。p−GaN層16は、濃度5.0×1019/cmのMgを含む。なお、Mgの原料として、シクロペンタジエニルマグネシウムガスを用いた。 The p-GaN layer 16 is a 150-nm-thick p-type GaN crystal film formed at a growth temperature of 1000 ° C. The p-GaN layer 16 contains Mg having a concentration of 5.0 × 10 19 / cm 3 . Note that cyclopentadienyl magnesium gas was used as a raw material for Mg.

コンタクト層17は、成長温度1000℃で形成された厚さ10nmのp型のGaN結晶膜である。コンタクト層17は、濃度1.5×1020/cmのMgを含む。 The contact layer 17 is a 10-nm-thick p-type GaN crystal film formed at a growth temperature of 1000 ° C. The contact layer 17 contains Mg having a concentration of 1.5 × 10 20 / cm 3 .

また、比較例として、高酸素濃度層14aの代わりに成長温度1050℃で形成された厚さ3μmのn型のGaN結晶膜を用いたLED素子を用意した。なお、このGaN結晶膜は、LED素子100の高酸素濃度層14aと同じ濃度のSiを含む。   As a comparative example, an LED element using an n-type GaN crystal film having a thickness of 3 μm formed at a growth temperature of 1050 ° C. instead of the high oxygen concentration layer 14a was prepared. This GaN crystal film contains Si having the same concentration as that of the high oxygen concentration layer 14 a of the LED element 100.

(LED素子の評価)
LED素子100及び比較例のLEDをキャンタイプのステムにAgペーストを用いてそれぞれ実装し、電極間に2.0Vの電圧を印加したときの電流値を測定した。
(Evaluation of LED elements)
The LED element 100 and the LED of the comparative example were each mounted on a can-type stem using Ag paste, and the current value when a voltage of 2.0 V was applied between the electrodes was measured.

その結果、比較例のLEDにおける電流値が20μAであったのに対して、LED素子100における電流値は0.35μAであった。この結果から、LED素子100において、低電圧領域におけるリーク電流の発生が抑えられていることが確認された。   As a result, the current value in the LED of the comparative example was 20 μA, whereas the current value in the LED element 100 was 0.35 μA. From this result, it was confirmed that the generation of leakage current in the low voltage region is suppressed in the LED element 100.

以上、本発明の実施の形態及び実施例を説明したが、上記に記載した実施の形態及び実施例は特許請求の範囲に係る発明を限定するものではない。また、実施の形態及び実施例の中で説明した特徴の組合せの全てが発明の課題を解決するための手段に必須であるとは限らない点に留意すべきである。   While the embodiments and examples of the present invention have been described above, the embodiments and examples described above do not limit the invention according to the claims. It should be noted that not all combinations of features described in the embodiments and examples are necessarily essential to the means for solving the problems of the invention.

1…結晶積層構造体、 2…Ga基板、 3…バッファ層、 4…窒化物半導体層、 4a…高酸素濃度層、 4b…低酸素濃度層 1 ... crystalline layered structure, 2 ... Ga 2 O 3 substrate, 3 ... buffer layer, 4 ... nitride semiconductor layer, 4a ... high oxygen concentration layer, 4b ... low oxygen concentration layer

Claims (10)

Ga基板と、
前記Ga基板上のAlGaInN(0≦x≦1、0≦y≦1、0≦z≦1、x+y+z=1)結晶からなるバッファ層と、
前記バッファ層上の、酸素を不純物として含むAlGaInN(0≦x≦1、0≦y≦1、0≦z≦1、x+y+z=1)結晶からなる窒化物半導体層と、
を含み、
前記窒化物半導体層の前記Ga基板側の200nm以上の厚さの領域の酸素濃度が1.0×1018/cm以上である、
結晶積層構造体。
A Ga 2 O 3 substrate;
A buffer layer made of Al x Ga y In z N (0 ≦ x ≦ 1, 0 ≦ y ≦ 1, 0 ≦ z ≦ 1, x + y + z = 1) crystal on the Ga 2 O 3 substrate;
A nitride semiconductor layer made of Al x Ga y In z N (0 ≦ x ≦ 1, 0 ≦ y ≦ 1, 0 ≦ z ≦ 1, x + y + z = 1) crystal containing oxygen as an impurity on the buffer layer;
Including
The oxygen concentration of a region having a thickness of 200 nm or more on the Ga 2 O 3 substrate side of the nitride semiconductor layer is 1.0 × 10 18 / cm 3 or more;
Crystal laminated structure.
前記窒化物半導体層の前記Ga基板の反対側の表面における転位密度が1.0×10/cm未満である、
請求項1に記載の結晶積層構造体。
The dislocation density on the surface of the nitride semiconductor layer opposite to the Ga 2 O 3 substrate is less than 1.0 × 10 9 / cm 2 .
The crystal laminated structure according to claim 1.
前記窒化物半導体層の前記Ga基板側の500nm以上の厚さの領域の酸素濃度が1.0×1018/cm以上である、
請求項1又は2に記載の結晶積層構造体。
The oxygen concentration of a region having a thickness of 500 nm or more on the Ga 2 O 3 substrate side of the nitride semiconductor layer is 1.0 × 10 18 / cm 3 or more;
The crystal laminated structure according to claim 1 or 2.
前記領域の酸素濃度が5.0×1018/cm以上である、
請求項1〜3のいずれか1つに記載の結晶積層構造体。
The oxygen concentration in the region is 5.0 × 10 18 / cm 3 or more,
The crystal laminated structure according to any one of claims 1 to 3.
前記バッファ層の前記AlGaInN結晶はAlN結晶である、
請求項1〜4のいずれか1つに記載の結晶積層構造体。
The Al x Ga y In z N crystal of the buffer layer is an AlN crystal,
The crystal laminated structure according to any one of claims 1 to 4.
前記窒化物半導体層の前記AlGaInN結晶はGaN結晶である、
請求項1〜5のいずれか1つに記載の結晶積層構造体。
The Al x Ga y In z N crystal of the nitride semiconductor layer is a GaN crystal.
The crystal laminated structure according to any one of claims 1 to 5.
Ga基板上に第1のAlGaInN(0≦x≦1、0≦y≦1、0≦z≦1、x+y+z=1)結晶を成長させてバッファ層を形成する工程と、
前記バッファ層上に第2のAlGaInN(0≦x≦1、0≦y≦1、0≦z≦1、x+y+z=1)結晶を成長させて窒化物半導体層を形成する工程と、
を含み、
前記窒化物半導体層を形成する工程において、初めに1000℃以下の第1の温度で前記第2のAlGaInN結晶を成長させ、その後、前記第1の温度よりも高い第2の温度で前記第2のAlGaInN結晶を成長させ、
前記第1の温度で成長する前記第2のAlGaInN結晶の厚さが200nm以上である、
結晶積層構造体の製造方法。
A buffer layer is formed by growing a first Al x Ga y In z N (0 ≦ x ≦ 1, 0 ≦ y ≦ 1, 0 ≦ z ≦ 1, x + y + z = 1) crystal on a Ga 2 O 3 substrate. Process,
A second Al x Ga y In z N (0 ≦ x ≦ 1, 0 ≦ y ≦ 1, 0 ≦ z ≦ 1, x + y + z = 1) crystal is grown on the buffer layer to form a nitride semiconductor layer. Process,
Including
In the step of forming the nitride semiconductor layer, first, the second Al x Ga y In z N crystal is grown at a first temperature of 1000 ° C. or lower, and then a second temperature higher than the first temperature. Growing the second Al x Ga y In z N crystal at a temperature of
The second Al x Ga y In z N crystal grown at the first temperature has a thickness of 200 nm or more;
Manufacturing method of crystal laminated structure.
前記第1の温度で成長する前記第2のAlGaInN結晶の厚さが500nm以上である、
請求項7に記載の結晶積層構造体の製造方法。
The thickness of the second Al x Ga y In z N crystal grown at the first temperature is 500 nm or more;
The manufacturing method of the crystal laminated structure of Claim 7.
前記第1のAlGaInN結晶はAlN結晶である、
請求項7又は8に記載の結晶積層構造体の製造方法。
The first Al x Ga y In z N crystal is an AlN crystal;
The manufacturing method of the crystal laminated structure of Claim 7 or 8.
前記第2のAlGaInN結晶はGaN結晶である、
請求項7〜9のいずれか1つに記載の結晶積層構造体の製造方法。
The second Al x Ga y In z N crystal is a GaN crystal.
The manufacturing method of the crystal laminated structure as described in any one of Claims 7-9.
JP2011225629A 2011-10-13 2011-10-13 Crystalline laminate structure and manufacturing method thereof Pending JP2013089616A (en)

Priority Applications (7)

Application Number Priority Date Filing Date Title
JP2011225629A JP2013089616A (en) 2011-10-13 2011-10-13 Crystalline laminate structure and manufacturing method thereof
KR1020147012854A KR20140085508A (en) 2011-10-13 2012-10-12 Crystal layered structure and method for manufacturing same, and semiconductor element
CN201280050003.5A CN103918061A (en) 2011-10-13 2012-10-12 Crystal layered structure and method for manufacturing same, and semiconductor element
US14/351,535 US9059077B2 (en) 2011-10-13 2012-10-12 Crystal layered structure and method for manufacturing same, and semiconductor element
PCT/JP2012/076517 WO2013054916A1 (en) 2011-10-13 2012-10-12 Crystal layered structure and method for manufacturing same, and semiconductor element
EP12839912.8A EP2768013A4 (en) 2011-10-13 2012-10-12 Crystal layered structure and method for manufacturing same, and semiconductor element
TW101137959A TW201334221A (en) 2011-10-13 2012-10-15 Crystal layered structure and method for manufacturing same, and semiconductor element

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2011225629A JP2013089616A (en) 2011-10-13 2011-10-13 Crystalline laminate structure and manufacturing method thereof

Publications (2)

Publication Number Publication Date
JP2013089616A true JP2013089616A (en) 2013-05-13
JP2013089616A5 JP2013089616A5 (en) 2015-02-19

Family

ID=48533274

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2011225629A Pending JP2013089616A (en) 2011-10-13 2011-10-13 Crystalline laminate structure and manufacturing method thereof

Country Status (1)

Country Link
JP (1) JP2013089616A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2015164162A (en) * 2014-02-28 2015-09-10 株式会社タムラ製作所 semiconductor laminated structure and semiconductor element

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2004056098A (en) * 2002-05-31 2004-02-19 Koha Co Ltd Light emitting device and method of manufacture the same
JP2006310765A (en) * 2005-03-31 2006-11-09 Toyoda Gosei Co Ltd Method for forming low-temperature growing buffer layer, method for manufacturing light-emitting element, the light-emitting element and light-emitting device
JP2009016505A (en) * 2007-07-03 2009-01-22 Showa Denko Kk Group iii nitride compound semiconductor light emitting element
JP2009227480A (en) * 2008-03-19 2009-10-08 Sumitomo Seika Chem Co Ltd Method for producing gallium hydride gas and method for producing gallium nitride crystal
JP2010263007A (en) * 2009-04-30 2010-11-18 Sumitomo Electric Ind Ltd Method for fabricating wafer product and method for fabricating gallium nitride semiconductor photonic element

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2004056098A (en) * 2002-05-31 2004-02-19 Koha Co Ltd Light emitting device and method of manufacture the same
JP2006310765A (en) * 2005-03-31 2006-11-09 Toyoda Gosei Co Ltd Method for forming low-temperature growing buffer layer, method for manufacturing light-emitting element, the light-emitting element and light-emitting device
JP2009016505A (en) * 2007-07-03 2009-01-22 Showa Denko Kk Group iii nitride compound semiconductor light emitting element
JP2009227480A (en) * 2008-03-19 2009-10-08 Sumitomo Seika Chem Co Ltd Method for producing gallium hydride gas and method for producing gallium nitride crystal
JP2010263007A (en) * 2009-04-30 2010-11-18 Sumitomo Electric Ind Ltd Method for fabricating wafer product and method for fabricating gallium nitride semiconductor photonic element

Non-Patent Citations (2)

* Cited by examiner, † Cited by third party
Title
JPN6015011206; Tsung-Yen Tsai, 外4名: 'MOCVD Growth of GaN on Sapphire Using a Ga2O3 Interlayer' Journal of The Electrochemical Society Vol. 158, No. 11, 20111005, pp. H1172-H1178 *
JPN6015011207; Christof Mauder, 外8名: 'Mechanisms of impurity incorporation during MOVPE growth of m-plane GaN layers on LiAlO2' Physica Status Solidi C Vol. 8, No. 7-8, 20110517, pp. 2050-2052 *

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2015164162A (en) * 2014-02-28 2015-09-10 株式会社タムラ製作所 semiconductor laminated structure and semiconductor element

Similar Documents

Publication Publication Date Title
JP4724256B2 (en) Light emitting diode element and method for manufacturing the same
JP2001160627A (en) Group iii nitride compound semiconductor light emitting element
WO2012137781A1 (en) Semiconductor stacked body, method for manufacturing same, and semiconductor element
US20180182916A1 (en) Group iii nitride semiconductor light-emitting device and production method therefor
US20150155356A1 (en) Semiconductor laminate structure and semiconductor element
JP4424680B2 (en) Laminated structure of group III nitride semiconductor, manufacturing method thereof, semiconductor light emitting device, and manufacturing method thereof
WO2013054916A1 (en) Crystal layered structure and method for manufacturing same, and semiconductor element
JP5551131B2 (en) Manufacturing method of nitride semiconductor multilayer structure
JP5865271B2 (en) Crystal laminated structure and light emitting device
JP2005072310A (en) Method for manufacturing group iii nitride compound semiconductor
US10461214B2 (en) Method for producing group III nitride semiconductor light-emitting device
JP2013089616A (en) Crystalline laminate structure and manufacturing method thereof
JP2016082200A (en) Crystal laminate structure and manufacturing method thereof, and semiconductor device
JP5734362B2 (en) Semiconductor laminated structure and semiconductor element
WO2013180057A1 (en) Semiconductor layered structure and semiconductor element
WO2012137783A1 (en) Semiconductor laminate and process for production thereof, and semiconductor element
JP2013089617A (en) Crystalline laminate structure, manufacturing method thereof and semiconductor element
TWI398016B (en) Photoelectric semiconductor device having buffer layer of iii-nitride based semiconductor and manufacturing method thereof
JP2015019061A (en) Semiconductor stacked structure and semiconductor element
JP2017011149A (en) Semiconductor laminate structure and method for manufacturing the same, and semiconductor element
JP2009170542A (en) Epitaxial-wafer manufacturing method and epitaxial wafer
JP2015017034A (en) Semiconductor multilayer structure, and semiconductor element
JP2014187388A (en) Crystal laminate structure and light-emitting element
JP2015017033A (en) Semiconductor multilayer structure, and semiconductor element
JP2014123765A (en) Wafer product and gallium nitride-based semiconductor optical element

Legal Events

Date Code Title Description
A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20141009

A521 Written amendment

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20141225

A871 Explanation of circumstances concerning accelerated examination

Free format text: JAPANESE INTERMEDIATE CODE: A871

Effective date: 20141225

A975 Report on accelerated examination

Free format text: JAPANESE INTERMEDIATE CODE: A971005

Effective date: 20150313

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20150324

A521 Written amendment

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20150525

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20150616

A02 Decision of refusal

Free format text: JAPANESE INTERMEDIATE CODE: A02

Effective date: 20151110