JP2013084832A - Method of manufacturing nitride semiconductor structure - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a method of manufacturing a nitride semiconductor structure capable of growing a nitride semiconductor base material layer with high crystallinity which has a flat surface, at a high growth speed while suppressing deflection.SOLUTION: During a step for forming a third nitride semiconductor base material layer in a method of manufacturing a nitride semiconductor structure, V/III ratio is set to be 700 or less which is a ratio between a molal quantity of V group material gas that is supplied per a unit time at the time of growth of the third nitride semiconductor base material layer and a molal quantity of III group material gas that is supplied per unit time, and a pressure during growth of the third nitride semiconductor base material layer is set to be 26.6 kPa or more, with the growth speed of the third nitride semiconductor base material layer being set to be 2.5 μm/hour or more.

Description

  The present invention relates to a method for manufacturing a nitride semiconductor structure.

  Since the III-V compound semiconductor (group III nitride semiconductor) containing nitrogen has a band gap corresponding to the energy of light having a wavelength in the infrared to ultraviolet region, the wavelength in the infrared to ultraviolet region is changed. It is useful as a material for a light emitting element that emits light having a wavelength and a light receiving element that receives light having a wavelength in the region.

  In addition, group III nitride semiconductors have strong bonds between atoms constituting group III nitride semiconductors, high dielectric breakdown voltage, and high saturation electron velocity. Therefore, electronic devices such as high temperature resistance, high output, and high frequency transistors It is also useful as a material.

  Furthermore, group III nitride semiconductors are attracting attention as materials that are hardly harmful to the environment and are easy to handle.

  In order to produce a practical nitride semiconductor device using a group III nitride semiconductor, which is an excellent material as described above, a group III nitride semiconductor comprising a group III nitride semiconductor thin film on a predetermined substrate The layers need to be stacked to form a predetermined device structure.

  Here, as the substrate, it is most preferable to use a substrate made of a group III nitride semiconductor having a lattice constant or a thermal expansion coefficient capable of directly growing a group III nitride semiconductor on the substrate. As the substrate made of a nitride semiconductor, for example, a gallium nitride (GaN) substrate is preferably used.

  However, the GaN substrate is not practical because its size is currently as small as 2 inches in diameter and is very expensive.

  Therefore, at present, a sapphire substrate, a silicon carbide (SiC) substrate, or the like that has a large lattice constant difference and a large thermal expansion coefficient difference from the group III nitride semiconductor is used as a substrate for manufacturing a nitride semiconductor element.

  There is a lattice constant difference of about 16% between the sapphire substrate and GaN, which is a typical group III nitride semiconductor. Further, there is a lattice constant difference of about 6% between the SiC substrate and GaN. When such a large lattice constant difference exists between the substrate and the group III nitride semiconductor grown thereon, it is generally difficult to epitaxially grow a group III nitride semiconductor crystal on the substrate. It is. For example, when a GaN crystal is directly epitaxially grown on a sapphire substrate, there is a problem that a three-dimensional growth of the GaN crystal is inevitable and a GaN crystal having a flat surface cannot be obtained.

  Therefore, a so-called buffer layer for eliminating a lattice constant difference between the substrate and the group III nitride semiconductor is generally formed between the substrate and the group III nitride semiconductor. Yes.

For example, Patent Document 1 describes a method of growing a group III nitride semiconductor made of Al _x Ga _1-x N after forming a buffer layer of AlN on a sapphire substrate by MOVPE.

However, even in the method described in Patent Document 1, it is difficult to obtain an AlN buffer layer having a flat surface with good reproducibility. This is presumably because when an AlN buffer layer is formed by the MOVPE method, trimethylaluminum (TMA) gas and ammonia (NH ₃ ) gas used as source gases are easily reacted in the gas phase.

Therefore, in the method described in Patent Document 1, a high-quality group III nitride semiconductor composed of Al _x Ga _1-x N having a flat surface and a low defect density is reproducibly formed on an AlN buffer layer. It was difficult to grow well.

Further, for example, Patent Document 2 discloses a method of forming an Al _x Ga _1-x N (0 <x ≦ 1) buffer layer on a sapphire substrate by a high-frequency sputtering method in which a DC bias is applied.

However, the Group III nitride semiconductor formed on the Al _x Ga _1-x N (0 <x ≦ 1) buffer layer by the method described in Patent Document 2 is disclosed in paragraph [0004] of Patent Document 3 and Patent As described in paragraph [0004] of Document 4, it did not have excellent crystallinity.

  Therefore, Patent Document 3 proposes a method for heat-treating a buffer layer made of a group III nitride semiconductor formed by DC magnetron sputtering in an atmosphere of a mixed gas of hydrogen gas and ammonia gas. Document 4 proposes a method of forming a buffer layer made of a group III nitride semiconductor having a thickness of 50 Å or more and 3000 Å or less on a sapphire substrate heated to 400 ° C. or more by DC magnetron sputtering. .

  Patent Document 5 proposes a method of forming a buffer layer made of AlN columnar crystals on a sapphire substrate heated to 750 ° C. by high-frequency sputtering.

  Further, Patent Document 6 describes that in order to grow a group III nitride semiconductor with few crystal defects, a concavo-convex structure is provided on the substrate surface, and the group III nitride semiconductor is laterally grown thereon.

  Further, paragraphs [0043] and [0044] of Patent Document 7 describe that an isosceles triangle having a facet inclined to the main surface of the sapphire substrate 11 on an inclined surface on a substrate provided with an uneven structure. “Grow the GaN layer 12 to have a cross-sectional shape” and “Next, set the growth condition to a condition in which the lateral growth is dominant and continue the growth. A two-stage growth is described, which includes a step of “growing in a lateral direction until a flat surface parallel to the main surface of the sapphire substrate 11”.

Japanese Patent No. 3026087 Japanese Patent Publication No. 5-86646 Japanese Patent No. 3440873 Japanese Patent No. 3700492 JP 2008-34444 A Japanese Patent No. 3950471 JP 2006-352084 A

  In order to grow a high-quality group III nitride semiconductor with few crystal defects, a nitride semiconductor underlayer serving as the underlayer is required to have few crystal defects and high crystallinity.

  In recent years, in order to efficiently produce a high-quality group III nitride semiconductor, a nitride semiconductor underlayer having a flat surface and high crystallinity is suppressed at a high growth rate while suppressing warpage. There is a growing demand for growth.

  In view of the above circumstances, an object of the present invention is to provide a nitride semiconductor structure having a flat surface and a high crystallinity nitride semiconductor underlayer capable of growing at a high growth rate while suppressing warpage. It is to provide a manufacturing method.

  The present invention provides a step of preparing a substrate made of a trigonal corundum or hexagonal crystal having a concave portion and a convex portion provided between the concave portions on the surface, and a step of forming a nitride semiconductor intermediate layer on the substrate, A step of forming a first nitride semiconductor underlayer on the nitride semiconductor intermediate layer, a step of forming a second nitride semiconductor underlayer on the first nitride semiconductor underlayer, and a second nitride Forming a third nitride semiconductor underlayer on the oxide semiconductor underlayer by MOCVD, wherein the surface of the first nitride semiconductor underlayer has a first oblique facet surface and a first flat surface. The area ratio of the first oblique facet surface on the surface of the first nitride semiconductor underlayer is smaller than the area ratio of the first flat region, and the second nitride semiconductor underlayer Has a second oblique facet surface surrounding the convex part The lower surface of the third nitride semiconductor underlayer is in contact with the second oblique facet surface, and in the step of forming the third nitride semiconductor underlayer, per unit time during the growth of the third nitride semiconductor underlayer When the third nitride semiconductor underlayer is grown, the V / III ratio, which is the ratio of the molar amount of the supplied group V source gas and the molar amount of the group III source gas supplied per unit time, is 700 or less. Is a method of manufacturing a nitride semiconductor structure, in which the pressure of 26.6 kPa or more and the growth rate of the third nitride semiconductor underlayer is 2.5 μm / hour or more.

  Here, in the method for manufacturing a nitride semiconductor structure of the present invention, in the step of forming the third nitride semiconductor underlayer, it is preferable to supply hydrogen of less than 198 slm during the growth of the third nitride semiconductor underlayer. .

  According to the present invention, it is possible to provide a method for manufacturing a nitride semiconductor structure that can grow a nitride semiconductor underlayer having a flat surface and high crystallinity at a high growth rate while suppressing warpage. it can.

3 is a schematic cross-sectional view illustrating a part of the manufacturing process of the method for manufacturing the nitride semiconductor structure according to the first embodiment. FIG. FIG. 6 is a schematic cross sectional view illustrating another part of the manufacturing step of the method for manufacturing the nitride semiconductor structure according to the first embodiment. It is a typical enlarged plan view of an example of the surface of the board | substrate shown in FIG. It is a typical expanded sectional view along the BB line which passes along the center of the convex part shown in FIG. FIG. 6 is a schematic cross sectional view illustrating another part of the manufacturing step of the method for manufacturing the nitride semiconductor structure according to the first embodiment. FIG. 6 is a schematic cross sectional view illustrating another part of the manufacturing step of the method for manufacturing the nitride semiconductor structure according to the first embodiment. FIG. 6 is a schematic cross sectional view illustrating another part of the manufacturing step of the method for manufacturing the nitride semiconductor structure according to the first embodiment. FIG. 6 is a schematic cross sectional view illustrating another part of the manufacturing step of the method for manufacturing the nitride semiconductor structure according to the first embodiment. FIG. 6 is a schematic cross sectional view illustrating another part of the manufacturing step of the method for manufacturing the nitride semiconductor structure according to the first embodiment. It is typical sectional drawing for demonstrating the growth mode of each layer of the nitride semiconductor base layer. It is a typical enlarged plan view of an example of the surface of the 1st nitride semiconductor foundation layer. FIG. 6 is a schematic enlarged plan view of another example of the surface of the first nitride semiconductor underlayer. It is a typical expanded sectional view along BB of FIG. FIG. 6 is a schematic enlarged plan view of another example of the surface of the first nitride semiconductor underlayer. It is a typical enlarged plan view of an example of the surface of the 2nd nitride semiconductor foundation layer grown after formation of the 1st nitride semiconductor foundation layer. It is a typical expanded sectional view along BB of FIG. It is a typical enlarged plan view of another example of the surface of the 2nd nitride semiconductor foundation layer grown after formation of the 1st nitride semiconductor foundation layer. FIG. 3 is a schematic cross-sectional view of the nitride semiconductor light-emitting diode element according to the first embodiment. 2 is a schematic cross-sectional view of the light emitting device of Embodiment 1. FIG. 6 is a schematic cross-sectional view of a nitride semiconductor transistor element according to a second embodiment. FIG. (A) is a figure which shows the in-plane distribution of the layer thickness of an Example, (b) is a figure which shows the in-plane distribution of the layer thickness of a comparative example. (A) is a figure which shows the in-plane distribution of the sheet resistance of an Example, (b) is a figure which shows the in-plane distribution of the sheet resistance of a comparative example. It is a typical side view illustrating the measuring method of the curvature of the wafer of an Example and a comparative example. (A) and (b) are observation images of the surface morphology of the wafer of the example by a differential interference microscope (metal microscope), and (c) and (d) are crystal defects of the example wafer by EPD measurement. It is an observation image. (A) And (b) is the observation image by the differential interference microscope (metal microscope) of the surface morphology of the wafer of a comparative example, (c) and (d) are the crystal defects by the EPD measurement of the wafer of a comparative example. It is an observation image.

  Embodiments of the present invention will be described below. In the drawings of the present invention, the same reference numerals represent the same or corresponding parts.

<Crystal orientation of sapphire substrate and nitride semiconductor crystal>
The crystal system of the (AlGaIn) N-based nitride semiconductor crystal is usually a hexagonal crystal, and the crystal system of sapphire is a trigonal corundum, but can be expressed by a hexagonal notation. Therefore, in both the sapphire substrate and the nitride semiconductor crystal, the c-axis direction is [0001], the a1-axis direction is [-2110], the a2-axis direction is [1-210], and the a3-axis direction is [11]. −20], and the three directions of the a1 axis direction, the a2 axis direction, and the a3 axis direction are collectively expressed as an a axis direction or a <11-20> direction. Further, three directions perpendicular to and equivalent to the c-axis direction and the <11-20> direction are referred to as an m-axis direction (most representatively, the <1-100> direction).

  In addition, when expressing a crystal plane and a direction, it should be expressed by adding a bar on a required number, but since there are restrictions on expression means, in this specification, the required number is used. Instead of the expression with a bar on top, the symbol “-” is added in front of the required number. For example, according to the notation of crystallography, the reverse direction of 1 describes a bar on 1 as “−1” for convenience.

<Embodiment 1>
A method for manufacturing a nitride semiconductor structure according to the first embodiment, which is an example of a method for manufacturing a nitride semiconductor structure of the present invention, will be described below with reference to FIGS. In the nitride semiconductor structure manufacturing method of the present invention, it goes without saying that other steps may be included between the steps described later.

(Process for preparing the substrate)
First, as shown in the schematic cross-sectional view of FIG. 1, a step of preparing the substrate 1 is performed. Here, as the substrate 1, for example, a substrate 1 made of trigonal corundum or hexagonal crystal can be prepared. As the substrate 1 made of trigonal corundum or hexagonal crystal, for example, a substrate made of sapphire (Al ₂ O ₃ ) single crystal, AlN single crystal or GaN single crystal can be used.

  Further, the surface 40 of the substrate 1 may be a c-plane or a surface having an inclination of 5 ° or less with respect to the c-plane, and the direction of the inclination is, for example, the m (sub) axis (<1-100>). It may be only the direction, may be only the a (sub) axis (<11-20>) direction, or may be a direction in which both directions are combined. More specifically, as the substrate 1, the surface 40 of the substrate 1 is 0.15 ° to 0.00 ° in the direction from the c-plane (the normal is the c-axis plane) to the m (sub) axis <1-100> direction of the substrate. It is possible to prepare the one inclined by 35 °.

  In this specification, since the crystal direction of the substrate is different from the crystal direction of the nitride semiconductor layer on the substrate, “sub” is added to the crystal direction of the substrate, and “layer” is added to the crystal direction of the nitride semiconductor layer. ". Here, it is necessary to pay attention to the relationship between the crystal axis of the substrate and the crystal axis of the nitride semiconductor layer. When the substrate is a sapphire single crystal, the a (sub) axis direction of the substrate coincides with the m (layer) axis direction of the nitride semiconductor layer, and the m (sub) axis direction of the substrate corresponds to the a (sub) axis of the nitride semiconductor layer. (Layer) coincides with the axial direction. On the other hand, when the substrate is an AlN single crystal or a GaN single crystal, the a (sub) axis direction of the substrate coincides with the a (layer) axis direction of the nitride semiconductor layer, and the m (sub) axis direction of the substrate is This coincides with the m (layer) axis direction of the nitride semiconductor layer.

  Further, the diameter of the substrate 1 is not particularly limited, but can be, for example, 150 mm (about 6 inches). Conventionally, a substrate having a diameter of about 50.8 mm (2 inches) has been generally used as the substrate 1, but a large-diameter substrate is preferably used in order to increase productivity. However, when the large-diameter substrate 1 is used, strain accumulates after the nitride semiconductor layer is formed on the substrate 1, so that the substrate 1 and the surface of the nitride semiconductor layer are likely to be cracked. As will be described later, the present invention can suppress cracks in the substrate 1 and the surface of the nitride semiconductor layer even when the substrate 1 having a large diameter of 100 mm (about 4 inches) or more is used. .

  Next, as shown in the schematic cross-sectional view of FIG. 2, the concave portion 1 b and the convex portion 1 a provided between the concave portions 1 b are formed on the surface 40 of the substrate 1. Such convex portions 1a and concave portions 1b on the surface of the substrate 1 are formed by, for example, a patterning step for forming a mask for defining the planar arrangement of the convex portions 1a on the surface 40 of the substrate 1, and a mask formed by the patterning step. And the step of etching the surface 40 of the substrate 1 to form the recess 1b. Here, the patterning process can be performed by a general photolithography process. The etching process can be performed by, for example, a dry etching method or a wet etching method. However, in order for the shape of the convex portion 1a to have a shape having a tip portion which will be described later, it is preferable to perform by a dry etching method in which the shape of the convex portion 1a is easy to control.

  FIG. 3 shows a schematic enlarged plan view of an example of the surface of the substrate 1 shown in FIG. In the plan view of the surface of the substrate 1 shown in FIG. 3, the convex portions 1a having a circular planar shape are located at the vertices of the virtual triangle 1t, for example, and each of the three sides of the virtual triangle 1t is Arranged in the direction. In this example, the convex portions 1 a are arranged in the a (sub) axis direction (<11-20> direction) of the surface of the substrate 1 and + 60 ° with respect to the a (sub) axis direction of the surface of the substrate 1. Are arranged in a direction that makes an inclination of −60 ° with respect to the a (sub) axis direction of the surface of the substrate 1. In this specification, in a plan view of the surface of the substrate 1, a direction that makes an inclination of + 60 ° with respect to the a (sub) axis direction and a direction that makes an inclination of −60 ° with respect to the a (sub) axis direction. Are called u directions.

  Note that the center of the circular circle, which is the planar shape of the convex portion 1a, does not necessarily need to be completely coincident with the apex of the triangle 1t, and may be substantially coincident. Specifically, when the center of the circle is a deviation smaller than the radius of the circle, the first nitride semiconductor underlayer described later is more stably on the region of the recess 1b than on the region of the protrusion 1a. It tends to start growing. When the growth of the first nitride semiconductor underlayer further proceeds, the first nitride semiconductor underlayer at least surrounds the convex portion 1a outside the convex portion 1a with the convex portion 1a as the center, as will be described later. Six inclined facet surfaces tend to be formed.

  The planar shape on the bottom surface of the convex portion 1a is not limited to a circle, and may be a polygon such as a hexagon and / or a triangle, for example.

  Further, in a plan view of the surface of the substrate 1, the angle of each internal angle of the virtual triangle 1t where the convex portion 1a is arranged at the apex is preferably 50 ° or more and 70 ° or less. In this case, the first nitride semiconductor underlayer described later tends to start growing on the region of the recess 1b more stably than on the region of the protrusion 1a. When the growth of the first nitride semiconductor underlayer further proceeds, the first nitride semiconductor underlayer at least surrounds the convex portion 1a outside the convex portion 1a with the convex portion 1a as the center, as will be described later. Six inclined facet surfaces tend to be formed.

  Further, in the plan view of the surface of the substrate 1, the interval between the adjacent convex portions 1a is preferably 0.2 μm or more and 7 μm or less, and more preferably about 2 μm. When the interval between the adjacent convex portions 1a is 0.2 μm or more and 7 μm or less, there is a tendency that process problems are reduced. As problems in the process, for example, it takes a long dry etching time to increase the height of the convex portion 1a, and it is necessary to completely flatten the upper surface of the second nitride semiconductor underlayer described later. Problems include growing too long. In addition, in this specification, the space | interval of the adjacent convex part 1a means the shortest distance between the adjacent convex parts 1a.

  Further, in a plan view of the surface of the substrate 1, it is preferable that the diameter of the circular circle of the convex portion 1a is not less than 1/2 and not more than 3/4 of the interval between the adjacent convex portions 1a. For example, when the interval between the adjacent convex portions 1a is 2 μm, the diameter of the circular circle of the convex portion 1a is more preferably about 1.2 μm. When the diameter of the circular circle of the convex portion 1a is not less than 1/2 and not more than 3/4 of the interval between the adjacent convex portions 1a, particularly about 1.2 μm, the first nitride semiconductor below will be described below. The formation tends to start growing on the region of the concave portion 1b more stably than on the region of the convex portion 1a. When the growth of the first nitride semiconductor underlayer further proceeds, the first nitride semiconductor underlayer at least surrounds the convex portion 1a outside the convex portion 1a with the convex portion 1a as the center, as will be described later. Six inclined facet surfaces tend to be formed.

  Moreover, it is preferable that the height of the convex part 1a shall be 1/4 or more and 1 or less of the diameter of the circular circle of the convex part 1a. For example, when the diameter of the circular circle of the convex portion 1a is 1.2 μm, the height of the convex portion 1a is more preferably about 0.6 μm. In this case, the first nitride semiconductor underlayer described later tends to start growing on the region of the recess 1b more stably than on the region of the protrusion 1a. When the growth of the first nitride semiconductor underlayer further proceeds, the first nitride semiconductor underlayer at least surrounds the convex portion 1a outside the convex portion 1a with the convex portion 1a as the center, as will be described later. Six inclined facet surfaces tend to be formed.

  FIG. 4 shows a schematic enlarged cross-sectional view along the line BB passing through the center of the convex portion shown in FIG. As shown in FIG. 4, it is preferable that the convex part 1a is a shape provided with the front-end | tip part 1c in the cross sectional view which passes along the center of the convex part 1a in planar view of the surface of the board | substrate 1. FIG. In the present specification, the shape in which the convex portion 1a includes the tip portion 1c means that the upper surface of the convex portion 1a is not flat in a sectional view passing through the center of the convex portion 1a in a plan view of the surface of the substrate 1. It means that it has a shape. When the upper surface of the convex portion 1a is flat, a first nitride semiconductor underlayer described later may grow not only on the concave portion 1b but also on the flat upper surface of the convex portion 1a. On the other hand, when the convex portion 1a has a shape including the tip portion 1c, a first nitride semiconductor base layer described later grows from the concave portion 1b, and a second nitride semiconductor base layer described later grows continuously. It is considered that the region where the crystal defects are generated is limited because the association is performed above the tip portion 1c of the portion 1a, and the number of defects as a whole can be reduced.

Pretreatment of the surface of the substrate 1 can also be performed before formation of a nitride semiconductor intermediate layer described later. Examples of the pretreatment of the surface of the substrate 1 include, for example, RCA cleaning (dilute hydrofluoric acid aqueous solution (HF) treatment, ammonia (NH ₄ OH) + hydrogen peroxide (H ₂ O ₂ ) treatment, hydrochloric acid (HC1) + peroxide A process of hydrogen-termination of the surface of the substrate 1 by performing a hydrogen oxide (H ₂ O ₂ ) process and a cleaning process in which ultrapure water cleaning is sequentially performed) can be given. Thereby, it exists in the tendency which can laminate | stack the favorable crystalline nitride semiconductor intermediate | middle layer on the surface of the board | substrate 1 with sufficient reproducibility.

  Further, as another example of the pretreatment of the surface of the substrate 1, there is a treatment in which the surface of the substrate 1 is exposed to a nitrogen gas plasma. As a result, foreign substances such as organic substances and oxides attached to the surface of the substrate 1 tend to be removed, and the surface state of the substrate 1 tends to be adjusted. Particularly, when the substrate 1 is a sapphire substrate, the surface of the substrate 1 is nitrided by exposing the surface of the substrate 1 to plasma of nitrogen gas, and the nitride semiconductor intermediate layer is laminated on the surface of the substrate 1. Tends to be formed uniformly in the plane.

(Step of forming nitride semiconductor intermediate layer)
Next, as shown in the schematic cross-sectional view of FIG. 5, the nitride semiconductor intermediate layer 2 is formed on the surface of the substrate 1. Here, the nitride semiconductor intermediate layer 2 can be formed by, for example, a reactive sputtering method in which an Al target is sputtered in a mixed atmosphere of N ₂ and Ar.

As nitride semiconductor intermediate layer 2, for example, a layer made of a nitride semiconductor represented by the formula of Al _x0 Ga _y0 N (0 ≦ x0 ≦ 1, 0 ≦ y0 ≦ 1, x0 + y0 ≠ 0) can be stacked. Among these, as the nitride semiconductor intermediate layer 2, a layer made of a nitride semiconductor (aluminum nitride) represented by the formula of AlN or Al _x1 Ga _1-x1 N (0.5 <x1 ≦ 1) is laminated. preferable. In this case, the nitride semiconductor intermediate layer 2 having a good crystallinity composed of an aggregate of columnar crystals with aligned crystal grains extending in the normal direction of the surface of the substrate 1 tends to be obtained. The nitride semiconductor intermediate layer 2 may contain a trace amount of oxygen.

  The thickness of the nitride semiconductor intermediate layer 2 is preferably 5 nm or more and 100 nm or less. When the thickness of the nitride semiconductor intermediate layer 2 is less than 5 nm, the nitride semiconductor intermediate layer 2 may not sufficiently function as a buffer layer. When the thickness of the nitride semiconductor intermediate layer 2 exceeds 100 nm, the function as the buffer layer is not improved, and only the formation time of the nitride semiconductor intermediate layer 2 may be increased. Moreover, it is more preferable that the thickness of the nitride semiconductor intermediate layer 2 is 10 nm or more and 50 nm or less. In this case, the function of the nitride semiconductor intermediate layer 2 as a buffer layer tends to be exhibited uniformly in the plane. As an example of the nitride semiconductor intermediate layer 2, an AlN film slightly containing oxygen can be formed with a thickness of about 30 nm.

  The temperature of the substrate 1 when forming the nitride semiconductor intermediate layer 2 is preferably 300 ° C. or higher and 1000 ° C. or lower. When the temperature of the substrate 1 at the time of forming the nitride semiconductor intermediate layer 2 is less than 300 ° C., the nitride semiconductor intermediate layer 2 cannot cover the entire surface of the substrate 1, and one surface of the substrate 1 is not covered. The portion may be exposed from the nitride semiconductor intermediate layer 2. In addition, when the temperature of the substrate 1 when the nitride semiconductor intermediate layer 2 is stacked exceeds 1000 ° C., the migration of the raw material on the surface of the substrate 1 becomes too active, rather than an aggregate of columnar crystals. The nitride semiconductor intermediate layer 2 close to a single crystal film is formed, and the function of the nitride semiconductor intermediate layer 2 as a buffer layer may be reduced.

(Step of forming a nitride semiconductor underlayer)
Next, as shown in the schematic cross-sectional view of FIG. 6, below the first nitride semiconductor having the first oblique facet surface 3f and the first flat region 3c on the surface of the nitride semiconductor intermediate layer 2. The formation 3 is formed. Then, as shown in the schematic cross-sectional view of FIG. 7, the second nitride having the second oblique facet surface 4 r and the second flat region 4 c on the surface of the first nitride semiconductor underlayer 3. A semiconductor underlayer 4 is formed. Further, as shown in the schematic cross-sectional view of FIG. 8, the third nitride semiconductor bottom layer is in contact with the second oblique facet surface 4 r and the second flat region 4 c of the second nitride semiconductor foundation layer 4. The formation 5 is formed. As described above, the nitride semiconductor intermediate layer 2, the first nitride semiconductor base layer 3, the second nitride semiconductor base layer 4, and the third nitride semiconductor base layer 5 are laminated on the substrate 1 in this order. The nitride semiconductor structure of the first embodiment is manufactured.

  Here, the first nitride semiconductor underlayer 3, the second nitride semiconductor underlayer 4, and the third nitride semiconductor underlayer 5 are each formed by, for example, MOCVD (Metal Organic Chemical Vapor Deposition). They can be sequentially formed on the surface of the semiconductor intermediate layer 2.

More specifically, as shown in the schematic cross-sectional view of FIG. 9, first, the first nitride semiconductor underlayer 3 (for example, the thickness t) is mainly formed on the surface of the nitride semiconductor intermediate layer 2 in the recess 1b. ₃ = 300 nm), and then a second nitride semiconductor underlayer 4 (for example, a thickness t ₄ = 1800 nm) is formed on at least the surface of the first nitride semiconductor underlayer 3, and then A third nitride semiconductor underlayer 5 (for example, thickness t ₅ = 6000 nm) is formed on at least the surface of second nitride semiconductor underlayer 4.

[Growth mode of each layer of nitride semiconductor underlayer]
Next, referring to the schematic cross-sectional view of FIG. 10, the growth of each layer of the nitride semiconductor base layer until the third nitride semiconductor base layer 5 having few crystal defects and having a flat upper surface 5U is manufactured. The mode will be described.

First, the first nitride semiconductor foundation layer 3, the second nitride semiconductor foundation layer 4, and the third nitride semiconductor foundation layer 5 (hereinafter referred to as “the respective layers of the nitride semiconductor foundation layer”), respectively. Choose an appropriate growth mode and grow. Hereinafter, in this specification, the growth mode is defined for convenience as follows.
Two-dimensional growth mode: Growth mode in which a flat surface is easily obtained Three-dimensional growth mode: Growth mode in which oblique facet surfaces are easily formed 2.5-dimensional growth mode: Intermediate growth between two-dimensional growth mode and three-dimensional growth mode Mode [Relationship between Growth Mode and Growth Parameters of Nitride Semiconductor Underlayer]
Next, switching of the growth mode used for the growth of each layer of the nitride semiconductor underlayer includes (A) growth temperature, (B) growth pressure, (C) V / III ratio, and (D) substrate rotation speed, respectively. , And (E) by appropriately selecting the five growth parameters of the volume ratio of hydrogen gas to the total volume of the carrier gas.

  Specifically, it can be realized by at least one of the following growth parameters (A), (B), (C), (D) and (E) or a combination thereof. Here, as a result of diligent research conducted by the present inventors, it was possible to know the correlation between each of these three growth parameters and the growth mode of the nitride semiconductor underlayer.

(A) Growth temperature The higher the growth temperature, the easier it is to enter the two-dimensional growth mode, and the lower the growth temperature, the easier it is to enter the three-dimensional growth mode.

(B) Growth pressure The lower the growth pressure, the easier it is to enter the two-dimensional growth mode, and the higher the growth pressure, the easier it is to enter the three-dimensional growth mode.

(C) V / III ratio The smaller the V / III ratio, the more likely it becomes a two-dimensional growth mode, and the larger the V / III ratio, the easier it becomes a three-dimensional growth mode. The V / III ratio is a ratio between the molar amount of the group V source gas supplied per unit time during the growth of the nitride semiconductor underlayer and the molar amount of the group III source gas supplied per unit time. is there.

(D) The number of rotations of the substrate The higher the number of rotations per unit time of the substrate, the easier it is to enter the two-dimensional growth mode.

(E) The volume ratio of hydrogen gas to the total volume of carrier gas The smaller the volume ratio of hydrogen gas to the total volume of carrier gas, the more likely it becomes a two-dimensional growth mode, and the larger the volume ratio of hydrogen gas to the total volume of carrier gas. It tends to be a three-dimensional growth mode.

  Therefore, in order to form the third nitride semiconductor base layer 5 having a flat top surface 5U with few crystal defects and high crystallinity, first, the first nitride semiconductor base layer 3 has a flat surface. The growth is preferably performed in the “2.5-dimensional growth mode” which is an intermediate growth mode between the “two-dimensional growth mode” and the “three-dimensional growth mode” in which the oblique facet crystal plane appears preferentially.

  Thereby, the surface of the first nitride semiconductor underlayer 3 has the first oblique facet surface 3f and the first flat region 3c. Then, the area ratio of the first oblique facet surface 3f on the surface of each first nitride semiconductor foundation layer 3 is smaller than the area ratio of the first flat region 3c.

  The second nitride semiconductor underlayer 4 is grown in the “three-dimensional growth mode” so that the second oblique facet 4r is formed.

  Thereby, the surface of the second nitride semiconductor underlayer 4 has the second oblique facet surface 4r and the second flat region 4c. Then, the area ratio of the second oblique facet surface 4r in plan view of the surface of each second nitride semiconductor foundation layer 4 is larger than the area ratio of the second flat region 4c.

  Furthermore, the lower layer 5A and the upper layer 5B of the third nitride semiconductor underlayer 5 are grown in the “two-dimensional growth mode” in order to form the flat upper surface 5U by embedding the second oblique facet surface 4r. Is preferred.

  Thereby, the third nitride semiconductor underlayer 5 having few crystal defects and good crystallinity and having a flat upper surface 5U can be formed.

  That is, dislocations extending in the c (layer) axis direction of the nitride semiconductor layer by providing the first oblique facet surface 3f on the surface of the first nitride semiconductor underlayer 3 are oriented in the direction of the first oblique facet surface 3f. The number is reduced by bending it into

  Then, by providing the second oblique facet surface 4r having an area ratio larger than the area ratio of the second flat region 4c in the plan view of the surface of the second nitride semiconductor foundation layer 4, the c of the nitride semiconductor layer is provided. (Layer) Dislocations extending in the axial direction are bent in the direction of the second oblique facet 4r to further reduce the number.

  In this way, the nitride semiconductor layer having a flat surface is grown on the surface of the second nitride semiconductor underlayer 4 in which the number of dislocations extending in the c (layer) axis direction of the nitride semiconductor layer is reduced. By growing the third nitride semiconductor underlayer 5 in the promoted two-dimensional growth mode, the third nitride semiconductor underlayer 5 having few crystal defects and good crystallinity and having a flat upper surface 5U is formed. be able to.

  Summarizing the above results, the steps of forming the first nitride semiconductor foundation layer 3 and the second nitride semiconductor foundation layer 4 include the following (i), (ii), (iii), (iv) and Preferably, the process is performed so as to satisfy at least one condition selected from the group consisting of (v). As a result, cracks are unlikely to occur, and a nitride semiconductor underlayer having a narrow half-value width of the X-ray rocking curve tends to be obtained.

  (I) The growth temperature during the growth of the first nitride semiconductor underlayer 3 is set to be equal to or higher than the growth temperature during the growth of the second nitride semiconductor underlayer 4.

  (Ii) The pressure during the growth of the first nitride semiconductor underlayer 3 is set to be equal to or lower than the pressure during the growth of the second nitride semiconductor underlayer.

  (Iii) The V / III ratio of the gas supplied during the growth of the first nitride semiconductor underlayer 3 is set to be equal to or lower than the V / III ratio of the gas supplied during the growth of the second nitride semiconductor underlayer 4.

  (Iv) The rotational speed per unit time of the substrate 1 when the first nitride semiconductor underlayer 3 is grown is equal to or higher than the rotational speed per unit time of the substrate 1 when the second nitride semiconductor base layer 4 is grown. And

  (V) The volume ratio of the hydrogen gas to the total volume of the carrier gas during the growth of the first nitride semiconductor underlayer 3 is defined as the hydrogen gas relative to the total volume of the carrier gas during the growth of the second nitride semiconductor underlayer 4. Or less than the volume ratio.

  The steps of forming the first nitride semiconductor underlayer 3, the second nitride semiconductor underlayer 4, and the third nitride semiconductor underlayer 5 include the following (I), (II), (III) , (IV) and (V) are performed so as to satisfy at least one condition selected from the group consisting of (a), (b), (c), (d) and (e) It is preferably performed so as to satisfy at least one condition selected from the group. Thereby, cracks are unlikely to occur, and the third nitride semiconductor underlayer 5 having a flat upper surface 5U having a narrow half-value width of the X-ray rocking curve and good crystallinity tends to be obtained.

  (I) The growth temperature during the growth of the third nitride semiconductor underlayer 5 is set to be equal to or higher than the growth temperature during the growth of the first nitride semiconductor underlayer 3.

  (II) The pressure during the growth of the third nitride semiconductor underlayer 5 is set to be equal to or lower than the pressure during the growth of the first nitride semiconductor underlayer 3.

  (III) The V / III ratio of the gas supplied during the growth of the third nitride semiconductor underlayer 5 is set to be equal to or lower than the V / III ratio of the gas supplied during the growth of the first nitride semiconductor underlayer 3.

  (IV) The rotational speed per unit time of the substrate 1 when the third nitride semiconductor underlayer 5 is grown is equal to or higher than the rotational speed per unit time of the substrate 1 when the first nitride semiconductor base layer 3 is grown. And

  (V) The volume ratio of the hydrogen gas to the total volume of the carrier gas during the growth of the third nitride semiconductor underlayer 5 is defined as the hydrogen gas relative to the total volume of the carrier gas during the growth of the first nitride semiconductor underlayer 3. Or less than the volume ratio. The carrier gas here is a gas that comes out of the shower head.

  (A) The growth temperature during the growth of the third nitride semiconductor underlayer 5 is set to be equal to or higher than the growth temperature during the growth of the second nitride semiconductor underlayer 4.

  (B) The pressure during the growth of the third nitride semiconductor underlayer 5 is set to be equal to or lower than the pressure during the growth of the second nitride semiconductor underlayer 4.

  (C) The V / III ratio of the gas supplied during the growth of the third nitride semiconductor underlayer 5 is set to be equal to or lower than the V / III ratio of the gas supplied during the growth of the second nitride semiconductor underlayer 4.

  (D) The rotational speed per unit time of the substrate 1 when the third nitride semiconductor underlayer 5 is grown is equal to or higher than the rotational speed per unit time of the substrate 1 when the second nitride semiconductor base layer 4 is grown. And

  (E) The volume ratio of the hydrogen gas to the total volume of the carrier gas during the growth of the third nitride semiconductor underlayer 5 is defined as the hydrogen gas relative to the total volume of the carrier gas during the growth of the second nitride semiconductor underlayer 4. Or less than the volume ratio.

  Further, in the step of forming the third nitride semiconductor underlayer 5, the third nitride having a flat surface and high crystallinity is satisfied by satisfying all the following conditions (f) to (h): The semiconductor underlayer 5 can be grown at a high growth rate while suppressing warpage.

  (F) The V / III ratio of the gas supplied during the growth of the third nitride semiconductor underlayer 5 is set to 700 or less.

(G) The pressure during growth of the third nitride semiconductor underlayer 5 is set to 26.6 kPa or more.
(H) The growth rate of the third nitride semiconductor underlayer 5 is set to 2.5 μm / hour or more.

  Further, in the step of forming the third nitride semiconductor underlayer 5, by satisfying the following condition (k), the concentration of the group III source gas increases during the growth of the third nitride semiconductor underlayer 5. In addition, since the residence time of the group III source gas in the growth chamber of the MOCVD apparatus can be increased, the growth rate of the third nitride semiconductor underlayer 5 can be further increased. In addition to the above conditions (f), (g), (h) and (k), the growth rate of the third nitride semiconductor underlayer 5 is reduced by reducing the exhaust rate in the growth chamber of the MOCVD apparatus. There is a tendency to make it even larger.

(K) Hydrogen of less than 198 slm is supplied during the growth of the third nitride semiconductor underlayer 5.
[First Nitride Semiconductor Underlayer 3]
FIG. 11 shows a schematic enlarged plan view of an example of the surface of the first nitride semiconductor foundation layer 3. As shown in FIG. 11, the first nitride semiconductor foundation layer 3 has a first oblique facet surface 3f surrounding the convex portion 1a outside the convex portion 1a.

  The first oblique facet surface 3f surrounding one convex portion 1a and the first oblique facet surface 3f surrounding one other convex portion 1a are the first nitride semiconductor underlayer 3 first They are connected by a flat region 3c.

  The first oblique facet surface 3f of the first nitride semiconductor underlayer 3 is inclined while descending from the first flat region 3c of the first nitride semiconductor underlayer 3 toward the convex 1a of the substrate 1. .

  FIG. 12 shows a schematic enlarged plan view of another example of the surface of the first nitride semiconductor foundation layer 3. In the example shown in FIG. 12, almost the entire surface of the recess 1b of the substrate 1 is uniformly covered with the first flat region 3c of the first nitride semiconductor underlayer 3, and the first oblique facet 3f is convex. It is characterized in that it is slightly formed around the portion 1a.

  That is, in the example shown in FIG. 12, compared to the example shown in FIG. 11, the area ratio occupied by the first flat region 3 c on the surface of the first nitride semiconductor base layer 3 is the first oblique facet plane. It is larger than the area ratio occupied by 3f.

  FIG. 13 shows a schematic enlarged cross-sectional view along the line BB in FIG. The first nitride semiconductor underlayer 3 is selectively grown from a region above the recess 1 b of the substrate 1. Then, as the growth of the first nitride semiconductor underlayer 3 progresses, almost the entire surface of the region above the recess 1b of the substrate 1 is uniformly covered with the first flat region 3c of the first nitride semiconductor underlayer 3. In other words, the first facet surface 3 f is slightly formed around the convex portion 1 a of the substrate 1.

  FIG. 14 is a schematic enlarged plan view of another example of the surface of the first nitride semiconductor foundation layer 3. In the example shown in FIG. 14, a rough surface region 3 d is formed on the surface of the first nitride semiconductor foundation layer 3.

  Here, even when the first nitride semiconductor base layer 3 has a large layer thickness of, for example, 60 nm or more, the surface of the first nitride semiconductor base layer 3 in the region above the recess 1b of the substrate 1 The first flat region 3c and the rough surface region 3d rougher than the first flat region 3c are mixed. In this case, when the second nitride semiconductor underlayer 4 is grown on the surface of the rough surface region 3d, the surface of the second nitride semiconductor underlayer 4 tends to become a larger rough surface, and further grows thereon. There is a possibility that the surface of the third nitride semiconductor underlayer 5 to be made is difficult to flatten.

  Therefore, the first nitride semiconductor underlayer 3 is preferably grown under the condition that the area ratio of the rough surface region 3d occupying the surface of the first nitride semiconductor underlayer 3 is 5% or less. In this case, the second nitride semiconductor base layer 4 and the third nitride semiconductor base layer 5 grown on the surface of the first nitride semiconductor base layer 3 each have few crystal defects and good crystallinity. It tends to be a film.

[Second Nitride Semiconductor Underlayer 4]
FIG. 15 is a schematic enlarged plan view showing an example of the surface of the second nitride semiconductor foundation layer 4 grown after the formation of the first nitride semiconductor foundation layer 3. The second nitride semiconductor underlayer 4 has six second oblique facet surfaces 4r surrounding the convex portion 1a outside the convex portion 1a of the substrate 1.

  In the plan view shown in FIG. 15, two second oblique facet surfaces 4r appear in the a (sub) axis direction and are inclined at an angle of + 60 ° with respect to the a (sub) axis direction and a (sub) Two appear each in a direction inclined at an angle of −60 ° with respect to the axial direction (both are u directions) (this case is referred to as “case 1”).

  More specifically, of the six second oblique facet surfaces 4r, the two second surfaces appearing in the a (sub) axis direction in a plan view of the surface of the second nitride semiconductor underlayer 4 shown in FIG. The oblique facet 4r is inclined obliquely upward with respect to the a (sub) axis direction (<11-20> direction), and the second oblique facet 4r extends in the inclined direction.

  Similarly, in a plan view of the surface of the second nitride semiconductor underlayer 4, the direction inclined at an angle of + 60 ° with respect to the a (sub) axis direction and −60 with respect to the a (sub) axis direction. The second oblique facet surfaces 4r appearing in two directions inclined in an angle of ° (both in the u direction) are also inclined in an angle of + 60 ° with respect to the a (sub) axis direction and a (sub) Inclined upward with respect to the direction inclined at an angle of −60 ° with respect to the axial direction, and the second oblique facet surface 4r extends in the inclined direction.

  FIG. 16 shows a schematic enlarged cross-sectional view along the line BB in FIG. The second oblique facet surface 4r appearing in FIG. 16 is a surface that also appears in the depth direction of the cross section within the range where the second oblique facet surface 4r exists.

  The second oblique facet surface 4r surrounding one convex portion 1a and the second oblique facet surface 4r surrounding the other convex portion 1a are the upper surface 4c of the second nitride semiconductor underlayer 4. It is connected.

  Here, the six second oblique facet surfaces 4r surrounding the outer periphery of the convex portion 1a are inclined by extending obliquely upward from the convex portion 1a.

  FIG. 17 is a schematic enlarged plan view of another example of the surface of the second nitride semiconductor foundation layer 4 grown after the formation of the first nitride semiconductor foundation layer 3. In the example shown in FIG. 17, the convex portion 1 a on the surface of the substrate 1 is inclined in a direction inclined by + 30 ° with respect to the a (sub) axis direction and in a direction inclined by −30 ° with respect to the a (sub) axis direction. The positional relationship between the second oblique facet surface 4r and the second flat region 4c of the second nitride semiconductor underlayer 4 when arranged is shown (this case is referred to as “case 2”). ).

  When the second nitride semiconductor underlayer 4 is grown in the three-dimensional growth mode in which the six second oblique facet surfaces 4r are formed, the second oblique facet surface of the second nitride semiconductor underlayer 4 is formed. 4r and the second flat region 4c are easily affected by the arrangement of the convex portions 1a of the substrate 1, respectively.

  In case 2, in the plan view of the surface of the second nitride semiconductor underlayer 4, the shape of the second flat region 4c of the second nitride semiconductor underlayer 4 is a shape in which triangles are connected, After switching to the two-dimensional growth mode which is the growth mode of the third nitride semiconductor underlayer 5, the third nitride semiconductor underlayer 5 is formed on the second flat region 4c. Since the crystal defects in the second flat region 4 c of the second nitride semiconductor underlayer 4 tend to be inherited and propagated by the third nitride semiconductor underlayer 5, In the case of the case 1 in which the area of the second flat region 4c occupying the surface is smaller, the third nitride semiconductor underlayer 5 has a better crystalline film with fewer crystal defects than in the case 2. There is a tendency.

[Third nitride semiconductor underlayer 5]
The thickness of the third nitride semiconductor underlayer 5 is preferably at least twice the height of the convex portion 1a. For example, when the height of the convex part 1a is 0.6 μm, it is preferably 1.2 μm or more. When the thickness of the third nitride semiconductor foundation layer 5 is twice or more the height of the projection 1a, the third nitride semiconductor foundation layer 5 tends to embed the projection 1a. Therefore, the tendency of the upper surface 5U of the third nitride semiconductor underlayer 5 to become flat increases.

[Others]
As the first nitride semiconductor underlayer 3, the second nitride semiconductor underlayer 4, and the third nitride semiconductor underlayer 5, for example, Al _x2 Ga _y2 In _z2 N (0 ≦ x2 ≦ 1, A layer made of a group III nitride semiconductor represented by the formula of 0 ≦ y2 ≦ 1, 0 ≦ z2 ≦ 1, x2 + y2 + z2 ≠ 0) can be used. Moreover, it is preferable that the first nitride semiconductor underlayer 3, the second nitride semiconductor underlayer 4 and the third nitride semiconductor underlayer 5 have the same composition as materials and change only the growth conditions.

  Switching from the growth mode during the growth of the first nitride semiconductor underlayer 3 to the growth mode during the growth of the second nitride semiconductor underlayer 4 and the growth during the growth of the second nitride semiconductor underlayer 4 It is preferable to provide a growth interruption time of, for example, about 2 seconds to 60 seconds, and change the growth conditions during the switching from the mode to the growth mode during the growth of the third nitride semiconductor underlayer 5. The conditions may be changed continuously.

  As the first nitride semiconductor underlayer 3, the second nitride semiconductor underlayer 4, and the third nitride semiconductor underlayer 5, dislocations in the nitride semiconductor intermediate layer 2 made of aggregates of columnar crystals are respectively used. It is preferable to use a nitride semiconductor layer containing Ga as a group III element so as not to inherit crystal defects such as.

  In order to prevent the dislocations in the nitride semiconductor intermediate layer 2 from being taken over, it is necessary to loop the dislocations near the interface with the nitride semiconductor intermediate layer 2. When the group III nitride semiconductor is included, a dislocation loop is likely to occur. Therefore, by using the first nitride semiconductor underlayer 3, the second nitride semiconductor underlayer 4, and the third nitride semiconductor underlayer 5 made of a group III nitride semiconductor containing Ga, nitrides are used. There is a tendency that dislocations are looped and confined in the vicinity of the interface with the semiconductor intermediate layer 2 to prevent the dislocations from being handed over from the nitride semiconductor intermediate layer 2 to the second nitride semiconductor underlayer 4.

The first nitride semiconductor foundation layer 3, the second nitride semiconductor foundation layer 4 and the third nitride semiconductor foundation layer 5 are preferably undoped, but the first nitride semiconductor foundation layer 3, The second nitride semiconductor underlayer 4 and the third nitride semiconductor underlayer 5 may each be n-type doped. In the case of n-type doping, the n-type dopant may be doped in the range of 1 × 10 ¹⁷ cm ^{−3 to} 1 × 10 ¹⁹ cm ⁻³ .

  As the n-type dopant, for example, at least one selected from the group consisting of silicon, germanium and tin can be used, and among these, silicon is preferably used. When silicon is used for the n-type dopant, it is preferable to use silane gas or disilane gas as the n-type doping gas.

  The temperature of the substrate 1 during the growth of each of the first nitride semiconductor underlayer 3, the second nitride semiconductor underlayer 4, and the third nitride semiconductor underlayer 5 is 800 ° C. or higher and 1250 ° C. or lower. It is more preferable that the temperature is 900 ° C. or higher and 1150 ° C. or lower. When the temperature of the substrate 1 during the growth of each of the first nitride semiconductor foundation layer 3, the second nitride semiconductor foundation layer 4 and the third nitride semiconductor foundation layer 5 is 800 ° C. or more and 1250 ° C. or less, In particular, when the temperature is 900 ° C. or higher and 1150 ° C. or lower, the first nitride semiconductor underlayer 3, the second nitride semiconductor underlayer 4, and the third nitride semiconductor underlayer excellent in crystallinity with few crystal defects. 5 tends to grow.

(Manufacturing method of nitride semiconductor light-emitting diode element)
Hereinafter, a method for manufacturing the nitride semiconductor light-emitting diode element according to the first embodiment, which is an example of the method for manufacturing a nitride semiconductor element of the present invention, will be described with reference to FIG. The nitride semiconductor light-emitting diode element according to the first embodiment is characterized by being manufactured using the nitride semiconductor structure according to the first embodiment. In the following description, it goes without saying that other steps may be included between the steps described later.

  First, n-type nitride semiconductor contact layer 7 is formed on flat upper surface 5U of third nitride semiconductor base layer 5 of the nitride semiconductor structure of Embodiment 1 manufactured as described above, for example, by MOCVD. To do.

The n-type nitride semiconductor contact layer 7 is, for example, a group III represented by the formula of Al _x3 Ga _y3 In _z3 N (0 ≦ x3 ≦ 1, 0 ≦ y3 ≦ 1, 0 ≦ z3 ≦ 1, x3 + y3 + z3 ≠ 0). A layer formed by doping an n-type dopant with a layer made of a nitride semiconductor can be formed.

In particular, the n-type nitride semiconductor contact layer 7 is made of Al _x4 Ga _1-x4 N (0 ≦ x4 ≦ 1, preferably 0 ≦ x4 ≦ 0.5, more preferably 0 ≦ x4 ≦ 0.1). The nitride semiconductor layer is preferably a group III nitride semiconductor represented by the formula in which silicon is doped as an n-type dopant.

The doping concentration of the n-type dopant into the n-type nitride semiconductor contact layer 7 is preferably 5 × 10 ¹⁷ cm ⁻³ or more and 5 × 10 ¹⁹ cm ⁻³ or less. In this case, good ohmic contact between n-type nitride semiconductor contact layer 7 and n-side electrode 20 is maintained, cracking in n-type nitride semiconductor contact layer 7 is suppressed, and n-type nitride semiconductor is maintained. There is a tendency that good crystallinity of the contact layer 7 can be maintained.

  Next, n-type nitride semiconductor cladding layer 9 is formed on the surface of n-type nitride semiconductor contact layer 7 by, for example, MOCVD.

The n-type nitride semiconductor clad layer 9 is, for example, a group III represented by the formula Al _x5 Ga _y5 In _z5 N (0 ≦ x5 ≦ 1, 0 ≦ y5 ≦ 1, 0 ≦ z5 ≦ 1, x5 + y5 + z5 ≠ 0). A layer formed by doping an n-type dopant with a layer made of a nitride semiconductor can be formed. Further, the n-type nitride semiconductor clad layer 9 may have a structure in which a plurality of nitride semiconductor layers made of a group III nitride semiconductor are heterojunction or a superlattice structure.

  The thickness of n-type nitride semiconductor cladding layer 9 is not particularly limited, but is preferably 0.005 μm or more and 0.5 μm or less, and more preferably 0.005 μm or more and 0.1 μm or less.

The doping concentration of the n-type dopant into the n-type nitride semiconductor cladding layer 9 is preferably 1 × 10 ¹⁷ cm ⁻³ or more and 1 × 10 ²⁰ cm ⁻³ or less, and preferably 1 × 10 ¹⁸ cm ⁻³ or more and 1 It is more preferable that it is 10 < ¹⁹ > cm <^-3> or less. In this case, the crystallinity of the n-type nitride semiconductor cladding layer 9 tends to be maintained and the operating voltage of the device can be reduced.

  Next, the nitride semiconductor active layer 11 is formed on the surface of the n-type nitride semiconductor clad layer 9 by MOCVD, for example.

In the case where the nitride semiconductor active layer 11 has a single quantum well (SQW) structure, for example, the nitride semiconductor active layer 11 is made of, for example, Ga _{1 -z6} In _z6 N (0 <z6 <0.4). A layer made of a group III nitride semiconductor represented by the formula can be used as a quantum well layer.

  The thickness of the nitride semiconductor active layer 11 is not particularly limited, but is preferably 1 nm or more and 10 nm or less, and more preferably 1 nm or more and 6 nm or less. When the thickness of the nitride semiconductor active layer 11 is 1 nm or more and 10 nm or less, particularly when it is 1 nm or more and 6 nm or less, the light emission output of the nitride semiconductor light emitting diode device 100 tends to be improved.

The nitride semiconductor active layer 11 is a single quantum well (SQW) in which a layer made of a group III nitride semiconductor represented by, for example, a formula Ga _{1 -z6} In _z6 N (0 <z6 <0.4) is used as a quantum well layer. ), The In composition and thickness of the nitride semiconductor active layer 11 can be controlled so that the emission wavelength of the nitride semiconductor light emitting diode element 100 becomes a desired emission wavelength.

However, if the temperature of the substrate 1 at the time of forming the nitride semiconductor active layer 11 is low, the crystallinity may be deteriorated. On the other hand, if the temperature of the substrate 1 at the time of forming the nitride semiconductor active layer 11 is high, the sublimation of InN is performed. Becomes prominent, the efficiency of incorporation of In into the solid phase is reduced, and the In composition may fluctuate. Therefore, a nitride semiconductor activity having a single quantum well (SQW) structure in which a layer made of a group III nitride semiconductor represented by the formula Ga _{1 -z6} In _z6 N (0 <z6 <0.4) is used as a well layer The temperature of the substrate 1 when forming the layer 11 is preferably 700 ° C. or higher and 900 ° C. or lower, and more preferably 750 ° C. or higher and 850 ° C. or lower.

Further, as the nitride semiconductor active layer 11, for example, a quantum well layer made of a group III nitride semiconductor represented by a formula Ga _{1 -z6} In _z6 N (0 <z6 <0.4) and a quantum well layer Quantum barrier layer made of a group III nitride semiconductor represented by the formula of Al _x7 Ga _y7 In _z7 N (0 ≦ x7 ≦ 1, 0 ≦ y7 ≦ 1, 0 ≦ z7 ≦ 1, x7 + y7 + z7 ≠ 0) And having a multiple quantum well (MQW) structure in which one layer is stacked alternately. The above quantum well layer and / or quantum barrier layer may be doped with an n-type or p-type dopant.

  Next, a p-type nitride semiconductor cladding layer 13 is formed on the surface of the nitride semiconductor active layer 11 by, for example, MOCVD.

The p-type nitride semiconductor clad layer 13 is, for example, a group III represented by the formula of Al _x8 Ga _y8 In _z8 N (0 ≦ x8 ≦ 1, 0 ≦ y8 ≦ 1, 0 ≦ z8 ≦ 1, x8 + y8 + z8 ≠ 0). A layer in which a nitride semiconductor is doped with a p-type dopant can be stacked. In particular, the p-type nitride semiconductor cladding layer 13 is a group III nitride represented by the formula of Al _x8 Ga _1-x8 N (0 <x8 ≦ 0.4, preferably 0.1 ≦ x8 ≦ 0.3). It is preferable to stack a layer doped with a p-type dopant in a physical semiconductor. In addition, as a p-type dopant, magnesium etc. can be used, for example.

  The band gap of the p-type nitride semiconductor cladding layer 13 is preferably larger than the band gap of the nitride semiconductor active layer 11 from the viewpoint of optical confinement in the nitride semiconductor active layer 11.

  The thickness of the p-type nitride semiconductor cladding layer 13 is not particularly limited, but is preferably 0.01 μm or more and 0.4 μm or less, and more preferably 0.02 μm or more and 0.1 μm or less.

The doping concentration of the p-type dopant into the p-type nitride semiconductor cladding layer 13 is preferably 1 × 10 ¹⁸ cm ⁻³ or more and 1 × 10 ²¹ cm ⁻³ or less, and preferably 1 × 10 ¹⁹ cm ⁻³ or more and 1 ×. More preferably, it is 10 ²⁰ cm ⁻³ or less. When the doping concentration of the p-type dopant into the p-type nitride semiconductor clad layer 13 is 1 × 10 ¹⁸ cm ⁻³ or more and 1 × 10 ²¹ cm ⁻³ or less, particularly 1 × 10 ¹⁹ cm ⁻³ or more and 1 × 10 ²⁰ When it is cm ⁻³ or less, it tends to be possible to obtain a p-type nitride semiconductor clad layer 13 with good crystallinity.

Further, as the p-type nitride semiconductor clad layer 13, for example, a group III represented by the formula of Al _x8a Ga _1-x8a N (0 <x8a ≦ 0.4, preferably 0.1 ≦ x8a ≦ 0.3). a nitride semiconductor layer as the (a layer), a small Al _x8b band gap than the layer a _{Ga y8b In z8b N (0 ≦} x8b ≦ 1,0 ≦ y8b ≦ 1,0 ≦ z8b ≦ 1, x8b + y8b + z8b ≠
A layer having a superlattice structure in which layers (B layers) made of a group III nitride semiconductor represented by the formula (0) are alternately stacked one by one can be used. In the superlattice structure, each of the A layer and the B layer may be doped with a p-type dopant, and only one of the A layer and the B layer may be doped with a p-type dopant.

  Next, the p-type nitride semiconductor contact layer 15 is formed on the surface of the p-type nitride semiconductor cladding layer 13 by, for example, MOCVD.

The p-type nitride semiconductor contact layer 15, for example, III-group of the formula of _{Al x9 Ga y9 In z9 N (} 0 ≦ x9 ≦ 1,0 ≦ y9 ≦ 1,0 ≦ z9 ≦ 1, x9 + y9 + z9 ≠ 0) A layer in which a nitride semiconductor is doped with a p-type dopant can be stacked. In particular, as the p-type nitride semiconductor contact layer 15, it is preferable to use a layer obtained by doping a GaN layer with a p-type dopant. In this case, good crystallinity of the p-type nitride semiconductor contact layer 15 is maintained, and good ohmic contact with the translucent electrode layer 19 tends to be obtained.

The doping concentration of the p-type dopant into the p-type nitride semiconductor contact layer 15 is preferably 1 × 10 ¹⁸ cm ⁻³ or more and 1 × 10 ²¹ cm ⁻³ or less, and 5 × 10 ¹⁹ cm ⁻³ or more and 5 ×. More preferably, it is 10 ²⁰ cm ⁻³ or less. When the doping concentration of the p-type dopant into the p-type nitride semiconductor contact layer 15 is 1 × 10 ¹⁸ cm ⁻³ or more and 1 × 10 ²¹ cm ⁻³ or less, it is particularly 5 × 10 ¹⁹ cm ⁻³ or more and 5 × 10 ^20. If it is cm ⁻³ or less, good ohmic contact with the translucent electrode layer 19 is maintained, cracking in the p-type nitride semiconductor contact layer 15 is suppressed, and the p-type nitride semiconductor contact layer 15 is suppressed. The good crystallinity tends to be maintained.

  The thickness of the p-type nitride semiconductor contact layer 15 is not particularly limited, but is preferably 0.01 μm or more and 0.5 μm or less, and more preferably 0.05 μm or more and 0.2 μm or less. . When the thickness of the p-type nitride semiconductor contact layer 15 is 0.01 μm or more and 0.5 μm or less, particularly when it is 0.05 μm or more and 0.2 μm or less, the light emission output of the nitride semiconductor light emitting diode device 100 is reduced. It tends to be improved.

  The n-type nitride semiconductor contact layer 7, the n-type nitride semiconductor clad layer 9, the nitride semiconductor active layer 11, the p-type nitride semiconductor clad layer 13 and the p-type nitride semiconductor contact layer 15 are each a group III nitride. When composed of a semiconductor, these layers can be laminated by, for example, MOCVD using the following gases.

  That is, an organic metal source gas of at least one group III element selected from the group consisting of trimethylgallium (TMG), trimethylaluminum (TMA), and trimethylindium (TMI), for example, inside the reactor of the MOCVD apparatus, Each of the above layers can be laminated by supplying a nitrogen source gas such as ammonia, thermally decomposing them, and reacting them.

In addition, when doping silicon which is an n-type dopant, for example, silane (SiH ₄ ) or disilane (Si ₂ H ₆ ) is added as a doping gas to the inside of the reactor of the MOCVD apparatus and supplied. By doing so, it is possible to dope silicon.

In addition, when doping with p-type dopant magnesium, biscyclopentadienyl magnesium (CP ₂ Mg), for example, is added as a doping gas to the inside of the reactor of the MOCVD apparatus and supplied. Thus, it is possible to dope magnesium.

  Next, after forming a translucent electrode layer 19 made of, for example, ITO (Indium Tin Oxide) on the surface of the p-type nitride semiconductor contact layer 15, a p-side electrode 21 is formed on the surface of the translucent electrode layer 19. Form. As the p-side electrode 21, for example, a laminated film of a nickel layer, an aluminum layer, a titanium layer, and a gold layer can be formed.

  Next, a part of the stacked body after the formation of the p-side electrode 21 is removed by etching, so that a part of the surface of the n-type nitride semiconductor contact layer 7 is exposed.

  Next, the n-side electrode 20 is formed on the exposed surface of the n-type nitride semiconductor contact layer 7. As the n-side electrode 20, for example, a laminated film of a nickel layer, an aluminum layer, a titanium layer, and a gold layer can be formed.

Thereafter, an insulating protective film 23 such as SiO ₂ is formed on the entire surface of the stacked body after the n-side electrode 20 is formed, and an opening is provided in the insulating protective film 23 so that the p-side electrode 21 and the n-side electrode 20 are exposed. The nitride semiconductor light-emitting diode device 100 of the first embodiment can be manufactured by dividing the wafer on which the plurality of nitride semiconductor light-emitting diode devices 100 are formed into individual devices.

  Here, for example, the wafer is divided by, for example, grinding and polishing the back surface of the wafer having the above structure formed on the substrate 1 to form a mirror-like surface, and then dividing the wafer into rectangular chips of 280 μm × 550 μm square It can be done by doing.

  The nitride semiconductor light emitting diode device 100 of the first embodiment manufactured as described above has a flat surface, high crystallinity, low warpage, and a third nitride manufactured at a high growth rate. N-type nitride semiconductor contact layer 7, n-type nitride semiconductor clad layer 9, nitride semiconductor active layer 11, p-type nitride semiconductor clad layer 13, and p-type nitride semiconductor contact on upper surface 5U of nitride semiconductor underlayer 5 Layers 15 are stacked in this order.

  Therefore, the n-type nitride semiconductor contact layer 7, the n-type nitride semiconductor clad layer 9, the nitride semiconductor active layer 11, the p-type nitride semiconductor clad layer 13 and the p-type nitride semiconductor contact layer 15 have a low dislocation density. It has excellent crystallinity.

  Therefore, the nitride semiconductor light-emitting diode device 100 of the first embodiment formed from such a nitride semiconductor layer having excellent crystallinity is a device having a low operating voltage and a high light-emission output, and is manufactured more efficiently. be able to.

  The nitride semiconductor light-emitting diode element 100 created under the conditions of Case 1 was used as a bare chip (no resin sealing described later) evaluation element, and a current of 30 mA was passed through 10 elements. It was confirmed that an element with a high light output was obtained with a low light output of 39 mW, an operating voltage of 3.0 V, and a light emitting wavelength of 455 nm.

(Light emitting device)
Further, the light emitting device 110 of the first embodiment having the configuration shown in FIG. 19 may be manufactured using the nitride semiconductor light emitting diode element 100 of the first embodiment.

  Here, in the light emitting device 110 according to the first embodiment, for example, the nitride semiconductor light emitting diode element 100 according to the first embodiment is installed on the second lead frame 31, and the p-side electrode of the nitride semiconductor light emitting diode element 100 is provided. 21 and the first lead frame 30 are electrically connected by the first wire 33, and the n-side electrode 20 of the nitride semiconductor light emitting diode element 100 and the second lead frame 31 are connected by the second wire 34. Connect electrically. The bullet-shaped light emitting device 110 can be manufactured by molding the nitride semiconductor light emitting diode element 100 with the transparent mold resin 35.

  The light-emitting device 110 according to the first embodiment having the configuration shown in FIG. 19 uses the nitride semiconductor light-emitting diode element 100 according to the first embodiment, so that the operating voltage is low, the light emission output is high, and the light-emitting device 110 is efficiently manufactured. A light emitting device capable of producing

<Embodiment 2>
The second embodiment is characterized in that it is a nitride semiconductor transistor element that is an electronic device using the nitride semiconductor structure manufactured according to the first embodiment.

  FIG. 20 is a schematic cross-sectional view of the nitride semiconductor transistor element 300 according to the second embodiment. The nitride semiconductor transistor device 300 includes a substrate 1 made of a sapphire substrate having a c-plane as a main surface and arranged in three a (sub) axial directions in which the convex portions 1a are equivalent, and a substrate 1 sequentially stacked on the surface. The nitride semiconductor intermediate layer 2 made of AlN or the like, the first nitride semiconductor underlayer 3 made of undoped GaN, the second nitride semiconductor underlayer 4 made of undoped GaN, undoped GaN, or the like A nitride semiconductor structure comprising a third nitride semiconductor underlayer 5 made of

  A nitride semiconductor electron transit layer 71 made of undoped GaN or the like is laminated on the flat upper surface 5a of the second nitride semiconductor underlayer 5 having good crystallinity with few crystal defects, and the nitride semiconductor electron transit layer is formed. An n-type nitride semiconductor electron supply layer 73 made of n-type AlGaN or the like is laminated on the surface of 71.

  A gate electrode 77 is provided on the surface of the n-type nitride semiconductor electron supply layer 73, and a source contact layer 75S and a drain contact layer 75D made of n-type GaN or the like are provided on both sides of the gate electrode 77. . A source electrode 78S is provided on the source contact layer 75S, and a drain electrode 78D is provided on the drain contact layer 75D.

  Hereinafter, an example of a method for manufacturing the nitride semiconductor transistor element 300 of the second embodiment will be described. First, in the same manner as in the first embodiment, the nitride semiconductor intermediate layer 2 made of AlN is formed on the surface of the substrate 1 having the convex portions 1a and the concave portions 1b by reactive sputtering.

  Next, the first nitride semiconductor underlayer 3 made of undoped GaN and the first nitride made of undoped GaN are formed on the surface of the nitride semiconductor intermediate layer 2 by the MOCVD method under the same conditions as in the first embodiment. The physical semiconductor underlayer 4 is grown in this order. Here, the second nitride semiconductor foundation layer 4 includes two oblique facet surfaces 4r appearing in the a (sub) axis direction in a plan view of the surface of the first nitride semiconductor foundation layer 4, and a (sub) Two oblique facet surfaces 4r appearing in each of a direction inclined at an angle of + 60 ° with respect to the axial direction and a direction inclined at an angle of −60 ° with respect to the a (sub) axial direction (for example, Growing under condition 1).

  Next, the third nitride semiconductor base layer 5 made of undoped GaN is grown on the surface of the second nitride semiconductor base layer 4 by the MOCVD method under the same conditions as in the first embodiment. Here, the third nitride semiconductor underlayer 5 is grown under the condition that the oblique facet surface 4r of the first nitride semiconductor underlayer 4 is buried and a flat upper surface 5U appears.

Next, a nitride semiconductor electron transit layer 71 made of n-type Al _x Ga _1-x N is stacked on the flat upper surface 5U of the third nitride semiconductor underlayer 5 by MOCVD, and nitride semiconductor electron transit is achieved. An n-type nitride semiconductor electron supply layer 73 is stacked on the surface of the layer 71.

  Then, after forming the source contact layer 75S and the drain contact layer 75D on the surface of the n-type nitride semiconductor electron supply layer 73, the source electrode 78S, the drain electrode 78D, and the gate electrode 77 are formed, respectively. Thus, the nitride semiconductor transistor element 300 of the second embodiment can be manufactured.

  Similarly to the first embodiment, the nitride semiconductor transistor element 300 according to the second embodiment also has a high crystallinity, the warpage is suppressed, and the third nitride semiconductor base layer 5 manufactured at a high growth rate. Nitride semiconductor layers such as the nitride semiconductor electron transit layer 71 and the n-type nitride semiconductor electron supply layer 73 are stacked on the flat upper surface 5U. Thereby, in particular, since crystal defects in the two-dimensional electron traveling region on the uppermost surface of the nitride semiconductor electron traveling layer 71 are reduced, the electron mobility can be improved.

  Therefore, also in the nitride semiconductor transistor element 300 of the second embodiment, each layer stacked on the surface of the third nitride semiconductor underlayer 5 is a layer having a low dislocation density and excellent crystallinity. Therefore, an element with improved characteristics such as electron mobility can be obtained.

<Example>
First, a substrate made of a sapphire single crystal having a diameter of 6 inches and a thickness of 1.3 mm was prepared. Next, a mask for defining the planar arrangement of the convex portions shown in FIG. 3 was formed on the substrate, and the surface of the substrate was dry-etched using the mask to form concave portions in the planar arrangement shown in FIG.

  Accordingly, the convex portions on the surface of the substrate are arranged in the a (sub) axis direction (<11-20> direction) of the surface of the substrate, and + 60 ° with respect to the a (sub) axis direction of the surface of the substrate. And a direction (−u direction) that makes an inclination of −60 ° with respect to the a (sub) axis direction of the surface of the substrate. Here, the convex portions are respectively located at the vertices of the virtual triangle 1t shown in FIG. 3 in a plan view of the surface of the substrate, and are periodically arranged in the direction of each of the three sides of the virtual triangle. It was. Furthermore, the planar shape at the bottom surface of the convex portion was circular. Further, in the plan view of the surface of the substrate, the interval between the adjacent convex portions is 2 μm, the diameter of the circular circle that is a planar shape on the bottom surface of the convex portion is about 1.2 μm, and the height of the convex portion is It was about 0.6 μm. Furthermore, the convex part and the concave part on the surface of the substrate each had a cross section shown in FIG. 4, and the convex part had a tip 1c.

Next, RCA cleaning was performed on the surface of the substrate after the formation of the convex portions and the concave portions. Then, the substrate after the above RCA cleaning is placed in the chamber, N ₂ and Ar are introduced, the substrate is heated to 650 ° C., and reactive sputtering is performed to sputter an Al target in a mixed atmosphere of N ₂ and Ar. 30 nm-thick nitride semiconductor intermediate layer made of an AlN crystal consisting of an aggregate of columnar crystals with aligned crystal grains extending in the normal direction of the surface of the substrate on the surface of the substrate having projections and depressions Formed.

  The wafer having the nitride semiconductor intermediate layer formed as described above is placed in a vertical MOCVD apparatus, and the wafer substrate is rotated at a rotational speed of 600 RPM while the wafer substrate temperature is heated to 1000 ° C. In a state where the atmospheric pressure in the MOCVD apparatus is 66.6 kPa, a mixture of ammonia gas as a group V source gas and TMG (trimethylgallium) as a group III source gas in the vertical MOCVD apparatus By supplying only hydrogen gas (flow rate: 129 slm) as a carrier gas, an undoped GaN crystal is grown for 5 minutes by MOCVD to form a first nitride semiconductor underlayer having a thickness of 300 nm. Formed.

  Here, the source gas was supplied such that the V / III ratio of the source gas was 1165. Since only hydrogen gas is supplied as the carrier gas, it is clear that the volume ratio of hydrogen gas to the total volume of carrier gas during the growth of the first nitride semiconductor underlayer is 1.

  Thereafter, an undoped GaN crystal was further grown under the same conditions as described above to form a second nitride semiconductor underlayer of Example 1 having a thickness of 1.8 μm.

  Thereafter, the substrate rotation speed is increased to 1200 RPM, and the pressure of the atmosphere in the growth chamber of the vertical MOCVD apparatus is reduced to 26.6 kPa, and ammonia gas that is a group V source gas (ammonia gas flow rate: 25 slm) ) And a group III source gas TMG (trimethylgallium flow rate: 340 sccm) is supplied (V / III ratio: 656), and only hydrogen gas (flow rate: 153 slm) is supplied as a carrier gas. An undoped GaN crystal is grown for 72 minutes by MOCVD to form a third nitride semiconductor underlayer having a thickness of 5.0 μm on the second nitride semiconductor underlayer (growth rate: 4.17 μm / hour) Thus, the nitride semiconductor structure of the example was manufactured. Then, an n-type nitride semiconductor contact layer made of n-type GaN having a thickness of 2.8 μm was stacked on the third nitride semiconductor underlayer of the nitride semiconductor structure of the example.

  Thereafter, an n-type nitride semiconductor superlattice layer, a nitride semiconductor light emitting layer, a p-type nitride semiconductor cladding layer, and a p-type nitride semiconductor contact are formed on the n-type nitride semiconductor contact layer by a conventionally used method. A layer and a translucent electrode layer were laminated in this order.

  Thereafter, the surface of the n-type nitride semiconductor contact layer is exposed by a conventionally used method, an n-side electrode is formed on the exposed surface of the n-type nitride semiconductor contact layer, and the surface of the translucent electrode layer is formed. A p-side electrode was formed.

Thereafter, the respective surfaces of the translucent electrode layer, the p-type nitride semiconductor contact layer, the p-type nitride semiconductor cladding layer, the nitride semiconductor light emitting layer, the n-type nitride semiconductor superlattice layer, and the n-type nitride semiconductor contact layer Was covered with an insulating protective film made of SiO ₂ .

  Thereafter, the nitride semiconductor light-emitting diode device of the example was fabricated by dividing into chips by a conventionally used method.

<Comparative example>
A comparative nitride semiconductor structure was fabricated in the same manner as in the example except that the third nitride semiconductor underlayer was fabricated as follows.

  In a state where the rotation speed of the substrate is increased to 1200 RPM and the pressure of the atmosphere in the growth chamber of the vertical MOCVD apparatus is 17.2 kPa, ammonia gas (ammonia gas flow rate: 25 slm) which is a group V source gas and III By supplying a mixed gas with TMG (trimethylgallium flow rate: 274 sccm) which is a group source gas (V / III ratio: 814) and supplying only hydrogen gas (flow rate: 198 slm) as a carrier gas, Then, an undoped GaN crystal is grown for 140 minutes to form a third nitride semiconductor underlayer having a thickness of 5.0 μm on the second nitride semiconductor underlayer (growth rate: 2.14 μm / hour), A nitride semiconductor structure of a comparative example was produced. Thereafter, in the same manner as in the example, an n-type nitride semiconductor contact layer made of n-type GaN having a thickness of 2.8 μm was laminated on the third nitride semiconductor underlayer of the nitride semiconductor structure of the comparative example.

<Evaluation>
Regarding the nitride semiconductor structure of the example manufactured as described above and the nitride semiconductor structure of the comparative example, at the stage of forming the n-type nitride semiconductor contact layer on the third nitride semiconductor underlayer ( 1) In-plane distribution of layer thickness, (2) In-plane distribution of sheet resistance, (3) Crystallinity, (4) Warpage magnitude, and (5) Surface morphology and crystal defects were evaluated.

(1) In-plane distribution of layer thickness The in-plane distribution of the layer thickness from the first nitride semiconductor underlayer to the n-type nitride semiconductor contact layer was measured by a photoluminescence measurement method. The layer thickness was calculated by determining spectral reflectance for each wavelength with a spectroscope using spectral interference. FIG. 21A shows the in-plane distribution of the layer thickness of the example, and FIG. 21B shows the in-plane distribution of the layer thickness of the comparative example.

  When comparing FIG. 21A and FIG. 21B, the in-plane distribution of the layer thickness of the comparative example shown in FIG. 21B is a contour line from the center to the end of the surface of the n-type nitride semiconductor contact layer. The layer thickness was thick. However, in the in-plane distribution of the layer thickness in the example shown in FIG. 21A, such a contour distribution was not obtained. In addition, a large difference does not appear in the deviation of the layer thickness of the in-plane distribution of the layer thickness of the example, and the end portion existing from the orientation flat to the clockwise direction that appeared in the in-plane distribution of the layer thickness of the comparative example is not shown. The generation of the layer thickness portion was also suppressed. Therefore, from this result, the surface of the third nitride semiconductor underlayer of the nitride semiconductor structure of the example is flatter than that of the third nitride semiconductor underlayer of the nitride semiconductor structure of the comparative example. Conceivable.

(2) In-plane distribution of sheet resistance FIG. 22A shows the in-plane distribution of sheet resistance of the example, and FIG. 22B shows the in-plane distribution of sheet resistance of the comparative example. Here, the sheet resistance was measured using a non-contact sheet resistance measuring instrument.

  When comparing FIG. 22A and FIG. 22B, the in-plane distribution of the sheet resistance of the embodiment shown in FIG. 22A is more in the surface of the sheet resistance of the comparative example shown in FIG. Although it seemed that the uniformity was higher than that of the internal distribution, there was no difference in the average value of the sheet resistance.

(3) Crystallinity The crystallinity of the n-type nitride semiconductor contact layer formed on the third nitride semiconductor underlayer of the nitride semiconductor structure of the example and the comparative example is determined by X-ray rocking curve diffraction (XRC). evaluated.

  The peak half-value width of the GaN (0004) plane by ω measurement is 30 arcsec for the example and 30 arcsec for the comparative example, and the peak half-value width for the GaN (10-12) plane is 116 arcsec for the example and 113 arcsec for the comparative example. There was no significant difference between the two. From this result, it is considered that the third nitride semiconductor underlayer has good crystallinity in any of the nitride semiconductor structures of the example and the comparative example.

  This is because the growth conditions of the first nitride semiconductor underlayer and the second nitride semiconductor underlayer of the nitride semiconductor structure of the example and the comparative example are the same. This is probably because there was no difference in the shape of the facets of the layers.

(4) Warpage magnitude The warpage of the wafer after the formation of the n-type nitride semiconductor contact layer was measured for each of the example and the comparative example. As shown in the schematic side view of FIG. 23, the warpage of the wafer was determined by setting the difference between the maximum value and the minimum value of all the measurement point data in the non-adsorption state as the reference plane as the least square plane.

  As a result, the warpage of the wafer of the example was 97 μm, the warpage of the wafer of the comparative example was 100 μm, and it was confirmed that the warpage of the example was suppressed more than that of the comparative example. Therefore, from this result, it is considered that the warpage of the nitride semiconductor structure of the example can be suppressed more than the nitride semiconductor structure of the comparative example.

(5) Surface morphology and crystal defects The surface morphology and crystal defects of the wafer after the formation of the n-type nitride semiconductor contact layer were observed for each of the examples and comparative examples. Here, the surface morphology was evaluated by observing with a differential interference microscope (metal microscope). The crystal defects were evaluated by EPD (etch pit density) measurement.

  FIGS. 24A and 24B show observation images of the surface morphology of the wafer of the example using a differential interference microscope (metal microscope), and FIGS. 24C and 24D show the example. The observation image of the crystal defect by the EPD measurement of a wafer is shown. Here, FIG. 24A and FIG. 24C are observation images at a magnification of 5 times, respectively, and FIG. 24B and FIG. 24D are observation images at a magnification of 20 times, respectively. .

  25 (a) and 25 (b) show images of the surface morphology of the wafer of the comparative example observed with a differential interference microscope (metal microscope), and FIGS. 25 (c) and 25 (d) show the comparative example. The observation image of the crystal defect by the EPD measurement of a wafer is shown. Here, FIG. 25 (a) and FIG. 25 (c) are observation images at a magnification of 5 times, respectively, and FIG. 25 (b) and FIG. 25 (d) are observation images at a magnification of 20 times, respectively. .

  As apparent from the comparison between FIGS. 24A to 24D and FIGS. 25A to 25D, there was almost no difference in the surface morphology and crystal defects of the wafers of the example and the comparative example. .

<Summary>
From the comparison between the above example and the comparative example, by satisfying the following conditions 1) to 3), the growth time of the third nitride semiconductor underlayer is greatly reduced from 140 minutes to 72 minutes, A third nitride semiconductor underlayer having a flat surface, high crystallinity, and reduced warpage can be grown. Thereby, it becomes possible to reduce the usage-amount of group III source gas significantly, and generation | occurrence | production of the edge part which has a large layer thickness locally at an edge part like a comparative example can be suppressed.

  1) The flow rate of TMG, which is a group III source gas, is increased from 274 sccm to 340 sccm.

  2) Decrease the flow rate of hydrogen gas as the carrier gas from 198 slm to 153 slm.

  3) Increase the pressure during the growth of the third nitride semiconductor underlayer from 17.2 kPa to 26.6 kPa.

  Further, it is not possible to desire a significant reduction in the growth time as described above only by increasing the flow rate of the group III source gas. However, by reducing the flow rate of the hydrogen gas that is the carrier gas to 153 slm, By increasing the concentration of the group III source gas in the growth chamber during the growth of the nitride semiconductor underlayer, it is possible to reduce the growth time. At this time, the growth rate of the third nitride semiconductor underlayer is further increased by lowering the exhaust rate of the exhaust device of the growth chamber of the vertical MOCVD apparatus and retaining the group III source gas in the growth chamber. Can do.

  It should be understood that the embodiments and examples disclosed herein are illustrative and non-restrictive in every respect. The scope of the present invention is defined by the terms of the claims, rather than the description above, and is intended to include any modifications within the scope and meaning equivalent to the terms of the claims.

  The present invention can be used in a method for manufacturing a nitride semiconductor structure, and can also be used in a method for manufacturing a nitride semiconductor light-emitting diode element and a nitride semiconductor transistor element.

  1 substrate 1a convex portion 1b concave portion 1c tip portion 1t triangle 2 nitride semiconductor intermediate layer 3 first nitride semiconductor underlayer 3c first flat region 3d rough surface region 3f first Oblique facet surface, 4 second nitride semiconductor underlayer, 4c second flat region, 4r second oblique facet surface, 5 third nitride semiconductor underlayer, 5U upper surface, 7 n-type nitride semiconductor contact layer , 9 n-type nitride semiconductor clad layer, 11 nitride semiconductor active layer, 13 p-type nitride semiconductor clad layer, 15 p-type nitride semiconductor contact layer, 19 translucent electrode layer, 20 n-side electrode, 21 p-side Electrode, 23 Insulating protective film, 30 First lead frame, 31 Second lead frame, 33 First wire, 34 Second wire, 35 Mold resin, 40 Surface, 71 Nitride semiconductor Child traveling layer, 73 n-type nitride semiconductor electron supply layer, 75S source contact layer, 75D drain contact layer, 77 gate electrode, 78S source electrode, 78D drain electrode, 100 nitride semiconductor light emitting diode element, 110 light emitting device, 300 nitride Semiconductor transistor element.

Claims (2)

Preparing a substrate made of a trigonal corundum or hexagonal crystal having a concave portion and a convex portion provided between the concave portions on the surface;
Forming a nitride semiconductor intermediate layer on the substrate;
Forming a first nitride semiconductor underlayer on the nitride semiconductor intermediate layer;
Forming a second nitride semiconductor underlayer on the first nitride semiconductor underlayer;
Forming a third nitride semiconductor underlayer by MOCVD on the second nitride semiconductor underlayer,
The surface of the first nitride semiconductor underlayer has a first oblique facet surface and a first flat region,
An area ratio of the first oblique facet surface on the surface of the first nitride semiconductor underlayer is smaller than an area ratio of the first flat region;
The second nitride semiconductor underlayer has a second oblique facet surface surrounding the convex portion,
A lower surface of the third nitride semiconductor underlayer is in contact with the second oblique facet surface;
In the step of forming the third nitride semiconductor underlayer, the molar amount of the group V source gas supplied per unit time during the growth of the third nitride semiconductor underlayer and the III supplied per unit time The V / III ratio, which is the ratio to the molar amount of the group source gas, is 700 or less, the pressure during growth of the third nitride semiconductor underlayer is 26.6 kPa or more, and the third nitride semiconductor underlayer A method for manufacturing a nitride semiconductor structure, wherein the growth rate of the semiconductor is 2.5 μm / hour or more.   2. The method of manufacturing a nitride semiconductor structure according to claim 1, wherein in the step of forming the third nitride semiconductor underlayer, hydrogen of less than 198 slm is supplied during the growth of the third nitride semiconductor underlayer.