JP2007184503A - Semiconductor member and manufacturing method thereof - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To obtain a semiconductor member having low dislocation density of a surface by preventing intersecting between crystal growth from a convex portion of a substrate having unevenness and crystal growth from a concave portion. <P>SOLUTION: This manufacturing method includes a preparing process of preparing a substrate 30 having the concave portion 30r and the convex portion 30p; a first growing process of growing a first semiconductor 31 in at least a lateral direction from the convex portion 30p; a second growing process of growing a second semiconductor 32 on the first semiconductor 31 to form a facet consisting of the second substrate 32; and a third growing process of growing a third semiconductor 33 in at least a lateral direction from the facet. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a semiconductor member and a manufacturing method thereof.

  Currently, many Group III nitride semiconductor devices are realized by heteroepitaxially growing Group III nitride on a substrate such as a sapphire substrate or a silicon carbide (SiC) substrate. However, there are large lattice constant differences and thermal expansion coefficient differences between the group III nitride crystal and a substrate such as a sapphire substrate or a silicon carbide (SiC) substrate. For this reason, very high density dislocations are generated at the substrate interface, and these dislocations become threading dislocations and reach the semiconductor surface. Therefore, for example, when a light-emitting element such as an LED is manufactured, high-density threading dislocations remain in the active layer, which is an important part of the light-emitting element. In particular, in short wavelength LEDs, threading dislocations act as non-light-emitting centers, so reduction of the dislocations is indispensable for improving luminous efficiency.

  A method of forming a group III nitride semiconductor with few crystal defects by utilizing lateral growth along the substrate surface has been reported. For example, in the methods disclosed in Non-Patent Document 1, Patent Document 1, Patent Document 2, and Patent Document 3, a stripe having a window on a substrate or a group III nitride semiconductor layer grown on the substrate is used. A mask layer is formed, and a facet structure is formed in the window by adjusting the vapor phase growth conditions, and the propagation direction of dislocations is bent in the lateral direction. Next, the growth conditions are changed, and the lateral growth is continued until the adjacent semiconductor layers meet. A void is formed under the meeting portion, and the dislocations propagated in the lateral direction are terminated at this void. Therefore, dislocations hardly propagate to the surface of the group III nitride semiconductor, and a surface with a low dislocation density can be obtained.

  Even if a mask is formed on the substrate and a group III nitride semiconductor containing Al in the window between the masks, for example, AlGaN is selectively grown, as disclosed in Non-Patent Document 2, AlGaN Grows as a single crystal structure from the window, but deposits as a polycrystalline structure on the mask. This AlGaN having a polycrystalline structure prevents AlGaN having good crystallinity from growing laterally from the window. Further, according to Non-Patent Document 3, even in the growth of a semiconductor by maskless pendeo epitaxy, a semiconductor polycrystal is deposited on a sapphire substrate, and the lateral growth of a semiconductor with good crystallinity is hindered. Such a problem becomes apparent when the Al concentration is increased in the group III nitride semiconductor.

In Patent Literature 5, Patent Literature 6, Patent Literature 7, and Non-Patent Literature 4, the width of the convex portion of the concavo-convex substrate is made smaller than 1 μm, and the surface is flattened by growing the semiconductor exclusively in the lateral direction from above the convex portion. A method is disclosed. In this method, since the raw material supply to the recess is suppressed, the semiconductor hardly grows in the recess. Further, since this method is a maskless method, there is no problem of growing a polycrystalline structure on the mask in the growth of the nitride semiconductor containing Al. However, in this method, facets are formed on the convex portions. Since they are not formed, a number of threading dislocations remain on the convex portion. Even if the width of the convex portion is smaller than 1 μm, high-density defect portions and low-density defect portions periodically exist on the semiconductor surface.
JP 2002-170778 A Japanese Patent Laid-Open No. 2003-77847 JP 2003-124124 A Japanese Patent No. 3556916 Japanese Patent No. 3441415 Japanese Patent No. 3471700 JP 2004-6931 A Y. Honda et al. , Jpn. J. et al. Appl. Phys. 40 (2001) L309 T.A. Dechprohm et al. Phys. Stat. Sol. A 188 (2001) 799 T.A. M.M. Katona et al. , Appl. Phys. Lett. 84 (2004) 5025 S. Heikman et al. , Jpn. J. et al. Appl. Phys. 44 (2005) L405 C. Chen et al. , Jpn. J. et al. Appl. Phys. 42 (2003) L818 B. A. Haskell et al. , Appl. Phys. Lett. 86 (2005) 11917

  In Patent Document 4, when a semiconductor is grown on a substrate having a concavo-convex surface, first, facets are formed on the convex portions and the concave portions, and then the crystals growing from the convex portions and the crystals growing from the concave portions are connected. A flat surface is disclosed.

  However, in the method described in Patent Document 4, the growth of crystals from the convex portions and the growth of crystals from the concave portions are interlaced, so that the meeting portion becomes complicated and the space is wide. . Therefore, there is a possibility that many new dislocations that propagate to the surface of the semiconductor substrate are generated from such an association portion.

  The present invention has been made in view of the above background, for example, by preventing the growth of crystals from the projections of the substrate having irregularities and the growth of crystals from the depressions from intersecting, dislocations on the surface An object is to obtain a semiconductor member having a low density.

  The 1st side of the present invention is related with the manufacturing method of a semiconductor member. The manufacturing method includes a preparation step of preparing a substrate having a concave portion and a convex portion, a first growth step of growing a first semiconductor at least in a lateral direction from the convex portion, and a second semiconductor on the first semiconductor. A second growth step of growing to form a facet made of the second semiconductor; and a third growth step of growing a third semiconductor from the facet at least in a lateral direction.

  According to a preferred embodiment of the present invention, in the first growth step, the distance from the bottom surface of the concave portion to the upper surface of the first semiconductor is equal to the gap of the first semiconductor growing from the adjacent convex portion. Or larger.

  According to a preferred embodiment of the present invention, in the first growth step, a cross section of a space formed by the gap between the first semiconductor growing from the adjacent convex portion and the concave portion becomes convex. Preferably, it is implemented.

  According to a preferred embodiment of the present invention, the first, second, and third semiconductors may include, for example, a group III nitride semiconductor.

  According to a preferred embodiment of the present invention, the first, second, and third semiconductors may include a group III nitride semiconductor containing Al, for example.

  According to a preferred embodiment of the present invention, the manufacturing method may further include, for example, a step of forming a light emitting device on the third semiconductor.

  A second aspect of the present invention relates to a semiconductor member, and the semiconductor member has a convex space inside in a cross section.

  A third aspect of the present invention relates to a semiconductor member, wherein the semiconductor member includes a substrate having a plurality of concave portions and a plurality of convex portions, and a plurality of semiconductor portions respectively disposed on the plurality of convex portions. And a semiconductor layer disposed so as to cover the plurality of semiconductor portions, wherein the plurality of semiconductor portions are disposed separately from each other so that a gap is formed on the recess. The cross section of the space formed by has a convex shape.

  According to a preferred embodiment of the present invention, the semiconductor layer may include a first portion faceted from each of the plurality of semiconductor portions and a second portion grown from the first portion.

  According to a preferred embodiment of the present invention, the plurality of semiconductor portions and the semiconductor layer may include, for example, a group III nitride semiconductor.

  According to a preferred embodiment of the present invention, the plurality of semiconductor portions and the semiconductor layer may include a group III nitride semiconductor containing Al, for example.

  According to the present invention, for example, the growth of crystals from the convex portions of the substrate having irregularities and the growth of crystals from the concave portions are prevented from intersecting, and a semiconductor member having a low surface dislocation density can be obtained.

  The present invention can be applied to any semiconductor member and manufacturing method thereof within the scope described in the claims. For example, a semiconductor member including a group III nitride semiconductor, particularly an Al-containing nitride semiconductor, and manufacturing thereof. Suitable for the method.

  According to a preferred embodiment of the present invention, for example, the dislocation density on the surface without using a mask for selective growth (for example, a silicon oxide film, a silicon nitride film, a refractory metal film, a metal oxide film, etc.). Can be obtained. More specifically, according to a preferred embodiment of the present invention, a threading dislocation is obtained by growing a group III nitride semiconductor on a convex portion of a substrate having a concavo-convex surface, and subsequently laterally growing the semiconductor. Bending can reduce the dislocation density on the surface of the group III nitride semiconductor substrate. Here, the increase in the transition density due to the intersection of the crystal growth from the convex portion and the crystal growth from the concave portion can be prevented by making the concave portion sufficiently deep.

  In this specification, the expression “the B layer formed on the A layer” or “the B layer formed on the A” refers to the B layer such that the bottom surface of the B layer is in contact with the top surface of the A layer or A. And a case where one or more layers are formed on the upper surface of the A layer or A, and a B layer is further formed on that layer. The above expression also applies to the case where the upper surface of the A layer or A and the bottom surface of the B layer are in partial contact and one or more layers exist between the A layer or the A and B layers in other portions. included. Further, “to” means a range including numerical values described before and after that as a minimum value and a maximum value, respectively.

  In this specification, the growth of a group III nitride semiconductor using a sapphire substrate is described as an exemplary embodiment of the present invention. However, instead of the sapphire substrate, for example, silicon, gallium arsenide, silicon carbide, oxide A substrate such as a zinc or gallium nitride substrate can also be used. The plane orientation of the substrate is not particularly limited, and a just substrate can be used, or a substrate with an off angle can be used.

  When the group III nitride semiconductor is grown on the substrate, it is preferable that after the buffer layer is formed on the substrate, the group III nitride semiconductor is grown on the buffer layer.

  The buffer layer is, for example, a microcrystalline or amorphous nitride semiconductor grown on the substrate at a low or high growth temperature, and may contain phosphorus or arsenic.

  The substrate may be peeled off from the semiconductor multilayer structure after the semiconductor multilayer structure is formed thereon. The peeling can be performed using, for example, laser lift-off. Or peeling can also be performed by the etching by the liquid containing an acid.

  The semiconductor or semiconductor layer may be a single layer, a multilayer structure with different composition or carrier concentration, or a superlattice structure. The composition or the carrier concentration can be varied in a stepwise manner in the thickness direction.

  The semiconductor or the semiconductor layer can be n-type or p-type by adding an impurity. Examples of the p-type impurity include magnesium, zinc, and calcium, and examples of the n-type impurity include silicon, sulfur, selenium, tellurium, and germanium.

  In the case of manufacturing a light emitting device, a laminated structure constituting the light emitting device may be further grown on the semiconductor member described below, or all or a part of the semiconductor member described below may be formed on the light emitting device. It may be used as an n-type contact layer, an n-type cladding layer, a p-type contact layer, or a p-type cladding layer.

  Hereinafter, preferred embodiments of the present invention will be described with reference to the accompanying drawings.

  FIG. 1 is a view schematically showing a method for manufacturing a semiconductor member (semiconductor laminated structure) in the first embodiment of the present invention. First, as schematically shown in FIG. 1A, a substrate preparation step having a concavo-convex surface and a first epitaxial growth step are performed.

  In the substrate preparation step, a substrate 30 having irregularities on the surface is prepared. The unevenness includes a plurality of concave portions 30r and a plurality of convex portions 30p. For example, the concave portions 30r or the convex portions 30p can be formed to have shapes such as discrete islands, stripes, or lattices.

  As a specific example, for example, a C-plane sapphire substrate can be adopted as the substrate 30 and the surface thereof can be processed to be uneven in a stripe shape. The width a of the recess 30r is preferably 0.2 μm to 40 μm, and more preferably 1 μm to 10 μm. The width b of the convex portion 30p is preferably 0.2 μm to 40 μm, and more preferably 1 μm to 10 μm. The stripe direction is preferably parallel to the <11-20> direction or the <1-100> direction of the group III nitride semiconductor grown on the substrate 30.

  Such a substrate 30 is formed by, for example, growing a group III nitride semiconductor layer on a flat material substrate by MBE or vapor phase growth to produce a template substrate, followed by photolithography and dry etching. It can be obtained by performing etching from the surface of the template substrate to the surface of the material substrate or a position deeper than the surface of the material substrate. Here, the buffer layer may be formed before the group III nitride semiconductor layer is grown on the material substrate.

  As another specific example, in order to obtain a nonpolar flat surface, for example, an r-plane sapphire substrate can be employed as the substrate 30. Here, a condition for facilitating facet growth and performing the subsequent lateral growth uniformly as much as when a C-plane sapphire substrate is employed is illustrated. The width a of the recess 30r is preferably 0.2 μm to 40 μm, and preferably 1 μm to 10 μm. The width b of the convex portion 30p is preferably 0.2 μm to 40 μm, and preferably 1 μm to 10 μm. The direction of the stripe is preferably parallel to the <0001> direction of the group III nitride semiconductor grown on the substrate 30.

  Next, after pre-processing the substrate 30 as necessary, the substrate 30 is placed in a chamber of a vapor phase growth apparatus such as MOCVD or HVPE. Here, the pretreatment can include, for example, treatment with an acid, an alkali, or an organic solvent.

  After the substrate 30 is placed in the chamber of the vapor phase growth apparatus, a mixed gas of hydrogen and nitrogen is supplied into the chamber, and the temperature is set to 1100 to 1200 ° C. Thereafter, the temperature is lowered, trimethylgallium and ammonia are supplied into the chamber, and a gallium nitride buffer layer (not shown) is grown on the surface of the substrate 30.

  Next, a first epitaxial growth step is performed. Specifically, the temperature is raised, trimethylgallium, trimethylaluminum, and ammonia are supplied into the chamber, and the first semiconductor layer 31 made of an Al-containing group III nitride semiconductor is mainly laterally extended from the convex portion 30p of the substrate 30. Grow direction. Here, the growth temperature is preferably 1000 to 1300 ° C. Here, when the first semiconductor layer 31 made of an Al-containing group III nitride semiconductor is mainly grown in the lateral direction from the convex portion 30p of the substrate 30, the semiconductor layer hardly grows from the concave portion 30r of the substrate 30.

  If the distance (groove depth) f from the bottom surface of the concave portion of the substrate 30 to the top surface of the first semiconductor layer 31 is not sufficient, after the second semiconductor layer 32 is facet grown from the first semiconductor layer 31 in the subsequent process, When the third semiconductor layer 33 is grown from the facet and the adjacent third semiconductor layers 33 are associated with each other, the semiconductor layer grown from the recess 30r of the substrate 30 inhibits the association. Therefore, the first semiconductor layer 31 is preferably formed so that the gap e and the groove depth f between the adjacent first semiconductor layers 31 satisfy e ≦ f, and so as to satisfy 1.2e ≦ f. More preferably. By forming the first semiconductor layer 31 under the condition that the semiconductor layer mainly grows laterally from the protrusion 30p (in this condition, the semiconductor layer hardly grows from the recess 30r), a deep recess (a As in the case of forming ≦ f), the association of adjacent semiconductor layers is not hindered by the semiconductor layer growing from the recess.

  In the first epitaxial growth step, the first semiconductor layer 31 is grown mainly in the lateral direction, so that the gap e between the adjacent first semiconductor layers 31 satisfies the relationship a> e.

  The growth of the semiconductor layer 31 is stopped before the adjacent semiconductor layers 31 meet each other. In other words, the growth of the semiconductor layer 31 is stopped in a state where there is a gap between the adjacent semiconductor layers 31. The association on the recess 30r is performed by the third semiconductor layer 33 grown from the first semiconductor layer 31 through the facet after the second semiconductor layer 32 is grown from the facet.

  A convex groove in the cross section is formed by the gap between the first semiconductor layer 31 growing from the adjacent convex portion 30p and the concave portion 30r.

  Next, as schematically shown in FIG. 1B, a second epitaxial growth step is performed. In the second epitaxial growth step, the growth conditions such as the growth temperature and the growth pressure are changed, and the second semiconductor layer 32 made of an Al-containing group III nitride semiconductor is facet grown on the first semiconductor layer 31 to form a facet. . The growth temperature in the second epitaxial growth step is preferably 900 to 1200 ° C., for example. At this time, the presence of the first semiconductor layer 31 restricts the supply of the raw material to the recess 30r of the substrate 30, and the facet growth from the recess 30r is suppressed. That is, the small gap e between the adjacent first semiconductor layers 32 contributes to suppression of facet or semiconductor layer growth from the recesses 30r. On the other hand, if the gap e is too small, the second semiconductor layer 32 (facet) grown from the adjacent first semiconductor layer 31 will be associated, so that the adjacent second semiconductor layer 32 will not be associated with the gap e. Should be determined.

  Next, as schematically shown in FIG. 1C, a third epitaxial growth step is performed. In the third epitaxial growth step, the growth conditions such as the growth temperature and the growth pressure are further changed, and the third semiconductor layer 33 made of an Al-containing group III nitride semiconductor is laterally grown with the faceted second semiconductor layer 32 as a nucleus. Let The growth temperature in the third epitaxial growth step is preferably 1000 to 1300 ° C., for example. The third semiconductor layer 33 that has continued to grow in the lateral direction eventually associates with the adjacent semiconductor layer 33.

  If the growth of the third semiconductor layer 33 is further continued, it grows not only in the horizontal direction but also in the vertical direction, and the surface of the third semiconductor layer 33 is flattened. Dislocations connected from the vicinity of the interface between the substrate 30 and the first semiconductor layer 31 are bent in the lateral direction by the second semiconductor layer 32 forming facets, and in a direction parallel to the substrate surface as the semiconductor layer 33 grows in the lateral direction. proceed. Therefore, an Al-containing group III nitride semiconductor member having a low surface dislocation density is obtained.

  In the Al-containing group III nitride semiconductor member thus obtained, the cross section of the space formed by the gap between the first semiconductor layer 31 growing from the adjacent convex portion 30p and the concave portion 30r has a convex shape.

  The first, second, and third epitaxial growth processes may be performed continuously by changing the growth conditions from when the substrate is put into the chamber of the vapor phase growth apparatus to when it is taken out, or using different growth apparatuses. May be implemented.

  As described above, the semiconductor layers 31, 32, and 33 can be, for example, Al-containing group III nitride semiconductors. The composition (for example, Al concentration) of the semiconductor layers 31, 32, and 33 may be the same or different from each other.

  By performing the first epitaxial growth step, it is possible to form deep convex grooves that function to prevent inhibition of crystal growth from the convex portion due to crystal growth from the concave portion. Since such a convex groove has a narrow entrance, it is possible to effectively suppress the growth of a semiconductor in the groove.

  Further, by performing the first epitaxial growth step, the groove aspect ratio (groove depth (f) / groove inlet width (e)) can be made larger than before. In order to form a sufficiently deep groove with a steep cross-sectional shape by processing a substrate, an expensive ICP (inductively coupled plasma) type RIE (reactive ion etching) apparatus is required, but the first epitaxial growth step is performed. In some cases, it is sufficient to form a relatively shallow groove with an inexpensive RIE apparatus.

  FIG. 2 is a diagram schematically showing a method for manufacturing a semiconductor member (semiconductor laminated structure) in the second embodiment of the present invention. First, as schematically shown in FIG. 2A, a substrate preparation step having a concavo-convex surface and a first epitaxial growth step are performed.

  In the substrate preparation step, a substrate 10 having irregularities on the surface is prepared. The unevenness includes a plurality of concave portions 10r and a plurality of convex portions 10p, and can be formed, for example, such that the concave portions 10r or the convex portions 10p have shapes such as discrete islands, stripes, or lattices.

  As a specific example, for example, a C-plane sapphire substrate can be adopted as the substrate 10 and the surface thereof can be processed to be uneven. The width a of the recess 10r is preferably 0.2 μm to 40 μm, and more preferably 1 μm to 10 μm. The width b of the convex portion 10p is preferably 0.2 μm to 40 μm, and more preferably 1 μm to 10 μm. The direction of the stripe is preferably parallel to the <11-20> direction or the <1-100> direction of the Al-containing group III nitride semiconductor grown on the substrate 10.

  For example, such a substrate 10 is formed by growing a group III nitride semiconductor layer on a flat material substrate by MBE method or vapor phase growth method to produce a template substrate, and then by photolithography and dry etching. It can be obtained by performing etching from the surface of the template substrate to the surface of the material substrate or from the surface of the material substrate to a deeper position. Here, the buffer layer may be formed before the group III nitride semiconductor layer is grown on the material substrate.

  As another specific example, in order to obtain a nonpolar flat surface, for example, an r-plane sapphire substrate can be employed as the substrate 30. Here, conditions for facilitating the facet growth and for allowing the subsequent lateral growth to proceed as uniformly as when the C-plane sapphire substrate is employed are illustrated. The width a of the recess 10r is preferably 0.2 μm to 40 μm, and preferably 1 μm to 10 μm. The width b of the convex portion 10p is preferably 0.2 μm to 40 μm, and preferably 1 μm to 10 μm. The direction of the stripe is preferably parallel to the <0001> direction of the group III nitride semiconductor grown on the substrate 10.

  The depth of the concave portion 10r (the distance from the bottom surface of the concave portion 10r to the upper surface of the convex portion 10p) g is sufficiently deep so that the semiconductor layer grown from the concave portion 10r does not affect the semiconductor layer grown from the convex portion 10p. For example, preferably a ≦ g, and more preferably 1.2a ≦ g.

  Next, after pre-processing the substrate 10 as necessary, the substrate 10 is put into a chamber of a vapor phase growth apparatus such as MOCVD or HVPE. Here, the pretreatment can include, for example, treatment with an acid, an alkali, or an organic solvent.

  After the substrate 10 is placed in the chamber of the vapor phase growth apparatus, a mixed gas of hydrogen and nitrogen is supplied into the chamber, and the temperature is set to 1100 to 1200 ° C. Thereafter, the temperature is lowered, trimethylgallium and ammonia are supplied into the chamber, and a gallium nitride buffer layer (not shown) is grown on the surface of the substrate 10.

  Next, a first epitaxial growth step is performed. In the first epitaxial growth step, trimethylgallium, trimethylaluminum, and ammonia are supplied into the chamber, and the first semiconductor layer 11 made of an Al-containing group III nitride semiconductor is facet grown on the convex portion 10p of the substrate 10 to perform facet growth. Form. At this time, the semiconductor layer 12 made of a group III nitride semiconductor is facet grown in the recess 10r of the substrate 10 to form a facet. The growth temperature in the first epitaxial growth step is preferably 900 to 1200 ° C., for example.

  Next, as schematically shown in FIG. 2B, a second epitaxial growth step is performed. In the second epitaxial growth step, the growth conditions such as the growth temperature and the growth pressure are changed, and the second semiconductor layer 13 made of an Al-containing group III nitride semiconductor is laterally grown with the faceted first semiconductor layer 11 as a nucleus. . The growth temperature in the second epitaxial growth step is preferably, for example, 1000 to 1300 ° C. During the growth of the second semiconductor layer 13, the semiconductor layer 14 also grows laterally from the semiconductor layer 12 in the recess 10 r, but the growth of the semiconductor layer 14 involves the lateral growth of the semiconductor layer 13 from the first semiconductor layer 11. Do not disturb. The semiconductor layer 13 that has continued to grow in the lateral direction eventually associates with the adjacent semiconductor layer 13 to form a flat portion.

  Dislocations connected from the vicinity of the interface between the substrate 10 and the first semiconductor layer 11 are bent in the lateral direction by the facets 11 and proceed in a direction parallel to the substrate surface as the second semiconductor layer 13 grows in the lateral direction. Therefore, an Al-containing group III nitride semiconductor member having a low surface dislocation density is obtained.

  The first and second epitaxial growth processes may be performed continuously while changing the growth conditions from when the substrate is put into the vapor phase growth apparatus to when it is taken out, or may be carried out using different growth apparatuses. .

  As described above, the semiconductor layer 11 (12) and the semiconductor layer 13 (14) may be, for example, an Al-containing group III nitride semiconductor. The composition (for example, Al concentration) of the semiconductor layer 11 (12) and the semiconductor layer 13 (14) may be the same or different from each other.

  FIG. 3 is a view schematically showing a method for manufacturing a semiconductor member (semiconductor laminated structure) in the third embodiment of the present invention. This embodiment is suitable for obtaining a non-polar group III-nitride semiconductor member that is flat and has a low dislocation density.

  First, the polarity and polarization peculiar to the group III nitride semiconductor will be described. When a group III nitride semiconductor is grown on a C-plane sapphire substrate, the group III nitride semiconductor grows epitaxially while maintaining the C-plane as a flat surface. Considering the case where a light emitting device or the like is formed on such a group III nitride semiconductor, spontaneous polarization occurs due to the presence of a Ga (Al) plane and an N plane in the C-axis direction. Furthermore, when an (Al) InGaN quantum well layer is used for the active layer, piezoelectric polarization is superimposed due to compressive strain. These greatly affect the quantum confined Stark effect, causing a shift in emission wavelength and a decrease in emission efficiency due to the injection current density.

  As a countermeasure against this, growing a-plane or m-plane, which is a nonpolar plane of a group III nitride semiconductor that does not receive a polarization electric field effect, has been studied. However, when the a-plane or m-plane is grown, a plane perpendicular to the C-plane grows, so that not only dislocations but also stacking faults occur at a high density, and even if a light-emitting device is formed thereon, high luminous efficiency Cannot be obtained.

  Therefore, a mask layer having an opening is formed on an a-plane or m-plane GaN template substrate, GaN is selectively grown, and GaN is laterally grown in the C-axis direction, thereby reducing dislocation density. A method for obtaining a GaN surface has been proposed. However, in this case, since one surface of the seed part is a Ga (Al) surface and the other is an N surface, the lateral growth rate of the Ga (Al) surface becomes dominant, and The meeting part exists not on the center of the mask layer but near the side surface of the seed part N surface.

  According to Non-Patent Document 5, a mask layer having an opening is provided on a GaN template substrate, a GaN seed layer is grown from the opening, and the upper part of the seed layer is also covered with a mask layer. By growing, a flat a-plane GaN can be obtained. Non-Patent Document 6 reports that a stripe mask is formed on an m-plane GaN template substrate formed by MBE, and lateral growth along the C-axis from an opening portion by HVPE. However, in an Al-containing group III nitride semiconductor, since polycrystals are deposited on the mask layer, these cannot be applied.

  In contrast, the method of growing a group III nitride semiconductor on a substrate having an uneven surface does not require a mask, which is advantageous for growing a group III nitride semiconductor containing Al.

  Hereinafter, a third embodiment of the present invention will be described with reference to FIG. First, as schematically shown in FIG. 3A, a step of preparing a substrate having irregularities on the surface and a first epitaxial growth step are performed.

  In the substrate preparation step, a substrate 20 having an uneven surface is prepared. The unevenness includes a plurality of concave portions 20r and a plurality of convex portions 20p. For example, the concave portions 20r or the convex portions 20p can be formed to have shapes such as discrete islands, stripes, or lattices. As a specific example, for example, an r-plane sapphire substrate can be adopted as the substrate 20. The width a of the recess 20r of the substrate 20 is preferably 0.2 μm to 40 μm, and preferably 1 μm to 10 μm. The width b of the convex portion 20p of the substrate 20 is preferably 0.2 μm to 40 μm, and preferably 1 μm to 10 μm. The direction of the stripe is preferably parallel to the <11-00> direction of the group III nitride semiconductor grown on the substrate 20. In this case, the surface of the group III nitride semiconductor grown on the substrate is a-plane.

As a method for obtaining a flat surface of a nonpolar group III nitride semiconductor, an m-plane group III nitride semiconductor can also be grown on a spinel (100) substrate such as γ-LiAlO ₂ . In this case, as described above, the width of the recess 20r is preferably 0.2 μm to 40 μm, and more preferably 1 μm to 10 μm. The width of the convex portion 20p is preferably 0.2 μm to 40 μm, and preferably 1 μm to 10 μm. However, the stripe direction is preferably parallel to the <112-0> direction of the group III nitride semiconductor grown on the substrate.

  The depth of the recess 20r (the distance from the bottom surface of the recess 20r to the top surface of the projection 20p) g is sufficiently deep so that the semiconductor layer grown from the recess 20r does not affect the semiconductor layer grown from the projection 20p. For example, preferably a ≦ g, and more preferably 1.2a ≦ g.

  Next, after pre-processing the substrate 20 as necessary, the substrate 20 is placed in a chamber of a vapor phase growth apparatus such as MOCVD or HVPE. Here, the pretreatment can include, for example, treatment with an acid, an alkali, or an organic solvent.

  After the substrate 20 is placed in the chamber of the vapor phase growth apparatus, a mixed gas of hydrogen and nitrogen is supplied into the chamber, and the temperature is set to 1100 to 1200 ° C. Thereafter, the temperature is lowered, trimethylgallium and ammonia are supplied into the chamber, and a gallium nitride buffer layer (not shown) is grown on the surface of the substrate 10.

  Next, a first epitaxial growth step is performed. In the first epitaxial growth step, trimethylgallium, trimethylaluminum, and ammonia are supplied into the chamber, and the first semiconductor layer 21 made of an Al-containing group III nitride semiconductor is grown on the convex portion 20p of the substrate 20. At this time, a semiconductor layer 22 made of a group III nitride semiconductor grows in the recess 20r of the substrate 20. The growth temperature in the first epitaxial growth step is preferably 1000 to 1300 ° C., for example. Under the conditions of this embodiment, facets are not formed, and the cross sections of the semiconductor layers 21 and 22 are substantially rectangular.

Similar cross-sectional structures can be obtained by other methods. For example, a flat r-plane sapphire substrate that has not been surface-treated or a spinel (100) substrate such as γ-LiAlO ₂ is used as a material substrate, and a vapor deposition method or a growth method such as MBE is performed on the material substrate. Then, the group III nitride semiconductor layer is grown through the buffer layer or without the buffer layer to produce an a-plane or m-plane non-polar group III nitride semiconductor template substrate. Such a template substrate is preferably produced by MBE rather than vapor phase epitaxy. Next, etching is performed from the surface of the template substrate to the surface of the material substrate or a position deeper than the surface of the material substrate by photolithography and dry etching. By such a method, a structure having features common to the structure schematically shown in FIG. 3A can be obtained. However, in this method, a semiconductor layer corresponding to the semiconductor layer 22 is not formed, but the semiconductor layer 22 is an originally unnecessary semiconductor layer.

  Next, as schematically shown in FIG. 3B, a second epitaxial growth step is performed. In the second epitaxial growth step, the growth conditions such as the growth temperature and the growth pressure are changed, and the second semiconductor layer 23 made of an Al-containing group III nitride semiconductor is laterally grown with the first semiconductor layer 21 as a nucleus. The growth temperature in the second epitaxial growth step is preferably, for example, 1000 to 1300 ° C. Although the semiconductor layer grows slightly from the semiconductor layer 22 in the recess 20r during the second semiconductor layer 23, the semiconductor layer grown from the semiconductor layer 22 grows when the relationship of a ≦ g is satisfied. It won't get in the way. The semiconductor layer 23 that has continued to grow in the lateral direction eventually associates with the adjacent semiconductor layer 23 to form a flat portion.

  The lateral growth rate of the semiconductor layer 23 is such that one of the ridge side surfaces is a Ga (Al) surface and the other is an N surface, so the lateral growth rate of the Ga (Al) surface is dominant, and the lateral direction The meeting portion between the tip portions that grows at a distance exists not near the center of the substrate groove but near the side surface of the ridge N surface.

  Dislocations generated from the interface between the substrate 20 and the semiconductor layer 21 become threading dislocations on the semiconductor layer 21 and remain on the semiconductor surface. On the other hand, in the semiconductor layer 23 that grows laterally with the semiconductor layer 21 as a nucleus, the dislocation proceeds in the direction parallel to the substrate surface along with the growth, so that the dislocation density on the surface of the semiconductor layer 23 is reduced. However, high-density dislocations and low-density dislocations are periodically repeated on the surface of the semiconductor laminated structure thus obtained.

  The first and second epitaxial growth processes may be performed continuously while changing the growth conditions from when the substrate is put into the vapor phase growth apparatus to when it is taken out, or may be carried out using different growth apparatuses. .

  The composition (for example, Al concentration) of the semiconductor layer 21 (22) and the semiconductor layer 23 (24) may be the same or different from each other.

  Furthermore, in order to obtain a semiconductor member having a low surface transition density, the steps schematically shown in FIGS. 3C and 3D may be additionally performed at least once.

  First, the semiconductor member schematically shown in FIG. 3B is taken out from the vapor phase growth apparatus, and irregularities are formed on the surface of the semiconductor member (second semiconductor layer 23) by photolithography and dry etching techniques. For example, the width a ′ of the recess 23r of the second semiconductor layer 23 is preferably 0.2 μm to 40 μm, and preferably 1 μm to 10 μm. The width b ′ of the convex portion 23p of the second semiconductor layer 23 is preferably 0.2 μm to 40 μm, and preferably 1 μm to 10 μm. In the case of an a-plane group III nitride semiconductor, the stripe direction is preferably formed so as to be parallel to the <11-00> direction of the group III nitride semiconductor grown on the substrate. In the case of an m-plane group III nitride semiconductor, the stripe direction is preferably formed to be parallel to the <112-0> direction.

  Furthermore, as schematically shown in FIG. 3C, the concave portion 23 r of the second semiconductor layer 23 is preferably disposed immediately above the convex portion 20 p of the substrate 20. Here, the portion immediately above the convex portion 20 p of the substrate 20 is a high dislocation density portion of the first semiconductor layer 21. The recess 23 r of the second semiconductor layer 23 is preferably arranged so as to cover the region of the protrusion 21 p of the semiconductor layer 21. However, if the width of the recess 23r is too wide, it takes time until the semiconductor layer 24 to be formed later associates with the adjacent semiconductor layer 24, and the semiconductor layer grown from the recess 23r of the semiconductor layer 23 during that time May interfere with lateral growth. Accordingly, the depth g ′ of the recess 23r is preferably deeper as long as it is equal to or smaller than the thickness of the semiconductor layer 23, and preferably satisfies a ′ ≦ g ′.

  Next, after pre-treating the semiconductor member schematically shown in FIG. 3C as necessary, a third epitaxial growth step is performed as schematically shown in FIG. Here, the pretreatment can include, for example, treatment with an acid, an alkali, or an organic solvent. In the third epitaxial growth step, the semiconductor member is placed in a chamber in a vapor phase growth apparatus, and the third semiconductor layer 24 made of an Al-containing group III nitride semiconductor is laterally grown with the ridge-shaped second semiconductor layer 23 as a nucleus. .

  At this time, the third semiconductor layer 24 made of a group III nitride semiconductor laterally grown from the second semiconductor layer 23 associates with the semiconductor layer 24 laterally grown from the adjacent semiconductor layer 23 to form a flat portion. . Third, the growth temperature in the epitaxial growth step is preferably 1000 to 1300 ° C., for example.

  The threading dislocations present in the semiconductor layer 21 are prevented from propagating upward by the voids formed in the recesses 23 disposed on the semiconductor layer 21. Furthermore, since the dislocation advances in a direction parallel to the substrate surface by the semiconductor layer 24 laterally grown from the ridge-shaped semiconductor layer 23, the dislocation density on the surface of the semiconductor layer 24 is reduced.

  The first, second, and third epitaxial growth steps can be performed by appropriately selecting growth conditions such as temperature and pressure. The composition (for example, Al concentration) of the semiconductor layers 21 (22), 23, and 24 may be the same or different from each other.

  By further repeating the additional steps schematically shown in FIGS. 3C and 3D, the dislocation density on the surface of the semiconductor multilayer structure can be reduced as much as possible. Such a method can also be applied to the first and second embodiments.

  Hereinafter, a method for manufacturing a device using the semiconductor member typified by the first to third embodiments will be exemplarily described.

  When forming a semiconductor device such as an LED or LD using a substrate on which an Al-containing group III nitride semiconductor is formed according to the manufacturing method represented by the first to third embodiments, which are exemplary embodiments In some cases, the substrate is removed from the vapor phase growth apparatus and stored. When the substrate is stored with the surface of the Al-containing group III nitride semiconductor exposed, even if the storage or the storage container is in an inert gas atmosphere such as a vacuum or nitrogen, the Al-containing group III nitride semiconductor The surface can be oxidized. Even when a substrate having a low dislocation density on the surface is obtained, it is meaningless to newly generate dislocations due to oxidation of the surface of the substrate in forming a device on the substrate.

  Therefore, in order to suppress oxidation of the substrate surface, when the surface is an Al-containing group III nitride semiconductor, a group III nitride semiconductor having an Al concentration lower than that of the Al-containing group III nitride semiconductor, or Al is used. It is preferable to grow a group III nitride semiconductor cap layer not included on the substrate surface. Thereby, even if the semiconductor substrate is stored in a vacuum chamber, a nitrogen packing, a nitrogen box, or exposed to the atmosphere after the semiconductor substrate is manufactured, natural oxidation of the surface can be suppressed.

  However, when handling a substrate having an Al-containing group III nitride semiconductor on the surface, it is impossible to completely prevent oxidation of the surface and a shallow portion near the surface. Therefore, it is preferable to perform a process for removing the oxide film before regrowth for producing a device on the substrate.

  The oxide film on the surface can be removed by an oxide film removing process that removes a part from the surface of the cap layer to a predetermined depth, or the entire cap layer or a part to a predetermined depth of the cap layer and the layer below it. . This oxide film removal process is performed in an atmosphere of hydrogen, nitrogen, ammonia, chlorine gas, hydrochloric acid gas, halogen gas or hydrogen halide gas, or a mixed gas atmosphere of all or a part of these before putting the substrate into the vapor phase growth apparatus. It may include a step of performing dry etching thermally or chemically, or a step of performing wet etching with acid or alkali.

  After the oxide film removal process, the substrate can be quickly placed in a vapor phase growth apparatus, and a layer structure for a group III nitride semiconductor electronic device and a light emitting device such as an LED or LD can be formed on the substrate. .

  Alternatively, the oxide film removal process may be performed in a vapor phase growth apparatus followed by the growth of the semiconductor layer. For example, in the vapor phase growth apparatus, a portion from the surface of the cap layer to a predetermined depth, or the entire cap layer, or a portion from the cap layer to the predetermined depth of the cap layer and the layer below it, is hydrogen, nitrogen, ammonia, chlorine. Gas, hydrochloric acid gas, halogen gas or hydrogen halide gas, or a gas mixture of all or a part thereof can be removed by in-situ etching thermally or chemically, followed by a growth process. can do.

  Alternatively, the oxide film removal process generates hydrogen radicals or nitrogen radicals by discharge in an atmosphere of hydrogen, nitrogen, ammonia, chlorine gas, hydrochloric acid gas, halogen gas or hydrogen halide gas, or a gas mixture of all or part thereof. The substrate surface may be physically or chemically attacked by the radicals. Such an oxide film removal process can be carried out in an apparatus different from the vapor phase growth apparatus or in a vapor phase growth apparatus having equipment for applying a direct current or alternating current high voltage to the anode and the cathode. When the oxide film removal process is performed in the vapor phase growth apparatus, a growth process can be performed subsequently.

  4 and 5 are schematic cross-sectional views showing examples of a semiconductor light emitting element formed using a semiconductor member manufactured according to the first embodiment. In the example shown in FIGS. 4 and 5, following the growth of the semiconductor layer 33, a semiconductor layer is further formed in the same vapor phase growth apparatus.

  FIG. 4 shows a cross-sectional structure of a near-ultraviolet light emitting diode having a light emitting layer having a multiple quantum well structure in which an AlInGaN semiconductor layer is a well layer. Hereinafter, a method for manufacturing the diode shown in FIG. 4 will be described as an example.

  First, a silicon-added n-type Al0.2GaN contact layer 121 having a thickness of 5.0 μm is grown on the group III nitride semiconductor layer 33 in the same vapor phase growth apparatus as the vapor phase growth apparatus in which it is formed. .

  Next, a silicon-added n-type Al0.2GaN cladding layer 122 having a thickness of 2.0 μm is grown. Next, a silicon-added n-type Al0.2GaN guide layer 123 having a thickness of 20 nm is grown.

  Next, the growth temperature is lowered to grow a light emitting layer 124 composed of a four-period multiple quantum well layer composed of an AlInGaN well layer having a thickness of 3.5 nm and an AlGaN barrier layer having a thickness of 5 nm. When the AlInGaN well layer is used, the emission wavelength shifts due to the injection current density and the emission efficiency decreases due to the quantum confined Stark effect. Such problems are alleviated by adding silicon to the gallium nitride barrier layer to shield part of the polarization electric field. However, it should be noted that excessive doping reduces crystallinity.

  Next, the growth temperature is raised, and a magnesium-added p-type Al0.2GaN guide layer 125 having a thickness of 20 nm is grown on the light emitting layer.

  Next, a magnesium-added p-type Al0.3GaN clad (current blocking) layer 126 having a thickness of 50 nm is formed. The p-type cladding (current block) layer may be a superlattice in which two layers having different compositions are stacked repeatedly. Next, a magnesium-added p-type gallium nitride contact layer 127 having a thickness of 20 nm is grown.

  Next, the substrate is taken out from the vapor phase growth apparatus, a mask having a predetermined shape is formed on the surface, and etching is performed from the p-type contact layer side in a dry etching apparatus to expose a part of the n-type contact layer 121.

  Next, an ohmic electrode 131 made of a material having high reflectivity (for example, Ag or the like) in the near ultraviolet to ultraviolet region is formed on the p-type contact layer. An ohmic electrode 132 made of Ti / Al is also formed on the n-type contact layer 121 exposed by dry etching.

  Next, after the substrate is polished and thinned, element isolation is performed by mechanical or physical scribing using a blade such as a cutter, or optical or thermal scribing using a YAG laser, an excimer laser, or the like.

  The light emitting diode thus obtained is preferably flip-chip mounted. This is because the projections and depressions are formed on the surface of the substrate 30, so that the light extraction efficiency is better when the light is extracted from the substrate 30 side. Of course, the light-emitting diode can be mounted face-up, but in this case, the p-type electrode needs to be translucent and the light extraction efficiency is poor.

  FIG. 5 shows a cross-sectional structure of a near-ultraviolet laser diode having a light emitting layer having a multiple quantum well structure in which an AlInGaN semiconductor layer is a well layer. Hereinafter, a method for manufacturing the diode shown in FIG. 5 will be described as an example.

  First, a 4.0 μm-thick silicon-added n-type Al0.2GaN contact layer 221 is grown on the group III nitride semiconductor layer 33 in the same vapor phase growth apparatus as the vapor phase growth apparatus on which it is formed. .

  Next, a silicon-added n-type Al0.2GaN cladding layer 222 having a thickness of 0.2 μm is grown. Next, a silicon-added n-type gallium nitride guide layer 223 having a thickness of 20 nm is grown.

  Next, the growth temperature is lowered to grow a light emitting layer 224 composed of a three-period multiple quantum well layer composed of an undoped AlInGaN well layer having a thickness of 3.5 nm and a silicon-added n-type AlGaN barrier layer having a thickness of 10 nm.

  Next, the growth temperature is raised to grow a magnesium-added p-type Al0.2GaN guide layer 225 having a thickness of 20 nm.

  Next, a magnesium-added p-type Al0.25GaN cladding layer 226 having a thickness of 0.5 μm is grown. Next, a magnesium-added p-type gallium nitride contact layer 227 having a thickness of 20 nm is grown.

  Next, the substrate is taken out from the vapor phase growth apparatus, a silicon oxide protective film is formed on the surface of the uppermost p-type gallium nitride contact layer 227, and an n-type gallium nitride contact layer 221 is formed by dry etching to form an n-side electrode. The n-side electrode 232 made of Ti / Al is formed on the exposed portion. At this time, the end face of the active layer to be the resonator face is exposed, and the etching end face is used as the resonator end face.

  Next, in order to form a striped waveguide region, a silicon oxide protective film is formed on the uppermost p-type contact layer 227, and the p-type contact layer 227 and the p-type are formed by photolithography and dry etching techniques. The cladding layer 226 is etched to form a ridge having a stripe width of 2 μm. By flowing a large current, the current rapidly spreads laterally below the ridge. Therefore, the etching depth for forming the ridge is preferably up to the p-type guide layer 225.

As a dry etching apparatus for forming a ridge, for example, simple RIE or ICP-RIE can be used. In this case, a chlorine-based gas such as Cl ₂ , CCl ₄ , or SiCl ₄ can be used.

  In order to form the current confinement portion, in addition to the above method, for example, a method in which silicon is ion-implanted from the p-type contact layer protected by a mask or a photoresist to the p-type cladding layer can be employed. . The silicon injection amount is preferably higher than the carrier concentration of the p-type layer, and can be controlled by the dose amount of silicon. Further, the formation depth of the current confinement layer can be controlled by the implantation energy of ion implantation.

  Next, after forming a striped ridge waveguide, a protective film 241 such as a silicon oxide film or a metal oxide film is formed on the ridge and the p-side etched exposed surface.

  Next, the surface of the p-type contact layer is exposed by, for example, lift-off or etching, and a p-side electrode 231 made of, for example, Ni / Au is formed on the p-type contact layer and the current blocking layer. Further, a protective film (not shown in FIG. 5) made of silicon oxide is also formed on the side surface.

  Next, after polishing and thinning the substrate, the wafer is broken into bars by mechanical or physical scribing using a blade such as a cutter, or by optical or thermal scribing using a YAG laser, excimer laser, or the like.

  Next, a reflection film (not shown in FIG. 5) made of a multilayer oxide film is formed on the resonator surface on the light reflection side or on the light reflection side and the light emission side in the sputtering or vapor deposition apparatus. . Next, a laser diode is obtained by isolating the substrate thus formed.

  Here, an example of manufacturing a semiconductor light emitting device formed using a semiconductor member manufactured according to the first embodiment has been described. However, a semiconductor member manufactured according to the second or third embodiment is used. It is also possible to manufacture a semiconductor light emitting device formed in this way.

It is a figure which shows typically the manufacturing method of the semiconductor member (semiconductor laminated structure) in 1st Embodiment of this invention. It is a figure which shows typically the manufacturing method of the semiconductor member (semiconductor laminated structure) in 2nd Embodiment of this invention. It is a figure which shows typically the manufacturing method of the semiconductor member (semiconductor laminated structure) in 3rd Embodiment of this invention. It is a figure which shows the cross-section of the near-ultraviolet light-emitting diode which has the light emitting layer of the multiple quantum well structure which used the AlInGaN semiconductor layer as the well layer. It is a figure which shows the cross-section of the near-ultraviolet laser diode which has the light emitting layer of the multiple quantum well structure which used the AlInGaN semiconductor layer as the well layer.

Explanation of symbols

DESCRIPTION OF SYMBOLS 10 Substrate 10p Convex part 10r Concave part 11 First semiconductor layer 12 Semiconductor layer 13 Second semiconductor layer 14 Semiconductor layer 20 Substrate 20p Convex part 20r Concave part 21 First semiconductor layer 22 Semiconductor layer 23 Second semiconductor layer 24 Third semiconductor layer 30 Substrate 30p convex portion 30r concave portion 31 first semiconductor layer 32 second semiconductor layer 33 third semiconductor layer 121 silicon-added n-type Al0.2GaN contact layer 122 silicon-added n-type Al0.2GaN cladding layer 123 silicon-added n-type Al0.2GaN guide layer 124 Light emitting layer 125 Magnesium-added p-type Al0.2GaN guide layer 126 Magnesium-added p-type Al0.3GaN cladding layer 127 Magnesium-added p-type gallium nitride contact layer 131 Ohmic electrode 132 Ohmic electrode 221 Silicon-added n-type Al0. GaN contact layer 222 Silicon-added n-type Al0.2GaN cladding layer 223 Silicon-added n-type gallium nitride guide layer 224 Light emitting layer 225 Magnesium-added p-type Al0.2GaN guide layer 226 Magnesium-added p-type Al0.25GaN cladding layer 227 Magnesium-added p-type Gallium nitride contact layer 231 p-side electrode 232 n-side electrode 241 protective film

Claims (11)

A method for manufacturing a semiconductor member, comprising:
A preparation step of preparing a substrate having recesses and protrusions;
A first growth step of growing a first semiconductor at least in a lateral direction from the convex portion;
A second growth step of growing a second semiconductor on the first semiconductor to form a facet made of the second semiconductor;
A third growth step for growing a third semiconductor at least laterally from the facet;
The manufacturing method of the semiconductor member characterized by including.   The first growth step is characterized in that the distance from the bottom surface of the recess to the top surface of the first semiconductor is equal to or greater than the gap between the first semiconductors growing from the adjacent projections. A method for producing a semiconductor member according to 1.   The first growth step is performed so that a cross section of a space formed by the gap between the first semiconductor growing from the adjacent convex portion and the concave portion has a convex shape. A method for producing a semiconductor member according to 1 or 2.   4. The method for manufacturing a semiconductor member according to claim 1, wherein the first, second, and third semiconductors include a group III nitride semiconductor. 5.   4. The method for manufacturing a semiconductor member according to claim 1, wherein the first, second, and third semiconductors include a group III nitride semiconductor containing Al. 5.   The method for manufacturing a semiconductor member according to claim 1, further comprising a step of forming a light emitting device on the third semiconductor.   A semiconductor member having a convex space in a cross section inside. A substrate having a plurality of concave portions and a plurality of convex portions;
A plurality of semiconductor portions respectively disposed on the plurality of convex portions;
A semiconductor layer disposed to cover the plurality of semiconductor portions;
The plurality of semiconductor parts are arranged separately from each other so that a gap is formed on the recess, and a cross section of a space formed by the recess and the gap has a convex shape. A semiconductor member.   The semiconductor member according to claim 8, wherein the semiconductor layer includes a first portion facet grown from each of the plurality of semiconductor portions and a second portion grown from the first portion.   The semiconductor member according to claim 8, wherein the plurality of semiconductor portions and the semiconductor layer include a group III nitride semiconductor.   The semiconductor member according to claim 8, wherein the plurality of semiconductor portions and the semiconductor layer include a group III nitride semiconductor containing Al.

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