JP2013084354A - Plasma display panel and method of manufacturing the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a power saving PDP in which electric power of address discharge is reduced.SOLUTION: A plasma display panel includes: a front substrate in which a plurality of display electrodes are disposed; and a rear substrate in which address electrodes are displayed so as to intersect with the display electrodes and an insulator layer is disposed on the address electrodes. The insulator layer includes a filler containing SiOas a main component. An average grain diameter of the filler and a film thickness T(μm) satisfy 0.2≤R/T≤1, and a relative permittivity of the insulator layer excluding the filler is 8 or more and a relative permittivity of the filler is 5 or less.

Description

  The present invention relates to a plasma display panel known as a display device and a manufacturing method thereof.

  In recent years, expectations for large screens and wall-mounted televisions are increasing as interactive information terminals, and there are many display devices such as liquid crystal display panels, field emission displays, and electroluminescence displays. Among these display devices, a plasma display panel (hereinafter referred to as “PDP”) is a thin display device with excellent visibility because it is self-luminous, can display beautiful images, and is easy to enlarge. Development for high definition and large screen is underway.

  The PDP has a front plate on which components such as a display electrode, a dielectric layer, and a protective layer made of MgO are formed, and a back plate on which components such as electrodes, partition walls, an insulator layer, and a phosphor layer are formed. -G and B are arranged opposite each other so as to form minute discharge cells (hereinafter simply referred to as cells), and the periphery is sealed with a sealing member. Then, a discharge gas obtained by mixing neon (Ne), xenon (Xe), and the like is sealed in the cell at a predetermined pressure, for example.

  Originally, PDP is a self-luminous type, so each cell has a very high viewing angle. However, with high definition and large screen, uniform panel characteristics are required in all areas. Various measures are taken against it. For example, by defining the discharge space and the phosphor shape, finding a method for realizing the structure using two coating processes at the same location, and obtaining uniform light emission from the phosphor with respect to changes in viewing angle Etc. are disclosed.

  For example, Patent Document 1 and Patent Document 2 are known as prior art document information relating to the invention of this application.

JP 2000-208057 A JP 2006-040794 A

  By the way, with increasing interest in energy saving in recent years, power saving of PDP is required. In order to cause the PDP to emit light, it is necessary to apply a voltage / current for causing discharge to each cell, and power is consumed at that time. In order to save power in the PDP, it is necessary to reduce the voltage and current necessary for causing discharge.

  There are roughly three types of discharge required for the PDP. That is, (1) “initialization discharge” for stabilizing discharge control, (2) “address discharge” for selecting light emitting cells, and (3) “sustain discharge” for projecting an image. It is. In recent PDPs, since the ratio of the power W required for address discharge is relatively increased, it is important to reduce the power W of the address discharge, that is, the voltage V / current I.

  In order to reduce the voltage V of the address discharge, it is effective to increase the relative dielectric constant of the insulator layer 33. The address discharge is generated when the charge amount Q between the display electrode 24 provided on the front plate 20 and the address electrode 32 provided on the back plate 30 becomes a certain level or more. Since the charge amount Q is determined by the product of the address discharge voltage V and the capacitance Cver between the display electrode 24 and the address electrode 32, the capacitance Cver is increased, that is, the relative dielectric constant of the insulator layer 33 is increased. This leads to a decrease in the voltage V of the address discharge.

  However, when the relative dielectric constant of the insulating layer 33 is increased, another problem that the current I of the address discharge increases occurs. This is because the capacitance Cin between the adjacent address electrodes 32 increases as the relative dielectric constant of the insulator layer 33 increases. When the capacitance Cin increases, the current leaked between the address electrodes 32 when the address discharge voltage V is applied increases. As a result, the current I for address discharge increases.

  As described above, when the relative dielectric constant of the insulating layer 33 is changed, the current V and the current I are reversed. Therefore, it is difficult to reduce the power W required for address discharge by simply changing the dielectric constant of the insulator layer 33, and a technique for increasing Cver and reducing Cin is required.

  One solution for this is to make the porosity of the insulator layer on the address electrode smaller than the porosity of the insulator layer other than on the address electrode. This solution aims to achieve the following effects. That is, an insulator having a large void ratio has a small relative dielectric constant of 1 in the void portion, and thus the relative dielectric constant is effectively reduced. Therefore, Cin can be relatively reduced by increasing the porosity of the insulator layer other than on the address electrode while keeping Cver large by decreasing the porosity of the insulator layer on the address electrode. .

  However, there are problems with this solution. If the porosity of the insulator layer other than on the address electrodes is increased, the insulator layer will break down during driving of the PDP, and the drive circuit may be broken or the data electrode on the back substrate may be disconnected. Is significantly reduced. This is because the possibility of local uneven distribution in the insulator layer increases due to an increase in the voids, and a portion where the insulator film thickness is effectively generated is generated, and dielectric breakdown occurs from that point. Another solution is needed to increase Cver and decrease Cin while keeping the porosity relatively small.

  The present invention has been made in view of the above situation, and an object of the present invention is to provide a high-quality and power-saving PDP with reduced address discharge power.

In order to achieve the above object, a PDP according to the present invention includes a front substrate on which a plurality of display electrodes are arranged, and a back surface on which address electrodes are arranged so as to intersect the display electrodes and an insulator layer is arranged on the address electrodes. The insulator layer includes a filler mainly composed of SiO ₂ , and the average particle size R (μm) of the filler and the film thickness T (μm) of the insulator layer are set to 0. The relationship is 2 ≦ R / T ≦ 1, wherein the dielectric layer excluding the filler has a relative dielectric constant of 8 or more, and the filler has a relative dielectric constant of 5 or less.

  As described above, according to the present invention, it is possible to provide a high-quality and power-saving PDP with reduced address discharge power.

Sectional perspective view which shows schematic structure of PDP in embodiment of this invention

  Hereinafter, a PDP according to an embodiment of the present invention will be described with reference to the drawings.

(Embodiment)
The configuration and characteristics of the PDP in this embodiment will be described. FIG. 1 is a cross-sectional perspective view showing a schematic configuration of a PDP in an embodiment of the present invention.

  In FIG. 1, the PDP 10 includes a front plate 20 and a back plate 30, and the front plate 20 and the back plate 30 are disposed to face each other so as to form a discharge space 40. The front plate 20 has a plurality of stripe-shaped display electrodes 24 that are paired with a scanning electrode 22 and a sustaining electrode 23 on a front glass substrate 21 such as sodium borosilicate glass formed by a float method. . Further, a black stripe 25 serving as a light shielding portion is formed between adjacent display electrodes 24. A dielectric layer 26 is formed so as to cover the display electrode 24 and the black stripe 25, and a protective layer 27 made of magnesium oxide (MgO) is further formed so as to cover the dielectric layer 26.

  On the other hand, the back plate 30 has an address electrode 32 formed on the back glass substrate 31 in a direction orthogonal to the display electrode 24 of the front plate 20, and an insulating layer 33 is provided to cover the address electrode 32. In addition, on the insulator layer 33, for example, stripe-shaped and cross-beam-shaped barrier ribs 34 are provided, and phosphor layers 35 are provided on the side surfaces of the barrier ribs 34 and on the surface of the insulator layer 33. In the discharge space 40 partitioned by the adjacent barrier ribs 34, the phosphor layer 35 has a red phosphor layer 35R that emits red light, a green phosphor layer 35G that emits green light, and a blue phosphor layer 35B that emits blue light in order. Is formed.

  The partition walls 34 of the PDP are formed in a grid pattern by a horizontal partition parallel to the display electrode 24 and a vertical partition perpendicular to the horizontal partition, and the vertical partition is formed to be slightly higher than the height of the horizontal partition. In addition to this, the present invention can also be applied to a flat cross-beam shape. The present invention can also be applied to a stripe-shaped partition excluding the horizontal partition.

  The scan electrode 22 and the sustain electrode 23 that constitute the display electrode 24 provided on the front plate 20 are each constituted by a transparent electrode and a bus electrode. It consists of materials, such as bus electrode Ag, and is each electrically connected to the transparent electrode.

  The front plate 20 and the back plate 30 are arranged opposite to each other with the partition wall 34 interposed therebetween so that the display electrode 24 and the address electrode 32 are orthogonal to each other and form a minute discharge space 40 inside, and the periphery is a sealing member. Seal with. Thereafter, the discharge space 40 is filled with a discharge gas mixed with Ne and Xe at a predetermined pressure to complete the PDP, and the video gas voltage is selectively applied to the display electrode 24 to discharge the discharge gas. The ultraviolet rays generated thereby excite the phosphor layers 35 of the respective colors to emit red, green, and blue colors, thereby displaying a color image.

(PDP manufacturing method)
Next, a method for manufacturing the back plate 30 will be described. First, a structure for the address electrode 32 by a method of screen printing a paste containing silver (Ag) material on the rear glass substrate 31 or a method of patterning using a photolithography method after forming a metal film on the entire surface. An address electrode 32 is formed by forming a material layer to be obtained and firing it at a desired temperature. Next, an insulating paste layer is formed by applying an insulating paste on the back glass substrate 31 on which the address electrodes 32 are formed by a die coating method or the like so as to cover the address electrodes 32. Thereafter, the insulator layer 33 is formed by firing the insulator paste layer. The insulator paste is a paint containing an insulator material such as glass powder, a binder, and a solvent.

  Specifically, in the embodiment of the present invention, the insulator paste is composed of 20% to 45% by weight of glass component, 15% to 50% by weight of filler, 10% to 20% by weight of binder, and 20% to 20% by weight of solvent. A blending ratio of 30% by weight was used.

  Moreover, the porosity of the insulator layer 33 can be changed by changing the ratio between the insulating filler and the glass component. In the experimental results described later, samples were prepared by changing these mixing ratios. In particular, good results were obtained by setting the glass components to 40 wt% to 45 wt% and fillers 15 wt% to 20 wt%.

Among them, the filler is a filler composed of an insulating material such as SiO ₂ or TiO ₂ , but in the experimental results described later, a sample is prepared by changing the filler material and particle size. did. In particular, the main component of the filler material is SiO _2, and the relationship between the average particle diameter R (μm) and the film thickness T (μm) of the insulator layer 33 is preferably 0.2 ≦ R / T ≦ 1. Results were obtained. Here, the average particle size R (μm) uses the value of D50 calculated by measuring the filler with a particle size distribution measuring instrument. The main component of SiO ₂ indicates that the proportion of SiO _{2 in} the entire filler is approximately 80% or more.

  The softening point Tg of the glass component is preferably close to the firing temperature of the back substrate described later. If the Tg is too small, the glass is softened from the initial stage of firing, so that the gas generated from the simultaneously fired address electrodes is easily trapped as bubbles in the insulator. This bubble is undesirable because it effectively increases the porosity of the insulator on the address electrode. If Tg is made relatively large, this problem can be solved since the densification of the insulator proceeds after the gas from the address electrode is emitted. In the experimental results described later, good results were obtained by setting the softening point Tg of the glass component to 540 ° C. to 570 ° C. and the firing temperature to 585 ° C. to 600 ° C.

  Note that the bubbles generated from the address electrode can be reduced even in the process of firing once after forming the address electrode, forming the insulator, and firing again without controlling the softening point Tg of the glass component. However, since this method requires firing to be divided into a plurality of times, leading to an increase in manufacturing cost, a method for controlling the softening point Tg as in the present invention is better.

  Next, a partition wall forming paste containing a partition wall material is applied on the insulator layer 33 and patterned into a predetermined shape to form a partition wall material layer, and then the entire back substrate is baked to form the partition walls 34. To do. Here, as a method of patterning the partition wall paste applied on the insulator layer 33, a photolithography method or a sandblast method can be used. Next, the phosphor layer 35 is formed by applying and baking a phosphor paste containing a phosphor material on the insulator layer 33 between the adjacent partition walls 34 and on the side surfaces of the partition walls 34. Through the above steps, the back plate 30 having predetermined constituent members on the back glass substrate 31 is completed.

  In this way, the front plate 20 and the back plate 30 provided with predetermined constituent members are arranged to face each other so that the scanning electrodes 22 and the address electrodes 32 are orthogonal to each other, and the periphery thereof is sealed with a glass frit, so that a discharge space is obtained. The PDP 10 is completed by enclosing a discharge gas containing Ne, Xe or the like in 40.

(Insulator layer of the present invention)
Hereinafter, a method for producing an insulator according to the present invention will be described. The insulator is applied in the form of a sheet on the rear glass substrate 31 and the address electrode 32 as shown in FIG. A die coating method is used for coating, and after applying the paste, it is formed into a sheet through a drying step and a firing step.

  As described above, the conventional PDP has a problem that the power of address discharge is large.

  In contrast, the inventors have included a low dielectric constant filler in the insulator layer, and the relationship between the average particle size R (μm) and the film thickness T (μm) is 0.2 ≦ R / T ≦ 1. It has been found that the above-mentioned problems can be solved by being expressed by the relationship.

  Here, the value of R / T, which is the ratio of the average particle size R (μm) to the film thickness T (μm), is closely related to the power of the address discharge. Here, the capacitance between the display electrode 24 and the address electrode 32 is Cver, and the capacitance between the adjacent address electrodes 32 is Cin.

  When the value of R / T is increased, a “size effect” that the electrostatic capacity Cver between the display electrode 24 and the address electrode 32 becomes larger than the electrostatic capacity Cin between the adjacent address electrodes 32 appears. come. This is because the low dielectric filler acts on Cver in parallel with other materials, whereas it acts on Cin in series.

  As described above, this effect is effective in reducing both the current V and the current I during address discharge, and leads to a reduction in address discharge power. As the value of R / T decreases, the size effect of the low dielectric constant filler is lost, and Cver and Cin approach the same value.

  However, when the value of R / T is set to 1 or more, the filler is exposed on the surface of the insulating layer, which hinders the formation of the partition wall 34. More specifically, the width of the partition wall may be uneven or the partition wall may fall down, thereby significantly reducing the quality of the PDP.

In order to sufficiently obtain the size effect of the low dielectric constant filler, the difference between the low dielectric constant filler and the relative dielectric constant of other materials must be large. The relative dielectric constant of the low dielectric constant filler may be 5 or less, and the relative dielectric constant of other materials may be 8 or more. In the study by the inventors, SiO ₂ was used as a material for the low dielectric constant filler.

  Further, in order to sufficiently obtain the size effect of the low dielectric constant filler, the blending ratio of the low dielectric constant filler is required to be at least 15% by weight. However, if the blending ratio exceeds 30% by weight, the sinterability of the insulator layer is significantly reduced.

  In the present invention, it is important that both the porosity of the insulator layer on the address electrode and the porosity of the insulator layer other than on the address electrode are in the range of 0.1 to 5%. is there. If the porosity exceeds 5%, the dielectric layer breaks down during the discharge of the PDP panel, leading to the deterioration of the quality of the PDP. When the porosity is less than 0.1%, the reflectance of the insulator layer is remarkably reduced, so that the light emission luminance of the PDP is lowered, and the quality of the PDP is also deteriorated. This is due to the fact that, since the porosity is reduced, the amount of light reflected at the interface of the gap of the insulator layer is reduced, and the amount of light extracted from the entire substrate is reduced. This porosity of 0.1 to 5% could be realized by adjusting the mixing ratio of the glass component and the filler.

Here, the porosity is a volume ratio of a portion of the insulator layer 33 where the insulator layer 33 does not exist, and is measured by the following method.
(1) The back plate 30 is cut and a sample in which the cross section of the insulator layer 33 is exposed is cut out.
(2) The insulator layer 33 is imaged with a secondary electron scanning electron microscope (SEM).
(3) The porosity is calculated from the captured image of the dielectric cross section.

  In addition, it is desirable that the dielectric cross section is coated with a resin in the gap and the periphery in order to increase the contrast during SEM imaging and to prevent measurement variations due to cracking during cleaving. This measurement was performed using a scanning electron microscope S-3000 manufactured by Hitachi. The imaging used for the calculation was performed in the reflected electron measurement mode with an acceleration voltage of 15 kV and a work distance of 15 mm.

  As a result of the above examination, it has been found that the quality of the PDP can be maintained while the address discharge power is reduced in the embodiment of the present invention.

  As described above, the PDP in the embodiment of the present invention includes a front substrate on which a plurality of display electrodes are arranged, and a rear substrate on which address electrodes are arranged so as to intersect the display electrodes and an insulating layer is arranged on the address electrodes. Between the front substrate, a plurality of display electrodes, and address electrodes arranged so as to intersect the display electrodes. In a plasma display panel having a back substrate on which an insulator layer is disposed, the insulator layer contains a low dielectric constant filler, and the relationship between the average particle diameter R (μm) and the film thickness T (μm) is 0. .. 2 ≦ R / T ≦ 1

  Further, the relative dielectric constant of the whole insulator layer is 8 or more, and the relative dielectric constant ε of the low dielectric constant filler is 5 or less.

Further, the low dielectric constant filler is a material mainly composed of SiO ₂ .

  The insulator layer has a thickness T (μm) of 5 to 15 μm, and the low dielectric constant filler has an average particle size R (μm) of 1 to 5 μm.

  Also, a front substrate on which a plurality of display electrodes are arranged, and a back surface in which address electrodes are arranged so as to intersect the display electrodes, an insulator layer is arranged on the address electrodes, and a partition is formed on the insulator layer A plasma display panel disposed opposite to a substrate so as to form a discharge space, wherein the void ratio of the insulator layer on the address electrode and the void of the insulator layer other than on the address electrode All the rates are in the range of 0.1 to 5%.

  In addition, when the back substrate is formed, the address electrodes and the insulating layer are not baked separately, but a process is performed in which both are patterned and then baked at the same time.

  This makes it possible to provide a high-quality power-saving PDP with reduced address discharge power.

  According to the PDP of the present invention, it is useful in that it is possible to provide a power-saving PDP with reduced address discharge power.

30 Back plate 31 Back glass substrate 32 Address electrode 33 Insulator layer 34 Partition 35 Phosphor layer

Claims (3)

A front substrate on which a plurality of display electrodes are arranged, and a rear substrate on which address electrodes are arranged so as to intersect the display electrodes and an insulating layer is arranged on the address electrodes,
Wherein the insulating layer comprises a filler mainly composed of SiO _2,
The average particle diameter R (μm) of the filler and the film thickness T (μm) of the insulator layer have a relationship of 0.2 ≦ R / T ≦ 1,
The plasma display panel, wherein a dielectric constant of the insulator layer excluding the filler is 8 or more, and a dielectric constant of the filler is 5 or less. 2. The plasma display panel according to claim 1, wherein a film thickness T (μm) of the insulator layer is 5 μm to 15 μm, and an average particle diameter R (μm) of the low dielectric constant filler is 1 μm to 5 μm. A method of manufacturing a plasma display panel according to claim 1,
A method for manufacturing a plasma display panel, wherein the address electrodes and the insulating layer are baked in the same step.

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