JP2013065691A - Semiconductor device manufacturing method and semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent an etchant from soaking from a memory cell region around a guard ring into a peripheral circuit region.SOLUTION: A semiconductor device manufacturing method comprises: forming a first interlayer insulation film on a semiconductor substrate in which a memory cell region and a peripheral circuit region are demarcated; removing a part of the first interlayer insulation film to form a guard ring groove around the memory cell region; filling the guard ring groove with a metal conductive material to form a guard ring and forming a support film on the first interlayer insulation film so as to cover the guard ring; forming openings in the support film in the memory cell region; and removing the first interlayer insulation film in the memory cell region with leaving the first interlayer insulation film in the peripheral circuit region by performing wet etching through the openings.

Description

  The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for manufacturing a semiconductor device including a guard ring surrounding a memory cell region.

  A technique is known in which a guard ring is formed at the boundary between the memory cell region and the peripheral circuit region, and this is used to leave the interlayer insulating film in the peripheral circuit region and gradually provide the interlayer insulating film in the memory cell region. (For example, refer to Patent Document 1).

  In addition, a technique is also known in which a guard ring groove surrounding a capacitor is embedded with the same material as that of wiring (for example, see Patent Document 2).

JP 2011-003598 A JP 2006-303545 A

  In the method of removing the interlayer insulating film in the memory cell region using the guard ring and leaving the interlayer insulating film in the peripheral circuit region, the guard ring is formed by the same process as the formation of the lower electrode of the capacitor. Here, since the lower electrode is formed so as to cover the inner surface in the cylinder hole formed in the interlayer insulating film, the surface area becomes smaller and the capacitance of the capacitor becomes smaller as the thickness of the lower electrode increases. . For this reason, it is desirable that the thickness of the lower electrode is small.

  However, if the thickness of the guard ring is small, the etching solution oozes from the memory cell region to the peripheral circuit region around the guard ring when the interlayer insulating film in the memory cell region is removed. As a result, the etching of the interlayer insulating film proceeds also in the peripheral circuit region, a cavity is formed, and a through hole to be formed later is short-circuited.

  The guard ring described in Patent Document 2 is formed in a process different from the capacitor forming process after the parallel plate type capacitor is formed. Even though the name is the same as the guard ring used in the capacitor structure of the crown structure, the purpose, function and effect are completely different. Therefore, the guard ring described in Patent Document 2 cannot be used for manufacturing a semiconductor device having a crown structure capacitor as it is.

  In a method for manufacturing a semiconductor device according to an embodiment of the present invention, a first interlayer insulating film is formed on a semiconductor substrate in which a memory cell region and a peripheral circuit region are defined, and a part of the first interlayer insulating film is formed. And a guard ring groove is formed around the memory cell region, the guard ring groove is filled with a metal conductive material to form a guard ring, and a support is provided on the first interlayer insulating film so as to cover the guard ring. Forming a film, forming an opening in the support film in the memory cell region, and performing wet etching through the opening, leaving the first interlayer insulating film in the peripheral circuit region; The first interlayer insulating film is removed.

  According to the present invention, since the guard ring groove is filled with the metal conductive material to form the guard ring, when the first interlayer insulating film in the memory cell region is wet-etched, the etching solution is removed from the memory cell region to the periphery. It is possible to prevent the seepage into the circuit area.

(A) thru | or (c) are process drawings for demonstrating the manufacturing method of the 1st related semiconductor device. (A) thru | or (c) are process drawings for demonstrating the process following the process of FIG.1 (c). It is a figure for demonstrating the problem in the manufacturing method of the 1st related semiconductor device. (A) thru | or (c) are process drawings for demonstrating the manufacturing method of the 2nd related semiconductor device. (A) thru | or (c) are process drawings for demonstrating the process following the process of FIG.4 (c). (A) And (b) is a figure for demonstrating the problem in the manufacturing method of the 2nd related semiconductor device. 1 is a schematic plan view of a semiconductor device according to a first embodiment of the present invention. (A) thru | or (c) are process drawings for demonstrating the manufacturing method of the semiconductor device which concerns on the 1st Embodiment of this invention. (A) thru | or (c) are process drawings for demonstrating the process following the process of FIG.8 (c). (A) thru | or (c) are process drawings for demonstrating the process following the process of FIG.9 (c). (A) thru | or (c) are process drawings for demonstrating the process following the process shown in FIG.10 (c).

  In order to facilitate understanding of the present invention, a related method for manufacturing a semiconductor device will be described before describing embodiments of the present invention.

  FIG. 1A to FIG. 1C and FIG. 2A to FIG. 2C are process diagrams for explaining a first related semiconductor device manufacturing method. The manufactured semiconductor device is a semiconductor device (for example, DRAM: Dynamic Random Memory) having a capacitor having a crown structure. This method is mainly used for the manufacture of semiconductor devices with a design rule of 40 nm or earlier. In each drawing, only the portions necessary for the description are shown, which is significantly simplified as compared with the actual configuration of the semiconductor device.

  FIG. 1A shows a state in which the process up to the formation of the lower electrode of the capacitor is completed. In the figure, the left side is a memory cell region 110 and the right side is a peripheral circuit region 130.

  In the figure, pads 151, 152, and 153 are formed on a semiconductor substrate (not shown), and an insulating film 154, a first interlayer insulating film 155, and a support film 156 are sequentially formed so as to cover the pads.

  In the memory cell region 110, a hole (cylinder hole) reaching the pad 151 through the support film 156, the first interlayer insulating film 155, and the insulating film 154 is formed, and a lower electrode 157 is formed so as to cover the inner surface of the hole. Has been. A guard ring 158 is formed at the boundary between the memory cell region 110 and the peripheral circuit region 130 so as to cover the inner surface of the guard ring groove formed so as to surround the memory cell region 110. The guard ring 158 is connected to the dummy pad 152 at the bottom. The hole for the lower electrode 157 and the guard ring groove, and the lower electrode 157 and the guard ring 158 are formed in the same process.

  The semiconductor device is manufactured as follows from the state of FIG.

  First, as shown in FIG. 1B, a part of the support film 156 in the memory cell region 110 is removed, and an opening 159 is formed. The opening 159 is used as an entrance for the etching solution. The positional relationship between the opening 159 and the lower electrode 157 is arbitrary.

  Subsequently, an etchant is introduced from the opening 159 formed in the support film 156, and the first interlayer insulating film 155 in the memory cell region 110 is removed as shown in FIG. Although it is difficult to understand in the drawing, since the etching solution also proceeds to the side, the first interlayer insulating film is etched in the memory cell region 110 even immediately below the support film 156. As a result, the first interlayer insulating film 155 in the memory cell region 110 is completely removed, and the outer peripheral surface of the lower electrode 157 is also exposed to the outside.

  On the other hand, in the peripheral circuit region 130, the guard ring 158 and the support film 156 prevent the etchant from entering, so the first interlayer insulating film 155 remains as it is.

  Next, as shown in FIG. 2A, a capacitor insulating film (not shown) is formed on the exposed inner and outer surfaces of the lower electrode 157, and the upper electrode 160 is formed thereon. The upper electrode 160 is formed so as to fill a gap between the inner peripheral side and the outer peripheral side of the lower electrode 157. In addition, an electrode plate 161 is formed on the upper electrode 160. Then, the electrode plate 161, the upper electrode 160, and the capacitor insulating film formed in the peripheral circuit region 130 are removed together with the support film 156.

  Next, as shown in FIG. 2B, a second interlayer insulating film 162 that covers the electrode plate 161 and the first interlayer insulating film 155 in the peripheral circuit region 130 is formed, and the surface thereof is planarized. Then, a through hole 163 that penetrates through the second interlayer insulating film 162, the first interlayer insulating film 155, and the insulating film 154 and reaches the corresponding pad 153 is formed.

  Next, as shown in FIG. 2C, an upper wiring 164 connected to the through hole 163 is formed on the second interlayer insulating film 162.

  Thereafter, if necessary, an upper wiring layer is formed and a protective film is formed to complete the semiconductor device.

  As described above, in the first related semiconductor device manufacturing method, the guard ring 158 is provided between the memory cell region 110 and the peripheral circuit region 130, and the first interlayer insulating film 155 in the memory cell region 110 is wet-etched. At this time, the first interlayer insulating film 155 in the peripheral circuit region 130 is prevented from being etched.

  However, as the semiconductor device is miniaturized and the capacitor is miniaturized, the thickness of the lower electrode 157 is further reduced, and the thickness of the guard ring 158 formed in the same process as the lower electrode 157 is also reduced. It was. As a result, the adhesion between the guard ring 158 and the support film 156 and the like is lowered, and the etchant oozes out between them as shown by the arrow in FIG. 3, so that the cavity 301 is formed in the peripheral circuit region 130. became. When such a cavity 301 exists, when the through hole 163 is formed later, a metal film is also formed on the inner surface of the cavity 301, causing a problem that the through holes 163 are short-circuited.

  This problem is caused by a decrease in the thickness of the guard ring 158, and can be solved by increasing the thickness of the guard ring 158. However, this means an increase in the film thickness of the lower electrode 156 of the capacitor, that is, a decrease in capacitance, which hinders the miniaturization of the element and the miniaturization of the semiconductor device.

  A method for solving the above problem (second related semiconductor device manufacturing method) will be described with reference to FIGS. 4 (a) to 4 (c) and FIGS. 5 (a) to 5 (c). This method is mainly used for manufacturing a semiconductor device of the design rule 30 or 25 nm generation.

  First, as shown in FIG. 4A, the lower electrode 457 is formed in the memory cell region 410. At this time, unlike the first method, no guard ring is formed.

  Next, as shown in FIG. 4B, a part of the support film 456 in the memory cell region 410 is removed to form an opening 459 and the support film 456 in the peripheral circuit region 430 is removed.

  Next, as shown in FIG. 4C, all of the sacrificial film 455 (corresponding to the first interlayer insulating film 155 in the related first method) is removed.

  Next, as shown in FIG. 5A, a capacitive insulating film (not shown), an upper electrode 460 are formed, and an electrode plate 461 is further formed. The capacitive insulating film, the upper electrode 460, and the electrode plate 461 in the peripheral circuit region 430 are removed.

  Next, as shown in FIG. 5B, an interlayer insulating film 462 that covers the memory cell region 410 and embeds the peripheral circuit region 430 is formed. Then, the upper surface of the interlayer insulating film 462 is planarized, and a through hole 463 that penetrates the interlayer insulating film 462 is formed.

  Next, as shown in FIG. 5C, an upper wiring 464 and the like connected to the through hole 463 are formed.

  Thereafter, a semiconductor device is completed by forming a protective film.

  As described above, in the second related method for manufacturing a semiconductor device, the guard ring is not provided, and all the sacrificial film 455 used for forming the lower electrode is removed. Thereafter, an interlayer insulating film 462 is formed, and the peripheral circuit region 430 is filled back. According to this method, unlike the first method, no cavity is formed in the interlayer insulating film 462 in the peripheral circuit region 430.

  However, since this method removes all the sacrificial film 455, it is not possible to provide accessories such as alignment marks in the first interlayer insulating film, which was possible with the first method. For example, it is assumed that an accessory 601 such as an alignment mark is formed on the sacrificial film 455 as shown in FIG. The accessory 601 is formed in a relatively shallow hollow shape, and the same metal film as the lower electrode 457 is formed on the inner surface thereof. However, the accessory 601 is not connected to a pad on the semiconductor substrate like the lower electrode 457. For this reason, when the sacrificial film 455 is removed, the sacrificial film 455 is scattered as shown by arrows. For this reason, when an accessory is provided on the sacrificial film 455, strict restrictions are imposed on the layout and the process so that the accessory is not scattered.

  In addition, in this method, a thick interlayer insulating film 462 needs to be formed due to a large step between the peripheral circuit region 430 and the memory cell region 410 when the peripheral circuit region 430 is backfilled. Further, as shown in FIG. 6B, since a large step (convex portion) 603 is formed in the memory cell region 410, etching is performed to remove most of the step 603 as indicated by an arrow A. CMP (Chemical Mechanical Polishing) or the like is required to remove the remaining irregularities as indicated by the arrow B. Since the step 603 is large, etching and CMP require a long time and are expensive.

  The present invention has been made in view of the above points.

  The method for manufacturing a semiconductor device according to the present invention generally includes forming a first interlayer insulating film on a semiconductor substrate in which a memory cell region and a peripheral circuit region are defined, and removing a portion of the first interlayer insulating film. A guard ring groove is formed around the memory cell region, the guard ring groove is filled with a metal conductive material to form a guard ring, and a support film is formed on the first interlayer insulating film so as to cover the guard ring. Forming an opening in the support film, and performing wet etching through the opening, thereby removing the first interlayer insulating film in the memory cell region while leaving the first interlayer insulating film in the peripheral circuit region. is there.

  Hereinafter, a method for manufacturing a semiconductor device according to the first embodiment of the present invention will be described in detail with reference to FIGS.

  FIG. 7 is a schematic plan view of the semiconductor device according to this embodiment. FIG. 7 shows a planar arrangement of each element constituting the semiconductor device, and each element is not necessarily visible.

  The illustrated semiconductor device 700 is a DRAM chip and has four memory cell regions 710 called mats. Further, a peripheral circuit region 730 is provided in the center in the left-right direction in the figure.

  In each memory cell region 710, a plurality of cell capacitors indicated by ◯ are arranged. A guard ring 756 is provided around each memory cell region 710.

  In the peripheral circuit region 730, a plurality of lower through holes 757 indicated by ◯ are arranged.

  Further, accessory recesses 760 each having a rectangular shape are formed near the center of the four sides of the semiconductor device 700.

  Hereinafter, the manufacturing process of the semiconductor device 700 will be described with reference to FIGS. The film formation technique and etching technique used in each process are known techniques. Each figure corresponds to a cross-sectional view taken along line A-A ′ of FIG. 7.

First, a memory cell region and a peripheral circuit region are defined on a circuit formation surface of a semiconductor substrate (Si substrate), and necessary elements such as FETs, wirings, pads, and the like are formed in each region. Then, an insulating film that covers the surface of the pad or the like, for example, a SiN film is formed, and the surface is planarized. Then, a first interlayer insulating film, for example, a SiO ₂ film is formed on the surface of the planarized insulating film. FIG. 8A shows the state. However, the semiconductor substrate is omitted, and an upper layer portion than the pad is shown. Further, parts not directly related to the present invention are omitted, and the configuration is significantly simplified as compared with an actual semiconductor device.

  In FIG. 8A, the memory cell region 710 is on the left side and the peripheral circuit region 730 is on the right side.

  In the memory cell region 710, a capacitor connecting pad 751 is formed. A dummy pad 752 is formed at the boundary between the memory cell region 710 and the peripheral circuit region 730. Further, a pad 753 for connecting a through hole is formed in the peripheral circuit region 730.

  An insulating film 754 is formed so as to cover the pads 751 to 753, and a first interlayer insulating film 755 is formed on the insulating film 754.

  Next, a part of the first interlayer insulating film 755 and the insulating film 754 is removed by using a photolithography technique, and a guard ring groove and a through hole hole reaching the dummy pad 752 and the through hole connection pad 753, respectively. Form. The guard ring groove is formed so as to surround the memory cell region 710. Then, as shown in FIG. 8B, the formed guard ring groove and through hole are filled with a metal conductive film, for example, a W (tungsten) film. This can be done by plug formation technology. Thus, the guard ring 756 embedded in the guard ring groove and the lower through hole 757 embedded in the through hole are formed.

  Next, as illustrated in FIG. 8C, a support film 758, for example, a SiN film, is formed on the upper surfaces of the guard ring 756 and the lower through-hole 757 and the first interlayer insulating film 755.

  Next, as shown in FIG. 9A, the support film 758, the first interlayer insulating film 755, and a part of the insulating film 754 are removed by photolithography, and the lower electrode hole reaching the capacitor connecting pad 751 is obtained. 759 is formed. Of the plurality of lower electrode holes 759, the hole located at the outermost periphery is for the dummy electrode, and may be formed so as to be in contact with the guard ring 756. Further, an accessory recess 760 such as an alignment mark may be formed simultaneously with the formation of the lower electrode hole 759. The depth of the accessory recess 760 may be smaller than the thickness of the first interlayer insulating film 755. Since it is not necessary to form the accessory recess 760 so as to penetrate the first interlayer insulating film 755, the restriction that the pattern size difference (rough density difference) of the process characteristics must be taken into consideration is eased.

  Next, as shown in FIG. 9B, a conductive film 761, which is a lower electrode, for example, a TiN film is formed. The conductive film 761 can be formed by a CVD (Chemical Vapor Developer) method so that the conductive film 761 is also formed on the inner peripheral wall surface of the lower electrode hole 759. Since the conductive film 761 is not related to the formation of the guard ring, the conductive film 761 can be thinned without considering the bleeding of the etching solution.

  Next, as shown in FIG. 9C, unnecessary portions of the conductive film 761 are removed by CMP or the like, so that the conductive film 761 in the lower electrode hole 759 becomes the lower electrode 762, and in the accessory recess 760. The conductive film 761 is an accessory 763. Further, an opening 764 is formed by removing part of the support film 758 in the memory cell region 710 using lithography. The opening 764 serves as an entrance for the etching solution. Note that the position of the opening 764 is arbitrary, and FIG. 9C does not correctly show the positional relationship between the opening 764 and the lower electrode 762.

  Next, as shown in FIG. 10A, the first interlayer insulating film 755 in the memory cell region 710 is removed by, for example, wet etching using hydrofluoric acid. The etching solution that has entered through the opening 764 also circulates to the side, and completely removes the first interlayer insulating film 755 in the memory cell region 710. Thereby, the outer peripheral wall surface of the lower electrode 762 is exposed.

  The etching solution tries to advance to the peripheral circuit region 730 but is blocked by the guard ring 756 and the support film 758. Unlike the related first method, the guard ring 756 is not the same thin conductive film as the lower electrode 762, but is a thick metal plug (plug structure). Effectively prevents oozing out.

  In addition, the accessory 763 is fixed to the support film 758, so that lift-off due to the etching solution does not occur, and the accessory 763 is not scattered even if it is not connected to a pad or the like on the semiconductor substrate side.

  Next, as shown in FIG. 10B, a capacitor insulating film (not shown), an upper electrode 765 are formed, and an electrode plate 766 is further formed. As the capacitor insulating film, a high dielectric film such as zirconium oxide, aluminum oxide, or hafnium oxide can be used. As the upper electrode 765, a field combination of a TiN film and boron-doped polysilicon can be used. Further, tungsten or the like can be used for the electrode plate 766.

  Next, as shown in FIG. 10C, the electrode plate 766 and the upper electrode 765 are processed. The support film 758 remains in the peripheral circuit region 730, and the surface thereof is flat. Therefore, a part of the upper electrode 765 and the electrode plate 766 formed on the support film 758 can be used as the wiring 767. In the related second method, since the support film in the peripheral circuit region is removed, such wiring cannot be realized.

Next, as shown in FIG. 11A, a second interlayer insulating film 768, for example, a SiO ₂ film, in which the electrode plate 766 and the wiring 767 are embedded is formed, and the surface thereof is flattened.

  Next, as shown in FIG. 11B, an upper through hole 769 that penetrates through the second interlayer insulating film 768 and connects to the lower through hole 757 is formed. The diameter of the upper through hole 769 may be different from the diameter of the lower through hole 757. Further, through-holes connected to the electrode plate 766 and the wiring 767 are also formed by the same process.

  Since the through-hole has a two-stage configuration, layout restrictions are eased. For example, since the etching time for the upper through hole is less than half that of the single-stage configuration, the hole diameter can be reduced. Thereby, the pitch of the upper wiring can be reduced. Further, since the wiring 767 can be interposed between the upper through-hole 769 and the lower through-hole 757, they do not necessarily have a positional relationship immediately above. In other words, the connection portion of the lower layer wiring and the connection portion of the upper layer wiring that are connected by the through hole may not be in a positional relationship directly below.

  Next, as shown in FIG. 11C, an upper wiring 772 made of, for example, aluminum or copper is formed.

  Thereafter, if necessary, an upper wiring layer is formed and a protective film is formed to complete the semiconductor device.

  As described above, according to the method for manufacturing a semiconductor device according to the present embodiment, since the guard ring has a plug structure, it is possible to effectively prevent the seepage of the etching solution in the vicinity thereof. In addition, there is no scattering of accessories.

  Although the present invention has been described with reference to the preferred embodiments, the present invention is not limited to the above-described embodiments, and various modifications can be made without departing from the spirit of the present invention.

  The materials, dimensions, film forming methods, film forming conditions, etching methods, etching conditions, and the like of each film described above are merely examples, and other materials, other methods, and different dimensions or conditions may be adopted. it can.

DESCRIPTION OF SYMBOLS 110 Memory cell area | region 130 Peripheral circuit area 151,152,153 Pad 154 Insulating film 155 1st interlayer insulation film 156 Support film 157 Lower electrode 158 Guard ring 159 Opening 160 Upper electrode 161 Electrode plate 162 Second 2nd interlayer insulation film 163 Through hole 164 Upper wiring 301 Cavity 410 Memory cell region 430 Peripheral circuit region 455 Sacrificial film 456 Support film 457 Lower electrode 459 Opening 460 Upper electrode 461 Electrode plate 462 Interlayer insulating film 463 Through hole 464 Upper wiring 601 Accessory 603 Step 710 Memory cell region 730 Peripheral circuit Region 751, 753 Pad 752 Dummy pad 754 Insulating film 755 First interlayer insulating film 756 Guard ring 757 Lower through hole 758 Support film 759 Part recess electrode hole 760 Accessories 761 conductive film 762 lower electrode 763 accessory 764 opening 765 upper electrode 766 electrode plate 767 wiring 768 second interlayer insulating film 769 upper through hole 770, 771 through-hole 772 upper wires

Claims (10)

Forming a first interlayer insulating film on a semiconductor substrate in which a memory cell region and a peripheral circuit region are defined;
Removing a part of the first interlayer insulating film to form a guard ring groove around the memory cell region;
The guard ring groove is filled with a metal conductive material to form a guard ring,
Forming a support film on the first interlayer insulating film so as to cover the guard ring;
Forming an opening in the support film in the memory cell region;
Performing wet etching through the opening to remove the first interlayer insulating film in the memory cell region while leaving the first interlayer insulating film in the peripheral circuit region;
A method for manufacturing a semiconductor device. When forming the guard ring groove, forming a first through hole in the first interlayer insulating film of the peripheral circuit region,
When the guard ring groove is filled with the metal conductive material, the first through hole is filled with the metal conductive material;
The method of manufacturing a semiconductor device according to claim 1. After the wet etching,
Forming a second interlayer insulating film on the support film;
Forming a second through hole hole that penetrates the second interlayer insulating film and reaches the metal conductive material buried in the first through hole hole;
The method of manufacturing a semiconductor device according to claim 2. After forming the support film and before forming the opening in the support film in the memory cell region,
Forming a capacitor hole penetrating the support film and the first interlayer insulating film in the memory cell region;
Forming a lower electrode covering the inner surface of the capacitor hole;
The method of manufacturing a semiconductor device according to claim 3.   The accessory hole or hole is formed by partially removing the support film and the first interlayer insulating film in the peripheral circuit region when forming the capacitor hole. A method for manufacturing a semiconductor device. After forming the lower electrode,
Forming a capacitive insulating film and an upper electrode film;
Patterning the capacitive insulating film and the upper electrode film;
Thereafter, the second interlayer insulating film is formed so as to embed the capacitive insulating film and the upper electrode film,
Forming a second through hole hole that penetrates at least the second interlayer insulating film and the support film and reaches the metal conductive material buried in the first through hole forming hole;
6. The method of manufacturing a semiconductor device according to claim 4, wherein the method is a semiconductor device.   7. The method of manufacturing a semiconductor device according to claim 6, wherein when patterning the capacitor insulating film and the upper electrode film, a part of the upper electrode film is left as a wiring on the second insulating film.   A semiconductor device manufactured by the method for manufacturing a semiconductor device according to claim 1. A guard ring formed at the boundary between the memory cell region and the peripheral circuit region and embedded with a metal conductive material;
A capacitor having a crown structure formed in the memory cell region and having an upper electrode in contact with one side wall of the guard ring;
A first interlayer insulating film formed in the peripheral circuit region and in contact with the other side wall of the guard ring;
A semiconductor device comprising: A lower through hole formed through the first interlayer insulating layer;
A second interlayer insulating film provided on the first interlayer insulating film;
An upper through hole formed through the second interlayer insulating film and connected to the lower through hole;
The semiconductor device according to claim 9, comprising:

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