JP2008244403A - Semiconductor device and manufacturing method thereof - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device in which the capacity of an MOS type capacitor can be increased without increasing the area of the MOS type capacitor. <P>SOLUTION: This semiconductor device provided with the MOS type capacitor is provided with an insulating film 3 formed on a semiconductor substrate 1, an upper electrode 40 formed on the insulating layer 3, a plurality of openings 42 formed on the upper electrode 40, and an impurity region 7 formed on the semiconductor substrate 1 positioned below each of the openings 42. The openings 42 and the impurity regions 7 are preferably disposed in a staggered way. The semiconductor device is further provided with an element isolation film 2 for isolating the element region where the MOS capacitor is formed, and the insulating film 3 and the upper electrode 40 are formed on the entire surface of the semiconductor substrate 1 positioned in the element region. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a semiconductor device having a MOS capacitor and a method for manufacturing the same. In particular, the present invention relates to a semiconductor device capable of increasing the capacitance of a MOS capacitor without increasing the area of the MOS capacitor and a method for manufacturing the same.

  FIG. 4A is a cross-sectional view for explaining the configuration of a conventional MOS capacitor 120. The MOS capacitor 120 shown in this figure has a first conductivity type well 101a formed on a silicon substrate 101, an insulating film 103, an upper electrode 104 which is a polysilicon electrode, and a first conductivity type impurity region 107. ing. The insulating film 103 is located on the well 101 a and the upper electrode 104 is located on the insulating film 103. The impurity region 107 is formed so as to surround the periphery of the upper electrode 104, and is provided to apply a potential to the well 101a functioning as the lower electrode.

  In the MOS capacitor 120 having the above-described configuration, when the area is increased for the purpose of increasing the capacity, the frequency characteristics (responsiveness) must be reduced unless the resistance of the upper electrode 104 and the well 101a which is the lower electrode is sufficiently lowered. descend. Reducing the resistance of the upper electrode 104 can be achieved relatively easily by introducing a sufficient amount of impurities or forming tungsten silicide, but it is difficult to reduce the resistance of the well 101a. In the case where the well 101a has a certain resistance value, a portion of the well 101a located below the central portion of the upper electrode 104 has a longer distance from the impurity region 107, so that the potential of the impurity region 107 changes. It becomes impossible to follow.

  Therefore, as shown in FIG. 4B, conventionally, when it is desired to increase the capacitance of a MOS capacitor, a plurality of MOS capacitors 120 having a size equal to or smaller than a certain size are formed, and these MOS capacitors 120 are connected in parallel. (For example, Patent Document 1).

JP 2002-217304 A

  As described above, in order to increase the capacitance of the MOS capacitor, when a plurality of MOS capacitors having an upper electrode of a certain size or less are formed, the potential for applying a potential to the well out of the area of the MOS capacitor The ratio occupied by the impurity region is increased. This is because only the portion on the upper electrode side of the outer periphery of the impurity region acts to apply a potential to the well. For this reason, the area of the MOS capacitor has been increased.

  The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a semiconductor device capable of increasing the capacitance of the MOS capacitor without increasing the area of the MOS capacitor and a method for manufacturing the same. There is.

In order to solve the above problems, a semiconductor device according to the present invention is a semiconductor device including a MOS capacitor,
The MOS type capacitor is
A first impurity region formed on the semiconductor substrate and functioning as a lower electrode;
An insulating film formed on the first impurity region;
An upper electrode formed on the insulating film;
A plurality of openings formed in the upper electrode;
A second impurity region formed in the first impurity region located below each of the plurality of openings and having an impurity concentration higher than that of the first impurity region;
It comprises.

  According to this semiconductor device, the second impurity region for applying a potential to the first impurity region which is the lower electrode is formed in the first impurity region located below the opening. Yes. Since the entire circumference of the second impurity region is surrounded by the first impurity region, the entire circumference acts to apply a potential to the second impurity region. Therefore, the area of the second impurity region can be reduced as compared with the conventional case, and as a result, the capacitance of the MOS capacitor can be increased without increasing the area of the MOS capacitor. This effect is particularly great when the plurality of openings and the plurality of second impurity regions are arranged in a staggered manner.

  It is preferable that the device further includes an element isolation film for isolating the element region where the MOS capacitor is formed, and the insulating film and the upper electrode are formed on the entire surface of the semiconductor substrate located in the element region. .

  An interlayer insulating film positioned on the upper electrode; a plurality of connection holes formed in the interlayer insulating film and positioned on each of the impurity regions; a conductor embedded in each of the plurality of connection holes; A conductive pattern formed on an interlayer insulating film and connected to the plurality of impurity regions via the plurality of conductors, and the conductive pattern may be formed above all of the element regions.

A method for manufacturing a semiconductor device according to the present invention includes a step of forming an element isolation film on a semiconductor substrate and isolating an element region;
Forming an insulating film on the entire surface of the semiconductor substrate located in the element region;
Forming a conductive film on the insulating film and the element isolation film;
Forming the upper electrode on the entire surface of the insulating film by selectively removing the conductive film, and forming a plurality of openings in the upper electrode;
Forming an impurity region in the semiconductor substrate located in the opening.

  After the step of forming the impurity region, a step of forming an interlayer insulating film on the element isolation film, the upper electrode, and the plurality of impurity regions; and a plurality of impurity regions on the interlayer insulating film. Forming a connection hole located in each of the plurality of connection holes, embedding a conductor in each of the plurality of connection holes, and forming a conductive pattern located above the upper electrode on the interlayer insulating film and on the conductor. You may comprise the process to do.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. 1A, 1 </ b> B, 2 </ b> A, 2 </ b> B, and 3 </ b> A are cross-sectional views for explaining a method of manufacturing a semiconductor device according to an embodiment of the present invention. It is. FIGS. 1C, 2C, and 3B are cross-sectional views taken along line AA ′ of FIGS. 1B, 2B, and 3A, respectively. The semiconductor device shown in this figure has a MOS capacitor.

  First, as shown in FIG. 1A, a first conductivity type impurity is introduced into a silicon substrate 1, and a well 1a is formed in an element region where a MOS type capacitor is formed. The well 1a functions as a lower electrode of the MOS capacitor. Next, an element isolation film 2 is formed on the silicon substrate 1 to isolate the element region from other regions. Next, the silicon substrate 1 is thermally oxidized. Thereby, the insulating film 3 is formed on the entire surface of the silicon substrate 1 located in the element region. Next, a polysilicon film 4 is formed on the insulating film 3 and the element isolation film 2 by a CVD method.

  Next, as shown in FIG. 1B, a photoresist film is applied on the polysilicon film 4, and this photoresist film is exposed and developed. As a result, a resist pattern 50 is formed on the polysilicon film 4. Next, the polysilicon film 4 is etched using the resist pattern 50 as a mask. Thereby, the upper electrode 40 of the MOS capacitor is formed.

  As shown in FIGS. 1B and 1C, the upper electrode 40 is located on the entire surface of the insulating film 3 and on the element isolation film 2 around it, and in a portion located on the insulating film 3, A plurality of openings 42 are provided. The plurality of openings 42 are arranged in a staggered pattern on the entire surface of the insulating film 3. The openings 42 are preferably arranged so that their distances are substantially the same.

  Thereafter, the resist pattern 50 is removed as shown in FIG. Next, a first conductivity type impurity is introduced into the silicon substrate 1 using the upper electrode 40 and the element isolation film 2 as a mask. As a result, impurity regions 7 each having an impurity concentration higher than that of the well 1a are formed in the silicon substrate 1 located below the opening 42. The impurity regions 7 have a function of applying a predetermined potential to the well 1a, and are arranged in a staggered manner on the entire surface of the well 1a located in the element region. When the openings 42 are arranged so that their distances are substantially the same, the impurity regions 7 are also arranged so that their distances are substantially the same.

  Next, as shown in FIGS. 2B and 2C, the interlayer insulating film 8 is formed on the entire surface including the upper electrode 40 and the inside of the opening 42 by the CVD method. Next, a resist pattern (not shown) is formed on the interlayer insulating film 8, and the interlayer insulating film 8 is etched using this resist pattern as a mask. As a result, a plurality of connection holes 8 a located on the upper electrode 40 and connection holes 8 b located on the impurity regions 7 are formed in the interlayer insulating film 8 and the insulating film 3. The plurality of connection holes 8 a are located on the portion of the upper electrode 40 that is located on the element isolation film 2, and are disposed so as to surround the insulating film 3. Thereafter, the resist pattern is removed.

  Next, as shown in FIGS. 3A and 3B, a tungsten film is formed by CVD on the interlayer insulating film 8 and in the connection holes 8a and 8b. Next, the tungsten film located on the interlayer insulating film 8 is removed by the CMP method. Thereby, the tungsten plug 9a is embedded in the connection hole 8a, and the tungsten plug 9b is embedded in the connection hole 8b.

  Next, an Al alloy film is formed on the tungsten plugs 9 a and 9 b and the interlayer insulating film 8. Next, a resist pattern (not shown) is formed on the Al alloy film, and the Al alloy film is etched using the resist pattern as a mask. As a result, a conductive pattern 10a for connecting the plurality of tungsten plugs 9a to each other and a conductive pattern 10b for connecting the plurality of tungsten plugs 9b to each other are formed on the interlayer insulating film 8. The conductive pattern 10b has a substantially square or rectangular planar shape. The conductive pattern 10a has a substantially square shape in plan view, and is disposed so as to surround the periphery of the conductive pattern 10b.

  As described above, according to the embodiment of the present invention, the upper electrode 40 has a plurality of openings 42, and the silicon substrate 1 located below the openings 42 has a potential applied to the well 1 a that is the lower electrode. Impurity regions 7 are provided for application. Since the entire periphery of the impurity region 7 is surrounded by the upper electrode 40, the entire periphery performs an action of applying a potential to the well. For this reason, the area of the impurity region 7 can be reduced as compared with the prior art, and as a result, the capacitance of the MOS capacitor can be increased without increasing the area of the MOS capacitor. This effect is particularly great when the intervals between the plurality of impurity regions 7 are substantially the same.

  The upper electrode 40 may be disposed on the entire surface of the insulating film 3 and above each of the plurality of impurity regions 7. The laminated structure of the upper electrode 40, the interlayer insulating film 8, and the conductive pattern 10b also functions as a capacitor. However, when each of the upper electrode 40 and the conductive pattern 10b is located above the entire surface of the element region, the capacitance of this capacitor is also conventional. Compared to

  Note that the present invention is not limited to the above-described embodiment, and various modifications can be made without departing from the spirit of the present invention. For example, the insulating film 3 located in the opening 42 may be removed before the interlayer insulating film 8 is formed.

(A), (B) is sectional drawing for demonstrating the manufacturing method of the semiconductor device which concerns on embodiment of this invention, (C) is AA 'sectional drawing of (B). (A), (B) is sectional drawing for demonstrating the next process of FIG. 1, (C) is AA 'sectional drawing of (B). (A) is sectional drawing for demonstrating the next process of FIG. 2, (B) is AA 'sectional drawing of (A). It is a figure for demonstrating the structure of the conventional MOS type | mold capacitor 120, (A) is sectional drawing, (B) is a top view.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1,101 ... Silicon substrate, 1a, 101a ... Well, 2 ... Element isolation film, 3,103 ... Insulating film, 4,104 ... Polysilicon film, 7, 107 ... Impurity region, 8 ... Interlayer insulating film, 8a, 8b ... Connection hole, 9a, 9b ... Tungsten plug, 10a, 10b ... conductive pattern, 40 ... upper electrode, 42 ... opening, 50 ... resist pattern, 120 ... MOS type capacitor

Claims (6)

A semiconductor device comprising a MOS capacitor,
The MOS type capacitor is
A first impurity region formed on the semiconductor substrate and functioning as a lower electrode;
An insulating film formed on the first impurity region;
An upper electrode formed on the insulating film;
A plurality of openings formed in the upper electrode;
A second impurity region formed in the first impurity region located below each of the plurality of openings and having an impurity concentration higher than that of the first impurity region;
A semiconductor device comprising:   The semiconductor device according to claim 1, wherein the plurality of openings and the plurality of second impurity regions are arranged in a staggered manner. An element isolation film for isolating the element region where the MOS capacitor is formed;
The semiconductor device according to claim 1, wherein the insulating film and the upper electrode are formed on the entire surface of the semiconductor substrate located in the element region as one electrode. An interlayer insulating film located on the upper electrode and in the plurality of openings;
A plurality of connection holes formed in the interlayer insulating film and positioned on each of the impurity regions;
A conductor embedded in each of the plurality of connection holes;
A conductive pattern formed on the interlayer insulating film and connected to the plurality of impurity regions via the plurality of conductors;
Comprising
The semiconductor device according to claim 3, wherein the conductive pattern is formed above all the element regions. Forming an element isolation film on a semiconductor substrate and isolating an element region;
Forming an insulating film on the entire surface of the semiconductor substrate located in the element region;
Forming a conductive film on the insulating film and the element isolation film;
Forming the upper electrode on the entire surface of the insulating film by selectively removing the conductive film, and forming a plurality of openings in the upper electrode;
Forming an impurity region in the semiconductor substrate located in the opening;
A method for manufacturing a semiconductor device comprising: After the step of forming the impurity region,
Forming an interlayer insulating film on the element isolation film, on the upper electrode and on the plurality of impurity regions;
Forming a connection hole located on each of the plurality of impurity regions in the interlayer insulating film;
Embedding a conductor in each of the plurality of connection holes;
Forming a conductive pattern located above the upper electrode on the interlayer insulating film and the conductor;
A method for manufacturing a semiconductor device according to claim 5.

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