JP2013046054A - Semiconductor package substrate and method of manufacturing semiconductor package substrate - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor package substrate and a method of manufacturing the semiconductor package substrate.SOLUTION: A method of manufacturing the semiconductor package substrate includes the steps of: preparing a carrier substrate having a pad formed; forming an insulator layer on the pad; removing the carrier substrate; forming a circuit layer on the insulator layer and the pad; and etching a part of the pad to form an aperture inside the insulator layer.

Description

  The present invention relates to a semiconductor package substrate and a method for manufacturing a semiconductor package substrate.

  With the advancement of high-density integrated and thin semiconductor devices, assembly techniques for manufacturing semiconductor packages have also been greatly developed. At the same time, as the market for portable electronic devices expands worldwide, miniaturization and weight reduction are rapidly promoted. As a result, various types of semiconductor packaging methods for realizing fine pitch, miniaturization and thinning have been developed (US Pat. No. 6,225,144). However, in the conventional semiconductor packaging method, the space between the substrate and the semiconductor element mounted on the substrate is reduced due to the downsizing of the electronic device. As a result, when the semiconductor element is mounted on the substrate and then molded, the epoxy cannot uniformly penetrate into the space between the semiconductor element and the substrate, making it difficult to perform reliable semiconductor packaging. Yes.

  One aspect of the present invention provides a semiconductor package substrate and a method for manufacturing the semiconductor package substrate, which can stably form a separation space between the semiconductor element and the insulating layer by etching the inside of the insulating layer. That is the purpose.

  According to another aspect of the present invention, the space between the semiconductor element and the insulating layer is secured using the thickness of the pad and the circuit layer, thereby insulating the semiconductor element from increasing the thickness of the semiconductor package. It is an object of the present invention to provide a semiconductor package substrate and a method for manufacturing the semiconductor package substrate capable of forming a sufficient space between the layers.

  According to an aspect of the present invention, a step of preparing a carrier substrate on which a pad is formed, a step of forming an insulating layer on the pad, a step of removing the carrier substrate, and a circuit layer on the insulating layer and the pad. And a step of etching a part of the pad and forming an opening in the insulating layer.

In forming the insulating layer, the pad can be embedded in the insulating layer.
The method may further include forming a via hole penetrating the insulating layer after removing the carrier substrate.
In the step of forming the circuit layer, the inside of the via hole can be plated.

Forming the opening includes applying an etching resist to the upper portion of the circuit layer, etching the pad, and removing the etching resist such that an upper portion of the pad is opened. be able to.
After forming the opening, the method may further include forming a bonding pad on the upper part of the circuit layer and the inner wall of the opening, and mounting a semiconductor element on the bonding pad.

  According to another aspect of the present invention, a step of preparing a base insulating layer, and a first carrier substrate, a first seed layer, a first pad, and a first pad are embedded on one side of the base insulating layer. Forming a first buildup layer formed by stacking the first insulating layer, the third seed layer, the third insulating layer, and the fifth seed layer; and forming the second buildup layer on the other side of the base insulating layer, The carrier substrate, the second seed layer, the second pad, the second insulating layer in which the second pad is embedded, the fourth seed layer, the fourth insulating layer, and the sixth seed layer are stacked and formed. Forming a second buildup layer; separating the first carrier substrate and the second carrier substrate from the base insulating layer; removing the first carrier substrate from the first buildup layer; Removing the second carrier substrate from the two build-up layers; A first circuit layer is formed on the first buildup layer from which the first carrier substrate has been removed, and a second circuit layer is formed on the second buildup layer from which the second carrier substrate has been removed. Etching a portion of the first pad to form a first opening in a portion of the first insulating layer, and etching a portion of the second pad to form a portion of the second insulating layer. Forming a second opening in the part, and a method for manufacturing a semiconductor package substrate.

In forming the first insulating layer and the second insulating layer, the first pad can be embedded in the first insulating layer.
In forming the first insulating layer and the second insulating layer, the second pad can be embedded in the second insulating layer.

The method may further include forming a first via hole penetrating the first buildup layer after separating the first carrier substrate and the second carrier substrate from the base insulating layer.
In the step of forming the first circuit layer, the inside of the first via hole can be plated.

In forming the first circuit layer, the first circuit layer may include an upper circuit layer formed on the first seed layer and a lower circuit layer formed on the fifth seed layer. .
The method may further include forming a second via hole penetrating the second buildup layer after separating the first carrier substrate and the second carrier substrate from the base insulating layer.

In the step of forming the second circuit layer, the inside of the second via hole can be plated.
In forming the second circuit layer, the second circuit layer may include an upper circuit layer formed on the second seed layer and a lower circuit layer formed on the sixth seed layer. .

The step of forming the first opening includes applying an etching resist to the upper portion of the first circuit layer so that an upper portion of the first pad portion is opened, and etching the first pad. And removing the etching resist.
The step of forming the second opening includes applying an etching resist to the upper part of the second circuit layer so that the upper part of the second pad part is opened, and etching the second pad. And removing the etching resist.

  According to still another aspect of the present invention, an insulating layer, a pad embedded in the insulating layer, having a first opening, formed on the insulating layer and the pad, and formed on the first opening. An upper circuit layer having a second opening formed is provided.

A lower circuit layer formed under the insulating layer may be further included.
A via may be formed to penetrate the insulating layer and electrically connect the upper circuit layer and the lower circuit layer.
A semiconductor device may be mounted on the upper circuit layer.

  According to still another aspect of the present invention, a lower insulating layer, a seed layer formed on the lower insulating layer and patterned to include a through hole, and formed on the seed layer, the seed layer is embedded. An upper insulating layer formed so as to be formed, a pad embedded in the upper insulating layer and formed with a first opening, and formed on the upper insulating layer and the pad, on the first opening A semiconductor package substrate including an upper circuit layer having a formed second opening and a lower circuit layer formed below the lower insulating layer is provided.

The semiconductor device may further include a via formed to penetrate the upper insulating layer, the lower insulating layer, and the seed layer, and electrically connecting the upper circuit layer and the lower circuit layer.
A semiconductor device may be mounted on the upper circuit layer.

The features and advantages of the present invention will become more apparent from the following detailed description taken in conjunction with the accompanying drawings.
Prior to the detailed description of the invention, the terms and words used in the specification and claims should not be construed in a normal and lexicographic sense, and the inventor best describes the invention. Therefore, it should be construed as meanings and concepts corresponding to the technical idea of the present invention in accordance with the principle that the concept of terms can be appropriately defined.

  The semiconductor package substrate and the semiconductor package substrate manufacturing method of the present invention can stably form a separation space between the semiconductor element and the insulating layer by etching the inside of the insulating layer using a pad. .

  In addition, the semiconductor package substrate and the semiconductor package substrate manufacturing method of the present invention secure the separation space between the semiconductor element and the insulating layer using the thickness of the pad and the circuit layer, and thereby the thickness of the semiconductor package. A sufficient separation space can be formed between the semiconductor element and the insulating layer without increasing.

Objects, specific advantages and novel features of the present invention will become more apparent from the following detailed description and examples when taken in conjunction with the accompanying drawings. In this specification, it should be noted that when adding reference numerals to the components of each drawing, the same components are given the same number as much as possible even if they are shown in different drawings. I must.
Further, in describing the present invention, when it is determined that a specific description of the related art related to the present invention may obscure the gist of the present invention, a detailed description thereof will be omitted. In this specification, terms such as “first” and “second” are used to distinguish one component from other components, and the component is not limited by the terms.

  Hereinafter, a semiconductor package substrate and a method for manufacturing the semiconductor package substrate according to embodiments of the present invention will be described in detail with reference to the accompanying drawings.

Method for Manufacturing Semiconductor Package Substrate FIGS. 1 to 9 are process cross-sectional views illustrating a method for manufacturing a semiconductor package substrate according to an embodiment of the present invention in order of steps.

Referring to FIG. 1, a pad 130 is formed on a carrier substrate 110 on which a seed layer 120 is formed.
The carrier substrate 110 may be formed using a thermoplastic polymer or a metal. The material of the carrier substrate 110 is not particularly limited, and the thermoplastic polymer may be PVC (poly vinyl chloride), PE (poly ethylene), PP (poly polypropylene), PS (poly polystyrene), ABS (acrylonitrile). Butadiene styrene copolymer), Nylon (polyamide), PET (polyethylene terephthalate) and the like may be included. The metal forming the carrier substrate 110 can be selected from the group consisting of copper, aluminum, nickel, zinc, chromium, cobalt, tungsten, and mixtures thereof.

The seed layer 120 is formed on the carrier substrate 110. Here, the seed layer 120 may be formed using sputtering or an electroless plating method.
A pad 130 is formed on the carrier substrate 110 on which the seed layer 120 is formed.
The pad 130 may be formed to protrude from the carrier substrate 110. The pad 130 is etched later, so that an opening (for a sufficient space between the insulating layer (140 in FIG. 9) and the semiconductor element (190 in FIG. 9) mounted on the semiconductor package substrate ( Used to form 300) of FIG. Depending on the height of the pad 130 protruding from the carrier substrate 110, the depth of the opening (300 in FIG. 9) which is a separation space between the insulating layer (140 in FIG. 9) and the semiconductor element (190 in FIG. 9). Can be adjusted.

  The pad 130 can be formed by patterning using an electrolytic plating method. The pad 130 in the embodiment of the present invention may be formed of the same material as the seed layer 120.

Referring to FIG. 2, an insulating layer 140 is formed on the carrier substrate 110 on which the pad 130 is formed.
The insulating layer 140 may be formed in such a manner that the pad 130 is embedded in the insulating layer 140 by applying pressure after laminating an insulating material on the carrier substrate 110 on which the pad 130 is formed. Here, the insulating layer 140 may be formed of a composite polymer resin that is normally used as an insulating material. For the insulating layer 140, for example, a prepreg, or an epoxy resin such as FR-4, BT (Bismaleimide Triazine), ABF (Ajinomoto Build up Film), or the like can be used.
Referring to FIG. 3, after forming the insulating layer 140, the carrier substrate (110 in FIG. 2) is removed from the seed layer 120.

  Referring to FIG. 4, after the carrier substrate (110 in FIG. 2) is removed, a photoresist 160 for forming a circuit layer (150) is formed on the seed layer 120 exposed to the outside. At this time, the photoresist 160 can be formed by performing exposure and development. After forming the photoresist 160 in this manner, plating can be performed to form the circuit layer 150. At this time, the plating can be performed using an electrolytic plating method. In the embodiment of the present invention, an electrolytic plating method is used, but the plating method is not limited to this, and can be performed by a known plating method. In addition, plating can be performed using the same material as the seed layer 120. According to the embodiment of the present invention, the circuit layer 150 can be plated so that the thickness of the seed layer 120 and the thickness of the circuit layer 150 are 5 to 25 μm. However, the thickness of the circuit layer 150 is only an example of the present invention and is not limited thereto.

Referring to FIG. 5, the photoresist (160 in FIG. 4) formed on the seed layer 120 can be removed.
Referring to FIG. 6, an etching resist 170 may be formed on the circuit layer 150. Here, the etching resist 170 may be formed such that a region where a separation space is formed in the insulating layer 140 is opened.

  Referring to FIG. 7, a region opened to form a separation space in the insulating layer 140 is etched. By such etching, the pad 130 embedded in the insulating layer 140 corresponding to the opened region is etched. As a result, an opening 300 is formed inside the insulating layer 140, which is a separation space from a semiconductor element (190 in FIG. 9) to be mounted later. After the opening 300 is thus formed in the insulating layer 140, the etching resist (170 in FIG. 6) formed on the circuit layer 150 is removed.

Referring to FIG. 8, the seed layer 120 exposed by removing the etching resist (170 in FIG. 6) formed on the circuit layer 150 is etched.
Referring to FIG. 9, a bonding pad 180 bonded to the semiconductor element 190 is formed on the circuit layer 150 and the inner wall of the opening 300. The bonding pad 180 can be formed by gold plating. The semiconductor element 190 can be mounted on the semiconductor package substrate by bonding the semiconductor element 190 to the bonding pad 180 formed in this way.
According to the method of manufacturing a semiconductor package substrate according to the embodiment of the present invention, the pad thickness and the circuit layer thickness are adjusted, so that the separation space between the substrate and the semiconductor device is not increased without increasing the substrate thickness. Can be sufficiently formed.

10 to 18 are process cross-sectional views illustrating a method of manufacturing a semiconductor package substrate according to another embodiment of the present invention in the order of processes.
Referring to FIG. 10, a first carrier substrate 110, a first seed layer 120, a pad 130, an insulating layer 140, a second carrier substrate 111, and a second seed layer 121 are provided. A pad 130 is formed on the first seed layer 120 on the first carrier substrate 110, and a second seed layer 121 is formed on the second carrier substrate 111.

Referring to FIG. 11, the insulating layer 140 is stacked on the first carrier substrate (110 in FIG. 10) on which the pad 130 is formed, and the second seed layer 121 is formed on the insulating layer 140. Two carrier substrates (111 in FIG. 10) are stacked. After the lamination, the pad 130 is embedded in the insulating layer 140 by applying pressure to the insulating layer 140 and the second carrier substrate (111 in FIG. 10), and the insulating layer 140 and the second seed layer are filled. 121 can be joined. Thereafter, the first carrier substrate (110 in FIG. 10) and the second carrier substrate (111 in FIG. 10) are removed.
Referring to FIG. 12, a via hole 191 penetrating the first seed layer 120, the second seed layer 121, and the insulating layer 140 is processed. The via hole 191 can be processed by laser processing or router processing.

Referring to FIG. 13, a first photoresist 160 and a second photoresist 161 for forming circuit layers (150, 151) are formed on the first seed layer 120 and the second seed layer 121. At this time, the first photoresist 160 and the second photoresist 161 can be formed by performing exposure and development. After forming the first photoresist 160 in this manner, plating for forming the upper circuit layer 150 can be performed. In addition, after forming the second photoresist 161, plating for forming the lower circuit layer 151 can be performed. At this time, the inside of the via hole (191 in FIG. 12) can also be filled by plating. Here, the plating can be performed using the same material as the first seed layer 120 and the second seed layer 121.

Referring to FIG. 14, the first photoresist (160 in FIG. 3) and the second photoresist (161 in FIG. 3) are removed.
Referring to FIG. 15, after removing the first photoresist 160 and the second photoresist 161, a first etching resist 170 and a second etching resist 171 may be formed. Here, the first etching resist 170 may be formed such that a region where a separation space is formed in the insulating layer 140 is opened. After the first etching resist 170 is formed in such a structure, the opened region can be etched. At this time, the insulating layer 140 located in the region opened by the first etching resist 170 can be etched. Also, the pad 130 located under the etched insulating layer 140 may be etched. By such etching, an opening 300 which is a space apart from a semiconductor element (190 in FIG. 18) to be mounted later is formed in the insulating layer 140.

Referring to FIG. 16, after the opening 300 is formed in the insulating layer 140, the first etching resist (170 in FIG. 15) and the second etching resist (171 in FIG. 15) are removed.
Referring to FIG. 17, the first seed layer 120 and the second seed layer exposed by removing the first etching resist (170 in FIG. 15) and the second etching resist (171 in FIG. 15). The upper circuit layer 150 and the lower circuit layer 151 are formed by etching 121.
Referring to FIG. 18, a bonding pad 180 bonded to the semiconductor element 190 is formed on the upper circuit layer 150 and the inner wall of the opening 300. The bonding pad 180 can be formed by gold plating. After bonding the semiconductor element 190 to the bonding pad 180 formed in this way, the semiconductor element 190 can be mounted on the semiconductor package substrate by applying a solder resist 192.

19 to 25 are process cross-sectional views illustrating a method of manufacturing a semiconductor package substrate according to still another embodiment of the present invention in the order of processes.
Referring to FIG. 19, an insulating base layer 210 is provided. Here, the insulating base layer 210 is a dual core, and build-up layers can be formed on both side surfaces. A first carrier substrate 214 in which a first seed layer 215 and a first pad 216 are formed is formed on one side of a base insulating layer 210 that is a dual core, and a second carrier insulating layer 210 is formed on the other side of the base insulating layer 210. A second carrier substrate 211 on which the seed layer 212 and the second pad 213 are formed is formed.

Referring to FIG. 20, a first insulating layer 231 is stacked on the first seed layer 215 and the first pad 216, and a second insulating layer is formed on the second seed layer 212 and the second pad 213. A layer 221 is stacked. After the first insulating layer 231 and the second insulating layer 221 are stacked in this manner, by applying pressure, the first pad 216 is embedded in the first insulating layer 231, and the second insulating layer The second pad 213 may be embedded inside the 221. Thereafter, a third seed layer 232 patterned to include the first through hole 237 is formed on the first insulating layer 231. In addition, a fourth seed layer 222 patterned to include the second through hole 227 is formed on the second insulating layer 221.
Here, although not shown in the drawing, an internal circuit layer may be formed on the third seed layer 232 and the fourth seed layer 222. Alternatively, the third seed layer 232 and the fourth seed layer 222 may be patterned to serve as a circuit layer.

  Referring to FIG. 21, a third insulating layer 233 is formed on the third seed layer 232, and a fourth insulating layer 223 is stacked on the fourth seed layer 222. At this time, after the third insulating layer 233 and the fourth insulating layer 223 are laminated, by applying pressure, the third insulating layer 233 passes through the first through hole (237 in FIG. 20). The fourth insulating layer 223 is bonded to the first insulating layer 231, and the fourth insulating layer 223 is bonded to the second insulating layer 221 through the second through hole (227 in FIG. 20). After the third insulating layer 233 and the fourth insulating layer 223 are stacked in this way, a fifth seed layer 234 is formed on the third insulating layer 233, and the fifth seed layer 223 is formed on the fourth insulating layer 223. Six seed layers 224 are formed. Here, the first seed layer 215, the first insulating layer 231, the third seed layer 232, the third insulating layer 233, and the fifth seed layer 234 formed on the first carrier substrate 214 are moved to the first seed layer 215. This is called the build-up layer. In addition, the second seed layer 212, the second insulating layer 221, the fourth seed layer 222, the fourth insulating layer 223, and the sixth seed layer 224 formed on the second carrier substrate 211 are formed as the second seed layer 212. This is called a buildup layer.

Referring to FIG. 22, the first carrier substrate (214 in FIG. 21) and the second carrier substrate (211 in FIG. 21) are separated from the base insulating layer (210 in FIG. 21), respectively. In addition, after separating the first carrier substrate (214 in FIG. 21) and the second carrier substrate (211 in FIG. 21) from the base insulating layer (210 in FIG. 21), the first carrier substrate (FIG. 21). 214) and the second carrier substrate (211 in FIG. 21) are removed.
Thereafter, a first via hole 191 penetrating the first buildup layer 200 is formed. Although not shown in the drawing, a second via hole is also formed in the second buildup layer.

  Referring to FIG. 23, an upper circuit layer 236 and a lower circuit layer 235, which are first circuit layers, can be formed on the first seed layer 215 and the fifth seed layer 234 by plating. That is, the upper circuit layer 236 can be formed on the first seed layer 215 by plating, and the lower circuit layer 235 can be formed on the fifth seed layer 234 by plating. At this time, the inside of the first via hole 191 can also be charged by plating. After that, the opening 300 is formed by etching the first pad 216 embedded in the first insulating layer 231.

Referring to FIG. 24, an upper circuit layer 236 and a lower circuit layer 235 are formed by removing the first seed layer 215 and the fifth seed layer 234 exposed after plating.
Referring to FIG. 25, a bonding pad 240 bonded to the semiconductor element 250 is formed on the upper circuit layer 236 and the inner wall of the opening 300. The bonding pad 240 can be formed by gold plating. After bonding the semiconductor element 250 to the bonding pad 240 formed in this way, the semiconductor element 250 can be mounted on the semiconductor package substrate by applying a solder resist 270.
Here, the first buildup layer 200 has been described as an example, but the semiconductor element can also be mounted on the second buildup layer according to the same process sequence.

Semiconductor Package Substrate FIG. 26 is an exemplary view showing a semiconductor package substrate according to an embodiment of the present invention.
Referring to FIG. 26, the semiconductor package substrate 400 according to the embodiment of the present invention may include an insulating layer 440, a pad 430, a seed layer 420, a circuit layer 450, and a bonding pad 480.

  The insulating layer 440 can be formed of a composite polymer resin that is usually used as an insulating material. The insulating layer 440 can be formed using, for example, a prepreg or an epoxy resin such as FR-4, BT (Bismaleimide Triazine), or ABF (Ajinomoto Build up Film).

The pad 430 can be embedded in the insulating layer and have a first opening 401. The depth of the first opening 401 formed in the pad 430 can vary depending on the thickness of the pad 430. For example, the depth of the first opening 401 may be the same as the thickness of the pad 430 or smaller than the thickness of the pad 430. However, the depth of the first opening 401 is not limited to this and can be changed by those skilled in the art.
The seed layer 420 may be formed on the insulating layer 440 and the pad 430. At this time, the seed layer 420 may be patterned so that the first opening 401 is exposed.

The circuit layer 450 may be formed on the insulating layer 440 and the pad 430. That is, the circuit layer 450 may be formed on the seed layer 420 formed on the insulating layer 440 and the pad 430. In addition, the circuit layer 450 can be formed to have the second opening 402 formed so as to be positioned on the first opening 401.
The bonding pad 480 may be formed on the circuit layer 450, the inner wall of the first opening 401, and the inner wall of the second opening 402. The bonding pad 480 can be formed by gold plating. A semiconductor element 490 can be mounted on the bonding pad 480 formed in this manner.

  Although not shown in the drawing, a solder resist may be applied on the insulating layer 440 and the circuit layer 450 after the semiconductor element 490 is mounted.

FIG. 27 is an exemplary view showing a semiconductor package substrate according to another embodiment of the present invention.
Referring to FIG. 27, a semiconductor package substrate 500 according to an embodiment of the present invention includes an insulating layer 540, a pad 530, a first seed layer 520, an upper circuit layer 550, a bonding pad 580, and a second seed. A layer 521, a lower circuit layer 551, a via 552, and a solder resist 592 may be included.

The insulating layer 540 can be formed of a composite polymer resin that is usually used as an insulating material. As the insulating layer 540, for example, a prepreg or an epoxy resin such as FR-4, BT (Bismaleimide Triazine), or ABF (Ajinomoto Build up Film) can be used.
The pad 530 can be embedded in the insulating layer 540 and have a first opening 501. The depth of the first opening 501 formed in the pad 530 can vary depending on the thickness of the pad 530. For example, the depth of the first opening 501 can be the same as the thickness of the pad 530 or smaller than the thickness of the pad 530. However, the depth of the first opening 501 is not limited to this, and can be changed by those skilled in the art.

The first seed layer 520 may be formed on the insulating layer 540 and the pad 530. At this time, the first seed layer 520 may be patterned so that the first opening 501 is exposed.
The upper circuit layer 550 may be formed on the insulating layer 540 and the pad 530. That is, the upper circuit layer 550 may be formed on the first seed layer 520 formed on the insulating layer 540 and the pad 530. Further, the upper circuit layer 550 can be formed to have a second opening 502 formed so as to be positioned on the first opening 501.

The bonding pad 580 can be formed on the upper circuit layer 550, the first opening 501, and the second opening 502. The bonding pad 580 can be formed by gold plating. The semiconductor element 590 can be mounted on the bonding pad 580 formed in this manner.
The second seed layer 521 may be formed under the insulating layer 540, and the second seed layer 521 may be formed to be patterned into a predetermined shape.

The lower circuit layer 551 may be formed below the insulating layer 540. That is, the lower circuit layer 551 can be formed under the second seed layer 521 formed under the insulating layer 540.
According to the embodiment of the present invention, the upper circuit layer 550 and the lower circuit layer 551 may be connected by the via 552. That is, the upper circuit layer 550 and the lower circuit layer 551 can be electrically connected by the via 552 formed so as to penetrate the insulating layer 540.
The solder resist 592 may be formed on the top and bottom of the first insulating layer 540.

FIG. 28 is an exemplary view showing a semiconductor package substrate according to another embodiment of the present invention.
Referring to FIG. 28, a semiconductor package substrate 600 according to an embodiment of the present invention includes an upper insulating layer 631, a lower insulating layer 633, a seed layer 632, an upper circuit layer 636, a lower circuit layer 635, a pad 616, and the like. , Bonding pads 640, vias 637, and solder resist 670.
The lower insulating layer 633 may be formed of a composite polymer resin that is usually used as an insulating material. For the lower insulating layer 633, for example, a prepreg, or an epoxy resin such as FR-4, BT (Bismaleimide Triazine), ABF (Ajinomoto Build up Film), or the like can be used.
The seed layer 632 may be formed on the lower insulating layer 633. The seed layer 632 may be patterned and formed on the lower insulating layer 633. Although not shown in FIG. 28, an internal circuit layer may be formed on the seed layer 632. Alternatively, the seed layer 632 may be patterned to serve as a circuit layer.

The upper insulating layer 631 may be formed on the seed layer 632. The upper insulating layer 631 can be formed of a composite polymer resin usually used as an insulating material. For the upper insulating layer 631, for example, a prepreg or an epoxy resin such as FR-4, BT (Bismaleimide Triazine), ABF (Ajinomoto Build up Film), or the like can be used.
According to the embodiment of the present invention, the upper insulating layer 631 may be formed to embed the seed layer 632. For example, when an internal circuit layer (not shown) is formed on the seed layer 632, the upper insulating layer 631 can be formed so as to embed all the seed layer 632 and the internal circuit layer (not shown).

The pad 616 may be embedded in the upper insulating layer 631 and may have a first opening 601. The depth of the first opening 601 formed in the pad 616 can vary depending on the thickness of the pad 616. For example, the depth of the first opening 601 can be the same as the thickness of the pad 616 or smaller than the thickness of the pad 616.
The upper circuit layer 636 may be formed on the upper insulating layer 631 and the pad 616. The upper circuit layer 636 can be formed to have a second opening 602 formed so as to be positioned on the first opening 601. It is obvious to those skilled in the art that the upper circuit layer 636 is formed on the upper seed layer 615 formed on the upper insulating layer 631 and the pad 616.

The bonding pad 640 may be formed on the upper portion of the upper circuit layer 636, the inner wall of the first opening 601, and the inner wall of the second opening 602. The bonding pad 640 can be formed by gold plating. The semiconductor element 650 can be mounted on the bonding pad 640 formed in this manner.
The lower circuit layer 635 may be formed below the lower insulating layer 633. It is obvious to those skilled in the art that the lower circuit layer 635 is formed on the lower seed layer 634 formed below the lower insulating layer 633.

The via 637 may be formed to penetrate the upper insulating layer 631 and the lower insulating layer 633. Thus, the upper circuit layer 636 and the lower circuit layer 635 can be electrically connected by the via 637 formed so as to penetrate the upper insulating layer 631 and the lower insulating layer 633.
The solder resist 670 can be formed on the upper insulating layer 631 and the lower insulating layer 633. In FIG. 28, the solder resist 670 is illustrated as being formed so that the upper circuit layer 636 formed in the upper insulating layer 631 and the lower circuit layer 635 formed in the lower insulating layer 633 are embedded. However, the present invention is not limited to this. That is, the degree to which the solder resist 670 is formed can be easily changed by those skilled in the art.

As described above, the present invention has been described in detail based on the embodiments. However, this is for the purpose of specifically explaining the present invention, and the semiconductor package substrate and the method for manufacturing the semiconductor package substrate according to the present invention are not limited thereto. Of course, those skilled in the art can understand that various modifications and variations can be made without departing from the spirit and scope of the present invention described in the appended claims. Will.
Any such simple modifications or alterations of the present invention belong to the scope of the present invention, and the specific scope of protection of the present invention will be apparent from the appended claims.

FIG. 6 is an exemplary diagram for explaining a process sequence of a method for manufacturing a semiconductor package substrate according to an embodiment of the present invention. FIG. 6 is an exemplary diagram for explaining a process sequence of a method for manufacturing a semiconductor package substrate according to an embodiment of the present invention. FIG. 6 is an exemplary diagram for explaining a process sequence of a method for manufacturing a semiconductor package substrate according to an embodiment of the present invention. FIG. 6 is an exemplary diagram for explaining a process sequence of a method for manufacturing a semiconductor package substrate according to an embodiment of the present invention. FIG. 6 is an exemplary diagram for explaining a process sequence of a method for manufacturing a semiconductor package substrate according to an embodiment of the present invention. FIG. 6 is an exemplary diagram for explaining a process sequence of a method for manufacturing a semiconductor package substrate according to an embodiment of the present invention. FIG. 6 is an exemplary diagram for explaining a process sequence of a method for manufacturing a semiconductor package substrate according to an embodiment of the present invention. FIG. 6 is an exemplary diagram for explaining a process sequence of a method for manufacturing a semiconductor package substrate according to an embodiment of the present invention. FIG. 6 is an exemplary diagram for explaining a process sequence of a method for manufacturing a semiconductor package substrate according to an embodiment of the present invention. FIG. 6 is an exemplary view for explaining a process sequence of a method for manufacturing a semiconductor package substrate according to another embodiment of the present invention. FIG. 6 is an exemplary view for explaining a process sequence of a method for manufacturing a semiconductor package substrate according to another embodiment of the present invention. FIG. 6 is an exemplary view for explaining a process sequence of a method for manufacturing a semiconductor package substrate according to another embodiment of the present invention. FIG. 6 is an exemplary view for explaining a process sequence of a method for manufacturing a semiconductor package substrate according to another embodiment of the present invention. FIG. 6 is an exemplary view for explaining a process sequence of a method for manufacturing a semiconductor package substrate according to another embodiment of the present invention. FIG. 6 is an exemplary view for explaining a process sequence of a method for manufacturing a semiconductor package substrate according to another embodiment of the present invention. FIG. 6 is an exemplary view for explaining a process sequence of a method for manufacturing a semiconductor package substrate according to another embodiment of the present invention. FIG. 6 is an exemplary view for explaining a process sequence of a method for manufacturing a semiconductor package substrate according to another embodiment of the present invention. FIG. 6 is an exemplary view for explaining a process sequence of a method for manufacturing a semiconductor package substrate according to another embodiment of the present invention. FIG. 10 is an exemplary diagram for explaining a process sequence of a method for manufacturing a semiconductor package substrate according to still another embodiment of the present invention. FIG. 10 is an exemplary diagram for explaining a process sequence of a method for manufacturing a semiconductor package substrate according to still another embodiment of the present invention. FIG. 10 is an exemplary diagram for explaining a process sequence of a method for manufacturing a semiconductor package substrate according to still another embodiment of the present invention. FIG. 10 is an exemplary diagram for explaining a process sequence of a method for manufacturing a semiconductor package substrate according to still another embodiment of the present invention. FIG. 10 is an exemplary diagram for explaining a process sequence of a method for manufacturing a semiconductor package substrate according to still another embodiment of the present invention. FIG. 10 is an exemplary diagram for explaining a process sequence of a method for manufacturing a semiconductor package substrate according to still another embodiment of the present invention. FIG. 10 is an exemplary diagram for explaining a process sequence of a method for manufacturing a semiconductor package substrate according to still another embodiment of the present invention. 1 is an exemplary view showing a semiconductor package substrate according to an embodiment of the present invention; FIG. 5 is an exemplary view showing a semiconductor package substrate according to another embodiment of the present invention. And FIG. 6 is an exemplary view showing a semiconductor package substrate according to another embodiment of the present invention.

110, 111, 211, 214 Carrier substrate 120, 121, 212, 215, 222, 224, 232, 420, 632 Seed layer 130, 213, 216, 430, 530, 616 Pad 140, 221, 223, 231, 223, 233, 440, 540 Insulating layer 150, 236, 450, 550, 636 Upper circuit layer 151, 235, 551, 635 Lower circuit layer 160, 161 Photoresist 170, 171 Etching resist 180, 240, 480, 580, 640 Bonding pad 190, 250, 490, 590, 650 Semiconductor element 191 Via hole 192, 592, 670 Solder resist 200, 260 Build-up layer 210 Base insulating layer 227 Second through hole 237 First through hole 300 Opening 400, 50 0, 600 Semiconductor package substrate 401, 501, 601 First opening 402, 502, 602 Second opening 520 First seed layer 552, 637 Via 615 Upper seed layer 631 Upper insulating layer 633 Lower insulating layer 634 Lower Seed layer

Claims (24)

Preparing a carrier substrate with pads formed thereon;
Forming an insulating layer on top of the pad;
Removing the carrier substrate;
Forming a circuit layer on top of the insulating layer and the pad;
Etching a part of the pad to form an opening in the insulating layer.   The method of manufacturing a semiconductor package substrate according to claim 1, wherein the pad is embedded in the insulating layer in the step of forming the insulating layer. After removing the carrier substrate,
The method of manufacturing a semiconductor package substrate according to claim 1, further comprising forming a via hole penetrating the insulating layer.   4. The method of manufacturing a semiconductor package substrate according to claim 3, wherein the via hole is plated in the step of forming the circuit layer. Forming the opening comprises:
Applying an etching resist to the upper part of the circuit layer so that an upper part of the pad part is opened;
Etching the pad;
The method for manufacturing a semiconductor package substrate according to claim 1, further comprising: removing the etching resist. After the step of forming the opening,
Forming bonding pads on top of the circuit layer and on the inner wall of the opening;
The method of manufacturing a semiconductor package substrate according to claim 1, further comprising mounting the semiconductor element on the bonding pad. Providing a base insulating layer;
On one side of the base insulating layer, a first carrier substrate, a first seed layer, a first pad, a first insulating layer in which the first pad is embedded, a third seed layer, a third insulating layer Forming a first buildup layer formed by laminating a layer and a fifth seed layer, and on the other side of the base insulating layer, a second carrier substrate, a second seed layer, a second pad, Forming a second build-up layer formed by laminating a second insulating layer, a fourth seed layer, a fourth insulating layer, and a sixth seed layer in which the second pad is embedded;
Separating the first carrier substrate and the second carrier substrate from the base insulating layer;
Removing the first carrier substrate from the first buildup layer and removing the second carrier substrate from the second buildup layer;
Forming a first circuit layer on the first buildup layer from which the first carrier substrate has been removed; and forming a second circuit on the second buildup layer from which the second carrier substrate has been removed. Forming a circuit layer;
A portion of the first pad is etched to form a first opening in the portion of the first insulating layer, and a portion of the second pad is etched to form the second insulating layer. Forming a second opening in a part of the semiconductor package substrate.   8. The method of manufacturing a semiconductor package substrate according to claim 7, wherein the first pad is embedded in the first insulating layer in the step of forming the first insulating layer and the second insulating layer. Method.   8. The method of manufacturing a semiconductor package substrate according to claim 7, wherein the second pad is embedded in the second insulating layer in the step of forming the first insulating layer and the second insulating layer. Method. After separating the first carrier substrate and the second carrier substrate from the base insulating layer,
The method of manufacturing a semiconductor package substrate according to claim 7, further comprising forming a first via hole that penetrates the first buildup layer.   11. The method of manufacturing a semiconductor package substrate according to claim 10, wherein the inside of the first via hole is plated in the step of forming the first circuit layer.   In forming the first circuit layer, the first circuit layer includes an upper circuit layer formed on the first seed layer and a lower circuit layer formed on the fifth seed layer. 8. The method of manufacturing a semiconductor package substrate according to claim 7, further comprising: After separating the first carrier substrate and the second carrier substrate from the base insulating layer,
The method of manufacturing a semiconductor package substrate according to claim 7, further comprising forming a second via hole that penetrates the second buildup layer.   14. The method of manufacturing a semiconductor package substrate according to claim 13, wherein the inside of the second via hole is plated in the step of forming the second circuit layer.   In the step of forming the second circuit layer, the second circuit layer includes an upper circuit layer formed on the second seed layer and a lower circuit layer formed on the sixth seed layer. 8. The method of manufacturing a semiconductor package substrate according to claim 7, further comprising: Forming the first opening comprises:
Applying an etching resist to the upper portion of the first circuit layer so that an upper portion of the first pad portion is opened;
Etching the first pad;
The method of manufacturing a semiconductor package substrate according to claim 7, further comprising: removing the etching resist. Forming the second opening comprises:
Applying an etching resist to the upper portion of the second circuit layer such that an upper portion of the second pad portion is opened;
Etching the second pad;
The method of manufacturing a semiconductor package substrate according to claim 7, further comprising: removing the etching resist. An insulating layer;
A pad embedded in the insulating layer and having a first opening;
An upper circuit layer formed on the insulating layer and the pad and having a second opening formed on the first opening.   The semiconductor package substrate of claim 18, further comprising a lower circuit layer formed under the insulating layer.   20. The semiconductor package substrate of claim 19, further comprising a via formed to penetrate the insulating layer and electrically connecting the upper circuit layer and the lower circuit layer.   19. The semiconductor package substrate according to claim 18, wherein a semiconductor element is mounted on the upper circuit layer. A lower insulating layer;
A seed layer formed on the lower insulating layer and patterned to include a through hole;
An upper insulating layer formed on the seed layer and embedded in the seed layer;
A pad embedded in the upper insulating layer and having a first opening;
An upper circuit layer formed on the upper insulating layer and the pad and having a second opening formed on the first opening;
A lower circuit layer formed under the lower insulating layer;
Including semiconductor package substrate.   23. The method of claim 22, further comprising a via formed to penetrate the upper insulating layer, the lower insulating layer, and the seed layer, and electrically connecting the upper circuit layer and the lower circuit layer. The semiconductor package substrate described.   23. The semiconductor package substrate according to claim 22, wherein a semiconductor element is mounted on the upper circuit layer.

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