JPH08213732A - Multilayer integrated circuit package and its manufacture - Google Patents

Abstract

PROBLEM TO BE SOLVED: To place a solder ball directly above a dielectric layer by providing a first flexible circuit, having a through-hole filled with a conductive material for connecting at least a part of a basic wiring pattern electrically with a first wiring pattern. SOLUTION: An electrical connection is made between a wiring pattern 114 formed on a basic dielectric layer 112 and a first wiring pattern 124 formed on a first dielectric layer 125 of a flexible circuit 120. A solder ball 134 is placed in an opening 128 made in the first dielectric layer 125. Since the temperature increases when the solder ball is fixed, it is fused partially and touches a part of the wiring pattern 114, formed on the basic dielectric layer 112 through the opening 128 in the first dielectric layer. According to the method, the solder ball 134 can be placed directly above the opening 128 in the dielectric layer 125.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to the field of integrated circuit packages, and more particularly to a multi-layer integrated circuit package and its manufacturing method.

[0002]

BACKGROUND OF THE INVENTION As the size of integrated circuits decreases,
Integrated circuit packages are becoming more complex and typically require more than 300 I / O connections per integrated circuit. At the same time, the high pin count, clean electrical environment, and the need for small dies necessitate the use of packaging techniques that provide multiple layers of alternating conductive and dielectric materials with path connections between them. Become. Co-fired ceramic and printed circuit board stacking are two multilayer packaging techniques that increase I / O capability with alternating conductor and dielectric layers interconnected by conductive paths (vias).

A printed circuit laminated package is typically formed by forming a wiring pattern on a dielectric layer, laminating a dielectric layer, forming a via opening in the dielectric layer, and plating the via opening to form an interlayer. Can be made by making electrical connections to the package, assembling the resulting structure into individual packages, and attaching integrated circuit die slugs to the package. Typically, the wiring pattern is copper and is formed on the individual polymer dielectric layers using photolithographic techniques. Dielectric layers are typically laminated together by placing an adhesive between the dielectric layers, aligning the dielectric layers, pressing the layers together and heating them to form a secure bond. After lamination, the layers are drilled into areas that require electrical interconnection between the layers to form via openings.

Problems with the printed circuit board lamination process result from dimensional changes that occur during processing. Because the dielectric layers used in printed circuit board processes are composed primarily of polymers, shrinkage occurs during the process of heating the layers to form a bond. Since the alignment is done before the heating step, another spatial tolerance is needed to account for dimensional changes due to shrinkage and distortion of the printed circuit board. The amount of shrinkage is a function of the type of polymer used and the percentage of polymeric material in the dielectric layer, the higher the percentage of polymeric material in the dielectric layer, the greater the dimensional changes that occur during the printed circuit lamination process. .

A problem associated with the printed circuit board lamination process is the warpage of the dielectric layers that causes the printed circuit board to distort. In addition, the cutout areas of each dielectric layer can cause adhesive between the layers to drain into the cavities of the cutout areas and contaminate the bond areas. Further, because solder balls must not be placed directly above the via holes, a separate package area is required for each package, increasing package size.

The co-fired ceramic package is a process of forming a wiring pattern on the surface of the "green" ceramic layer, a process of precisely aligning the ceramic layer, a process of forming a via hole, a process of filling the via hole with metal, and a structure. And sintering the sintered structure into individual packages. In the co-fired ceramic process, the alignment of the ceramic layers is done while in the green state, causing significant dimensional changes due to shrinkage of the finished structure. Since the alignment is done prior to the sintering process, additional space tolerances are needed to account for dimensional changes due to shrinkage, increasing package size. Furthermore, because screen printing is used to form the wiring pattern, the density achieved in the green layer is much less than in photolithographic patterning. This means that a larger number of layers are required and therefore the costs associated with this technology are typically very high.

Both the co-firing process and the printed circuit board laminating process have significant dimensional shrinkage after alignment of the dielectric layers, requiring increased spatial tolerances to properly route. Furthermore, the cost and performance characteristics of co-fired ceramic and printed circuit stacking techniques are limited by the thickness of the individual layers, the number of layers required, and the number and method of making the path interconnects. What is needed is a structure and method for providing high pin count interconnects that provides small dimensional changes, reduced thickness of individual dielectric layers, and simple interconnections between dielectric layers.

[0008]

OBJECTS OF THE INVENTION The present invention reduces dimensional changes during processing,
It is an object of the present invention to provide a structure and method for reducing the thickness of individual dielectric layers and providing a high pin count interconnect that provides easy interconnection between layers of a multi-layer package.

[0009]

SUMMARY OF THE INVENTION In the present invention, a flexible circuit replaces the ceramic layer or printed circuit board layer used as an alternating dielectric layer in conventional techniques. Each flexible circuit comprises a wiring pattern formed on the dielectric layer, and at least one opening penetrates the dielectric layer of the flexible circuit. The flexible circuit is laminated on the surface of the basic dielectric layer and the wiring pattern, or alternatively, the flexible circuit layer is laminated on another flexible circuit layer to form a multilayer. Lamination is typically accomplished by using a non-conductive adhesive between the layers. An opening is formed in the first dielectric pattern in a region where an electrical connection is required between layers.

Electrical interconnections between layers are typically made during solder ball attachment. For a two-level package, the electrical interconnection is between the wiring pattern formed on the base dielectric layer and the wiring pattern formed on the dielectric layer of the first flexible circuit. The solder balls are placed in the openings formed in the first flexible circuit. As the temperature rises during solder ball attachment, some of the solder balls melt through the openings in the first flexible circuit and come into contact with some of the wiring patterns formed in the underlying dielectric layer. Solder balls can be placed directly above the opening in the dielectric layer, as opposed to being placed laterally to the opening as in conventional techniques, thus reducing package size.

High pin count packages provide a new way to make interlayer connections that reduce package size.
First, the use of flexible circuit layers results in a thin multilayer package resulting from the use of thin dielectric layers compared to those used in printed circuit board lamination or co-fired ceramic processes. Furthermore, the size of the package can be reduced by sharing the ground plane. In one embodiment of the present invention, the wiring patterns formed on the first dielectric layer and the second dielectric layer share the ground plane. The unique controlled impedance configuration of the shared ground plane package results in improved electrical performance with the least number of layers.

The present invention provides a new method of electrically interconnecting the layers of a multi-layer package that eliminates the need for conventional path forming methods. The multi-layer package includes a step of obtaining a substrate having a basic dielectric layer and a basic wiring pattern, and a step of providing at least a first dielectric layer and a first wiring pattern formed on a surface of the first dielectric layer. 1. A step of obtaining a flexible circuit, a step of forming a plurality of openings in the first flexible circuit, a step of laminating the first flexible circuit on a substrate using an adhesive placed between them, a basic dielectric Electrically interconnecting the wiring pattern to the first dielectric wiring pattern. Electrical interconnects are formed between the alternating conductive layers before the integrated circuit die is attached to the package body. After die attachment, the integrated circuit die is electrically coupled to the wiring pattern.

Compared to the co-fired ceramic and printed circuit board lamination process, the shrinkage that occurs during the lamination process is minimal due to the properties of the dielectric and adhesive materials involved. Since there is no significant shrinkage, the required spatial tolerances are small compared to conventional interconnects. For the same reason, the outflow of adhesive to the bondable parts of the package is also limited. Moreover, unlike the co-fired ceramic and printed circuit board lamination process, lamination of the flexible circuit layers occurs after assembly. This ensures higher dimensional accuracy and less layer-to-layer misalignment as compared to conventional printed circuit and co-fired ceramic technology.

In the preferred embodiment, the base dielectric layer and the base wiring layer form the base flexible circuit. Prior to laminating the first flexible circuit to the base flexible circuit, the first flexible circuit and the base flexible circuit are aligned. In one embodiment, the opening in the first flexible circuit is formed after the first flexible circuit is aligned and laminated to the base flexible circuit. In an alternative embodiment, the opening in the first flexible circuit is formed prior to aligning and laminating the first flexible circuit with the underlying flexible circuit. The opening is typically formed in the first flexible circuit by mechanical punching or abrading through the flexible circuit, by wet chemical etching, or by dry etching (including plasma etching and laser techniques). In contrast to the ceramic or printed circuit board dielectric layers used in conventional technology, the first dielectric layer of the flexible circuit is also thin so that a laser is used to form the opening in the process of forming the path. Can be simplified.

A further understanding of the nature and advantages of the invention described herein may be realized by reference of the remaining portions of the specification and the accompanying drawings.

[0016]

DETAILED DESCRIPTION OF THE INVENTION The present invention is a structure and method that provides high pin count interconnections that reduce dimensional changes during processing, reduce the thickness of individual dielectric layers, and simplify interconnections between layers of a multi-layer package. is there. The multilayer package 100 includes a basic dielectric layer 112, a basic wiring pattern 114 formed on a surface 116 of the basic dielectric layer 112, and a basic dielectric layer 1.
12 and the first flexible circuit 120 laminated on the basic wiring pattern 114. The first flexible circuit 120 is formed on the first dielectric layer 125 and the surface 126 of the first dielectric layer 125. One wiring pattern layer 124, and at least one opening 12
8 extends through the first flexible circuit 120, the opening 128 is at least partially filled with a conductive material, and at least a part of the basic wiring pattern 114 is formed on at least a part of the first wiring pattern 124. It is electrically connected.

The package body 102 typically includes a first region 104, typically a cavity, for mounting an integrated circuit die, and a second region 108. In one embodiment, second region 108 provides a bond for wire bonding. In the preferred embodiment, package body 102 is formed from a conductive material such as copper or aluminum. In an alternative embodiment, package body 102 can be constructed of a non-conductive material such as ceramic or polyimide.

In the embodiment shown in FIG. 1, the base dielectric layer 11
1, the adhesive layer 113, and the basic wiring layer 114 are the substrate 1
Forming 10. In the preferred embodiment, the substrate 110 is a thin flexible circuit, and the basic flexible circuit 11
Also called 0. No. filed on Dec. 10, 1992 Continuation of 07 / 988,640 2nd 1994
No. No. filed on 18th of March 08 / 198,7
The U.S. patent application having No. 23 describes a package in which a thin flexible circuit is laminated to the package body, thus providing a basic dielectric layer and a basic wiring pattern. The substrate 110 is composed of a basic dielectric layer 112 and a basic wiring pattern 114 formed on the surface of the basic dielectric layer 112. In one embodiment, the base dielectric layer 112 comprises an adhesive layer 113 and a thin polyimide layer 11
1 is comprised. In an alternative embodiment, the base dielectric layer 112 is simply an adhesive layer 113.

The substrate is preferably a thin flexible circuit, but this is not critical to the invention. Alternatively, the base wiring pattern can be formed on the surface of the printed circuit board or ceramic layer. Package body 1
If 02 is composed of a conductive material, the basic dielectric layer 1
12 is a layer separated from the package body 102. However, if the package body 102 is made of the same non-conductive material as the basic dielectric layer 112, the package body 1
02 and the base dielectric layer 112 can form an integral unit.

Path connections are made between the alternating dielectric and conductive layers. In conventional packaging technology, the ceramic and printed circuit board layers act as dielectric layers,
The wiring pattern formed on the dielectric layer functions as a conductive layer. In the present invention, the flexible circuit replaces the wiring patterns and ceramic layers or wiring patterns and printed circuit board layers used in conventional technology. Each flexible circuit comprises a wiring pattern formed on the dielectric layer and has at least one opening penetrating the dielectric layer of the flexible circuit. A multilayer is constructed by laminating a flexible circuit on a substrate or by laminating a flexible circuit layer on another flexible circuit layer. Lamination is typically performed using a non-conductive adhesive between the layers.

FIG. 1 shows a first flexible circuit 120 having a first dielectric layer 122 and a first wiring pattern 124. Typically, the first dielectric layer is composed of polyimide with a thickness of less than 0.050 mm.
In the preferred embodiment, flexible circuit 120 includes adhesive layer 1
30 is laminated on the surface of the substrate 110. Two alternative structures for laminating the first flexible circuit 120 to the substrate are shown in FIG. In one embodiment, adhesive layer 130 and thin polyimide layer 122 form first dielectric layer 125. In other embodiments, only the adhesive layer 130 is first
Of the dielectric layer 125 are formed.

FIG. 2A shows an enlarged portion of a three-layer flexible circuit 120 composed of an adhesive layer 130, a thin dielectric polyimide layer 122, and a wiring pattern 124. In the structure shown in FIG. 2A, both the adhesive layer 130 and the polyimide layer 122 are non-conductive materials, and both are the first
Of the dielectric layer 125 are formed. Adhesive layer 130 is typically thermoplastic.

Typical dimensions of the three-layer flexible circuit shown in FIG. 2A are as follows. Adhesive layer 130 is about 12 microns thick, polyimide dielectric layer 122 is about 25 microns thick, and copper wiring layer 124 is about 18 microns thick. Flexible circuits incorporating the three-layer structure shown in Figure 2A are commercially available from suppliers such as Rogers Corporation and Mitsui Toatsu Chemicals. However, instead of these structures, the adhesive film is replaced by a more standard copper /
It can be created by application to the backside of a polyimide (124/122) structure or by other means.

FIG. 2B shows an alternative embodiment of a flexible circuit that can be substituted for the flexible circuit shown in FIG. 2A. Flexible circuit 120
Is composed of an adhesive layer 130 and a copper wiring layer 124. In the example shown in FIG. 2B, the adhesive layer 130 is also the first dielectric layer 125. Adhesive layer 130 is typically about 12 microns thick. The thickness of the first wiring layer 124 of the flexible circuit 120 is typically about 18
Micron. In FIGS. 2A and 2B, the adhesive is shown as an integral part of the flexible circuit structure. This is the preferred variant. Alternatively, the adhesive can be its own separate layer.

FIG. 3 is a top view showing the top flexible circuit 120 of the two-level circuit shown in FIG. 1 according to the present invention. The area array 132 is shown in FIG.
Is shown as having hundreds of solder bumps 134 along its perimeter. Each bump 134 corresponds to an I / O connection. As an example, if the flexible circuit 120 measures 42 mm × 42 mm, then about 600 available I / O connections are available. More specifically, in FIG. 3, since the area array 134 is a two-dimensional array in which each side of the area array 132 is provided with the bumps 134 of depth 6 rows and the bumps 134 of 25 columns, a total of 600 bumps are provided. Is provided. However, the number of rows and columns in the area array is not important and can vary.

Each bump 134 does not need to be connected to the line of the wiring pattern 124. For example, area array 1
Some of the 32 bumps 134 may be grounded as opposed to signal connected. Bump 1 acting as a ground connection
34 need not be connected to the integrated circuit die using striations 124. Striations 124 are not needed for ground connection,
The number and density of wiring lines 124 are reduced. Moreover, it may even be desirable to use the outermost row of bumps 134 around the perimeter as a ground connection.

The multi-layer package 102 includes the basic dielectric layer 1
12 and the step of obtaining the basic wiring pattern 114 formed on the first surface of the basic dielectric layer 112, the first dielectric layer 125 and the first wiring pattern formed on the surface of the first dielectric layer 125. A step of obtaining a first flexible circuit 120 having 124, a step of forming at least one opening 128 in a first dielectric layer 125, a step of laminating the first flexible circuit 120 on a substrate 110, a basic dielectric wiring Electrically interconnecting layer 114 to first wiring pattern 124.

The first step in forming the multi-layer package 100 is to obtain a substrate 110 with a basic dielectric layer 112, an adhesive layer 113, and a basic wiring pattern 114. The substrate 110 is a flexible circuit that is typically laminated to the second region of the package body 102 by an adhesive layer 113. First dielectric layer 125
The flexible circuit 120 including the first wiring layer 124 is laminated on the surface of the substrate 110.

After obtaining the basic dielectric layer 112 having the basic wiring pattern 114 and the first flexible circuit 120, an opening is formed in the first flexible circuit 120,
The first flexible circuit is laminated on the basic dielectric layer 112 and the basic wiring pattern 114. In the preferred embodiment, the substrate 110 is a flexible circuit and the substrate is laminated to the package body 102 at the same time as the first flexible circuit 120 is laminated to the surface of the substrate 110. Opening 128
Are formed in regions of the first flexible circuit that require electrical interconnection between layers. In one method of package formation, openings are formed in the first dielectric layer prior to the laminating process. In the alternative, the openings are formed after the laminating process.

FIG. 4 is an exploded cross-sectional view before stacking the board on the package body and before stacking the flexible circuit 120 on the board. In the method shown in FIG. 4, it can be seen that the opening 128 is formed in the first flexible circuit before the laminating step. FIG. 5A is an enlarged cross-sectional view of a portion of the two-level multilayer package interconnect after hole formation and lamination, but before solder ball attachment, where holes are formed before the lamination process. There are several ways to form an opening in the first flexible circuit 120. In the method shown in FIG. 4, openings are typically formed in the flexible circuit 120 by forming the openings using a drill or punch. Although the embodiments shown in FIGS. 1, 4 and 5A and 5B show a two-level structure, a multilayer structure having three or more wiring patterns may be added to another flexible circuit layer. Can be formed more easily.

In the embodiment shown in FIG. 5A, the opening 128
Is filled with a solder ball conductive material. However, it is only necessary to partially fill the opening and cover at least part of the sidewall with a conductive material. An important objective is to provide a conductive path from one level (eg, the first wire path) to another level (eg, the base dielectric wire path).

FIG. 5B is a sectional view of a part of the two-level multilayer package shown in FIG. 5A after forming holes and attaching solder balls. Electrical interconnections between layers are typically made during solder ball attachment. During the process of attaching the solder balls, the flow of solder is flexible circuit 12
Bridging the 0 conductors to the conductors of the wiring pattern 114 helps to effectively form path connections between the flexible circuits. In the case of a two-level package, electrical interconnection is made between the wiring pattern 114 formed on the basic dielectric layer 112 and the first wiring pattern 124 formed on the first dielectric layer 125 of the flexible circuit 120. Be done.

The solder balls 134 are formed on the first dielectric layer 12
It is installed in the opening 128 formed in 5. As the temperature rises during solder ball attachment, some of the solder balls melt through the openings 128 in the first dielectric layer and come into contact with some of the wiring patterns 114 formed in the underlying dielectric layer 112. The size of the package is reduced because the solder balls 134 can be placed directly above the openings 128 in the dielectric layer 125, as opposed to being placed laterally to the openings with conventional techniques. Although the described method of making vias using solder balls is the most attractive from a manufacturing cost standpoint, vias are accomplished using solder paste or conductive adhesive, or by plating holes or by other means. You can also

FIGS. 6A to 6C are sectional views showing a part of the three-level multilayer package. Another interconnect layer can be easily formed by adding another flexible circuit, eg, a second flexible circuit layer 150, as can be seen in FIGS. 6 (A)-(C). In contrast to the embodiment shown in FIGS. 4 and 5A, 5B, the openings in the dielectric layers of the first and second flexible circuit layers are the first flexible circuit layer 120 and the second flexible circuit layer. It is formed after the circuit layer 150 is laminated.

In the process shown in FIGS. 6A to 6C,
The openings are formed in the dielectric layer using a laser after lamination.
FIG. 6A shows an exploded view of a portion of the package interconnect structure before the stacking process. Similar to the embodiment shown in FIG. 1, in the preferred embodiment, the substrate 110 shown in FIGS. 6A-6C is a flexible circuit consisting of a basic dielectric layer 112 and a wiring pattern 114. The three-level structure further includes a first flexible circuit 120 and a second flexible circuit 150.
It has. The first flexible circuit 120 includes a first dielectric layer 125 and a first wiring pattern 124. Next, the second flexible circuit 140 is installed above the first flexible circuit 120. Second
Flexible circuit includes a second dielectric layer 152 and a second dielectric layer 152.
The wiring pattern 15 is provided.

FIG. 6B shows a cross-sectional view of a portion of the package interconnect structure after the laminating step but before the hole forming step.
Dielectric layers 125, 1 requiring electrical interconnection between layers
Lasers can be installed above the individual areas of 52. The wiring patterns 124 and 154 can act as masks during laser irradiation. Another option is to align a metal mask protecting the required area over the surface of the flexible circuit, followed by a global laser exposure of the surface. In contrast to conventional co-fired ceramic and printed circuit board lamination processes, laser hole forming is feasible with the present invention because the flexible dielectric is composed of a polymer and is thin. In contrast, glass dielectrics used in printed circuit board lamination techniques melt but do not burn and do not easily form openings. Furthermore, the thickness and number of layers in co-fired ceramic and printed circuit board packaging techniques make the formation of openings using lasers impractical.

Hole formation using a laser is believed to be preferred due to the size advantages offered by using a laser as opposed to drilling a via hole. The size of the passage opening is limited by the size of the drill. The smallest size produced by current drilling technology is about .0 for a drill compared to a laser that can produce an aperture of 0.025 to 0.05 mm (1-2 mils).
25 mm (10 mils) and 0.1 mm for punches
(4 mil). Moreover, the use of lasers to form the openings reduces the processing time for package formation. Mechanically milling individual holes one at a time is expensive and time consuming. Laser hole forming, by contrast, is a gang process that takes a minimal amount of time compared to mechanical abrading or punching of via holes.

Applicants believe that yet another advantage of using a laser is the elimination of spills. The thin adhesive layer used in connection with the ablation process minimizes outflow into openings compared to conventional co-fired ceramic and printed circuit board lamination processes, but uses laser or other dry etch techniques. Then the outflow is completely eliminated.

FIG. 6C is a cross-sectional view of a portion of the package interconnect after hole formation. In the staircase path structure shown in FIG. 6C, the opening of each flexible circuit is larger than the opening of the next lower level flexible circuit. As shown in FIG. 6C, the opening of the first flexible circuit 150 is larger than the opening of the flexible circuit 120. FIG. 5 (A),
Similar to the embodiment shown in (B), electrical interconnections between layers are typically made during solder ball attachment. With three-level electrical interconnections, electrical interconnections can be established between any or all of the individual levels. It is not necessary for each flexible circuit level to be electrically connected to each other. Further, metallized lands 154a, 124a, 11
It is not necessary to connect any one of 4a to their respective wiring patterns. They only perform the function of providing a consistent environment for each solder ball.

As detailed above, another interconnection level is easily formed by simply adding another flexible circuit layer. The packages can all include multiple flexible circuits (n). Here, n is an integer of 1 or more. For example, for a 5-level interconnect structure in which the underlying dielectric layer is a flexible circuit, n equals 5. The five flexible circuits are stacked together and each flexible circuit layer has at least one opening. At least one opening formed in each flexible circuit is at least partially filled with a conductive material to electrically connect any of the wiring patterns together. For example, connecting the fourth wiring pattern to the second wiring pattern,
The wiring pattern can be connected to the basic wiring pattern. It is not necessary that each flexible circuit level be electrically connected to each other. Alternatively, if the base dielectric layer and the base wiring pattern do not form a flexible circuit, eg, the base wiring pattern is not formed on a printed circuit board, then n equals 1 for a two level package, The basic wiring pattern is connected to the first wiring pattern formed on the first dielectric layer.

The base dielectric layer, which typically has a base wiring layer, is laminated to the package body, but the base dielectric and the wiring layer may be described as intermediate interconnect layers if they are flexible circuits. it can. For example, in the three-level structure shown in FIGS. 6A to 6C, the flexible circuit 120 can be referred to as a basic dielectric and a basic wiring layer, and the flexible circuit 150 can be referred to as a first flexible circuit.

Although the individually described packages are designed for wirebonding to integrated circuits, wirebonding is the cheapest and most popular interconnect mechanism currently in use. Other means (TAB and flip chip) can be incorporated relatively easily. The two bonding binders connect the central opening of the flexible circuit 140 to the flexible circuit 1.
It is made by selecting larger than the central opening of 20. 154 microns (1 for each bonding bond)
Bond finger pitches of 02 micron stripes, 52 micron spacing) are typically possible, which results in a low effective bond pitch capability of 77 microns (about 3 mils).

Referring to FIG. 7, there is shown a cross sectional view of a two level ground plane shared package. An important electrical property of the package according to the invention is that it provides a low controlled impedance environment for both signal layers. Low impedance can be achieved by sharing the same ground plane by judicious choice of line width and dielectric thickness. It is important to note that this scenario is only possible due to the thin line capability provided by thin dielectric and flexible circuit technology, and cannot be achieved by conventional printed circuit and co-firing technology.
In conventional printed circuit and co-firing techniques, the dielectric layer is much thicker, requiring a separate ground plane for each signal layer.

In one embodiment of the present invention, the wiring pattern 114 of the basic dielectric and the wiring pattern 12 of the first dielectric layer 125 are used.
4 and 4 share a ground plane. In the embodiment shown in FIG. 7, the first flexible circuit 120 has a two-layer structure as shown in FIG. 2A, and the first dielectric layer 125 is the adhesive layer 130. The adhesive material used in this illustration is a thermoplastic polyimide whose dielectric constant is the same as that of the polyimide layer 122, although other adhesive materials can be used. In the ground plane sharing embodiment, the package body is made of a conductive material and the first wiring pattern and the basic wiring pattern are both electrically coupled to the package body.

The width of the signal line of the basic dielectric wiring pattern 114 is 50 μm, and the dielectric thickness between the signal line and the ground plane (metal package body) is 35 μm. The width of the signal line 124 of the flexible circuit 120 is 78.
Micron and the predielectric thickness between the signal line and the ground plane 102 is 55 microns (3 of dielectric from the base dielectric).
2 of dielectric from flexible circuit 120 to 5 microns
0 micron is added). Therefore, the ratio of the width of the signal line to the dielectric thickness is given by the same microstrip control impedance for the signals on both layers:
The same for both layers avoids the need for separate ground lines.

The descriptions above are intended to be illustrative, not limiting. The scope of the invention should, therefore, be determined not with reference to the above description, but with reference to the various embodiments described below.

That is, the multilayer integrated circuit package of the present invention is [1] a basic wiring pattern formed on the surface of a basic dielectric layer and a first flexible circuit laminated on the basic dielectric layer. Of the dielectric layer and the first wiring pattern formed on the first surface of the first dielectric layer, and at least one opening penetrating the first flexible circuit, wherein the at least one opening is at least partially And a first flexible circuit filled with a conductive material for electrically connecting a part of the basic wiring pattern to the first wiring pattern,
It has an embodiment like [2]-[8].

[2] The multi-layer integration according to [1], further including a package body having a first region and a second region, and a basic dielectric layer formed in the second region. Circuit package.

[3] Further, the first dielectric layer comprises a combination of a polyimide layer and a tacky thermoplastic layer, the total thickness of the first dielectric layer being less than 4 mils [1]. The multi-layer integrated circuit package described in.

[4] Further, a second flexible circuit layer is provided, and the second flexible circuit layer is provided with a second dielectric layer and a second wiring pattern formed on the surface of the second dielectric layer. The second flexible circuit is laminated on the first flexible circuit layer, and at least one opening is formed in the second flexible circuit. [1].

[5] An opening extends from the second flexible circuit layer to the basic flexible circuit, and a conductive material for electrically connecting the second wiring pattern to the basic wiring pattern is at least partially formed in the opening. Clogged [4]
The multi-layer integrated circuit package described in.

[6] The opening extends from the second flexible circuit layer to the first flexible circuit layer, and the second wiring pattern is electrically connected to the first wiring pattern at least partially in the opening. The multilayer integrated circuit package according to [4], in which conductive materials to be connected are packed.

[7] The package body is made of metal, and further has an opening formed through the basic wiring pattern and the basic dielectric layer to the package body, and the opening is made of a conductive material for connecting the basic wiring pattern to the package body. The multilayer integrated circuit package according to [2], wherein the material is packed.

[8] The multilayer integrated circuit package according to [1], wherein the basic dielectric layer and the basic wiring pattern form a flexible circuit.

Further, the multilayer integrated circuit package of the present invention is

[9] Where n is an integer of 1 or more, it is composed of n flexible circuits, each flexible circuit has a dielectric layer and a wiring pattern formed on the surface of the dielectric layer, and the n flexible circuits are laminated together. At least one opening extends through each flexible circuit, and at least one opening is at least partially filled with a conductive material for electrically connecting any of the wiring patterns together.

Further, in the method for manufacturing a multilayer integrated circuit package of the present invention, [10] a step of obtaining a basic dielectric layer having a basic wiring pattern formed on the surface thereof, and a first wiring pattern formed on the surface thereof. At least one first formed
A step of obtaining a first flexible circuit having a dielectric layer, a step of forming a plurality of openings in the first flexible circuit, a step of laminating the first flexible circuit on a basic dielectric layer and a basic wiring pattern, And a step of at least partially filling a plurality of openings of the first flexible circuit with a conductive material for electrically connecting the basic wiring pattern to the first wiring pattern,
It has an embodiment like [11]-[20].

[11] The method for manufacturing a multi-layer integrated circuit package according to [10], wherein the plurality of openings of the first flexible circuit are mechanically formed by milling.

[12] The method for manufacturing a multilayer integrated circuit package according to [19], wherein the plurality of openings of the first flexible circuit are mechanically formed by punching.

[13] The method for manufacturing a multilayer integrated circuit package according to [10], wherein the plurality of openings are formed by dry etching a flexible circuit.

[14] The opening is formed by exposing the structure to light emitted from a laser after the laminating process [13].
A method for manufacturing a multilayer integrated circuit package according to.

[15] The method further comprises the step of aligning a mask above the first flexible circuit and exposing the structure to the light emitted from the laser, the step of aligning forming at least one opening in the first flexible circuit. The method for manufacturing a multilayer integrated circuit package according to [14], which is performed before the step of forming.

[16] The method for manufacturing a multi-layer integrated circuit package according to [14], wherein the laser is individually moved to a position requiring an opening, and the wiring pattern is used as a mask.

[17] The multilayer wiring according to [10], wherein the basic wiring pattern is electrically connected to the first wiring pattern by filling a conductive material in an opening between the first flexible circuit and the basic wiring pattern. Manufacturing method of integrated circuit package.

[18] The method for manufacturing a multilayer integrated circuit package as described in [17], wherein the opening is filled by placing a solder ball above the opening and melting the solder ball to fill the opening.

[19] Furthermore, the second dielectric layer and the second
To obtain a second flexible circuit having a second wiring pattern formed on the dielectric layer, and to form an opening between the first flexible circuit and the second flexible circuit,
The step of connecting a first wiring pattern to a second wiring pattern by at least partially filling a conductive material into an opening between the first flexible circuit and the second flexible circuit is described in [10]. Of manufacturing a multi-layer integrated circuit package.

[20] Further, the second dielectric layer and the second
To obtain a second flexible circuit having a second wiring pattern formed on the dielectric layer, and to form an opening between the first flexible circuit and the basic wiring pattern. The method further comprises the step of connecting the second wiring pattern to the basic wiring pattern by at least partially filling the opening with the basic wiring pattern with a conductive material.
0] The method for manufacturing a multilayer integrated circuit package described in [0].

[0067]

The present invention reduces dimensional changes during processing,
The thickness of the individual dielectric layers can be reduced to provide high pin count interconnects that provide easy interconnection between layers of a multi-layer package.

[Brief description of drawings]

FIG. 1 is a cross-sectional view of a two-level multilayer package according to an exemplary embodiment of the present invention.

2A and 2B are cross-sectional views of portions of two different flexible circuit structures useful in practicing the present invention.

FIG. 3 is a top view showing a top flexible circuit layer of a two-level package according to the present invention.

FIG. 4 is an exploded cross-sectional view of a two-level multilayer package according to the present invention before forming holes.

FIG. 5A is a cross-sectional view of a part of the two-level multilayer package after forming the holes and before attaching the solder balls, and FIG.
FIG. 6 is a cross-sectional view of a part of the two-level multilayer package after forming the holes and attaching the solder balls.

6A-6C are cross-sectional views showing one method of forming a three-level multilayer package.

FIG. 7 is a cross-sectional view showing a two-level ground plane sharing structure.

[Explanation of symbols]

 100 Multilayer Package 102 Package Body 104 First Region 108 Second Region 110 Substrate 111 Polyimide Layer 112 Basic Dielectric Layer 113 Adhesive Layer 114 Basic Wiring Pattern 120 First Flexible Circuit 122 First Dielectric Layer 124 First Wiring pattern layer 125 First dielectric layer 128 Opening 130 Adhesive layer 134 Solder bump 140 Second flexible circuit 150 Second flexible circuit 152 Second dielectric layer 154 Second wiring pattern

Claims (3)

[Claims] 1. A multilayer integrated circuit package constituting an interconnection system, comprising: a basic wiring pattern formed on a surface of a basic dielectric layer; and a first flexible circuit laminated on the basic dielectric layer. Of the dielectric layer and the first wiring pattern formed on the first surface of the first dielectric layer, and at least one opening penetrating the first flexible circuit, wherein the at least one opening is at least partially A multi-layer integrated circuit package including a first flexible circuit filled with a conductive material for electrically connecting a part of the basic wiring pattern to the first wiring pattern. 2. A multilayer integrated circuit package constituting an interconnection system, comprising n flexible circuits, where n is an integer of 1 or more, and each flexible circuit is formed on a dielectric layer and a surface of the dielectric layer. A wiring pattern is provided, n flexible circuits are stacked together, at least one opening extends through each flexible circuit, and at least one opening electrically connects at least partially any of the wiring patterns together. Multilayer integrated circuit package filled with conductive material to connect. 3. A method of manufacturing a multi-layer integrated circuit package for electrically interconnecting multi-layer packages, the method comprising: obtaining a basic dielectric layer having a basic wiring pattern formed on its surface; A step of obtaining a first flexible circuit having at least one first dielectric layer on which the wiring pattern is formed; a step of forming a plurality of openings in the first flexible circuit; From the step of laminating the dielectric layer and the basic wiring pattern, and the step of at least partially filling a plurality of openings of the first flexible circuit with a conductive material that electrically connects the basic wiring pattern to the first wiring pattern. Method of manufacturing a multilayer integrated circuit package configured.