JP2013045015A - Display device and method of driving the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a display device with reduced wiring loss capable of displaying high-resolution images, and a method of driving the same.SOLUTION: A display device 1 includes a plurality of pixels, a scan line 51 provided for every two pixel rows, and an address line 71 provided for every pixel column. A pixel 11A includes a diode 112 which turns conductive in accordance with the electrical potential of the scan line 51, a capacitor 115 which maintains a voltage corresponding to the electrical potential of the address line 71 when the diode 112 is conductive, a TFT switch 114 which is turned on by the voltage of the capacitor 115, and an organic EL element 111 which illuminates when the TFT switch 114 turns on. A pixel 21A includes a diode 212 whose conduction state is kept opposite to that of the diode 112 in accordance with the electrical potential of the scan line 51, a capacitor 215 which maintains a voltage corresponding to the electrical potential of the address line 71 when the diode 212 is conductive, a TFT switch 214 which is turned on by the voltage of the capacitor 215, and an organic EL element 211 which illuminates when the TFT switch 214 turns on.

Description

  The present invention relates to a display device and a driving method thereof, and more particularly to an active matrix display device that controls display luminance in accordance with a light emission time of a pixel and a driving method thereof.

  As one of display devices, a display panel using an organic EL (electroluminescence) element using an organic material for a light emitting layer as a pixel component has already been commercialized. As a display device using an organic EL element, an active matrix display device using a lighting control element such as a TFT (Thin Film Transistor) is known for each pixel arranged in a matrix.

  In an active matrix display device, an analog driving method and a digital driving method are known as gradation expression methods. In the analog drive method, a voltage corresponding to video data is held in a capacitor connected to the gate terminal of the TFT. Then, in one frame period, the organic EL element of each pixel continues to emit light with a luminance corresponding to the voltage held in the capacitor. As described above, in the analog driving method, the amount of electric charge held in the capacitor is changed according to the video data, and the luminance of the organic EL element of each pixel is controlled to express the gradation. On the other hand, in the digital driving method, one frame period is divided into a plurality of subfields having different light emission possible periods, and each pixel is selected to emit light or not to emit light for each subfield according to video data. The gradation is expressed by the sum of the light emission times in one field period.

  FIG. 10 is a circuit diagram of pixels arranged in a digital drive type display panel described in Patent Document 1. In FIG. In the pixel 900 shown in the figure, the data signal from the data driver corresponding to the video signal is supplied to the source of the data writing transistor 901 via the data line 914 arranged on the display panel. A scanning signal is supplied to the gate of the data writing transistor 901 through a scanning line 913 connected to a scanning driver. The drain of the data writing transistor 901 is connected to the gate of the driving transistor 902 and to one terminal of the capacitor 905. The source of the driving transistor 902 is connected to the other terminal of the capacitor 905 and a driving voltage is supplied through the power supply line 916. The drain of the drive transistor 902 is connected to the anode terminal of the organic EL element 904, and the cathode terminal of the organic EL element 904 is connected to a reference potential point. Further, the source and drain of the erasing transistor 903 are connected to each end of the capacitor 905. An erase signal is supplied from the erase driver to the gate of the erase transistor 903 via the erase line 915.

  The above configuration is different from the general analog driving method in that an erasing transistor 903 and an erasing line 915 that connect both ends of the capacitor 905 are provided. By applying an erasing signal to the erasing line 915, the erasing transistor 903 is short-circuited and the voltage held in the capacitor 905 is cancelled. By varying the time from when the electric charge is accumulated in the capacitor 905 until the voltage is applied to the erasing line 915 in each subfield, the light emission possible period for each subfield is varied. In the digital drive method, since only the switching function is required for the lighting control element, it is possible to reduce the power loss in the lighting control element.

JP 2007-108366 A

  However, since the digital drive method of Patent Document 1 described above needs to arrange a scanning line and an erasing line for each pixel, for example, FHD (full high-definition display), SHD (4k2k display), etc. In a high-definition display, wiring design becomes a problem. That is, in order to obtain a higher-definition image, it is necessary to narrow the wiring width, which increases the wiring resistance. When the wiring resistance increases, the loss due to the wiring increases and the power consumption also increases.

  The present invention has been made in view of the above problems, and an object of the present invention is to provide a display device capable of reducing loss due to wiring and achieving high definition and a driving method thereof.

  In order to solve the above problems, a display device according to one embodiment of the present invention includes a plurality of pixels arranged in a matrix, a scanning line arranged every two pixel rows, and an address arranged every pixel column. A first pixel of two pixels corresponding to an intersection of one scanning line and one address line among the plurality of pixels is in a conductive state according to a potential of the scanning line The first switch unit, the first capacitor that holds the voltage determined according to the potential of the address line and the scanning line when the first switch unit becomes conductive, and the first capacitor A first switch transistor that causes a light-emitting current to flow according to a voltage; and a first light-emitting element that emits light when the light-emitting current flows, and of the plurality of pixels, of the two pixels corresponding to the intersection, First pixel genus A second pixel arranged in a pixel row different from the first pixel row includes a second switch portion that is in a conductive state exclusively with the first switch portion according to a potential of the scanning line; and the second switch A second capacitor that holds a voltage that is determined according to the potential of the address line and the scanning line when the unit is in a conductive state, and a second switch transistor that causes a light emission current to flow according to the voltage held in the second capacitor And a second light emitting element that emits light when the light emission current flows.

  According to the above configuration, the scanning line for controlling the timing of voltage writing to each pixel only needs to be arranged for every two pixel rows, and the number of wirings can be reduced. Therefore, loss due to wiring can be reduced. Also, high definition can be achieved.

  The first switch unit is a first diode element having an anode electrode connected to the address line and a cathode electrode connected to one electrode of the first capacitor, and the other electrode of the first capacitor. Is connected to the scanning line, the gate electrode of the first switch transistor is connected to one electrode of the first capacitor, the drain electrode is connected to a power supply line, the source electrode is connected to the scanning line, The one light emitting element is inserted in series between the power line and the drain electrode of the first switch transistor, and the second switch unit includes an anode electrode connected to the scan line and a cathode electrode connected to the first electrode. A second diode element connected to one electrode of two capacitors, and the other electrode of the second capacitor is connected to the address line; The gate electrode of the two switch transistor is connected to one electrode of the second capacitor, the drain electrode is connected to the power line, the source electrode is connected to the address line, and the second light emitting element is connected to the power line and the power line. It may be inserted in series between the drain electrode of the second switch transistor.

  The driving unit further controls a potential of the scanning line and the address line, the driving unit sets the scanning line potential to a low potential, sets the scanning lines other than the scanning line to a high impedance state, and By setting the potential of the address line to a high potential higher than the threshold voltage of the first switch transistor with respect to the low potential, the first diode is made conductive and the voltage is held in the first capacitor. The scanning line potential is set to a high potential, scanning lines other than the scanning line are set to a high impedance state, and the potential of the address line is lower than the threshold voltage of the second switch transistor with respect to the high potential. By setting the address line as a low potential, the second diode is made conductive, the voltage is held in the second capacitor, and the scanning line is turned on. The first switch transistor and the second switch transistor are turned on according to the voltage held in the first capacitor and the second capacitor by setting the address line to a low potential and setting the address line to the address line low potential. It is preferable that the first light emitting element and the second light emitting element emit light.

  Accordingly, by setting the scanning line potential to a low potential and the address line potential to be a high potential, voltage writing to the first pixel is performed, and the scanning line potential is set to a high potential and the address line potential is set to a low potential. As a result, voltage writing to the second pixel is executed.

  The first pixel further includes an erasing line for erasing the voltage held in the first capacitor and the second capacitor, and the first pixel further has an anode electrode connected to one electrode of the first capacitor, The second pixel further includes a third diode element having a cathode electrode connected to the erasing line, the anode electrode being connected to one electrode of the second capacitor, and the cathode electrode being connected to the erasing line. Further, a fourth diode element may be provided.

  In addition, when the driving unit causes the first capacitor and the second capacitor to hold a voltage, the potential of the erasing line is set to a high potential, and the voltage held in the first capacitor and the second capacitor is set. In the case of erasing, the potential of the erasing line may be a low potential applied to the scanning line and a low potential not more than a low potential applied to the address line.

  Thereby, the reset operation can be executed for all the pixels at the same time, so that the light emission possible period for each subfield can be controlled. Therefore, a display operation by a digital driving method is possible.

  The first switch unit includes a third switch transistor having a gate electrode connected to the scan line, a source electrode connected to the first power supply line, a gate electrode connected to the address line, and a source electrode connected to the address line. A fourth switch transistor connected to one electrode of the first capacitor and having a drain electrode connected to the drain electrode of the third switch transistor; and the gate electrode of the second switch section has a predetermined bias potential A fifth switch transistor connected to a bias terminal, a source electrode connected to the scan line, a gate electrode connected to the address line, a source electrode connected to one electrode of the second capacitor, and a drain electrode A sixth switch transistor connected to a drain electrode of the fifth switch transistor; The gate electrode of the switch transistor is connected to one electrode of the first capacitor, the drain electrode is connected to the second power supply line, the source electrode is connected to the other electrode of the first capacitor, and the first light emitting element is The anode electrode is connected to the source electrode of the first switch transistor, the cathode electrode is grounded, the gate electrode of the second switch transistor is connected to one electrode of the second capacitor, and the drain electrode is connected to the first electrode. Two power lines, a source electrode is connected to the other electrode of the second capacitor, and the second light emitting element has an anode electrode connected to the source electrode of the second switch transistor and a cathode electrode grounded. May be.

  The driving unit further controls a potential of the scanning line and the address line, and the driving unit sets the potential of the scanning line to the power supply potential of the first power supply line. The scanning line has a low potential lower than the threshold voltage, the scanning lines other than the scanning line are in a high impedance state, and the potential of the address line is higher than the threshold voltage of the first switch transistor with respect to the ground potential. By making the potential, the third switch transistor and the fourth switch transistor are turned on, the voltage is held from the first power supply line to the first capacitor, and the potential of the scanning line is changed to the bias potential. In contrast, the potential is higher than the threshold voltage of the fifth switch transistor, and the scanning lines other than the scanning line are in a high impedance state, The potential of the address line is set to a high potential higher than the threshold voltage of the second switch transistor with respect to the ground potential, thereby bringing the fifth switch transistor and the sixth switch transistor into a conductive state and the scanning line. It is preferable that the second capacitor holds the voltage.

  As a result, the scanning lines for controlling the timing of voltage writing to each pixel need only be arranged for every two pixel rows, and further, the number of wirings can be reduced because no erasing line is required. Therefore, loss due to wiring can be reduced. Also, high definition can be achieved. Furthermore, since the switch part is composed of TFTs without using a diode, the manufacturing process can be simplified.

  Further, an erasing line connected to one electrode of the first capacitor and one electrode of the second capacitor for erasing the voltage held in the first capacitor and the second capacitor may be provided. .

  When the driving unit erases the voltage held in the first capacitor and the second capacitor, the driving unit sets the potential of the address line to the source potential of the fourth switch transistor. By lowering the threshold voltage of the sixth switch transistor than the threshold voltage of the sixth switch transistor, the fourth switch transistor and the sixth switch transistor are made non-conductive. In the conductive state, the potential of the erase line may be a low potential that is lower than the low potential applied to the address line.

  Thereby, the reset operation can be executed for all the pixels at the same time, so that the light emission possible period for each subfield can be controlled. Therefore, a display operation by a digital driving method is possible.

  The first light emitting element and the second light emitting element may be organic EL elements.

  The first light emitting element and the second light emitting element may be inorganic EL elements.

  Further, the present invention can be realized not only as a display device having such characteristic means, but also as a display device driving method using the characteristic means included in the display device as a step. .

  According to the display device and the driving method thereof of the present invention, since the number of wirings can be reduced, loss due to wirings can be reduced. Also, high definition can be achieved.

It is a functional block diagram of the display apparatus which concerns on Embodiment 1 of this invention. FIG. 3 is a circuit configuration diagram of a pixel portion included in the display device according to Embodiment 1 of the present invention. FIG. 3 is an internal circuit diagram of a scanning line control circuit included in the display device according to Embodiment 1 of the present invention. It is an internal circuit diagram of the data line control circuit which the display apparatus of this invention has. 4 is a drive timing chart of the display device according to the first embodiment of the present invention. FIG. 6 is a state transition diagram illustrating a pixel reset operation according to the first embodiment. FIG. 6 is a state transition diagram illustrating a write operation for odd-numbered row pixels according to the first embodiment. FIG. 6 is a state transition diagram illustrating a write operation for even-numbered row pixels according to the first embodiment. FIG. 6 is a state transition diagram illustrating a light emission operation of the pixel according to the first embodiment. It is a circuit block diagram of the pixel part which the display apparatus which concerns on Embodiment 2 of this invention has. It is a drive timing chart of the display apparatus which concerns on Embodiment 2 of this invention. FIG. 10 is a state transition diagram illustrating a pixel reset operation according to the second embodiment. FIG. 10 is a state transition diagram for explaining an odd-row pixel write operation according to the second embodiment; FIG. 10 is a state transition diagram illustrating a write operation for even-numbered rows pixels according to the second embodiment. FIG. 10 is a state transition diagram illustrating a light emission operation of a pixel according to Embodiment 2. FIG. 6 is a circuit diagram of pixels arranged in a digital drive type display panel described in Patent Document 1.

  Hereinafter, embodiments for carrying out the present invention will be described with reference to the drawings.

(Embodiment 1)
<Configuration of display device>
FIG. 1 is a functional block diagram of a display device according to Embodiment 1 of the present invention. The display device 1 illustrated in FIG. 1 includes a subfield processing circuit 2, a scanning line control circuit 5, an erase line control circuit 6, a data line control circuit 7, and a pixel unit 10.

  The subfield processing circuit 2 assigns a subfield to emit light for each pixel of the pixel unit 10 in accordance with the input video signal, and controls the scanning line control circuit 5, the erase line control circuit 6, and the data line control circuit 7. Is output.

  The scanning line control circuit 5 applies a scanning voltage to the pixel unit 10, the data line control circuit 7 applies an address voltage to the pixel unit 10, and the erasing line control circuit 6 applies an erasing voltage to the pixel unit 10. Hereinafter, components of the display device 1 described above will be described in detail. The scanning line control circuit 5, the data line control circuit 7, and the erasing line control circuit 6 are drive units that control the potentials of the scanning line, address line, and erasing line, respectively.

  FIG. 2 is a circuit configuration diagram of a pixel portion included in the display device according to Embodiment 1 of the present invention. The pixel unit 10 is a display unit in which a plurality of pixels arranged in a matrix according to the resolution (m × n) of the display is arranged. FIG. Four pixels are described. The pixel unit 10 illustrated in FIG. 2 includes four adjacent pixels 11A, 12A, 21A, and 22A, address lines 71 and 72 that are arranged for each pixel column, and scanning lines 51 that are arranged for every two pixel rows. And a power supply line 81 and an erasing line 61 which are arranged in a grid pattern corresponding to each pixel.

  The pixel 11A is the first pixel of the two pixels corresponding to the intersection of the scanning line 51 and the address line 71 among the plurality of pixels, and the pixel 12A is the scanning line 51 of the plurality of pixels. And the first pixel of the two pixels corresponding to the intersection of the address line 72. The pixel 21A is a second pixel arranged in a pixel row different from the pixel row to which the pixel 11A belongs, out of the two pixels corresponding to the intersection of the scanning line 51 and the address line 71 among the plurality of pixels. The pixel 22A is a second pixel arranged in a pixel row different from the pixel row to which the pixel 12A belongs, out of two pixels corresponding to the intersection of the scanning line 51 and the address line 72 among the plurality of pixels. Pixel.

  The plurality of pixels included in the pixel unit 10 all have the same circuit element. For example, the pixel 11A illustrated in FIG. 2 includes an organic EL element 111, diodes 112 and 113, a TFT switch 114, and the like. , A capacitor 115 and a constant current source 116.

  Here, each component of the pixels 11A to 22A and their connection relationship will be described.

  First, a connection relationship common to the pixels 11A to 22A will be described using the pixel 11A as an example. The anode electrode of the organic EL element 111 is connected to the power supply line 81 via the constant current source 116, and the cathode electrode is connected to the drain electrode of the TFT switch 114. The gate electrode of the TFT switch 114 is connected to the cathode electrode of the diode 112, the anode electrode of the diode 113, and one electrode of the capacitor 115. The cathode electrode of the diode 113 is connected to the erasing line 61.

  Further, the source electrodes of the TFT switches 114 and 314 are connected to the scanning line 51 in the pixels 11A and 12A arranged in the same pixel row. On the other hand, in the pixels 21A and 22A arranged in the same pixel row, the source electrodes of the TFT switches 214 and 414 are connected to the address lines 71 and 72, respectively.

  In the pixel 11A, the address line 71 is connected to the anode electrode of the diode 112, and in the pixel 21A, the address line 71 is connected to the other electrode of the capacitor 215.

  In the pixel 12A, the address line 72 is connected to the anode electrode of the diode 312. In the pixel 22A, the address line 72 is connected to the other electrode of the capacitor 415.

  Next, each component of the pixels 11A to 22A will be described.

  The organic EL elements 111, 211, 311 and 411 are current-driven light emitting elements. The organic EL elements 111 and 311 are first light emitting elements that emit light when the TFT switches 114 and 314 are turned on, respectively. The organic EL elements 211 and 411 are second light emitting elements that emit light when the TFT switches 214 and 414 are turned on, respectively. Specifically, the organic EL elements 111 and 311 are inserted in series between the power supply line 81 and the drain electrodes of the TFT switches 114 and 314, respectively. The organic EL elements 211 and 411 are inserted in series between the power supply line 81 and the drain electrodes of the TFT switches 214 and 414, respectively.

  The TFT switches 114, 214, 314, and 414 are, for example, n-type MOSFETs, and are switch elements that make the drain-source conductive when the gate-source voltage is larger than the threshold voltage. The TFT switches 114 and 314 are first switch transistors that are turned on according to the voltages held in the capacitors 115 and 315, respectively. The TFT switches 214 and 414 are second switch transistors that are turned on according to the voltages held in the capacitors 215 and 415, respectively.

  The capacitors 115, 215, 315, and 415 are charged with charges corresponding to the potential difference between the address line and the scanning line via the diodes 112, 212, 312 and 412, and the erase voltage is applied to the erase line 61. In some cases, the charged electric charge is discharged through the diodes 113, 213, 313 and 413. Capacitors 115 and 315 are first capacitors that hold voltages determined according to the potentials of the address lines 71 and 72 and the scanning line 51 when the diodes 112 and 312 are in a conductive state, respectively. Capacitors 215 and 415 are second capacitors that hold voltages determined according to the potentials of the address lines 71 and 72 and the scanning line 51 when the diodes 212 and 412 are turned on, respectively.

  The diode 112 is a first switch unit that is turned on in accordance with the potential of the scanning line 51, and has a first diode in which an anode electrode is connected to the address line 71 and a cathode electrode is connected to one electrode of the capacitor 115. It is an element. The diode 312 is a first switch unit that becomes conductive according to the potential of the scanning line 51, and has a first diode in which an anode electrode is connected to the address line 72 and a cathode electrode is connected to one electrode of the capacitor 315. It is an element.

  The diode 212 is a second switch unit that is in a conductive state exclusively with the diode 112 in accordance with the potential of the scanning line 51, the anode electrode is connected to the scanning line 51, and the cathode electrode is one electrode of the capacitor 215. Is a second diode element connected to. The diode 412 is a second switch unit that is in a conductive state exclusively with the diode 312 according to the potential of the scanning line 51, the anode electrode is connected to the scanning line 51, and the cathode electrode is one electrode of the capacitor 415. Is a second diode element connected to.

  The diode 113 is a third diode element having an anode electrode connected to one electrode of the capacitor 115 and a cathode electrode connected to the erasing line 61, and the diode 313 has an anode electrode connected to one electrode of the capacitor 315. The third diode element having the cathode electrode connected to the erasing line 61.

  The diode 213 is a fourth diode element having an anode electrode connected to one electrode of the capacitor 215 and a cathode electrode connected to the erasing line 61. The diode 413 has an anode electrode connected to one electrode of the capacitor 415. The fourth diode element having the cathode electrode connected to the erasing line 61.

  The erase line 61 discharges the charges accumulated in the capacitors 115, 215, 315 and 415 when an erase voltage is applied. In other words, the erasing line 61 is a control line for erasing the voltage held in the capacitors 115, 215, 315 and 415.

  In this embodiment, a constant power supply voltage is applied to all the pixels through the power supply line 81. The erase voltage is applied to all the pixels through the erase line 61 at the same timing. Therefore, the erase line 61 and the power supply line 81 may each be a common line across all pixels. Thereby, the driving load of the erase line control circuit 6 is reduced.

  When the potentials of the address lines 71 and 72 are higher than the threshold voltage of the TFT switches 114 and 314 with respect to the potential of the scanning line 51 due to the connection relations and components, the capacitors 115 and 315 have the address lines 71 respectively. And the voltage corresponding to the potential difference between 72 and the scanning line 51 is held. Further, when the potentials of the address lines 71 and 72 are lower than the threshold voltage of the TFT switches 214 and 414 with respect to the potential of the scanning line 51, the capacitors 215 and 415 are connected to the scanning line 51 and the address lines 71 and 72. A voltage corresponding to the potential difference is held. As described above, the potential of the address line and the potential of the scanning line are exclusively controlled, so that the voltage writing to the even pixel row is executed after the voltage writing to the odd pixel row. After the writing is completed, by setting the scanning line 51 to a predetermined potential (for example, GND potential), the organic EL elements of the pixels in which a voltage higher than the threshold voltage of the TFT switch is held in the capacitor emit light all at once. .

  According to the above configuration, the scanning lines for controlling the timing of voltage writing need only be arranged for every two pixel rows, and the number of wirings can be reduced. Therefore, loss due to wiring can be reduced. Also, high definition can be achieved.

  Next, the scanning line control circuit 5 will be described. The scanning line control circuit 5 outputs a scanning signal for selecting a light emitting pixel row to the pixel portion through the scanning line in accordance with a control signal from the subfield processing circuit 2 in the writing period.

FIG. 3 is an internal circuit diagram of the scanning line control circuit included in the display device according to Embodiment 1 of the present invention. The scanning line control circuit 5 has a circuit configuration in which two FET switches for supplying the high potential pulse Vscn or the low potential pulse V _GND to the scanning lines 51 to 5k as output lines are arranged for each line. . When the number of pixel rows is n, the scanning line control circuit 5 is connected to the pixel unit 10 via n / 2 scanning lines 51 to 5k. Each scanning line can be supplied with a high potential pulse Vscn or a low potential pulse V _GND to the scanning lines 51 to 5k in every two pixel rows in an arbitrary order in accordance with a signal from the scanning line control circuit 5. . The timing for applying the high potential pulse or the low potential pulse will be described later.

In the circuit shown in FIG. 3, for example, when the low potential pulse V _GND is applied to the scanning line 51, the scanning line control circuit 5 turns the FET 514 on and the FET 513 off. When applying the high potential pulse Vscn to the scanning line 51, the scanning line control circuit 5 turns the FET 513 on and the FET 514 off. When both the FET 513 and the FET 514 are turned off, the scanning line 51 is in a high impedance state and does not constitute a current path. In other words, the scanning line control circuit 5 selects the ON state and the OFF state of the two FETs arranged for each scanning line, so that the scanning line is placed in a low potential pulse V _GND state, a high potential pulse Vscn state, and a high potential state. Any one of the three impedance states can be used.

  Next, the erase line control circuit 6 will be described. The erasing line control circuit 6 uses the control signal from the subfield processing circuit 2 to transfer the erasing voltage held in the capacitors 115, 215, 315 and 415 to erase the signal voltage via the erasing line via the diode 113, Output to the cathode electrodes of 213, 313 and 413.

  The erase line control circuit 6 supplies the erase line 61 with a low potential pulse applied to the scanning line and a low potential equal to or lower than the low potential pulse applied to the address line, for example, a GND potential as an erase voltage. As a result, a forward current flows from one electrode of the capacitors 115, 215, 315, and 415 holding the signal voltage toward the erase line 61, and the capacitors 115, 215, 315, and 415 are reset. If the reset is not performed, the erase line control circuit 6 applies a positive voltage to the erase line 61 that is higher than, for example, a high potential pulse applied to the scanning line or a high potential pulse signal voltage applied to the address line. Supply. The timing for applying the erase voltage pulse will be described later.

  Next, the data line control circuit 7 will be described.

FIG. 4 is an internal circuit diagram of a data line control circuit included in the display device of the present invention. In response to the control signal from the subfield processing circuit 2, the data line control circuit 7 synchronizes with the scanning signal output from the scanning line control circuit 5 during the writing period and turns on and off the TFT switches 114, 214, 314 and 414. An address voltage for switching conduction is output to each pixel via the address line 71 or 72. Further, as shown in FIG. 4, the data line control circuit 7 may supply different address voltages to the respective pixels via the address lines 71 or 72 according to the R pixel, the G pixel, and the B pixel. For example, if the pixel 11A and the pixel 21A is R pixel, the data line control circuit 7 to the pixel 11A, when the scanning line 51 is low potential pulse _{V GND} state, by conducting the switch SW3A _R An address voltage (V _R ) is supplied to the address line 71. Further, when the scanning line 51 is at a high potential pulse Vscn state, it supplies an address voltage (-V _R) to the address line 71 by conducting a switch SW3B _R. The timing for applying the address voltage will be described later. In addition, the data line control circuit 7 has a memory function for simultaneously controlling the address lines of the number m of pixel columns corresponding to the resolution of the pixel unit 10.

<Operation of display device>
Hereinafter, the operation of the display device 1 will be described with reference to FIGS. 2, 5, and 6 </ b> A to 6 </ b> D. FIG. 5 is a drive timing chart of the display device according to Embodiment 1 of the present invention. In FIG. 2, it is assumed that the pixels 11A and 12A in FIG. 2 are pixels belonging to the third pixel row, and the pixels 21A and 22A are pixels belonging to the fourth pixel row. The case where all light is emitted in the subfield period is illustrated.

[Reset operation]
First, from time t01 to time t02, the erase line control circuit 6 supplies an erase voltage to the erase line 61 and resets capacitors included in all pixels. The erase line control circuit 6 supplies, for example, a GND potential as an erase voltage to the erase line 61. As a result, forward current flows from the one electrode of the capacitors 115, 215, 315, and 415 holding the signal voltage toward the erasing line 61 to the diodes 113, 213, 313, and 413, and the capacitors 115, 215, 315 And 415 are reset.

  FIG. 6A is a state transition diagram illustrating a reset operation of the pixel according to the first embodiment. That is, when a LOW potential is applied to the erasing line 61, as shown in FIG. 6A, a discharge current flows in the order of capacitors 115, 215, 315 and 415 → diodes 113, 213, 313 and 413 → erasing line 61, The voltage held in the capacitors 115, 215, 315 and 415 is erased.

  In the operation of the erase line control circuit 6 from the time t01 to the time t02, the potential of the erase line 61 is set to the low potential applied to the scanning line 51 and the low potential applied to the address lines 71 and 72 before the write operation. By setting the following low potential, it corresponds to an erasing step for erasing the voltage held in the capacitor 115 and the capacitor 315.

[Write operation]
At time t03, the scanning line control circuit 5 sets the gate potential of the n-type FET 514 to the LOW potential to be in the OFF state, and the gate potential of the p-type FET 513 is already the HIGH potential and is in the OFF state. Is in a high impedance state. Thus, preparation for writing a signal to the capacitor of the pixel is completed.

  Next, the write operation to the odd-numbered pixel rows is executed sequentially in the odd-numbered rows.

  For example, from time t04 to time t05, the scanning line control circuit 5 sets the gate potential of the FET 514 to the HIGH state and sets the potential of the scanning line 51 to LOW in order to execute voltage writing to the pixel belonging to the third row. (GND) potential. On the other hand, the data line control circuit 7 synchronizes with the above operation of the scanning line control circuit 5, and the thresholds of the TFT switches 114 and 314 with respect to the HIGH potential corresponding to the pixels in the third row, that is, the potential of the scanning line 51. A high potential higher than the voltage is supplied to the address lines 71 and 72.

  As a result, the HIGH potential of the address lines 71 and 72 is applied to one electrode of the capacitor 115 and one electrode of 315 via the diodes 112 and 312 that are in the conductive state, respectively. Since the LOW (GND) potential of the scanning line 51 is applied to the other electrode of 315, the capacitors 115 and 315 hold a voltage corresponding to the HIGH potential of the address lines 71 and 72. That is, the writing operation to the pixels 11A and 21A is executed.

  FIG. 6B is a state transition diagram illustrating the write operation of the odd-numbered row pixels according to the first embodiment. That is, when a LOW potential is applied to the scanning line 51 and a HIGH potential is applied to the address lines 71 and 71, as shown in FIG. 6B, the address lines 71 and 72 → the diodes 112 and 312 → the capacitors 115 and 315 A charging current sequentially flows, and the voltage is held in the capacitors 115 and 315.

  The operations of the scanning line control circuit 5 and the data line control circuit 7 from the time t04 to the time t05 are such that the potential of the scanning line 51 is low, the scanning lines other than the scanning line 51 are in a high impedance state, and the address lines 71 and 72 are. Is set to a high potential higher than the threshold voltage of the TFT switches 114 and 314 with respect to the low potential of the scanning line 51, so that the diodes 112 and 312 are turned on and the capacitors 115 and 315 hold the voltage. This corresponds to the first voltage holding step.

  After time t05, the writing operation to the odd-numbered pixel row is sequentially executed in the odd-numbered row, similarly to the writing operation in the third pixel row described above. During this period, the scanning lines of the pixel rows that are not in the writing operation are set to the high impedance state. Therefore, even in a pixel for which writing has been completed, since the source potential of the FET is not fixed, the organic EL element does not start a light emitting operation during the writing period to the odd pixel row.

  Next, when the write operation to the odd pixel row is completed, the write operation to the even pixel row is executed.

  For example, from time t06 to time t07, the scanning line control circuit 5 sets the gate potential of the FET 513 to the LOW potential and turns on the potential of the scanning line 51 in order to write the signal voltage to the pixels belonging to the fourth row. A HIGH (Vscn) potential is set. On the other hand, the data line control circuit 7 synchronizes with the above operation of the scanning line control circuit 5, and the TFT switch 214 with respect to the LOW (GND) potential corresponding to the pixels in the fourth row, that is, the HIGH potential of the scanning line 51. And a low potential lower than the threshold voltage of 414 is supplied to the address lines 71 and 72.

  Accordingly, the HIGH (Vscn) potential of the scanning line 51 is applied to the one electrode of the capacitor 215 and the one electrode of 415 via the diodes 212 and 412 that are in the conductive state, respectively, and the capacitor 215 Since the LOW (GND) potential of the address lines 71 and 72 is applied to the other electrode of 415 and 415, a voltage corresponding to the HIGH potential of the scanning line is held in the capacitors 215 and 415. That is, the writing operation to the pixels 11A and 21A is executed.

  FIG. 6C is a state transition diagram illustrating the write operation of even-numbered rows pixels according to the first embodiment. That is, when a HIGH potential is applied to the scanning line 51 and a LOW potential is applied to the address lines 71 and 71, charging is performed in the order of the scanning line 51 → the diodes 212 and 412 → the capacitors 215 and 415, as shown in FIG. 6C. A current flows, and the voltage is held in the capacitors 215 and 415.

  The operation of the scanning line control circuit 5 and the data line control circuit 7 from time t06 to time t07 is such that the potential of the scanning line 51 is set to a high potential, the scanning lines other than the scanning line 51 are set to a high impedance state, and the address lines 71 and 72 are operated. Is set to a low potential lower than the threshold voltage of the TFT switches 214 and 414 with respect to the high potential of the scanning line 51, so that the diodes 212 and 412 are turned on and the capacitors 215 and 415 hold the voltage. This corresponds to the second voltage holding step.

  After time t07, the writing operation to the even-numbered pixel rows is sequentially performed in the same manner as the writing operation in the fourth pixel row described above. During this period, the scanning lines of the pixel rows that are not in the writing operation are set to the high impedance state. Accordingly, the gate potential of the TFT switch is not fixed even in a pixel for which writing has been completed, and thus the organic EL element does not start a light emitting operation during the writing period to the even pixel row.

  Note that the potential difference between the HIGH potential and the GND potential of the address lines 71 and 72 applied when writing to the odd-numbered rows, and the HIGH potential (Vscn) and the GND potential of the scanning lines applied when writing to the even-numbered rows. The condition is that the potential difference is larger than the threshold voltage of the TFT switch.

[Light emission operation]
Next, at time t08, the scanning line control circuit 5 sets the gate potential of the FET 514 to the HIGH state and the ON state, and sets the potential of the scanning line 51 to the LOW (GND) potential so that all the pixels emit light all at once. Similarly, the potentials of the other scanning lines are set to the LOW potential. All address lines are set to the LOW potential.

  Thereby, the source potential of the TFT switch included in the pixels of the odd pixel row and the gate potential of the TFT switch included in the pixels of the even pixel row are determined, and the TFT of the pixel having a capacitor holding a voltage higher than the threshold voltage. The switch is turned on. Therefore, in the odd-numbered pixel row, the light emission current flows through a path of the power supply line 81 → the constant current source → the organic EL element → the on-state TFT switch → the scanning line having the LOW potential. In the even-numbered pixel row, the light emission current flows through a path of the power supply line 81 → the constant current source → the organic EL element → the on-state TFT switch → the address line having the LOW potential.

  FIG. 6D is a state transition diagram illustrating the light emitting operation of the pixel according to Embodiment 1. That is, when a LOW potential is applied to the scanning line 51 and the address lines 71 and 72, as shown in FIG. 6D, the power line 81 → the constant current sources 116, 216, 316 and 416 → the organic EL elements 111, 211, The light emission current flows in the order of 311 and 411 → TFT switches 114, 214, 314 and 414 → scanning line 51 or address lines 71 and 72, and the organic EL elements 111, 211, 311 and 411 emit light all at once.

  The operations of the scanning line control circuit 5 and the data line control circuit 7 from the time t08 to the time t09 are performed by setting the scanning lines 51 and the address lines 71 and 72 to a low potential after the writing operation, so that the capacitors 115, 215, This corresponds to a light emission step in which the TFT switches 114, 214, 314, and 414 are turned on according to the voltages held at 315 and 415 to cause the organic EL elements 111, 211, 311, and 411 to emit light simultaneously.

  The reset period, the write operation, and the light emission operation period from time t01 to time t09 described above are subfield periods, and digital gradation control is performed by repeating the subfield period a plurality of times. That is, for example, the light emission period of the first subfield is 1 μs, the light emission period of the second subfield is 2 μs, the light emission period of the third subfield is 4 μs, the light emission period of the fourth subfield is 8 μs, The gradation display is performed by combining the first to ninth subfields with a light emission period of the ninth subfield of 256 μsec. Specifically, it is as follows. In the case of 0 gradation, no light is emitted in all subfields. In one gradation, light is emitted only in the first subfield (1 μsec). In the second gradation, light is emitted only in the second subfield (2 μsec). For the 3 gradations, the (first + second) subfield (1 μsec + 2 μsec = 3 μsec) is emitted. In the 4 gradations, only the third subfield (4 μs) is emitted. For the 5 gradations, the (first + third) subfield (1 μsec + 4 μsec = 5 μsec) is emitted. Six gradations cause (second + third) subfields (2 μs + 4 μs = 6 μs) to emit light. Seven gradations emit (first + second + third) subfields (1 μsec + 2 μsec + 4 μsec = 7 μsec). Eight gradations emit light only in the fourth subfield (8 μsec). In this way, 0 to 511 gradations are displayed.

  The gradation display combining the subfield periods is executed during one frame to create an image. Note that the writing order of the odd pixel rows and the even pixel rows may be reversed.

  As described above, according to the driving method of the display device of the present invention, a conventional display device in which scanning lines are arranged for each pixel row by driving pixels for two pixel rows by one scanning line. Compared to the above, the number of wires and the area required for the wires can be reduced. In addition, since the electrode resistance and the electrode stray capacitance can be reduced, loss due to wiring can be reduced. In addition, high definition is facilitated.

(Embodiment 2)
Compared with the pixel circuit of the display device according to the first embodiment, the pixel circuit of the display device according to the present embodiment uses a TFT switch without using a diode as a component of the switch unit. However, the scanning line potential is controlled exclusively between the odd-numbered pixel row and the even-numbered pixel row, and the basic operation for executing writing is the same by holding the voltage determined according to the potential of the address line and the scanning line. . Hereinafter, description of the same points as in the first embodiment will be omitted, and only different points will be described.

<Configuration of display device>
FIG. 7 is a circuit configuration diagram of a pixel portion included in the display device according to Embodiment 2 of the present invention. 7 includes four adjacent pixels 11B, 12B, 21B and 22B, address lines 91 and 92 arranged for each pixel column, and scanning lines 51 arranged for every two pixel rows. The power supply lines 81 and the erasing lines 62 are arranged in a grid pattern corresponding to each pixel.

  The pixel 11B is the first pixel of the two pixels corresponding to the intersection of the scanning line 51 and the address line 91 among the plurality of pixels, and the pixel 12B is the scanning line 51 of the plurality of pixels. And the first pixel of the two pixels corresponding to the intersection of the address line 92. The pixel 21B is a second pixel arranged in a pixel row different from the pixel row to which the pixel 11B belongs, out of the two pixels corresponding to the intersection of the scanning line 51 and the address line 91 among the plurality of pixels. The pixel 22B is a second pixel arranged in a pixel row different from the pixel row to which the pixel 12B belongs, out of two pixels corresponding to the intersection of the scanning line 51 and the address line 92 among the plurality of pixels. Pixel.

  The plurality of pixels included in the pixel portion all have the same circuit element. For example, the pixel 11B illustrated in FIG. 7 includes the organic EL element 121, TFT switches 122, 123, and 124, and the capacitor 125. And a constant current source 126.

  Here, each component of the pixels 11B to 22B and their connection relationship will be described.

  First, a connection relationship common to the pixels 11B to 22B will be described using the pixel 11B as an example.

  The anode electrode of the organic EL element 121 is connected to the source electrode of the n-type TFT switch 124, and the cathode electrode is grounded.

  The drain electrode of the TFT switch 124 is connected to the power supply line 82 via the constant current source 126, and the gate electrode is connected to the source electrode of the n-type TFT switch 123.

  The drain electrode of the TFT switch 123 is connected to the drain electrode of the p-type TFT switch 122, and the gate electrode is connected to the address line 91.

  The capacitor 125 is connected to the gate electrode and the source electrode of the TFT switch 124, and is further connected to the erase line 62 common to all pixels.

  Further, in the pixels 11B and 12B arranged in the same odd pixel row, the source electrodes of the TFT switches 122 and 322 are connected to the power supply line 82, and the gate electrodes are connected to the scanning line 51.

  On the other hand, in the pixels 21B and 22B arranged in the same even pixel row, the source electrodes of the TFT switches 222 and 422 are connected to the scanning line 51, and the gate electrodes are connected to a bias terminal having a bias potential Vb.

  Next, each component of the pixels 11B to 22B will be described.

  The organic EL elements 121 and 321 are first light emitting elements in which the anode electrode is connected to the source electrodes of the TFT switches 124 and 324 and the cathode electrode is grounded. The organic EL elements 221 and 421 are second light emitting elements in which the anode electrode is connected to the source electrodes of the TFT switches 224 and 424 and the cathode electrode is grounded.

  The TFT switches 122, 222, 322, and 422 are, for example, p-type MOSFETs, and are low active elements that conduct between the drain and the source when the gate potential with respect to the source potential is smaller than the threshold voltage.

  The TFT switches 123, 223, 323, and 423 are, for example, n-type MOSFETs, and are high active elements that conduct between the drain and the source when the gate potential with respect to the source potential is larger than the threshold voltage.

  The TFT switches 122 and 322 are third switch transistors having a gate electrode connected to the scanning line 51 and a source electrode connected to the power supply line 82 which is the first power supply line.

  The TFT switches 123 and 323 have gate electrodes connected to the address lines 91 and 92, source electrodes connected to one electrodes of capacitors 125 and 325, and drain electrodes connected to the drain electrodes of the TFT switches 122 and 322, respectively. The fourth switch transistor.

  The TFT switch 122 and the TFT switch 123 constitute a first switch unit that is turned on according to the potential of the scanning line 51. In addition, the TFT switch 322 and the TFT switch 323 constitute a first switch unit that becomes conductive according to the potential of the scanning line 51.

  The TFT switches 222 and 422 are fifth switch transistors in which the gate electrode is connected to the bias terminal having the bias potential Vb, and the source electrode is connected to the scanning line 51.

  The TFT switches 223 and 423 have a gate electrode connected to the address lines 91 and 92, a source electrode connected to one electrode of the capacitors 225 and 425, and a drain electrode connected to the drain electrodes of the TFT switches 222 and 422, respectively. The sixth switch transistor.

  The TFT switches 222 and 223 constitute a second switch portion that is in a conductive state exclusively with the first switch portion, depending on the potential of the scanning line 51. Further, the TFT switches 422 and 423 constitute a second switch unit that is in a conductive state exclusively with the first switch unit, depending on the potential of the scanning line 51.

The gate electrodes of the TFT switches 124 and 324 are connected to one electrode of the capacitors 125 and 325, the drain electrode is connected to the power source V _DD , and the source electrode is connected to the other electrode of the capacitors 125 and 325, respectively. One switch transistor.

The gate electrodes of the TFT switches 224 and 424 are connected to one electrode of the capacitors 225 and 425, the drain electrode is connected to the second power supply line V _DD , and the source electrode is connected to the other electrode of the capacitors 225 and 425. The second switch transistor.

  Capacitors 125 and 325 are charged via the TFT switches 122 and 123 and 322 and 323, and discharged via the erase line 62, corresponding to the potential (for example, 10 V) of the power supply line 82.

  The capacitors 225 and 425 charge the charge corresponding to the HIGH potential (for example, 10 V) of the scanning line 51 through the TFT switches 222 and 223 and 422 and 423, and discharge the charge through the erase line 62.

  Capacitors 125 and 325 are first capacitors that hold voltages determined according to the potentials of the address lines 91 and 92, the scanning line 51, and the power supply line 82, respectively, when the first switch unit is turned on. Capacitors 225 and 425 are second capacitors that hold voltages determined according to the potentials of the address lines 91 and 92 and the scanning line 51, respectively, when the second switch unit is in a conductive state.

  The erasing line 62 is normally set to a high impedance state, and the charge accumulated in the capacitors 125, 225, 325 and 425 is discharged by applying a LOW potential (for example, 0 V) only during the erasing operation.

Further, the power supply V _DD to which the constant current sources 126, 226, 326, and 426 are connected and the power supply line 82 may be shared.

  When the potential of the scanning line 51 is LOW potential that is sufficiently lower than the threshold voltage of the TFT switches 122 and 322 with respect to the power supply potential of the power supply line 82 due to the above connection relations and components, the TFT switches 122 and 322 that perform low active operation. Conducts from source to drain. In this state, when the potential of the address lines 91 and 92 is higher than the threshold voltage of the TFT switches 124 and 324 with respect to the ground potential, the conduction of the TFT switches 123 and 323 causes the capacitors 125 and 325 to In each case, the voltage corresponding to the power supply potential of the power supply line 82 is held.

  Further, when the potential of the scanning line 51 is a high potential sufficiently higher than the threshold voltage of the TFT switches 222 and 422 with respect to the bias potential Vb, the TFT switches 222 and 422 that perform the low active operation are conducted from the source to the drain. In this state, when the potential of the address lines 91 and 92 is higher than the threshold voltage of the TFT switches 224 and 424 with respect to the ground potential, the conduction of the TFT switches 223 and 423 causes the capacitors 225 and 425 to pass through. In each case, a voltage corresponding to the HIGH potential of the scanning line 51 is held.

  In this way, the potential of the scanning line is exclusively controlled in the odd-numbered pixel row and the even-numbered pixel row, so that the voltage writing to the even-numbered pixel row is sequentially performed after the voltage is written to the odd-numbered pixel row. Is done. After the writing is completed, the scanning line 51 and the address lines 91 and 92 are set to the LOW potential, so that the organic EL elements of the pixels in which a voltage equal to or higher than the threshold voltage of the TFT switch is held in the capacitor simultaneously emit light.

  According to the above configuration, since the scanning line for controlling the writing timing of the signal voltage only needs to be arranged every two pixel rows, the number of wirings can be reduced. Therefore, loss due to wiring can be reduced. Also, high definition can be achieved. Further, as compared with the first embodiment, since the switch portion is composed of TFTs without using a diode, the manufacturing process can be simplified.

<Operation of display device>
Hereinafter, the operation of the display device according to the present embodiment will be described with reference to FIGS. 7, 8 and 9A to 9D. FIG. 8 is a drive timing chart of the display device according to Embodiment 2 of the present invention. In FIG. 7, it is assumed that the pixels 11B and 12B in FIG. 7 are pixels belonging to the third pixel row, and the pixels 21B and 22B are pixels belonging to the fourth pixel row. The case where all light is emitted in the subfield period is illustrated.

[Reset operation]
First, at time t21 to time t22, the erasing line control circuit 6 supplies an erasing voltage to the erasing line 62 and resets capacitors included in all pixels. The erase line control circuit 6 supplies, for example, a GND potential as an erase voltage to the erase line 62. As a result, a discharge current flows from one electrode of the capacitors 125, 225, 325, and 425 holding the signal voltage to the direction of the erase line control circuit 6 via the erase line 62, and the capacitors 125, 225, 325, and 425 are discharged. Is reset.

  In this period, the data line control circuit 7 supplies a LOW potential to the address lines 91 and 92. As a result, a voltage lower than the threshold voltage is applied between the gate and source of the TFT switches 123, 223, 323, and 423, so that the drain and source are in a non-conductive state.

  FIG. 9A is a state transition diagram illustrating a reset operation of the pixel according to the second embodiment. That is, when a LOW potential is applied to the erase line 62, as shown in FIG. 9A, a discharge current flows in the order of the capacitors 125, 225, 325 and 425 → the erase line 62, and the capacitors 125, 225, 325 and 425 are passed through. The held voltage is erased.

  The operation of the erase line control circuit 6 from the time t21 to the time t22 is such that the potential of the address lines 91 and 92 is set to the TFT switch 123, the source potential of the TFT switches 123, 223, 323 and 423 before the write operation. By making the TFT switches 123, 223, 323, and 423 non-conductive by lowering the threshold voltages of 223, 323, and 423, the potential of the erase line 62 is set to a low potential that is lower than the low potential of the address lines 91 and 92. This corresponds to an erasing step of erasing the voltage held in the capacitors 125, 225, 325 and 425.

  In the period other than the reset period described above, the erase line control circuit 6 keeps the potential of the erase line 62 in a high impedance state.

[Write operation]
At time t23, the scanning line control circuit 5 turns off the gate potential of the n-type FET 514 as the LOW potential, and the gate potential of the p-type FET 513 is already the HIGH potential and is in the OFF state. Is in a high impedance state. Thus, preparation for writing a signal to the capacitor of the pixel is completed.

  Next, the write operation to the odd-numbered pixel rows is executed sequentially in the odd-numbered rows.

  For example, from time t24 to time t25, the scanning line control circuit 5 sets the gate potential of the FET 514 to the HIGH state and sets the potential of the scanning line 51 to LOW in order to execute voltage writing to the pixels belonging to the third row. (GND) potential. Thereby, the LOW potential (GND) is applied to the gate electrodes of the TFT switches 122 and 322. A power supply potential (10 V) is applied to the source electrodes of the TFT switches 122 and 322. Then, since a negative voltage whose absolute value is sufficiently larger than the threshold voltage is applied between the gate and the source of the TFT switches 122 and 322, a current can flow from the source to the drain.

  On the other hand, the data line control circuit 7 synchronizes with the above-described operation of the scanning line control circuit 5 according to the threshold voltage of the TFT switches 124 and 324 with respect to the HIGH potential corresponding to the pixels in the third row, that is, the GND potential. A higher potential is supplied to the address lines 91 and 92. Thereby, the HIGH potential is applied to the gate electrodes of the TFT switches 123 and 323. Then, since a positive voltage sufficiently larger than the threshold voltage is applied between the gates and the sources of the TFT switches 123 and 323, the drain and the source become conductive.

  Depending on the conductive state of the TFT switches 122 and 322 and the TFT switches 123 and 323, the capacitors 125 and 325 are determined according to the HIGH potential of the address lines 91 and 92, the LOW potential of the scanning line 51, and the power supply potential of the power supply line 82. The voltage is maintained. That is, the writing operation to the pixels 11B and 12B is executed.

  FIG. 9B is a state transition diagram illustrating the write operation of the odd-numbered row pixels according to the second embodiment. That is, when a LOW potential is applied to the scanning line 51 and a HIGH potential is applied to the address lines 91 and 91, as shown in FIG. 9B, the power line 82 → TFT switches 122 and 322 → TFT switches 123 and 323 → A charging current flows in the order of the capacitors 125 and 325, and the voltage is held in the capacitors 125 and 325.

  The operation of the data line control circuit 7 and the scanning line control circuit 5 from the time t24 to the time t25 is such that the potential of the scanning line 51 is lower than the threshold voltage of the TFT switches 122 and 322 with respect to the power supply potential of the power supply line 82. The scanning line is set to a low potential, the scanning lines other than the scanning line 51 are set in a high impedance state, and the potentials of the address lines 91 and 92 are set to a high potential higher than the threshold voltage of the TFT switches 124 and 324 with respect to the ground potential. This corresponds to the first voltage holding step in which the TFT switches 122, 123, 322, and 323 are turned on to hold the voltage from the power supply line 82 to the capacitors 125 and 325.

  After time t25, the writing operation to the odd-numbered pixel row is sequentially executed in the odd-numbered row, similarly to the writing operation in the third pixel row described above.

  Next, when the write operation to the odd pixel row is completed, the write operation to the even pixel row is executed.

  For example, from time t26 to time t27, the scanning line control circuit 5 sets the gate potential of the FET 513 to the LOW potential and turns on the potential of the scanning line 51 in order to execute signal voltage writing to the pixels belonging to the fourth row. A HIGH (Vscn) potential is set. Thereby, the HIGH potential (Vscn, for example, 10 V) is applied to the source electrodes of the TFT switches 222 and 422. A bias potential (for example, 5 V) is applied to the gate electrodes of the TFT switches 222 and 422. Then, since a negative voltage whose absolute value is sufficiently larger than the threshold voltage is applied between the gate and the source of the TFT switches 222 and 422, a current can flow from the source to the drain.

  On the other hand, the data line control circuit 7 synchronizes with the above-described operation of the scanning line control circuit 5 according to the threshold voltage of the TFT switches 224 and 424 with respect to the HIGH potential corresponding to the pixels in the fourth row, that is, the GND potential. A higher potential is supplied to the address lines 91 and 92. Accordingly, the HIGH potential is applied to the gate electrodes of the TFT switches 223 and 423. Then, since a positive voltage sufficiently larger than the threshold voltage is applied between the gates and the sources of the TFT switches 223 and 423, the drain and the source become conductive.

  Due to the conductive state of the TFT switches 222 and 422 and the TFT switches 223 and 423, the capacitors 225 and 425 hold a voltage determined according to the HIGH potential of the address lines 91 and 92 and the HIGH potential of the scanning line 51. That is, the writing operation to the pixels 21B and 22B is executed.

  FIG. 9C is a state transition diagram illustrating the write operation of even-numbered rows pixels according to the second embodiment. That is, when a HIGH potential is applied to the scanning line 51 and a HIGH potential is applied to the address lines 91 and 91, as shown in FIG. 9C, the scanning line 51 → TFT switches 222 and 422 → TFT switches 223 and 423 → A charging current flows in the order of the capacitors 225 and 425, and the voltage is held in the capacitors 225 and 425.

  The operation of the data line control circuit 7 and the scanning line control circuit 5 from the time t26 to the time t27 is such that the potential of the scanning line 51 is set higher than the threshold voltage of the TFT switches 222 and 422 with respect to the bias potential Vb. The scanning lines other than the scanning line 51 are set in a high impedance state, and the potentials of the address lines 91 and 92 are set higher than the threshold voltage of the TFT switches 224 and 424 with respect to the ground potential. This corresponds to a second voltage holding step in which the voltages 223, 422, and 423 are turned on to hold the voltage from the scanning line 51 to the capacitors 225 and 425.

  After time t27, the writing operation to the even-numbered pixel row is sequentially executed in the same manner as the writing operation in the fourth pixel row described above.

[Light emission operation]
Next, at time t <b> 28, the scanning line control circuit 5 sets the gate potential of the FET 514 to the HIGH state and the ON state, and sets the potential of the scanning line 51 to the LOW (GND) potential so that all the pixels emit light simultaneously. Similarly, the potentials of the other scanning lines are set to the LOW potential.

Thereby, in all the pixels, a light emission current flows through a path of power supply V _DD → constant current source → on-state TFT switch → organic EL element → ground terminal.

FIG. 9D is a state transition diagram illustrating the light emitting operation of the pixel according to Embodiment 2. That is, when the LOW potential is applied to the scanning line 51 and the address lines 91 and 92, as shown in FIG. 9D, the power source V _DD → the constant current sources 126, 226, 326 and 426 → the TFT switches 124, 224, 324 And 424 → the organic EL elements 121, 221, 321 and 421 → the ground terminal in this order, the organic EL elements 121, 221, 321 and 421 emit light all at once.

  The period of the writing operation and the light emitting operation from the time t21 to the time t29 described above is a subfield period, and the digital gradation control is executed by repeating the subfield period a plurality of times. The gradation display combining the subfield periods is executed during one frame to create an image. Note that the writing order of the odd pixel rows and the even pixel rows may be reversed.

  As described above, according to the driving method of the display device according to the present embodiment, the conventional display device in which the scanning lines are arranged for each row by driving the pixels in two rows by one scanning line. Compared to the above, the number of wires and the area required for the wires can be reduced. In addition, since the electrode resistance and the electrode stray capacitance can be reduced, loss due to wiring can be reduced. In addition, high definition is facilitated. Furthermore, as compared with the first embodiment, since the switch portion is composed of TFTs without using a diode, the manufacturing process can be simplified.

  The display device and the driving method thereof according to the present invention have been described based on the first and second embodiments. However, the display device and the driving method thereof according to the present invention are limited to the above-described first and second embodiments. is not. The present invention includes modifications obtained by making various modifications conceivable by those skilled in the art to Embodiments 1 and 2 without departing from the gist of the present invention, and various devices incorporating the display device according to the present invention. It is.

  In Embodiments 1 and 2, an organic EL element is used as a light-emitting element. However, the light-emitting element may be a current-driven light-emitting element, and may be, for example, an inorganic EL element.

  The display device and the driving method thereof according to the present invention are particularly useful for an active display that changes the luminance by a digital gradation control method, and useful for a wall-mounted television, a large monitor, and the like.

DESCRIPTION OF SYMBOLS 1 Display apparatus 2 Subfield processing circuit 3 Power supply line control circuit 5 Scan line control circuit 6 Erase line control circuit 7 Data line control circuit 10 Pixel part 11A, 11B, 12A, 12B, 21A, 21B, 22A, 22B, 900 Pixel 51 , 913 Scan line 61, 62, 915 Erase line 71, 72, 91, 92 Address line 81, 82, 916 Power supply line 111, 121, 211, 221, 311, 321, 411, 421, 904 Organic EL element 112, 113 212, 213, 312, 313, 412, 413 Diode 114, 122, 123, 124, 214, 222, 223, 224, 314, 322, 323, 324, 414, 422, 423, 424 TFT switch 115, 125, 215, 225, 315, 325, 415, 425, 905 Capacitors 116, 126, 216, 226, 316, 326, 416, 426 Constant current source 513, 514 FET
901 Data writing transistor 902 Drive transistor 903 Erase transistor 914 Data line

Claims (17)

A plurality of pixels arranged in a matrix;
A scanning line arranged every two pixel rows;
An address line arranged for each pixel column,
Of the plurality of pixels, a first pixel of two pixels corresponding to an intersection of one scanning line and one address line is:
A first switch unit that is conductive according to the potential of the scanning line;
A first capacitor that holds a voltage determined according to the potential of the address line and the scanning line when the first switch unit is turned on;
A first switch transistor for causing a light emission current to flow in accordance with a voltage held in the first capacitor;
A first light emitting element that emits light when the light emission current flows;
Of the plurality of pixels, of the two pixels corresponding to the intersection, the second pixel arranged in a pixel row different from the pixel row to which the first pixel belongs is
A second switch unit that is electrically connected to the first switch unit in accordance with the potential of the scanning line;
A second capacitor that holds a voltage determined according to the potential of the address line and the scanning line when the second switch unit is in a conductive state;
A second switch transistor for causing a light emission current to flow in accordance with the voltage held in the second capacitor;
And a second light emitting element that emits light when the light emission current flows. The first switch unit is a first diode element having an anode electrode connected to the address line and a cathode electrode connected to one electrode of the first capacitor;
The other electrode of the first capacitor is connected to the scanning line;
The gate electrode of the first switch transistor is connected to one electrode of the first capacitor, the drain electrode is connected to a power supply line, the source electrode is connected to the scanning line,
The first light emitting element is inserted in series between the power line and the drain electrode of the first switch transistor,
The second switch unit is a second diode element having an anode electrode connected to the scanning line and a cathode electrode connected to one electrode of the second capacitor;
The other electrode of the second capacitor is connected to the address line;
The gate electrode of the second switch transistor is connected to one electrode of the second capacitor, the drain electrode is connected to a power supply line, the source electrode is connected to the address line,
The display device according to claim 1, wherein the second light emitting element is inserted in series between the power line and a drain electrode of the second switch transistor. Furthermore, a drive unit for controlling the potential of the scanning line and the address line is provided,
The drive unit is
The scanning line potential is set to a low potential, scanning lines other than the scanning line are set to a high impedance state, and the address line potential is set to a high potential higher than the threshold voltage of the first switch transistor with respect to the low potential. By making the first diode conductive, the first capacitor holds the voltage,
The scanning line potential is set to a high potential, scanning lines other than the scanning line are set to a high impedance state, and the address line potential is set to a potential lower than the threshold voltage of the second switch transistor with respect to the high potential. By making a certain address line low potential, the second diode is made conductive and the second capacitor holds the voltage,
By setting the scanning line to the low potential and the address line to the address line low potential, the first switch transistor and the second switch according to the voltage held in the first capacitor and the second capacitor. The display device according to claim 2, wherein a transistor is turned on to cause the first light emitting element and the second light emitting element to emit light. further,
An erasing line for erasing the voltage held in the first capacitor and the second capacitor;
The first pixel further includes
A third diode element having an anode electrode connected to one electrode of the first capacitor and a cathode electrode connected to the erase line;
The second pixel further includes:
The display device according to claim 2, further comprising a fourth diode element having an anode electrode connected to one electrode of the second capacitor and a cathode electrode connected to the erase line. The drive unit is
When the voltage is held in the first capacitor and the second capacitor, the potential of the erase line is set to a high potential,
When erasing the voltage held in the first capacitor and the second capacitor, the potential of the erase line is set to a low potential lower than a low potential applied to the scan line and a low potential applied to the address line. It is set as an electric potential. The display apparatus of Claim 4. The first switch unit includes:
A third switch transistor having a gate electrode connected to the scan line and a source electrode connected to the first power line;
A fourth switch transistor having a gate electrode connected to the address line, a source electrode connected to one electrode of the first capacitor, and a drain electrode connected to the drain electrode of the third switch transistor;
The second switch unit is
A fifth switch transistor having a gate electrode connected to a bias terminal having a predetermined bias potential and a source electrode connected to the scan line;
A sixth switch transistor having a gate electrode connected to the address line, a source electrode connected to one electrode of the second capacitor, and a drain electrode connected to the drain electrode of the fifth switch transistor;
The gate electrode of the first switch transistor is connected to one electrode of the first capacitor, the drain electrode is connected to a second power supply line, the source electrode is connected to the other electrode of the first capacitor,
The first light emitting element has an anode electrode connected to a source electrode of the first switch transistor and a cathode electrode grounded.
A gate electrode of the second switch transistor is connected to one electrode of the second capacitor; a drain electrode is connected to the second power line; a source electrode is connected to the other electrode of the second capacitor;
The display device according to claim 1, wherein the second light emitting element has an anode electrode connected to a source electrode of the second switch transistor and a cathode electrode grounded. Furthermore, a drive unit for controlling the potential of the scanning line and the address line is provided,
The drive unit is
The scanning line potential is set to a scanning line low potential lower than the threshold voltage of the third switch transistor with respect to the power supply potential of the first power supply line, the scanning lines other than the scanning line are set to a high impedance state, and By setting the potential of the address line to a higher potential than the threshold voltage of the first switch transistor with respect to the ground potential, the third switch transistor and the fourth switch transistor are turned on, and the first switch transistor is turned on. Holding the voltage from the power line to the first capacitor;
The potential of the scanning line is set to a high potential higher than the threshold voltage of the fifth switch transistor with respect to the bias potential, the scanning lines other than the scanning line are set in a high impedance state, and the potential of the address line is grounded. By making the potential higher than the threshold voltage of the second switch transistor with respect to the potential, the fifth switch transistor and the sixth switch transistor are made conductive, and the voltage is applied from the scanning line to the second capacitor. The display device according to claim 6. further,
The erasing line for erasing the voltage hold | maintained at the said 1st capacitor | condenser and the said 2nd capacitor | condenser connected to one electrode of the said 1st capacitor | condenser and the 2nd capacitor | condenser is provided. Display device. The drive unit is
When erasing the voltage held in the first capacitor and the second capacitor, the potential of the address line is set to be higher than the threshold voltage of the fourth switch transistor with respect to the source potential of the fourth switch transistor. In a state in which the fourth switch transistor and the sixth switch transistor are made non-conductive by being lower and lower than the threshold voltage of the sixth switch transistor with respect to the source potential of the sixth switch transistor, The display device according to claim 8, wherein the potential of the erasing line is set to a low potential equal to or lower than the low potential applied to the address line. The display device according to claim 1, wherein the first light emitting element and the second light emitting element are organic EL elements. The display device according to claim 1, wherein the first light emitting element and the second light emitting element are inorganic EL elements. A driving method of a display device in which a plurality of pixels are arranged in a matrix,
Among the plurality of pixels, a first pixel arranged at an intersection of one scanning line among the scanning lines arranged every two pixel rows and one address line among the address lines arranged every pixel column is: ,
A first switch unit that is conductive according to the potential of the scanning line;
A first capacitor that holds a voltage corresponding to the potential of the address line;
A first switch transistor that becomes conductive in response to a voltage held in the first capacitor;
A first light emitting element that emits light when the first switch transistor is turned on;
Among the plurality of pixels, the second pixel arranged in a pixel row different from the pixel row to which the first pixel belongs at the intersection point,
A second switch unit that is conductive according to the potential of the scanning line;
A second capacitor for holding a voltage corresponding to the potential of the address line;
A second switch transistor that becomes conductive in response to a voltage held in the second capacitor;
A second light emitting element that emits light when the second switch transistor becomes conductive,
A first voltage holding step of setting the first switch unit to a conductive state and holding the voltage in the first capacitor by setting the potential of the scanning line to a low potential;
A second voltage holding step of setting the second switch unit in a conductive state and holding the voltage in the second capacitor by setting the potential of the scanning line to a high potential;
After the first voltage holding step and the second voltage holding step, the scanning line and the address line are set to a low potential, so that the first voltage and the second capacitor are set according to the voltage held in the first capacitor and the second capacitor. A light-emitting step of bringing the first light-emitting element and the second light-emitting element into simultaneous light emission by bringing the first switch transistor and the second switch transistor into a conductive state. The first switch unit is a first diode element having an anode electrode connected to the address line and a cathode electrode connected to one electrode of the first capacitor;
The other electrode of the first capacitor is connected to the scanning line;
The gate electrode of the first switch transistor is connected to one electrode of the first capacitor, the drain electrode is connected to a power supply line, the source electrode is connected to the scanning line,
The first light emitting element is inserted in series between the power line and the drain electrode of the first switch transistor, or between the drain electrode of the first switch transistor and the scanning line.
The second switch unit is a second diode element having an anode electrode connected to the scanning line and a cathode electrode connected to one electrode of the second capacitor;
The other electrode of the second capacitor is connected to the address line;
The gate electrode of the second switch transistor is connected to one electrode of the second capacitor, the drain electrode is connected to a power supply line, the source electrode is connected to the address line,
The second light emitting element is inserted in series between the power line and the drain electrode of the second switch transistor, or between the drain electrode of the second switch transistor and the address line,
In the first voltage holding step, the potential of the scanning line is set to a low potential, the scanning lines other than the scanning line are set to a high impedance state, and the potential of the address line is set to be lower than that of the first switch transistor. By setting the potential higher than the threshold voltage, the first diode is turned on to hold the voltage in the first capacitor,
In the second voltage holding step, a potential of the scanning line is set to a high potential, a scanning line other than the scanning line is set to a high impedance state, and the potential of the address line is set to be higher than the potential of the second switch transistor. The method for driving a display device according to claim 12, wherein the second diode is made conductive by setting the potential lower than a threshold voltage, and the second capacitor holds the voltage. further,
An erasing line for erasing the voltage held in the first capacitor and the second capacitor;
The first pixel further includes
A third diode element having an anode electrode connected to one electrode of the first capacitor and a cathode electrode connected to the erase line;
The second pixel further includes:
A fourth diode element having an anode electrode connected to one electrode of the second capacitor and a cathode electrode connected to the erase line;
Further, before the first voltage holding step and the second voltage holding step, the potential of the erase line is set to a low potential applied to the scanning line and a low potential equal to or lower than a low potential applied to the address line. The display device driving method according to claim 13, further comprising: an erasing step of erasing the voltage held in the first capacitor and the second capacitor. The first switch unit includes:
A third switch transistor having a gate electrode connected to the scan line and a source electrode connected to the first power line;
A fourth switch transistor having a gate electrode connected to the address line, a source electrode connected to one electrode of the first capacitor, and a drain electrode connected to the drain electrode of the third switch transistor;
The second switch unit is
A fifth switch transistor having a gate electrode connected to a bias terminal having a predetermined bias potential and a source electrode connected to the scan line;
A sixth switch transistor having a gate electrode connected to the address line, a source electrode connected to one electrode of the second capacitor, and a drain electrode connected to the drain electrode of the fifth switch transistor;
The gate electrode of the first switch transistor is connected to one electrode of the first capacitor, the drain electrode is connected to a second power supply line, the source electrode is connected to the other electrode of the first capacitor,
The first light emitting element has an anode electrode connected to a source electrode of the first switch transistor and a cathode electrode grounded.
A gate electrode of the second switch transistor is connected to one electrode of the second capacitor; a drain electrode is connected to the second power line; a source electrode is connected to the other electrode of the second capacitor;
The second light emitting element has an anode electrode connected to a source electrode of the second switch transistor and a cathode electrode grounded,
In the first voltage holding step, the scanning line potential is set to a scanning line low potential lower than the threshold voltage of the third switch transistor with respect to the power supply potential of the first power supply line, and scanning other than the scanning line is performed. The line is set to a high impedance state, and the potential of the address line is set to a high potential higher than the threshold voltage of the first switch transistor with respect to the ground potential, so that the third switch transistor and the fourth switch transistor are In a conducting state, the voltage is held from the first power line to the first capacitor,
In the second voltage holding step, the potential of the scanning line is set to a high potential higher than a threshold voltage of the fifth switch transistor with respect to the bias potential, and the scanning lines other than the scanning line are set to a high impedance state, By making the potential of the address line higher than the threshold voltage of the second switch transistor with respect to the ground potential, the fifth switch transistor and the sixth switch transistor are made conductive, and the scanning line The display device driving method according to claim 12, wherein the second capacitor holds the voltage. further,
An erasing line connected to one electrode of the first capacitor and one electrode of the second capacitor, for erasing the voltage held in the first capacitor and the second capacitor;
Further, before the first voltage holding step and the second voltage holding step, the potential of the address line is lower than the threshold voltage of the fourth switch transistor with respect to the source potential of the fourth switch transistor, and The potential of the erase line in a state in which the fourth switch transistor and the sixth switch transistor are made non-conductive by lowering the source voltage of the sixth switch transistor below the threshold voltage of the sixth switch transistor. The display device driving method according to claim 15, further comprising: an erasing step of erasing a voltage held in the first capacitor and the second capacitor by setting the scanning line to a low potential. The display device driving method according to claim 16, wherein in the first voltage holding step, the second voltage holding step, and the light emission step, the potential of the erasing line is set to a high impedance state.

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