JP2013041921A - Vacuum sealing device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a vacuum sealing device which reduces the influences of heat generation of an IC chip which acts on a device chip.SOLUTION: A vacuum sealing device includes: a device chip 100A; an IC chip 200A cooperating with the device chip 100A; and a package 300 where the device chip 100A and the IC chip 200A are housed being spaced apart from each other in the thickness direction of these chips. In the package 300, double-tiered recessed parts 301a, 301b are provided at one surface side of a package body 301. The IC chip 200A is joined to an inner bottom surface of the lower tier recessed part 301a through a second joining part 312, and the device chip 100A is hermetically joined to an entire periphery in a peripheral part of the lower tier recessed part 301a on an inner bottom surface of the upper tier recessed part 301b through a third joining part 313. In the vacuum sealing device, a first hermetic space 321, which is enclosed by the package body 301, the device chip 100A, the third joining part 313, and a package lid 302, has a vacuum atmosphere.

Description

  The present invention relates to a vacuum sealing device.

  Conventionally, an infrared sensor is known as one of vacuum-sealed devices (for example, Patent Document 1). Further, as a vacuum sealing device, a gyro sensor, a MEMS optical scanner, and the like are also known.

  Patent Document 1 describes an infrared sensor device 430 configured as shown in FIG. In this infrared sensor device 430, an infrared array sensor 410 and a signal processing chip 437 cooperating with the infrared array sensor 410 are accommodated on the inner bottom surface 431 a side of the recess of the package 431. Further, the infrared sensor device 430 is hermetically sealed in a vacuum atmosphere by a lid 433 including a convex lens-shaped infrared transmitting member 434 inside the concave portion of the package 431 on which the infrared array sensor 410 and the signal processing chip 437 are mounted. It has stopped. Here, the lid 433 has an opening 433a serving as a window with respect to the infrared array sensor 410, and the infrared transmitting member 434 is hermetically bonded so as to seal the opening 433a.

  In the infrared array sensor 410, m × n thermal infrared detectors are arranged in a two-dimensional array on one surface side of the silicon substrate 401. Here, the thermal infrared detection unit includes a thermopile. The infrared array sensor 410 has a cavity 405 formed from the other surface side of the silicon substrate 401.

JP 2010-243365 A

  Incidentally, in the infrared sensor device 430 described above, the infrared array sensor 410 and the signal processing chip 437 are mounted side by side on the inner bottom surface 431a side of the recess of the package 431. For this reason, in the infrared sensor device 430, compared to the case where only the infrared array sensor 410 is housed in the package 431, the area of the joint for hermetically sealing becomes larger, and the possibility of occurrence of leakage increases. Further, in the infrared sensor device 430, the output signal (output voltage) of each thermal infrared detection unit of the infrared array sensor 410 includes an offset voltage due to heat generation of the signal processing chip 437. In this infrared sensor device 430, the temperature of the thermal infrared detector varies due to the distance from the signal processing chip 437 in the infrared array sensor 410, and the S / N ratio is within the plane of the infrared array sensor 410. There were occasional variations. Note that the heat transferred from the signal processing chip 437 to the silicon substrate 401 of the infrared array sensor 410 through a path passing through the package 431 mainly increases the temperature of the cold junction of the thermopile, which causes a negative offset voltage. .

  Further, in the above-described infrared sensor device 430, there is a concern that the degree of vacuum is lowered by the gas released from the signal processing chip 437 when the signal processing chip 437 generates heat, and the device characteristics of the infrared array sensor 410 are deteriorated. is there.

  The present invention has been made in view of the above reasons, and an object of the present invention is to provide a vacuum sealed device capable of reducing the influence of heat generated by an IC chip on a device chip.

  The vacuum sealing device of the present invention includes a device chip that is required to be used in a vacuum, an IC chip that cooperates with the device chip, and the device chip and the IC chip that are separated from each other in the thickness direction. A package housed, the package having a package body and a package lid hermetically joined to the package body via a first joint, and having two stages on one surface side of the package body. A recess is provided, and the IC chip is bonded to the inner bottom surface of the lower recess through a second bonding portion, and the device chip is attached to the entire periphery of the lower recess on the inner bottom of the upper recess. A first hermetic space is formed that is hermetically joined via a third joint portion around the circumference, and is surrounded by the package body, the device chip, the third joint portion, and the package lid. Characterized in that it is empty atmosphere.

  In this vacuum sealing device, it is preferable that the third bonding portion is formed of an inorganic bonding material.

  In this vacuum sealing device, it is preferable that the second airtight space surrounded by the package body, the device chip, and the third bonding portion is a vacuum atmosphere.

  In this vacuum sealing device, it is preferable that the device chip is an electromagnetic wave sensor chip, and the package lid is formed of a material that transmits an electromagnetic wave to be detected by the electromagnetic wave sensor chip.

  In this vacuum sealing device, the electromagnetic wave to be detected is infrared, and the electromagnetic wave sensor chip has a plurality of thermal infrared detectors arranged in an array on one surface side of the semiconductor substrate, It is preferable that the infrared sensor chip has a hollow portion formed directly below a part of the thermal infrared detecting portion on the surface side.

  In the vacuum sealing device of the present invention, it is possible to reduce the influence of heat generated by the IC chip on the device chip.

It is a schematic sectional drawing of the vacuum sealing device of embodiment. It is a plane layout figure of the infrared sensor chip in an embodiment. It is an equivalent circuit diagram of the infrared sensor chip in the embodiment. It is a principal part equivalent circuit diagram of the infrared sensor chip in an embodiment. It is a plane layout figure of the pixel part of the infrared sensor chip in an embodiment. It is a schematic plane layout figure of the pixel part of the infrared sensor chip in an embodiment. The principal part of the pixel part of the infrared sensor chip | tip in embodiment is shown, (a) is a plane layout figure, (b) is a schematic sectional drawing corresponding to the D-D 'cross section of (a). The principal part of the pixel part of the infrared sensor chip | tip in embodiment is shown, (a) is a plane layout figure, (b) is a schematic sectional drawing corresponding to the D-D 'cross section of (a). It is a plane layout figure of the principal part of the pixel part of the infrared sensor chip in an embodiment. It is a plane layout figure of the principal part of the pixel part of the infrared sensor chip in an embodiment. The principal part of the pixel part of the infrared sensor chip | tip in embodiment is shown, (a) is a plane layout figure, (b) is a schematic sectional drawing corresponding to the D-D 'cross section of (a). The principal part containing the cold junction of the infrared sensor chip | tip in embodiment is shown, (a) is a plane layout figure, (b) is a schematic sectional drawing. The principal part containing the hot junction of the infrared sensor chip | tip in embodiment is shown, (a) is a plane layout figure, (b) is a schematic sectional drawing. It is a schematic sectional drawing of the principal part of the pixel part of the infrared sensor chip in embodiment. It is a schematic sectional drawing of another principal part of the pixel part of the infrared sensor chip in an embodiment. It is principal part explanatory drawing of the infrared sensor chip in embodiment. Regarding the infrared sensor chip in the embodiment, (a) is a plan layout view of the main part, (b) is an enlarged view of the Zener diode of (a), and (c) is a schematic sectional view of the Zener diode. It is a principal part schematic sectional drawing of the other structural example of the infrared sensor chip | tip in embodiment. It is a principal part schematic sectional drawing of the other structural example of the infrared sensor chip | tip in embodiment. It is a principal part schematic sectional drawing of another structural example of the infrared sensor chip | tip in embodiment. It is a schematic sectional drawing of the infrared sensor apparatus which shows a prior art example.

  Below, the vacuum sealing device of this embodiment is demonstrated based on FIG.

  The vacuum sealing device stores a device chip 100A that is required to be used in a vacuum, an IC chip 200A that cooperates with the device chip 100A, and the device chip 100A and the IC chip 200A that are separated from each other in the thickness direction. Package 300 is provided.

  The package 300 includes a package main body 301 and a package lid 302 that is airtightly bonded to the package main body 301 via the first bonding portion 311. Here, the package 300 is provided with two-level recesses 301 a and 301 b on one surface side of the package main body 301. In the package 300, the IC chip 200 </ b> A is bonded to the inner bottom surface of the lower recess 301 a via the second bonding portion 312. In the package 300, the device chip 100 </ b> A is airtightly bonded through the third bonding portion 313 over the entire periphery of the lower recess 301 a on the inner bottom surface of the upper recess 301 b. In the vacuum sealing device, the first hermetic space 321 surrounded by the package main body 301, the device chip 100A, the third bonding portion 313, and the package lid 302 is in a vacuum atmosphere.

  Thus, in the vacuum sealing device of the present embodiment, it is possible to reduce the influence of the heat generated by the IC chip 200A on the device chip 100A. The influence of the heat generated by the IC chip 200A on the device chip 100A includes the influence that the decrease in the degree of vacuum due to the gas released from the IC chip 200A when the IC chip 200A generates heat affects the device characteristics of the device chip 100A, The influence of the temperature rise of the device chip 100A due to heat generation on the device characteristics can be considered. Further, in the vacuum sealed device of the present embodiment, the device chip 100A and the IC chip 200A are stored in the package 300 so as to be spaced apart from each other in the thickness direction, so that the device chip 100A and the IC chip 200A are stored side by side. Compared with the case where it is made, the area of the 1st junction part 311 which joins the package main body 301 and the package lid | cover 302 can be made small, and possibility that a leak will generate | occur | produce in the 1st junction part 311 is reduced. Is possible.

  In this vacuum sealing device, a pad (not shown) of the device chip 100A is electrically connected to a wiring (not shown) provided on the package body 301 via a wire 381. Further, the pad (not shown) of the IC chip 200A is electrically connected to the wiring (not shown) provided in the package body 301 via the second bonding portion 312, but not limited to this. It is also possible to make an electrical connection via a wire. However, the former is advantageous in that the package 300 is reduced in size, and heat generated in a circuit portion (not shown) on the main surface side of the IC chip 200A is less likely to be transmitted to the device chip 100A. Is advantageous.

  In this vacuum sealing device, it is preferable that the third bonding portion 313 is formed of an inorganic bonding material (for example, a metal bonding material such as glass, AuSn, or Au). Thereby, the vacuum sealing device can reduce the gas generated from the third bonding portion 313 as compared with the case where the third bonding portion 313 is formed of an organic bonding material (for example, an epoxy resin). In addition, the airtightness of the first airtight space 321 can be improved. Moreover, it is preferable that the 1st junction part 311 is formed with the inorganic type joining material. Thereby, the vacuum sealing device can reduce the gas generated from the first bonding portion 311 as compared with the case where the first bonding portion 311 is formed of an organic bonding material. It becomes possible to improve the airtightness of the 1 airtight space 321. Moreover, it is preferable that the 2nd junction part 312 is formed with the inorganic type joining material, and when the above 2nd junction parts 312 also serve as an electrical connection, if a metal type joining material is employ | adopted. Good. Thereby, the vacuum sealing device can reduce the gas released into the second hermetic space 322 as compared with the case where the second bonding portion 312 is formed of an organic bonding material.

  In this vacuum sealing device, it is preferable that the second hermetic space 322 surrounded by the package main body 301, the device chip 100A, and the third bonding portion 313 is in a vacuum atmosphere. Thereby, in the vacuum sealing device, since the IC chip 200A is in a vacuum atmosphere, the heat generated in the IC chip 200A is not easily transmitted to the device chip 100A, and the first airtight space 321 and the second airtight space 322 It is possible to prevent the airtightness of the third joint portion 313 from being lowered or the device characteristics of the device chip 100A from fluctuating due to the pressure difference. It is preferable that the vacuum degree of the 1st airtight space 321 and the vacuum degree of the 2nd airtight space 322 are substantially the same as a vacuum sealing device.

  In this vacuum sealed device, it is preferable that the device chip 100A is, for example, an electromagnetic wave sensor chip, and the package lid 302 is formed of a material that transmits an electromagnetic wave to be detected by the electromagnetic wave sensor chip.

  In this vacuum sealing device, the electromagnetic wave to be detected is infrared, and the electromagnetic wave sensor chip includes a plurality of thermal infrared detectors 3 (see FIG. 7, FIG. 8, etc.) as described below. 8) (see FIG. 8, etc.) are arranged in an array on the one surface side, and on the one surface side of the semiconductor substrate 1, a cavity 11 (see FIG. 7, FIG. 8, etc.) is provided directly below a part of the thermal infrared detector 3. It is preferable that the infrared sensor chip 100 is formed. The vacuum sealing device in this case is an infrared sensor. When the vacuum sealing device is an infrared sensor, the material of the package lid 302 is preferably, for example, silicon or germanium. By adopting silicon, the cost can be reduced compared to the case where germanium is employed. Is possible. The IC chip 200A preferably has a function of processing the output signal of the infrared sensor chip 100.

  The electromagnetic wave sensor chip is not limited to the infrared sensor chip 100, and may be, for example, a photodiode chip or a terahertz wave sensor chip.

  The device chip 100A is not particularly limited as long as it is required to be used in a vacuum, and is not limited to an electromagnetic wave sensor chip. For example, a gyro sensor chip or a MEMS optical scanner chip (MEMS mirror chip) is used. Etc. Moreover, what is necessary is just to set suitably about the function of IC chip 200A which cooperates with device chip 100A with the function of device chip 100A. For example, when the device chip 100A is an electromagnetic wave sensor chip, the IC chip 200A preferably has a function of performing signal processing on the output signal of the electromagnetic wave sensor chip. Further, when the device chip 100A is a gyro sensor chip, it is preferable that the IC chip 200A has a function of driving the gyro sensor chip and a function of processing an output signal of the gyro sensor chip. When the device chip 100A is a MEMS optical scanner chip, it is preferable that the IC chip 200A has a function of driving at least the MEMS optical scanner chip.

  Further, in the vacuum sealing device, it is preferable that a getter is accommodated in the first hermetic space 322 of the package 300. As the getter, a non-evaporable getter is preferable.

  In the vacuum sealing device, an electronic device chip other than the device chip 100A and the IC chip 200A may be housed in the package 300.

  The package 300 has a plurality of external connection electrodes (not shown) that are appropriately connected to the device chip 100A and the IC chip 200A. Each external connection electrode is preferably provided on the other surface of the package main body 301, and is preferably provided across the other surface and the side surface of the package main body 301. As a result, the vacuum sealing device can be used by being mounted on the surface of a substrate such as a printed circuit board, and it is possible to improve the bonding reliability by forming a solder fillet.

  Below, each component of the infrared sensor which is an example of a vacuum sealing device is demonstrated in detail.

  Here, first, the infrared sensor chip 100 will be described with reference to FIGS.

  As shown in FIG. 2, the infrared sensor chip 100 includes i × j (8 × 8 in the illustrated example) pixel units 2, i rows and j columns (in the illustrated example, in the illustrated example). They are arranged in a two-dimensional array of 8 rows and 8 columns. In the illustrated example, i = 8 and j = 8, but i ≧ 2 and j ≧ 2 may be satisfied.

  As shown in FIGS. 3 to 8, the pixel unit 2 includes a temperature sensing unit 30 that is a thermoelectric conversion unit that converts thermal energy from infrared rays into electrical energy, and a MOS transistor 4 for extracting the output voltage of the temperature sensing unit 30. It has.

  As shown in FIGS. 7, 8 and 15, the MOS transistor 4 described above has a second conductivity type source region in the first conductivity type well region 41 formed on the one surface side of the semiconductor substrate 1. 44 and the drain region 43 of the second conductivity type are formed apart from each other. In the present embodiment, the well region 41 constitutes a channel formation region. FIG. 3 shows an equivalent circuit diagram of the infrared sensor chip 100 when the first conductivity type is p-type, the second conductivity type is n-type, and the MOS transistor 4 is an n-channel MOS transistor. In the equivalent circuit diagram of FIG. 3, the temperature sensing unit 30 is represented by a resistance symbol.

  As can be seen from FIGS. 3, 5, and 7, in the infrared sensor chip 100, one end of the temperature sensing unit 30 of the j (eight) pixel units 2 in each column is the source region 44 -drain region of the MOS transistor 4. J first wirings 101 are commonly connected to each column via 43.

  In addition, the infrared sensor chip 100 includes i (eight) second wirings 102 in which the gate electrodes 46 of the MOS transistors 4 corresponding to the temperature sensing units 30 in each row are commonly connected for each row. In addition, the infrared sensor chip 100 has j third wirings 103 in which the well regions 41 of the MOS transistors 4 in each row are commonly connected for each column, and the other ends of the i temperature sensing units 30 in each column. And j fourth wirings 104 commonly connected to each column.

  In addition, the infrared sensor chip 100 is used for selecting a pixel unit in which the j first pads Vout1 to Vout8 for output to which the first wiring 101 is connected individually and the second wiring 102 are connected to each other. i second pads Vsel1 to Vsel8 are provided. Further, the infrared sensor chip 100 includes a third pad Vch to which each third wiring 103 is connected in common, and a reference bias fourth pad Vrefin to which the fourth wiring 104 is connected in common. . Therefore, the infrared sensor chip 100 can read the outputs of all the temperature sensing units 30 in time series. In the infrared sensor, the IC chip 200A controls the potential of the second pads Vsel1 to Vsel8 for selecting each pixel unit 2 so that the MOS transistors 4 are sequentially turned on by the IC chip 200A. The output voltage of each pixel unit 2 can be read sequentially. If it is not necessary to distinguish between the pads Vout1 to Vout8, Vsel1 to Vsel8, Vch, and Vrefin, the pads Vout1 to Vout8, Vsel1 to Vsel8, Vch, and Vrefin are all referred to as pads 80 for convenience of explanation. explain.

  Here, the potential of the first pads Vout1 to Vout8 is Vout, the potential of the second pads Vsel1 to Vsel8 is Vs, the potential of the third pad Vch is Vwell, and the potential of the fourth pad Vrefin is Vref. The output voltage of the temperature sensing unit 30 is Vo, and a first parasitic diode composed of a well region 41 and a source region 44, which are channel forming regions, and a second parasitic diode composed of a well region 41 and a drain region 43. Let Vth be the threshold voltage of the parasitic diode.

When the MOS transistor 4 is an nMOS transistor, the IC chip 200A sets the potential Vs of the second pads Vsel1 to Vsel8 when the i number of MOS transistors 4 connected to the second wiring 102 are turned on to Von. To do. Further, the IC chip 200A sets the potential Vs of the second pads Vsel1 to Vsel8 to Voff when the i MOS transistors 4 connected to the second wiring 102 are turned off. When the potential Vs of the second pads Vsel1 to Vsel8 is set to Von, the IC chip 200A
−Vth <{Vwell− (Vref + Vo)} <Vth
It is preferable to control the infrared sensor chip 100 under the conditions of Vref and Vwell set so as to satisfy the relationship.

Further, in the IC chip 200A, when the MOS transistor 4 is a pMOS transistor,
−Vth <{(Vref + Vo) −Vwell} <Vth
It is preferable to control the infrared sensor chip 100 under the conditions of Vref and Vwell set so as to satisfy the relationship.

  In the present embodiment, a silicon substrate of the second conductivity type is used as the semiconductor substrate 1, and the reverse breakdown voltage of the first parasitic diode and the second parasitic diode is about −10V, while Vth is It becomes about 0.6V to 0.7V. Therefore, in the infrared sensor, the IC chip 200A has, for example, i pieces of potential Vref of the fourth pad Vref 1.2V, potential Vwell of the third pad Vch 1.2V, and connected to the second wiring 102. When Von, which is the potential Vs of the second pads Vsel1 to Vsel8 when the MOS transistor 4 is turned on, is set to 5 V, the MOS transistor 4 is turned on and the output of the pixel unit 2 is output from the first pads Vout1 to Vout8. The voltage (Vref + Vo) can be read out. In addition, the infrared sensor has the MOS transistor 4 provided that Voff, which is the potential Vs of the second pads Vsel1 to Vsel8 when the i number of MOS transistors 4 connected to the second wiring 102 are turned off, is 0V. Is turned off, and the output voltage of the pixel portion 2 is not read from the first pads Vout1 to Vout8.

  Further, the infrared sensor chip 100 has a plurality of Zener diodes ZD (see FIGS. 3, 4 and 17) in order to prevent an overvoltage from being applied between the gate electrode 46 and the source electrode 48 of each MOS transistor 4. It has. Each Zener diode ZD has a cathode connected to each second wiring 102. As shown in FIG. 17, the zener diode ZD has a second conductivity type second diffusion region 82 formed in the first conductivity type first diffusion region 81 formed on the one surface side of the semiconductor substrate 1. Is. The infrared sensor chip 100 includes a fifth pad Vzd to which the first diffusion regions 81 of the Zener diodes ZD are commonly connected. Here, when the potential of the fifth pad Vzd is Vhogo, the IC chip 200A preferably makes Vhogo and Vwell different. In the IC chip 200A, for example, as described above, when the potential Vwell of the third pad Vch is set to 1.2V, the potential Vhogo of the fifth pad Vzd is preferably set to 0V.

  Further, the infrared sensor chip 100 includes a sixth pad Vsu for substrate bias to which the semiconductor substrate 1 is connected. Here, when the potential of the sixth pad Vsu is Vsub, the IC chip 200A preferably has Vwell = Vsub. That is, in the IC chip 200A, for example, as described above, when the potential Vwell of the third pad Vch is set to 1.2V, the potential Vsub of the sixth pad Vsu is preferably set to 1.2V. In the equivalent circuit diagram of FIG. 4, a third parasitic diode D3 composed of the well region 41 and the semiconductor substrate 1 and a fourth parasitic diode D4 composed of the first diffusion region 81 and the semiconductor substrate 1 are shown. Is also described. Further, since the fifth pad Vzd and the sixth pad Vsu also constitute the pad 80 in FIG. 2, both are described as the pad 80 when it is not necessary to distinguish them for convenience of explanation. .

  The infrared sensor chip 100 includes a plurality of (i × j) pixel units 2 each including the thermal infrared detection unit 3 in which the temperature sensing unit 30 is embedded and the MOS transistor 4 on the one surface side of the semiconductor substrate 1. They are arranged in a dimensional array. Here, the one surface of the semiconductor substrate 1 is a Si (100) plane. The temperature sensing unit 30 is configured by connecting a plurality of (here, six) thermopiles 30a (see FIG. 5) in series.

  The thermal infrared detector 3 of each pixel unit 2 is formed in the region A1 for forming the thermal infrared detector 3 on the one surface side of the semiconductor substrate 1 (see FIGS. 7 and 8). Further, the MOS transistor 4 of each pixel portion 2 is formed in the formation region A2 of the MOS transistor 4 (see FIGS. 7 and 8) on the one surface side of the semiconductor substrate 1.

  As shown in FIGS. 5 to 8, the infrared sensor chip 100 has a cavity 11 formed immediately below a part of the thermal infrared detector 3 on the one surface side of the semiconductor substrate 1. The thermal infrared detector 3 includes a support 3d formed on the periphery of the cavity 11 on the one surface side of the semiconductor substrate 1, and a first cover that covers the cavity 11 in plan view on the one surface side of the semiconductor substrate 1. 1 thin film structure portion 3a. The first thin film structure portion 3a includes an infrared absorbing portion 33 that absorbs infrared rays. Here, the first thin film structure portion 3a includes a plurality of second thin film structure portions 3aa arranged in parallel along the circumferential direction of the cavity portion 11 and supported by the support portion 3d, and adjacent second thin film structure portions. It has the connection piece 3c (refer FIG. 5) which connects 3aa mutually. In the thermal infrared detector 3 in FIG. 5, the first thin film structure 3a is separated into six second thin film structures 3aa by providing a plurality of linear slits 13. Below, each part divided | segmented corresponding to each 2nd thin film structure part 3aa among the infrared absorption parts 33 (it calls 1st infrared absorption part 33) is called 2nd infrared absorption part 33a.

  The thermal infrared detector 3 is provided with a thermopile 30a for each second thin film structure 3aa. Here, in the thermopile 30a, the hot junction T1 is provided in the second thin film structure portion 3aa, and the cold junction T2 is provided in the support portion 3d. In short, the hot junction T1 is formed in a region overlapping the cavity 11 in the thermal infrared detector 3, and the cold junction T2 is formed in a region not overlapping the cavity 11 in the thermal infrared detector 3.

  In addition, the temperature sensing unit 30 of the thermal infrared detection unit 3 has a connection relationship in which the output change with respect to the temperature change is larger than when the output is taken out for each thermopile 30a, and all the thermopile 30a are electrically connected. Yes. The temperature sensing unit 30 in FIG. 5 has six thermopiles 30a connected in series. However, the connection relationship described above is not limited to the connection relationship in which all of the plurality of thermopiles 30a are connected in series. For example, if the infrared sensor chip 100 is a temperature sensing unit 30 in which a series circuit of three thermopiles 30a is connected in parallel, the case where six thermopiles 30a are connected in parallel, or an output for each thermopile 30a is provided. The sensitivity can be increased compared to the case of taking out. Moreover, the infrared sensor chip 100 can reduce the electrical resistance of the temperature sensing unit 30 and reduce thermal noise compared to the temperature sensing unit 30 when all six thermopiles 30a are connected in series. Therefore, the S / N ratio is improved.

  In the thermal infrared detector 3, for each second thin film structure portion 3 aa, two planar strip-like bridge portions 3 bb and 3 bb connecting the support portion 3 d and the second infrared absorber 33 a are formed in the cavity portion 11. They are formed spaced apart in the circumferential direction. As a result, the infrared sensor chip 100 is formed with a U-shaped slit 14 in plan view that spatially separates the two bridge portions 3bb and 3bb and the second infrared absorbing portion 33a and communicates with the cavity portion 11. . The support part 3d which is a site | part surrounding the 1st thin film structure part 3a in planar view among the thermal-type infrared detection parts 3 has a rectangular frame shape. Note that the bridge portion 3bb has a space other than the second infrared absorption portion 33a and the support portion 3d, and the space between the second infrared absorption portion 33a and the support portion 3d. Separated. Here, in the second thin film structure portion 3aa, the dimension in the extending direction from the support part 3d is 93 μm, the dimension in the width direction orthogonal to the extending direction is 75 μm, the width dimension of each bridge portion 3bb is 23 μm, and each slit Although the widths 13 and 14 are set to 5 μm, these values are merely examples and are not particularly limited.

  The first thin film structure portion 3a is formed on the thermal oxide film 1b formed on the one surface side of the semiconductor substrate 1, the silicon nitride film 32 formed on the thermal oxide film 1b, and the silicon nitride film 32. A laminated structure of the temperature sensitive portion 30, the interlayer insulating film 50 formed so as to cover the temperature sensitive portion 30 on the surface side of the silicon nitride film 32, and the passivation film 60 formed on the interlayer insulating film 50. It is formed by patterning. The interlayer insulating film 50 is composed of a BPSG film. The passivation film 60 is composed of a laminated film of a PSG film and an NSG film formed on the PSG film, but is not limited thereto, and may be composed of, for example, a silicon nitride film.

  In the thermal infrared detector 3 described above, portions of the silicon nitride film 32 other than the bridge portions 3bb and 3bb of the first thin film structure portion 3a constitute the first infrared absorber 33. The support portion 3d is composed of a thermal oxide film 1b, a silicon nitride film 32, an interlayer insulating film 50, and a passivation film 60.

Further, in the infrared sensor chip 100, the laminated film of the interlayer insulating film 50 and the passivation film 60 is formed on the one surface side of the semiconductor substrate 1 for forming the formation region A 1 of the thermal infrared detector 3 and the MOS transistor 4. It is formed across the area A2. In the infrared sensor chip 100, the portion formed in the formation region A1 of the thermal infrared detector 3 is the infrared absorbing film 70 (see FIGS. 7B and 8B). Also serves as. Here, when the refractive index of the infrared absorption film 70 is n ₂ and the center wavelength of the infrared ray to be detected is λ, the thickness t2 of the infrared absorption film 70 is set to λ / 4n _2. The absorption efficiency of infrared rays of the target wavelength (for example, 8 to 12 μm) can be increased, and high sensitivity can be achieved. For example, when n ₂ = 1.4 and λ = 10 μm, t2≈1.8 μm may be set. In the present embodiment, the interlayer insulating film 50 has a thickness of 0.8 μm, the passivation film 60 has a thickness of 1 μm (the PSG film has a thickness of 0.5 μm, and the NSG film has a thickness of 0.5 μm). .

  In each pixel unit 2, the inner peripheral shape of the cavity 11 is rectangular. As shown in FIGS. 5 and 11A, the connecting piece 3c in each pixel portion 2 is formed in an X shape in plan view, and in an oblique direction intersecting with the extending direction of the second thin film structure portion 3aa. The adjacent second thin film structure portions 3aa, 3aa, the second thin film structure portions 3aa, 3aa adjacent to each other in the extending direction of the second thin film structure portion 3aa, and the extending direction of the second thin film structure portion 3aa are orthogonal to each other. The second thin film structures 3aa and 3aa adjacent in the direction are connected to each other.

  The thermopile 30a has a second end portion of the n-type polysilicon layer 34 and the p-type polysilicon layer 35 formed on the silicon nitride film 32 across the second thin film structure portion 3aa and the support portion 3d. A plurality of (9 in the example shown in FIG. 5) thermocouples electrically connected by the connecting portion 36 on the infrared incident surface side of the infrared absorbing portion 33a are provided. The connecting portion 36 is made of a metal material (for example, Al—Si). In the thermopile 30a, the other end portion of the n-type polysilicon layer 34 of the thermocouple adjacent to each other on the one surface side of the semiconductor substrate 1 and the other end portion of the p-type polysilicon layer 35 are joined by the connection portion 37. Electrically connected. The connection portion 37 is formed of a metal material (for example, Al—Si). In the thermopile 30a, the one end portion of the n-type polysilicon layer 34, the one end portion of the p-type polysilicon layer 35, and the connection portion 36 constitute a hot junction T1. In the thermopile 30a, the other end portion of the n-type polysilicon layer 34, the other end portion of the p-type polysilicon layer 35, and the connection portion 37 constitute a cold junction T2. Note that the infrared sensor chip 100 includes silicon nitride on the n-type polysilicon layer 34 and the p-type polysilicon layer 35 formed on the bridge portions 3bb and 3bb and on the one surface side of the semiconductor substrate 1. Infrared rays can also be absorbed at a site formed on the film 32.

  Further, in the infrared sensor chip 100, the shape of the cavity 11 is a quadrangular pyramid, and the depth of the central portion in plan view is larger than that of the peripheral portion. The planar layout of the thermopile 30a in each pixel unit 2 is designed so that the hot junction T1 gathers at the center of 3a. Here, in the two second thin film structure portions 3aa in the middle in the vertical direction of FIG. 5, as shown in FIGS. 5 and 9, the hot junctions are arranged along the juxtaposed direction of the three second thin film structure portions 3aa. T1 is arranged side by side. On the other hand, in the two second thin film structure portions 3aa on the upper side in the vertical direction of FIG. 5, as shown in FIGS. 5 and 10, the middle second in the juxtaposition direction of the three second thin film structure portions 3aa. The hot junctions T1 are concentrated on the side close to the thin film structure portion 3aa. Further, in the two second thin film structure portions 3aa on the lower side in the vertical direction in FIG. 5, the temperature is increased to the side closer to the second thin film structure portion 3aa in the middle in the juxtaposition direction of the three second thin film structure portions 3aa. The contacts T1 are concentrated. Therefore, in the infrared sensor chip 100 in the present embodiment, the arrangement of the plurality of hot junctions T1 of the upper and lower second thin film structure portions 3aa in the vertical direction in FIG. 5 is the second thin film structure portion 3aa in the middle. Since the temperature change of the hot junction T1 can be increased as compared with the arrangement of the plurality of hot junctions T1, the sensitivity can be improved. In the present embodiment, the predetermined depth dp is set to 200 μm when the depth of the deepest portion of the cavity 11 is set to the predetermined depth dp (see FIGS. 7B and 8B). However, this value is an example and is not particularly limited. However, the predetermined depth dp needs to be set smaller than the thickness dimension of the semiconductor substrate 1.

  In the second thin film structure portion 3aa, an infrared absorption layer 39 made of an n-type polysilicon layer that absorbs infrared rays is formed in a region where the thermopile 30a is not formed on the infrared incident surface side of the silicon nitride film 32. Yes. The infrared absorption layer 39 also has a function of suppressing warpage of the second thin film structure portion 3aa. Further, the connecting piece 3c that connects the adjacent second thin film structures 3aa, 3aa is provided with a reinforcing layer 39b (see FIG. 11) made of an n-type polysilicon layer that reinforces the connecting piece 3c. . Here, the reinforcing layer 39 b is formed integrally with the infrared absorption layer 39. Therefore, in the infrared sensor chip 100, since the connecting piece 3c is reinforced by the reinforcing layer 39b, it is possible to prevent damage due to stress generated due to external temperature change or impact during use. Therefore, it is possible to reduce breakage during production and to improve production yield. In the present embodiment, the length L1 of the connecting piece 3c shown in FIG. 11 is set to 24 μm, the width L2 is set to 5 μm, and the width L3 of the reinforcing layer 39b is set to 1 μm. There is no particular limitation. However, when a silicon substrate is used as the semiconductor substrate 1 and the reinforcing layer 39b is formed of an n-type polysilicon layer, in order to prevent the reinforcing layer 39b from being etched during the formation of the cavity 11, The width dimension of the reinforcing layer 39b is set to be smaller than the width dimension of the connecting piece 3c, and both side edges of the reinforcing layer 39b need to be positioned inside the both side edges of the connecting piece 3c in plan view.

  In addition, as shown in FIGS. 11 and 16B, the infrared sensor chip 100 has chamfered portions 3d and 3d formed between both side edges of the connecting piece 3c and side edges of the second thin film structure portion 3aa. A chamfered portion 3e is also formed between the side edges of the X-shaped connecting piece 3c that are substantially orthogonal to each other. Therefore, in the infrared sensor chip 100, compared to the case where the chamfered portion is not formed as shown in FIG. 11A, the stress concentration at the connecting portion between the connecting piece 3c and the second thin film structure portion 3aa is reduced. This can alleviate the residual stress generated during the manufacturing process and can reduce the damage during the manufacturing process, thereby improving the manufacturing yield. Further, the infrared sensor chip 100 can prevent damage due to stress generated due to an external temperature change or impact during use. In the example shown in FIG. 11, each of the chamfered portions 3 d and 3 e is an R chamfered portion having an R (R) of 3 μm, but is not limited to the R chamfered portion, and may be a C chamfered portion, for example.

  In addition, as shown in FIGS. 5, 9 and 10, the infrared sensor chip 100 includes a supporting portion 3 d, one bridge portion 3 bb, a second infrared absorbing portion 33 a, and the other one. A failure diagnosis wiring (heater for failure diagnosis) 139 made of an n-type polysilicon layer routed across the bridge portion 3bb and the support portion 3d is provided. Further, the infrared sensor chip 100 has all the failure diagnosis wirings 139 connected in series. Accordingly, it is possible to detect the presence or absence of breakage such as breakage of the bridge portion 3bb by energizing the series circuit of the i × j failure diagnosis wirings 139 of the infrared sensor chip 100.

  In short, the infrared sensor chip 100 is configured such that the bridge portion 3bb is broken or the failure diagnosis wiring 139 depends on whether or not the ixj failure diagnosis wirings 139 are energized during inspection or use during manufacture. Can be detected. Further, in the infrared sensor chip 100, during the above-described inspection and use, the temperature sensing unit 30 detects the output of each temperature sensing unit 30 by energizing the series circuit of ixj failure diagnosis wirings 139. It is possible to detect the presence / absence of disconnection of 30 and variations in sensitivity (variations in output of the temperature sensing unit 30). Here, regarding the sensitivity variation, it is possible to detect the sensitivity variation for each pixel unit 2. For example, the warp of the first thin film structure unit 3 a or the semiconductor substrate 1 of the first thin film structure unit 3 a. It is possible to detect variations in sensitivity due to sticking or the like. Here, in the infrared sensor chip 100, the failure diagnosis wiring 139 is folded and meandered in the vicinity of the group of the plurality of hot junctions T1 in a plan view. Therefore, in this infrared sensor chip 100, each hot junction T1 can be efficiently heated by Joule heat generated by energizing the failure diagnosis wiring 139. The above-described failure diagnosis wiring 139 is formed with the same thickness on the same plane as the n-type polysilicon layer 34 and the p-type polysilicon layer 35.

The infrared absorption layer 39 and the failure diagnosis wiring 139 described above contain the same n-type impurity (for example, phosphorus) as the n-type polysilicon layer 34 at the same impurity concentration (for example, 10 ¹⁸ to 10 ²⁰ cm ⁻³ ). The n-type polysilicon layer 34 is formed at the same time. Further, for example, boron may be adopted as the p-type impurity of the p-type polysilicon layer 35, and the impurity concentration may be appropriately set within a range of, for example, about 10 ¹⁸ to 10 ²⁰ cm ⁻³ . In the infrared sensor chip 100 of the present embodiment, the impurity concentration of each of the n-type polysilicon layer 34 and the p-type polysilicon layer 35 is 10 ¹⁸ to 10 ²⁰ cm ⁻³ , and the resistance value of the thermocouple can be reduced. The N ratio can be improved. The infrared absorption layer 39 and the failure diagnosis wiring 139 are doped with the same n-type impurity as the n-type polysilicon layer 34 at the same impurity concentration. However, the present invention is not limited to this. For example, the p-type polysilicon layer 35 The same impurity may be doped with the same impurity concentration.

In the infrared sensor chip 100, the refractive index of the n-type polysilicon layer 34, the p-type polysilicon layer 35, the infrared absorption layer 39, and the failure diagnosis wiring 139 is n ₁ , and the center wavelength of the infrared ray to be detected is λ. to time, so as to set the n-type polysilicon layer 34, p-type polysilicon layer 35, the infrared-absorbing layer 39, and the failure diagnosis wirings 139 respectively thicknesses t1 to lambda / 4n _1. Therefore, in the infrared sensor chip 100, the absorption efficiency of infrared rays having a wavelength to be detected (for example, 8 to 12 μm) can be increased, and high sensitivity can be achieved. For example, when n ₁ = 3.6 and λ = 10 μm, t 1 ≈0.69 μm may be set.

In the present embodiment, since the n-type polysilicon layer 34, the p-type polysilicon layer 35, the infrared absorption layer 39, and the failure diagnosis wiring 139 have impurity concentrations of 10 ¹⁸ to 10 ²⁰ cm ⁻³ , the infrared Infrared reflection can be suppressed while increasing the absorption rate of the light, and the S / N ratio of the output of the temperature sensing unit 30 can be increased. Further, in the infrared sensor chip 100 according to the present embodiment, the infrared absorption layer 39 and the failure diagnosis wiring 139 can be formed in the same process as the n-type polysilicon layer 34, so that the cost can be reduced.

In addition, as shown in FIGS. 8, 12, and 13, the infrared sensor chip 100 includes the interlayer insulating film 50 in which the connection portion 36 and the connection portion 37 of the temperature sensing portion 30 are located on the one surface side of the semiconductor substrate 1. Insulated and separated by. That is, the connecting portion 36 on the warm junction T1 side is electrically connected to the one end portions of the polysilicon layers 34 and 35 through the contact holes 50a ₁ and 50a ₂ formed in the interlayer insulating film 50. Further, the connecting portion 37 on the cold junction T2 side is electrically connected to the other end portions of the polysilicon layers 34 and 35 through contact holes 50a ₃ and 50a ₄ formed in the interlayer insulating film 50. .

  Further, the MOS transistor 4 is formed in the formation region A2 of the MOS transistor 4 on the one surface side of the semiconductor substrate 1 as described above.

As shown in FIGS. 7, 8, and 15, the MOS transistor 4 has a p-type (p ⁺ ) well region 41 of the first conductivity type formed on the one surface side of the semiconductor substrate 1. An n-type (n ⁺ ) drain region 43 of the second conductivity type and an n-type (n ⁺ ) source region 44 of the second conductivity type are formed apart from each other. Further, in the well region 41, a p-type (p ⁺⁺ ) channel stopper region 42 which is a first conductivity type surrounding the drain region 43 and the source region 44 is formed.

  A gate electrode 46 made of an n-type polysilicon layer is disposed on a portion of the well region 41 located between the drain region 43 and the source region 44 via a gate insulating film 45 made of a silicon oxide film (thermal oxide film). Is formed.

  A drain electrode 47 made of a metal material (for example, Al—Si) is formed on the drain region 43, and a source electrode 48 made of a metal material (for example, Al—Si) is formed on the source region 44. Is formed.

  The gate electrode 46, the drain electrode 47, and the source electrode 48 are insulated and separated by the interlayer insulating film 50 described above. Here, the drain electrode 47 is electrically connected to the drain region 43 through a contact hole 50 d formed in the interlayer insulating film 50, and the source electrode 48 is electrically connected to the source region 44 through a contact hole 50 e formed in the interlayer insulating film 50. Connected.

  In each pixel unit 2 of the infrared sensor chip 100, as shown in FIGS. 3 and 5, the source electrode 48 of the MOS transistor 4 and one end of the temperature sensing unit 30 are electrically connected, and the other end of the temperature sensing unit 30 is connected. Are electrically connected to the fourth wiring 104. In each pixel unit 2, the drain electrode 47 of the MOS transistor 4 is electrically connected to the first wiring 101, and the gate electrode 46 is electrically connected to the second wiring 102 made of n-type polysilicon wiring. It is connected. In each pixel unit 2, as shown in FIGS. 7 and 8, an electrode 49 made of a metal material (for example, Al—Si) is formed on the channel stopper region 42 of the MOS transistor 4. Thus, the well region 41 is electrically connected to the third wiring 103 through the channel stopper region 42 and the electrode 49. The electrode 49 is electrically connected to the channel stopper region 42 through a contact hole 50f formed in the interlayer insulating film 50.

  In the Zener diode ZD, the anode electrode 83 is formed on the first diffusion region 81, and the two cathode electrodes 84a and 84b are formed on the second diffusion region 82, as shown in FIG. In this Zener diode ZD, the anode electrode 83 is electrically connected to the fifth pad Vzd, and one cathode electrode 84a is connected to the second wiring 102 via one second wiring 102. The MOS transistor 4 is electrically connected to the gate electrode 46, and the other cathode electrode 84 b is electrically connected to one of the second pads Vsel 1 to Vsel 8 connected to the second wiring 102.

  Since the infrared sensor chip 100 includes the failure diagnosis wiring 139 that warms the hot junction T1 by Joule heat generated by being energized, the failure diagnosis wiring 139 is energized to output the thermopile 30a. By measuring, it is possible to determine the presence or absence of a failure such as disconnection of the thermopile 30a, and the reliability can be improved. In addition, the infrared sensor chip 100 is arranged so that the failure diagnosis wiring 139 does not overlap the thermopile 30a in a region where the failure detection wiring 139 overlaps the cavity 11 of the semiconductor substrate 1 in the thermal infrared detection unit 3. It is possible to prevent the heat capacity of the hot junction T1 of the thermopile 30a from increasing by 139, and to improve the sensitivity and response speed.

  Here, in the infrared sensor chip 100, since the failure diagnosis wiring 139 also absorbs infrared rays from the outside during normal times when self-diagnosis is not performed during use, the temperature of the plurality of hot junctions T1 can be made uniform and the sensitivity can be improved. Can be improved. In the infrared sensor chip 100, since the infrared absorbing layer 39 and the reinforcing layer 39b also absorb infrared rays from the outside, the temperature of the plurality of hot junctions T1 can be made uniform, and the sensitivity can be improved. Further, the self-diagnosis at the time of using the infrared sensor chip 100 may be periodically performed by, for example, a self-diagnosis circuit provided in the IC chip 200A, but is not necessarily performed periodically.

  In addition, the infrared sensor chip 100 includes a plurality of linear slits 13 provided in the first thin film structure portion 3 a along the inner circumferential direction of the cavity portion 11. It is separated into a plurality of second thin film structure portions 3aa extending inward from a support portion 3d that is a portion surrounding the cavity portion 11. The infrared sensor chip 100 is provided with a hot junction T1 of the thermopile 30a for each second thin film structure 3aa, and the output change with respect to the temperature change is larger than when the output is taken out for each thermopile 30a. Since all the thermopile 30a is electrically connected in relation, it becomes possible to improve response speed and sensitivity. Further, in the infrared sensor chip 100, since the connecting pieces 3c that connect the adjacent second thin film structure portions 3aa and 3aa are formed, the warpage of each second thin film structure portion 3aa can be reduced, and the structural stability can be reduced. Improve the stability and stabilize the sensitivity.

  In the infrared sensor chip 100, the n-type polysilicon layer 34, the p-type polysilicon layer 35, the infrared absorption layer 39, the reinforcing layer 39b, and the failure diagnosis wiring 139 are set to the same thickness. The uniformity of the stress balance of the second thin film structure portion 3aa can be improved, the warpage of the second thin film structure portion 3aa can be suppressed, and the variation in sensitivity between products and the variation in sensitivity between pixel portions 2 can be reduced. It becomes possible to do.

  In the infrared sensor chip 100, the fault diagnosis wiring 139 is formed of the same material as the n-type polysilicon layer 34 that is the first thermoelectric element or the p-type polysilicon layer 35 that is the second thermoelectric element. Therefore, the failure diagnosis wiring 139 can be formed simultaneously with the first thermoelectric element or the second thermoelectric element, and the cost can be reduced by simplifying the manufacturing process.

  In the infrared sensor chip 100, a plurality of pixel units 2 each including an infrared absorption unit 33 and a failure diagnosis wiring 139 are provided in a two-dimensional array on the one surface side of the semiconductor substrate 1. Therefore, in the configuration of the infrared sensor chip 100, the self-diagnosis at the time of manufacture or use is energized to the failure diagnosis wiring 139 of each pixel unit 2, so that the sensitivity of the temperature sensing unit 30 of each pixel unit 2 is increased. It becomes possible to grasp the variation.

  The outer peripheral shape of the infrared sensor chip 100 described above is rectangular (square or rectangular).

  In the infrared sensor chip 100 described above, a cavity is formed by anisotropic etching using the crystal plane orientation dependence of the etching rate, using the single crystal silicon substrate whose one surface is the (100) plane as the semiconductor substrate 1. 11 is a quadrangular pyramid shape, but is not limited to a quadrangular pyramid shape, and may be a quadrangular pyramid shape. Further, the plane orientation of the one surface of the semiconductor substrate 1 is not particularly limited. For example, a single crystal silicon substrate having the one surface of (110) may be used as the semiconductor substrate 1.

Further, the conductivity type of the semiconductor substrate 1 is not limited to the n-type, and may be, for example, a p-type as shown in FIGS. FIG. 18 shows an example in which the p-type semiconductor substrate 1 constitutes a channel formation region, and the conductivity type of the drain region 43 and the source region 44 is n-type (n ⁺ ). In FIG. 19, a p-type (p ⁺ ) well region 41 formed in a p-type semiconductor substrate 1 constitutes a channel formation region, and the conductivity type of the drain region 43 and the source region 44 is n-type (n ⁺ ). FIG. 20 shows an example in which the n-type well region 41 formed in the p-type semiconductor substrate 1 constitutes a channel formation region, and the conductivity type of the drain region 43 and the source region 44 is p-type (p ⁺ ). It is.

  In the infrared sensor chip 100, a plurality of pixel portions 2 each having a temperature sensing portion 30 that is a thermoelectric conversion portion are arranged in an array on one surface side of the semiconductor substrate 1, but the structure is not particularly limited. In addition, the number of thermopiles 30a constituting the temperature sensing unit 30 is not limited to a plurality and may be one. The temperature sensing unit 30 is not limited to one or more thermopiles 30a, and may be a thermocouple, a resistance bolometer, a pyroelectric element, or the like. Accordingly, the circuit configuration of the circuit portion of the IC chip 200A may be changed as appropriate.

  Further, in the above-described infrared sensor chip 100, the n-type polysilicon layer is used as the material of the first thermoelectric element, and the p-type polysilicon is used as the material of the second thermoelectric element. N-type silicon germanium may be employed as the material of the first thermoelectric element, and p-type silicon germanium may be employed as the material of the second thermoelectric element.

  The IC chip 200A is an ASIC (Application Specific IC) and is formed using a silicon substrate. The outer peripheral shape of the IC chip 200A is rectangular (square or rectangular). Note that the IC chip 200A is not limited to an ASIC, and may be any chip on which a circuit unit including an appropriate integrated circuit is formed.

  The IC chip 200A has the above-described circuit portion (not shown) formed on the main surface side. The circuit unit includes, for example, a control circuit that controls the infrared sensor chip 100. The circuit unit includes an amplifier circuit that amplifies output voltages of a plurality of input pads electrically connected to the plurality of output pads 80 of the infrared sensor chip 100, and outputs of the plurality of input pads. A multiplexer that alternatively inputs a voltage to the amplifier circuit. Here, the output of the amplifier circuit is an output corresponding to the temperature difference between the hot junction T1 and the cold junction T2 in the pixel unit 2. Then, the IC chip 200A can display an infrared image on an external display device. The circuit unit also includes the above-described self-diagnosis circuit. The circuit configuration of the circuit part of the IC chip 200A is not particularly limited. The infrared sensor has a thermistor (not shown), which is an electronic device chip, mounted on the inner bottom surface of the upper recess 301b of the package 300, and electrically connects the thermistor and the IC chip 200A. An arithmetic circuit for obtaining the temperature of each pixel unit 2 based on the output of the and the thermistor may be provided.

  The package main body 301 of the package 300 is made of a multilayer ceramic substrate, and wiring (first conductor pattern) for electrically connecting the pads 80 of the infrared sensor chip 100 via the wires 381 is formed on the inner bottom surface of the upper recessed portion 301b. A wiring (second conductor pattern) is formed on the inner bottom surface of the lower recessed portion 301a, and the pad (not shown) of the IC chip 200A is electrically connected through the second bonding portion 312. Further, in the package body 301, wiring (not shown) for connecting the first conductor pattern to which the infrared sensor chip 100 is connected and the second conductor pattern to which the IC chip 200A is connected is embedded. The package 300 has external connection electrodes that are appropriately connected to the infrared sensor chip 100 and the IC chip 200A. In addition, as the wire 381, it is preferable to use an Au wire having higher corrosion resistance than an Al wire.

  The IC chip 200A may be bonded to the package body 301 by, for example, a room temperature bonding method or a eutectic bonding method using Au—Sn eutectic or Au—Si eutectic.

  In the package 300, the package lid 302 is formed of a material that transmits infrared rays to be detected by the infrared sensor chip 100. Here, the infrared sensor employs silicon or germanium as the material of the package lid 302, and employs a conductive material such as solder as the material of the first joint 311. It is preferable to electrically connect the formed electromagnetic shield layer (not shown). Thereby, the infrared sensor can reduce the influence of electromagnetic noise.

  The package lid 302 has a flat plate shape, but is not limited thereto. For example, at least a part of the package lid 302 may form a lens. In the infrared sensor of this embodiment, if at least a part of the package lid 302 is formed in the shape of a lens, the light receiving efficiency of the infrared sensor chip 100 can be improved as compared with the case where the package lid 302 is in the shape of a flat plate. It becomes possible to plan. Further, in the infrared sensor of this embodiment, the detection area of the infrared sensor chip 100 can be set by the package lid 302.

  As the above-mentioned lens, a plano-convex aspherical lens is preferable. Thereby, the infrared sensor can achieve high sensitivity by improving the infrared light receiving efficiency of the infrared sensor chip 100 while reducing the thickness of the lens.

  The package lid 302 having at least a part in the shape of a lens is formed using a semiconductor substrate different from the semiconductor substrate 1 of the infrared sensor chip 100. More specifically, the lens has an anode whose contact pattern is designed with a semiconductor substrate (here, a silicon substrate) in accordance with a desired lens shape, and the contact with the semiconductor substrate is ohmic contact on one surface side of the semiconductor substrate. After forming the porous portion to be a removal site by anodizing the other surface side of the semiconductor substrate in an electrolytic solution composed of a solution for removing oxides of constituent elements of the semiconductor substrate by etching, the porous It is composed of a semiconductor lens (here, a silicon lens) formed by removing the mass portion. Thus, the lens has conductivity. As a method for manufacturing a semiconductor lens to which this kind of anodization technology is applied, for example, a method for manufacturing a semiconductor lens disclosed in Japanese Patent No. 3897055 and Japanese Patent No. 3897056 can be applied.

  In this embodiment, the detection area of the infrared sensor chip 100 can be set by a lens made of the above-described semiconductor lens, and a semiconductor lens having a shorter focal length, a larger aperture diameter, and smaller aberration than a spherical lens is used as the lens. Therefore, the package 300 can be thinned by shortening the focus. The infrared sensor of the present embodiment is assumed to be an infrared ray to be detected by the infrared sensor chip 100, and an infrared ray having a wavelength band of about 10 μm (8 μm to 13 μm) emitted from the human body. Compared to gallium arsenide and the like, silicon is used which has a lower environmental burden, can be manufactured at a lower cost than germanium, and has a smaller wavelength dispersion than zinc sulfide.

  The package lid 302 includes an optical multilayer film (multilayer interference filter film) that transmits infrared rays in a desired wavelength range including infrared wavelengths to be detected by the infrared sensor chip 100 and reflects infrared rays outside the wavelength ranges. It is preferable to provide a filter part (not shown). By providing such a filter unit, it becomes possible to cut infrared rays and visible light in unnecessary wavelength regions other than the desired wavelength region by the filter unit, and it is possible to suppress the generation of noise due to sunlight or the like. It becomes possible to achieve high sensitivity.

  In the infrared sensor according to the present embodiment described above, the infrared sensor chip 100 and the IC chip 200A are arranged in the package 300 so as to be separated from each other in the thickness direction. Therefore, in the infrared sensor of the present embodiment, variation in offset voltage in the plane of the infrared sensor chip 100 due to heat generation of the IC chip 200A can be suppressed, and the S / N ratio in the plane of the infrared sensor chip 100 can be suppressed. It is possible to suppress the variation of. In short, in the infrared sensor of the present embodiment, it is possible to suppress variations in the S / N ratio of the output of each thermal infrared detector 3 of the infrared sensor chip 100. In the infrared sensor, it is preferable to arrange the infrared sensor chip 100 and the IC chip 200A so that the center line along the thickness direction of the infrared sensor chip 100 and the center line along the thickness direction of the IC chip 200A substantially coincide. . Thereby, the infrared sensor can further suppress the variation in the S / N ratio of the output of each thermal infrared detector 3 of the infrared sensor chip 100.

DESCRIPTION OF SYMBOLS 1 Semiconductor substrate 3 Thermal type infrared detection part 11 Cavity part 100 Infrared sensor chip (electromagnetic wave sensor chip)
100A Device chip 200 IC chip 300 Package 301 Package body 301a Concave part 301b Concave part 302 Package lid 311 First joint part 312 Second joint part 313 Third joint part 321 First airtight space 322 Second airtight space

Claims (5)

  A device chip that is required to be used in a vacuum, an IC chip that cooperates with the device chip, and a package in which the device chip and the IC chip are stored separately in the thickness direction of the device chip, The package includes a package main body and a package lid that is airtightly bonded to the package main body via a first bonding portion, and a two-step recess is provided on one surface side of the package main body. , The second chip is bonded to the inner bottom surface of the lower concave portion via a second bonding portion, and the device chip has a third bonding portion over the entire circumference of the peripheral portion of the lower concave portion on the inner bottom surface of the upper concave portion. And a first airtight space surrounded by the package body, the device chip, the third joint, and the package lid is a vacuum atmosphere. Vacuum sealing device that.   The vacuum sealing device according to claim 1, wherein the third bonding portion is formed of an inorganic bonding material.   3. The vacuum sealed device according to claim 1, wherein the second hermetic space surrounded by the package body, the device chip, and the third joint is a vacuum atmosphere.   4. The device according to claim 1, wherein the device chip is an electromagnetic wave sensor chip, and the package lid is formed of a material that transmits an electromagnetic wave to be detected by the electromagnetic wave sensor chip. 5. 2. A vacuum sealing device according to item 1.   The electromagnetic wave to be detected is infrared, and the electromagnetic wave sensor chip has a plurality of thermal infrared detectors arranged in an array on one surface side of the semiconductor substrate, and the thermal infrared ray on the one surface side of the semiconductor substrate. The vacuum-sealed device according to claim 4, wherein the vacuum-sealed device is an infrared sensor chip in which a cavity is formed immediately below a part of the detection unit.

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