JP2013038903A - Discharge circuit for capacitor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a discharge circuit for a capacitor that prevents a reduction in determination accuracy of the presence or absence of abnormality of discharge resistors 26a and 26b.SOLUTION: A power conversion system includes: a high-voltage battery 16; an inverter 12 that has a pair of input terminals and is connected to the high-voltage battery 16 via the pair of input terminals; a capacitor 15 that is connected between the pair of input terminals; and a delay circuit 36 that is connected between the pair of input terminals. The delay circuit 36 includes a pair of discharge resistors 26a and 26b, and a delay capacitor 32 connected in parallel to the discharge resistor 26b. The presence or absence of abnormality of the discharge resistors 26a and 26b are determined based on a voltage at a connection point of the discharge resistor 26b and the delay capacitor 32.

Description

  The present invention includes a DC power supply, a power conversion circuit having a pair of input terminals and connected to the DC power supply via the pair of input terminals, a capacitor connected between the pair of input terminals, The present invention relates to a capacitor discharge circuit applied to a system including a discharge path connected between the pair of input terminals.

  Conventionally, as can be seen in Patent Documents 1 and 2 below, a system in which a battery is connected in parallel to a discharge path having an inverter, a capacitor, and a discharge resistor via a switch (relay) is known. Specifically, the capacitor provided in the system has a function of suppressing voltage fluctuation between the pair of input terminals of the inverter. Further, the discharge resistor has a function of discharging the capacitor in a situation where the switch is turned off and the battery and the inverter are disconnected.

JP-A-10-257778 Japanese Patent No. 4679675

  By the way, if an abnormality occurs in the discharge path such as disconnection (open failure) in the discharge resistor, the capacitor may not be discharged. In order to avoid such a situation, it is conceivable to incorporate into the system a technique for determining whether there is an abnormality in the discharge path. Here, the present inventors pay attention to the fact that the potential at the intermediate point of the discharge path changes depending on whether there is an abnormality in the discharge path, and determine whether there is an abnormality in the discharge path based on the potential at the intermediate point. The technology has been incorporated into the above system.

  However, if the change in potential at the midpoint of the discharge path according to the presence / absence of an abnormality in the discharge path is small, the determination accuracy of the presence / absence of an abnormality in the discharge path may be reduced.

  The present invention has been made to solve the above-described problems, and an object of the present invention is to provide a capacitor discharge circuit capable of suppressing a decrease in accuracy in determining whether there is an abnormality in the discharge path.

  Hereinafter, means for solving the above-described problems and the operation and effects thereof will be described.

  The invention according to claim 1 is connected between the pair of input terminals, and a power conversion circuit having a pair of input terminals and connected to the DC power supply via the pair of input terminals. And a delay circuit that delays and outputs a change in potential at an intermediate point of the discharge path, and is applied to a system that includes a capacitor and a discharge path connected between the pair of input terminals.

  In the above invention, the potential change at the midpoint of the discharge path is delayed and a signal is output from the delay circuit. According to the output signal of such a delay circuit, it is possible to grasp the transition of the potential at the intermediate point according to the presence or absence of abnormality in the discharge path by enlarging the time scale. That is, according to the above-described invention including the delay circuit, it is possible to suppress a decrease in the accuracy of determining whether there is an abnormality in the discharge path.

  According to a second aspect of the present invention, in the first aspect of the invention, the abnormality in the discharge path is determined based on a time from when the output signal of the delay circuit starts to change until the output signal reaches a predetermined threshold value. It further comprises an abnormality determining means for determining whether or not there is any.

  In the above invention, the time from when the change of the output signal of the delay circuit is started until the output signal reaches a predetermined threshold value is used for determining the abnormality of the discharge path, so that the presence or absence of abnormality of the discharge path can be easily and accurately determined. Can be judged.

  According to a third aspect of the present invention, in the first or second aspect of the invention, the discharge path includes a series connection body of a plurality of resistors, and the delay circuit further includes a delay capacitor, and the plurality of resistors The delay capacitor is connected in parallel to a part of the body.

  In the above invention, by configuring the delay circuit in the above manner, for example, the voltage at the connection point of the delay capacitor and the resistor can be used as the output signal of the delay circuit.

  The invention according to claim 4 is the invention according to claim 1 or 2, wherein the discharge path is formed of a resistor, the delay circuit further includes a reactor, and the reactor is connected in series to the resistor. It is characterized by that.

  In the above invention, by configuring the delay circuit in the above manner, for example, the voltage at the connection point of the resistor and the reactor can be used as the output signal of the delay circuit.

  According to a fifth aspect of the invention, in the third aspect of the invention, the delay circuit includes an electronically controlled first opening / closing means for opening / closing an electric path connecting the capacitor and the delay capacitor, and the delay circuit. It further comprises a member having a voltage lower than the charging voltage of the capacitor and an electronically controlled second opening / closing means for opening / closing an electrical path connecting the delay capacitor.

  In the above invention, the first and second opening / closing means are provided. According to the opening / closing operation of these opening / closing means, since the delay capacitor can be charged / discharged, it is possible to expand the time when the output signal used for determining the abnormality of the resistor as the discharge path can be output from the delay circuit. . That is, it is possible to increase the time when the abnormality of the resistor can be determined using the output signal of the delay circuit.

  According to a sixth aspect of the present invention, in the fifth aspect of the present invention, the delay circuit further includes a resistor having a member having a voltage lower than a charging voltage of the delay capacitor and an electric path connecting the delay capacitor. It is characterized by providing.

  In the above invention, by further providing a resistor, for example, the output signal of the delay circuit can be used as a signal for determining abnormality of the resistor as a discharge path in the discharge period of the delay capacitor.

  According to a seventh aspect of the invention, in the sixth aspect of the invention, when the first opening / closing means is in a closed state and the second opening / closing means is in an open state, the output signal of the delay circuit When the output signal reaches the first threshold, and when the first opening / closing means is open and the second opening / closing means is closed. , An abnormality for determining whether or not the resistor as the discharge path is abnormal based on a ratio to a time from when the change of the output signal of the delay circuit is started until the output signal reaches the second threshold value It further comprises a judging means.

  The capacitance of the delay capacitor is affected by various factors such as variations due to individual differences of capacitors and changes depending on the temperature of the capacitors. When the capacitances of the delay capacitors are different, the time from when the change of the output signal of the delay circuit is started until the output signal reaches a predetermined threshold value may be different. In this case, for example, if the presence / absence of the abnormality of the resistor as the discharge path is determined using the above-described time, the determination accuracy of the presence / absence of the abnormality of the resistor may be lowered. In this regard, in the above invention, the use of the above ratio can eliminate as much as possible the influence of the difference in capacitance of the delay capacitor on the abnormality determination of the resistor. Thereby, the fall of the determination precision of the presence or absence of abnormality of a resistor can be suppressed suitably.

1 is a system configuration diagram according to a first embodiment. FIG. The figure which shows the structure of the discharge resistor concerning the embodiment. The figure which shows the abnormality judgment method of the discharge resistor concerning the embodiment. The figure which shows the delay circuit concerning 2nd Embodiment. The figure which shows the abnormality judgment method of the discharge resistor concerning the embodiment. The figure which shows the delay circuit concerning 3rd Embodiment. The figure which shows the abnormality judgment method of the discharge resistor concerning the embodiment. The figure which shows the delay circuit concerning 4th Embodiment. The figure which shows the abnormality judgment method of the discharge resistor concerning the embodiment. The figure which shows the delay circuit concerning 5th Embodiment. The figure which shows the abnormality judgment method of the discharge resistor concerning the embodiment.

(First embodiment)
Hereinafter, a first embodiment in which a capacitor discharge circuit according to the present invention is applied to a power conversion system connected to a main rotating machine of a hybrid vehicle will be described with reference to the drawings.

  FIG. 1 shows a system configuration according to the present embodiment.

  As shown in the figure, the motor generator 10 is an in-vehicle main machine and is mechanically coupled to drive wheels (not shown). The motor generator 10 is connected to a high voltage battery 16 via an inverter 12 and a booster circuit 14.

  Specifically, the high voltage battery 16 is a storage battery having a terminal voltage of 100 V or more, for example. Further, the booster circuit 14 includes a series connection body of a pair of switching elements (not shown) and a capacitor 15 (smoothing capacitor) connected in parallel thereto, and the voltage of the high voltage battery 16 is controlled by operating these switching elements. It has a function of boosting a predetermined voltage (for example, “650 V”) as an upper limit. Here, the capacitor 15 is for suppressing the fluctuation of the output voltage with respect to the inverter 12. In the figure, for convenience of explanation, the capacitor 15 is shown outside the booster circuit 14.

  Between the high voltage battery 16 and the booster circuit 14, a relay 18 and a precharge relay 20 are provided for conducting or blocking between them. Specifically, a relay 18 is provided on the high potential side of a pair of electrical paths connecting each of the positive electrode and the negative electrode of the high-voltage battery 16 and each of the pair of input terminals of the booster circuit 14. The relay 18 is connected in parallel with a series connection body of a precharging relay 20 and a precharging resistor 22. According to such a configuration, the precharge relay 20 and the precharge are more than the resistance value of the electric path including the relay 18 among the electric paths connecting the positive electrode of the high voltage battery 16 and the high potential side input terminal of the booster circuit 14. The resistance value of the electrical path including the resistor 22 for use is larger. In practice, a relay is also provided in the electrical path connecting the negative electrode of the high voltage battery 16 and the low potential side input terminal of the booster circuit 14.

  The pair of output terminals of the booster circuit 14 are connected to a pair of input terminals (points connecting U, V, and W phases) of the inverter 12. The inverter 12 includes a series connection body of switching elements Sup and Sun, a series connection body of switching elements Svp and Svn, and a series connection body of switching elements Swp and Swn. Connection points are connected to the U, V, and W phases of the motor generator 10, respectively. In this embodiment, an insulated gate bipolar transistor (IGBT) is used as the switching element S * # (* = u, v, w, # = p, n). In addition, a diode D * # is connected in antiparallel to each of the switching elements S * #.

  A pair of discharge resistors 26 a and 26 b are connected between the pair of input terminals of the inverter 12. The discharge resistors 26a and 26b have a function of discharging the capacitor 15 in an emergency when it becomes impossible to perform a discharge control process described later. Specifically, the discharge resistor 26a and the discharge resistor 26b are connected in series. One end of the series connection body of the resistors 26a and 26b is connected to the high potential side of the pair of input terminals of the inverter 12, and the other end is connected. Connected to the low potential side.

  In the present embodiment, actually, as shown in FIG. 2, the discharge resistor 26a is composed of a parallel connection body of a pair of discharge resistors 26al and 26ar, and the discharge resistor 26b is a pair of discharge resistors 26bl. , 26br in parallel connection. That is, the series connection body of the discharge resistors 26a and 26b is formed by connecting a parallel connection body of a pair of discharge resistors in series. This configuration is intended to disperse heat generated in the discharge resistor.

  Returning to the description of FIG. 1, the hybrid control device (HVECU 28) is a control device that is higher than the motor generator control device (MGECU 30) (upstream from the user's request input from a user interface such as an accelerator pedal). is there.

  The HVECU 28 performs a relay control process for opening and closing the relay 18 and the precharge relay 20 when the motor generator 10 is driven.

  The relay control process is a process including a precharge for avoiding that a large current flows and the relay 18 is welded as the high voltage battery 16 and the inverter 12 are brought into conduction.

  That is, when connecting the high voltage battery 16 and the booster circuit 14, first, the relay 18 is opened and the precharge relay 20 is closed. Thereby, the resistance value of the electrical path connecting between the positive electrode of the high voltage battery 16 and the input terminal of the booster circuit 14 can be increased, and the current flowing from the high voltage battery 16 to the capacitor 15 and the like can be suppressed. After the capacitor 15 is charged more than a predetermined value, the relay 18 is closed and the precharge relay 20 is opened. Thereby, the high voltage battery 16 and the booster circuit 14 are connected with a low resistance.

  In the present embodiment, the relay control process is executed by the HVECU 28, but is not limited thereto, and may be executed by another ECU.

  On the other hand, MGECU 30 is a control device for controlling the control amount (for example, torque) of motor generator 10 as desired by operating switching element S * # of inverter 12. The MGECU 30 includes a microcomputer (a microcomputer 30a) and a gate drive circuit 30b for adjusting the gate voltage of the switching element S * #.

  The MGECU 30 (microcomputer 30a) performs control processing of the motor generator 10 by opening / closing the switching element S * #, boosting processing of the voltage of the high voltage battery 16 by operating the boosting circuit 14, and the like.

  In particular, the microcomputer 30a performs a discharge control process. In this process, the capacitor 15 is discharged in a state where the relay 18 and the precharge relay 20 are opened and the high voltage battery 16 and the booster circuit 14 are disconnected, and in preparation for subsequent vehicle maintenance or the like. The purpose is to ensure safety. In the present embodiment, the discharge control process is a process of operating the inverter 12 so that a reactive current flows through the motor generator 10 (so that the generated torque of the motor generator 10 is zero). According to such a discharge control process, the capacitor 15 can be discharged quickly.

  The MGECU 30 and the like are arranged in an in-vehicle low-voltage system including a low-voltage battery (not shown) whose terminal voltage is sufficiently lower than that of the high-voltage battery 16, and the relay 18, the switching element S * # and the like are arranged in the in-vehicle high-voltage system including the high-voltage battery 16. Be placed. For this reason, the MGECU 30 and the like operate the switching elements S * # and the like via insulation transmission means such as a photocoupler that transmits signals between these systems while insulating the high-pressure system and the low-pressure system.

  By the way, a power conversion system may be damaged by a vehicle collision or the like. Specifically, for example, the power supply source of the microcomputer 30a is cut off, or the circuit board on which the switching element S * # is mounted is damaged. If the power conversion system is damaged, there is a concern that the discharge control process cannot be performed because the inverter 12 cannot be properly energized. Although the discharge resistors 26a and 26b are provided for such an emergency, there is a concern that the capacitor 15 cannot be discharged when an abnormality occurs in the resistors 26a and 26b.

  In order to avoid such a situation, the present embodiment includes a delay circuit 36 having the discharge resistors 26a and 26b, a capacitor (delay capacitor 32) and a determination unit 34. Based on the output signal of the delay circuit 36, the discharge resistor An abnormality determination process is performed to determine whether or not the bodies 26a and 26b are abnormal. Hereinafter, this process will be described.

  First, the delay circuit 36 will be described.

  The delay circuit 36 is connected between a pair of input terminals of the inverter 12. Specifically, a delay capacitor 32 is connected in parallel to the discharge resistor 26b (a parallel connection body of the discharge resistors 26bl and 26br). The delay circuit 36 functions to delay the change in voltage at the connection point (intermediate point of the discharge path) of the series connection body of the discharge resistors 26a and 26b and output it as the abnormality determination voltage Vdelay. In the present embodiment, the voltage (charge voltage) of the delay capacitor 32 is used as the abnormality determination voltage Vdelay.

  The abnormality determination voltage Vdelay is taken into the determination unit 34. In a situation where power supply from the high voltage battery 16 to the inverter 12 is started by relay control processing prior to the start of the inverter 12, the determination unit 34 determines that the voltage Vdelay is a threshold value after the rise of the abnormality determination voltage Vdelay is started. Based on the time until the voltage Vth is reached (rise time τa), it is determined whether or not the discharge resistors 26a and 26b are abnormal. Note that the determination unit 34 also captures the input voltage of the inverter 12 (charge voltage of the capacitor 15). Further, although not shown, the determination unit 34 is also configured to capture information related to the starting point of the rise time τa.

  Next, an abnormality determination processing mode of the discharge resistors 26a and 26b according to the present embodiment will be described with reference to FIG.

  In the present embodiment, the starting point of the rising time τa is the closing timing (time t1) of the precharging relay 20. As shown by the solid line in the figure, when it is determined that the rising time τa is within the specified time range (τa = τ1), the discharge resistors 26a and 26b are not abnormal (normal). to decide.

  On the other hand, as shown by a two-dot chain line in the figure, when it is determined that the rise time τa is less than the lower limit value of the specified time range (τa = τs), any one of the discharge resistors 26al, 26ar, 26bl, 26br It is determined that there is a short circuit (short fault). Further, as shown by a broken line in the figure, when it is determined that the rising time τa exceeds the upper limit value of the specified time range (τa = τo), one of the discharge resistors 26al, 26ar, 26bl, 26br is disconnected ( Determine that an open failure has occurred.

  When it is determined that an abnormality has occurred in the discharge resistors 26a and 26b, a signal dig to that effect is transmitted from the determination unit 34 to the microcomputer 30a. Then, a fail process is performed in which a fail signal FL is output from the fail processing unit 30c in the microcomputer 30a to the HVECU 28 (see FIG. 1 above). As a result, it is possible to grasp that an abnormality has occurred on the HVECU 28 side, and as a result, the HVECU 28 can notify the user to that effect.

  Next, the reason why the discharge resistors 26a and 26b can be determined abnormally using the rise time τa will be described.

  The transition of the abnormality determination voltage Vdelay when the stepped voltage VL (> Vth) is input to the delay circuit 36 is that the capacitance of the delay capacitor 32 is Ct, the resistance value of the discharge resistor 26a is Rh, and the discharge resistor. If the resistance value of 26b is Rl, the total resistance value of these resistors 26a and 26b is Rhl, and the elapsed time from the starting point of the rise time τa (the application start timing of the stepped voltage VL) is t, the following equation (e1 ).

Vdelay = Va * [1-exp {-t / (Ct * Rhl)}] (e1)
Va = Rl / (Rh + Rl) × VL (e2)
Rhl = Rh × Rl / (Rh + Rl) (e3)
Here, it is assumed that the resistance value of the precharging resistor 22 is sufficiently smaller than the resistance values Rh and Rl of the discharge resistors 26a and 26b. Further, the voltage Va represented by the above formula (e2) will be referred to as a convergence voltage hereinafter.

  When the above equation (e1) is solved for t by substituting the threshold voltage Vth into the abnormality determination voltage Vdelay, the rise time τa is expressed by the following equation (e4).

τa = −Ct × Rhl × ln (1-Vth / Va) (e4)
Here, when an abnormality occurs in any of the discharge resistors 26al, 26ar, 26bl, and 26br, the total resistance value Rhl changes. Specifically, if a short circuit failure occurs in either one of the discharge resistors 26al, 26ar, the resistance value Rh of the discharge resistor 26a decreases, and if a short circuit failure occurs in either the discharge resistor 26bl, 26br, the discharge resistor 26b The resistance value Rl decreases. When the resistance value Rh of the discharge resistor 26a and the resistance value Rl of the discharge resistor 26b are lowered, the total resistance value Rhl is lowered, and the time constant of the delay circuit 36 (due to the change in the input signal to the delay circuit 36). When the abnormality determination voltage Vdelay changes, the time until the ratio of the actual change amount of the abnormality determination voltage Vdelay to the total change amount of the abnormality determination voltage Vdelay reaches approximately 63% is reduced. That is, the rise time τa is shortened.

  On the other hand, if an open failure occurs in either of the discharge resistors 26al and 26ar, the resistance value Rh of the discharge resistor 26a increases, and if an open failure occurs in either of the discharge resistors 26bl and 26br, the resistance of the discharge resistor 26b. The value Rl increases. When the resistance value Rh of the discharge resistor 26a and the resistance value Rl of the discharge resistor 26b increase, the total resistance value Rhl increases and the time constant of the delay circuit 36 increases. That is, the rise time τa becomes longer.

  Therefore, it is possible to determine whether or not the discharge resistors 26a and 26b are abnormal based on the rise time τa.

  The rise time τa tends to be shorter as the input voltage VL of the delay circuit 36 is higher. Therefore, for example, it is desirable to variably set the specified time range based on the input voltage VL of the delay circuit 36.

  Further, the transition of the abnormality determination voltage Vdelay in FIG. 3A is not the transition of the voltage calculated from the above equation (e1) (for example, the solid line in FIG. 5A described later). This is because the rise of the input voltage VL of the delay circuit 36 is somewhat moderate due to the voltage being applied to the delay circuit 36 via the precharge resistor 22 at the time of starting 12.

  Here, in this embodiment, the merit of using the output signal of the delay circuit 36 in the abnormality determination process of the discharge resistors 26a and 26b will be described.

  If the delay circuit 36 (delay capacitor 32) is not employed and the voltage at the connection point of the series connection body of the discharge resistors 26a and 26b is used as the abnormality determination voltage Vdelay, for example, as shown in FIG. The difference between the rise time τ1 when the discharge resistors 26a and 26b are normal and the rise time τs when an abnormality occurs in the discharge resistors 26a and 26b (example of short failure in the figure) may be excessively small. is there. At this time, due to variations in the rise time τa detected by the determination unit 34, it may not be possible to accurately determine whether the discharge resistors 26a and 26b are abnormal based on the rise time τa.

  On the other hand, according to the circuit configuration in which the output signal of the delay circuit 36 is the abnormality determination voltage Vdelay, the change in the voltage at the connection point of the series connection body of the discharge resistors 26a and 26b (the voltage of the delay capacitor 32) is changed. Can be delayed. That is, according to the abnormality determination voltage Vdelay output from the delay circuit 36, it is possible to grasp the transition of the voltage of the delay capacitor 32 according to the presence or absence of abnormality of the discharge resistors 26a and 26b by enlarging the time scale. it can. Therefore, it is possible to suppress a decrease in accuracy in determining whether or not the discharge resistors 26a and 26b are abnormal based on the rise time τa.

  According to the embodiment described in detail above, the following effects can be obtained.

  (1) The delay capacitor 32 is connected in parallel to the discharge resistor 26b to form the delay circuit 36, and the voltage of the delay capacitor 32 is used as the abnormality determination voltage Vdelay. Then, abnormality determination processing for the discharge resistors 26a and 26b was performed based on the rise time τa obtained from the voltage Vdelay. As a result, it is possible to accurately determine whether or not the discharge resistors 26a and 26b are abnormal, and it is possible to suitably suppress a decrease in accuracy of determining whether or not the discharge resistors 26a and 26b are abnormal.

  Further, in order to determine whether or not the discharge resistors 26a and 26b are abnormal using the rise time τa, for example, the waveform of the abnormality determination voltage when the discharge resistors 26a and 26b are normal and the actual abnormality determination voltage Compared with the abnormality determination method based on the comparison with the waveform, the presence or absence of abnormality of these resistors 26a and 26 can be easily determined.

  (2) When it is determined that an abnormality has occurred in the discharge resistors 26a and 26b, fail processing was performed. Thereby, the situation where this system is continuously used in the state where the reliability of the power conversion system is lowered can be avoided.

(Second Embodiment)
Hereinafter, the second embodiment will be described with reference to the drawings with a focus on differences from the first embodiment.

  FIG. 4 shows a delay circuit 36 according to the present embodiment. In FIG. 4, the same members as those shown in FIG. 1 are indicated by the same reference numerals for the sake of convenience.

  As shown in the figure, a first switch SW1 that is energized to open and close this path is provided in the electrical path that connects the connection point of the discharge resistors 26a and 26b and the delay capacitor 32. In addition, a second switch that is energized to open and close this path is connected to an electrical path connecting the first switch SW1 side of both ends of the delay capacitor 32 and the input terminal on the low potential side of the inverter 12. SW2 is provided. The switches SW1 and SW2 are opened and closed by the microcomputer 30a through the insulation transmission means.

  Next, the abnormality determination process for the discharge resistors 26a and 26b according to the present embodiment will be described.

  In the present embodiment, the presence or absence of abnormality in the discharge resistors 26a and 26b is determined based on the rise time τa in a state where the first switch SW1 is closed and the second switch SW2 is opened. This is because the abnormality determination process can be executed not only when the inverter 12 is started but also within a period during which the motor generator 10 is driven.

  FIG. 5 shows an example of an abnormality determination processing mode of the discharge resistors 26a and 26b according to the present embodiment. Specifically, FIG. 5A shows the transition of the abnormality determination voltage Vdelay, FIG. 5B shows the transition of the operation mode of the first switch SW1, and FIG. 5C shows the second The transition of the operation mode of the switch SW2 is shown.

  As illustrated, when the first switch SW1 is closed at time t1, charging of the delay capacitor 32 is started, and the abnormality determination voltage Vdelay starts to rise.

  Then, the first switch SW1 is opened at time t2, and then the second switch SW2 is closed at time t3. Here, the process relating to the second switch SW2 is for discharging the delay capacitor 32 in preparation for the next abnormality determination process.

  Incidentally, in this embodiment, for example, the abnormality determination process is executed in a predetermined cycle (for example, several hours) sufficiently longer than the cycle in which the control process of the motor generator 10 is performed. Further, the capacitance Ct of the delay capacitor 32 takes into account, for example, that the time scale of the output signal of the delay circuit 36 is expanded and that the influence of the delay capacitor 32 on the driving of the motor generator 10 is reduced. You can set it.

  Thus, in this embodiment, it was set as the structure provided with 1st switch SW1 and 2nd switch SW2. For this reason, for example, the abnormality determination process of the discharge resistors 26a and 26b can be performed at an arbitrary timing during the period when the motor generator 10 is driven.

(Third embodiment)
Hereinafter, the third embodiment will be described with reference to the drawings with a focus on differences from the second embodiment.

  In the present embodiment, the delay capacitor 32 is charged / discharged using a single switch.

  FIG. 6 shows a delay circuit 36 according to this embodiment. In FIG. 6, the same members as those shown in FIG. 4 are denoted by the same reference numerals for the sake of convenience.

  As shown in the drawing, the electrical path connecting the discharge resistor 26a side of the both ends of the series connection body of the discharge resistors 26a and 26b and the input terminal on the high potential side of the inverter 12 is opened and closed. Accordingly, a third switch SW3 that is energized is provided. The third switch SW3 is opened / closed by the microcomputer 30a via the insulation transmission means.

  Next, the abnormality determination process for the discharge resistors 26a and 26b according to the present embodiment will be described.

  In the present embodiment, the presence or absence of abnormality in the discharge resistors 26a and 26b is determined based on the rise time τa in a state where the third switch SW3 is in the closed state.

  FIG. 7 shows an example of an abnormality determination processing mode of the discharge resistors 26a and 26b according to the present embodiment. Specifically, FIGS. 7A and 7B correspond to FIGS. 5A and 5B.

  As illustrated, when the third switch SW3 is closed at time t1, charging of the delay capacitor 32 is started, and the abnormality determination voltage Vdelay starts to rise.

  Thereafter, the third switch SW3 is opened at time t2, so that the delay capacitor 32 is discharged in preparation for the next abnormality determination process.

  Here, in the present embodiment, the third switch SW3 is not normally closed. For this reason, it is possible to suppress power loss and heat generation of the discharge resistors 26a and 26b due to the constant flow of current through the discharge resistors 26a and 26b.

  Thus, in this embodiment, since the said 3rd switch SW3 is not normally closed, wasteful power consumption etc. of a power conversion system can be suppressed.

(Fourth embodiment)
Hereinafter, the fourth embodiment will be described with reference to the drawings with a focus on differences from the second embodiment.

  FIG. 8 shows a delay circuit 36 according to the present embodiment. In FIG. 8, the same members as those shown in FIG. 4 are denoted by the same reference numerals for the sake of convenience.

  As shown in the drawing, the second switch SW2 and the input terminal on the low potential side of the inverter 12 are connected via a resistor (reference resistor 38). The reference resistor 38 is provided in order to avoid a decrease in abnormality determination accuracy of the discharge resistors 26a and 26b due to a difference in the capacitance Ct of the delay capacitor 32.

  The capacitance Ct of the delay capacitor 32 is affected by various factors such as variations due to individual differences of the delay capacitors 32 and changes depending on the temperature of the delay capacitor 32. Here, if the capacitance Ct of the delay capacitor 32 is different, the rise time τa changes, and the abnormality determination accuracy of the discharge resistors 26a, 26b using this time τa may be lowered.

  In order to solve such a problem, in the present embodiment, when the first switch SW1 is opened and the second switch SW2 is closed, the abnormality determination voltage Vdelay starts to decrease. Based on the time ratio “τa / τb”, which is the ratio of the rise time τa to the time (fall time τb) until the voltage Vdelay reaches the second threshold voltage Vtl (<Vth), the discharge resistors 26a, 26b The abnormality judgment process is performed. Thereby, suppression of the fall of the determination precision of the presence or absence of abnormality of discharge resistor 26a, 26b is aimed at.

  FIG. 9 shows an abnormality determination processing mode of the discharge resistors 26a and 26b according to the present embodiment. Specifically, FIG. 9 (a) to FIG. 9 (c) correspond to the previous FIG. 5 (a) to FIG. 5 (c). In the present embodiment, the threshold voltage Vth in the second embodiment is referred to as a first threshold voltage Vth.

  In the present embodiment, the starting point (time t2) of the falling time τb is set as the closing timing of the second switch SW2. Here, the fall time τb is expressed by the following equation (e4), where the resistance value of the reference resistor 38 is Rref.

τb = −Ct × Rref × ln (Vtl / Va) (e5)
When the above equations (e4) and (e5) are used, the time ratio “τa / τb” is expressed by the following equation (e6).

τa / τb =
Rhl / Rref × ln (1-Vth / Va) / ln (Vtl / Va) (e6)
According to the above equation (e6), the time ratio “τa / τb” is not affected by the capacitance Ct of the delay capacitor 32. Therefore, according to the time ratio, even when the temperature of the delay capacitor 32 is changed, it is possible to determine whether or not the discharge resistors 26a and 26b are abnormal by eliminating these influences as much as possible. .

  Here, in this embodiment, the threshold voltages Vth, Vth, Vth, and Vth are set so that the sum of the first threshold voltage Vth and the second threshold voltage vtl becomes equal to the convergence voltage Va (so that “Va = Vth + Vtl”). Set Vtl. According to this setting, the above equation (e6) becomes the following equation (e7).

τa / τb = Rhl / Rref (e7)
As a specific abnormality determination method using the time ratio “τa / τb” represented by the above formula (e7), for example, the time ratio “τa / τb” is determined to be within a specified range. In this case, when it is determined that the discharge resistors 26a and 26b are normal and the time ratio “τa / τb” is determined to be less than the lower limit value of the specified range, a short circuit failure has occurred in the discharge resistors 26a and 26b. When it is determined that the time ratio “τa / τb” exceeds the upper limit of the specified range, it may be determined that an open failure has occurred in the discharge resistors 26a and 26b. Here, the specified range can be set as a fixed value, for example.

  As described above, in the present embodiment, by performing the abnormality determination process for the discharge resistors 26a and 26b based on the time ratio “τa / τb”, it is possible to suitably suppress a decrease in the abnormality determination accuracy of the resistors 26a and 26b. be able to.

(Fifth embodiment)
Hereinafter, a fifth embodiment will be described with reference to the drawings, focusing on differences from the first embodiment.

  FIG. 10 shows a delay circuit 36 according to this embodiment. In FIG. 10, the same members as those shown in FIG. 1 are denoted by the same reference numerals for the sake of convenience.

  In the present embodiment, the delay circuit 36 includes a discharge resistor 26 a and a reactor 40. In the present embodiment, the discharge resistor 26a is formed by connecting three or more parallel connections of a pair of resistors in series.

  Specifically, the series connection body of the discharge resistor 26 a and the reactor 40 is connected between the pair of input terminals of the inverter 12. Specifically, the discharge resistor 26a side of both ends of the series connection body is connected to the input terminal on the high potential side of the inverter 12, and the reactor 40 side is connected to the input terminal on the low potential side of the inverter 12. Yes.

  The delay circuit 36 outputs the voltage at the connection point of the discharge resistor 26a and the reactor 40 as the abnormality determination voltage Vdelay.

  Next, an abnormality determination processing mode of the discharge resistor 26a according to the present embodiment will be described with reference to FIG.

  In the present embodiment, the time (time t1 to t2) from when the precharging relay 20 closes (time t1) until the abnormality determination voltage Vdelay decreases to the threshold voltage Vth is defined as the falling time τc. Then, abnormality determination processing for the discharge resistor 26a is performed using the fall time τc. Here, the fall time τc is expressed by the following equation (e8), where the inductance of the reactor 40 is Lt.

τc = −Lt / Rh × ln (Vth / VL) (e8)
When an open failure occurs in any of the resistors constituting the discharge resistor 26a, the resistance value Rh of the discharge resistor 26a increases, so that the fall time τc is shortened. On the other hand, when a short circuit failure occurs in any of the resistors constituting the discharge resistor 26a, the fall time τc becomes longer because the resistance value Rh of the discharge resistor 26a decreases.

  Thus, in this embodiment, the abnormality determination process of the discharge resistor 26a can be appropriately performed by providing the delay circuit 36 including the reactor 40 in the power conversion system.

(Other embodiments)
Each of the above embodiments may be modified as follows.

  The method for determining whether or not the discharge resistor is abnormal is not limited to the method using the rise time τa or the fall time τb. For example, in the second embodiment, a method using the waveform of the abnormality determination voltage Vdelay during the charging period or discharging period of the delay capacitor 32 may be used. In this case, for example, a waveform of the abnormality determination voltage (reference waveform) assumed when the discharge resistor is normal in the charging period or discharging period of the delay capacitor 32 and the waveform of the actual abnormality determination voltage Vdelay. Based on the comparison, it is determined whether or not the discharge resistor is abnormal. More specifically, it may be determined that an abnormality has occurred in the discharge resistor based on the determination that the difference between the reference waveform and the actual abnormality determination voltage Vdelay is large.

  In the second embodiment, instead of directly detecting the change in potential (abnormality determination voltage Vdelay) at the intermediate point of the discharge path, the change in current (abnormality determination current Idelay) at the intermediate point is detected. Also good. In this case, for example, when the current flowing through the discharge resistor 26a (the total value of the current flowing through the pair of discharge resistors 26al and 26ar) is used as the abnormality determination current Idelay, the time t1 in FIG. 5 is used as a reference. The transition of the abnormality determination current Idelay is expressed by the following equation (e9).

Idelay = Va / Rh
× [Rh / Rl + exp {−t / (Ct × Rhl)}] (e9)
For this reason, the presence or absence of abnormality of the discharge resistor is determined based on the time from the time t1 until the abnormality determination current Idelay reaches a predetermined threshold value.

  In each of the above embodiments, the discharge resistor is configured by connecting two parallel connections of a pair of resistors in series, but the present invention is not limited to this. For example, the discharge resistor may be configured by connecting three or more of the parallel connection bodies in series. Further, for example, a series connection body of a plurality of resistors may be configured as a discharge resistor. Even in this case, since the rise time changes due to an abnormality occurring in any of the resistors constituting the discharge resistor, it is possible to determine whether or not the discharge resistor is abnormal.

  In each of the above embodiments, a smoothing capacitor may be connected between the high voltage battery 16 and the booster circuit 14. In this case, a delay circuit may be further provided between the high voltage battery 16 and the booster circuit 14.

  In the first embodiment, the abnormality determination process for the discharge resistors 26a and 26b may be performed when the inverter 12 is stopped. In this case, the abnormality determination process of the discharge resistors 26a and 26b is performed using the falling time τb starting from the timing when both the relay 18 and the precharge relay 20 are opened.

  In the fourth embodiment, the abnormality determination process may be performed using the time ratio “τa / τb” represented by the above equation (e6). Even in this case, if the specified range is variably set according to the input voltage VL to the delay circuit 36, it can be determined whether or not the discharge resistors 26a and 26b are abnormal.

  In the second embodiment, the electrical path connecting the discharge resistor 26a and the input terminal on the high potential side of the inverter 12 may be provided with opening / closing means (switch) that is energized to open / close this path. Good. According to such a configuration, for example, by not always closing the switch, it is possible to suppress wasteful power consumption or the like of the power conversion system due to the constant current flowing through the discharge resistor.

  Further, the position where the first switch SW1 is provided may be on an electrical path connecting the discharge resistor 26a and the input terminal on the high potential side of the inverter 12.

  In each of the above embodiments, the determination unit 34 determines whether or not the discharge resistor is abnormal. However, the present invention is not limited to this. For example, the determination unit 34 detects only the rise time τa and the fall time τb, transmits this information from the determination unit 34 to the microcomputer 30a via the insulation transmission means, and performs the abnormality determination process in the microcomputer 30a. Also good.

  -As a power converter circuit (inverter), it is not restricted to what is connected to the rotary machine mechanically connected with a driving wheel. For example, it may be connected to a rotating machine or the like built in a compressor of an air conditioner using the high voltage battery 16 as a direct power source. Further, for example, it may be a DCDC converter that steps down the voltage of the high voltage battery 16 and outputs it to the battery in the low voltage system.

  The power conversion circuit provided in the power conversion system is not limited to both the inverter 12 and the booster circuit 14. For example, only the inverter 12 may be provided.

  The vehicle to which the present invention is applied is not limited to a hybrid vehicle, and may be, for example, an electric vehicle or a fuel cell vehicle that does not include an internal combustion engine as an in-vehicle main engine.

  DESCRIPTION OF SYMBOLS 12 ... Inverter, 15 ... Capacitor, 16 ... High voltage battery, 18 ... Relay, 20 ... Precharge relay, 26a, 26b ... Discharge resistor, 30a ... Microcomputer, 32 ... Delay capacitor, S * # ... Switching element.

Claims (7)

A DC power supply, a power conversion circuit having a pair of input terminals and connected to the DC power supply via the pair of input terminals, a capacitor connected between the pair of input terminals, and the pair of inputs Applied to a system comprising a discharge path connected between terminals,
A capacitor discharge circuit comprising a delay circuit that delays and outputs a change in potential at an intermediate point of the discharge path.   The apparatus further comprises abnormality determining means for determining whether there is an abnormality in the discharge path based on a time from when the change of the output signal of the delay circuit is started until the output signal reaches a predetermined threshold value. The capacitor discharge circuit according to claim 1. The discharge path comprises a series connection of a plurality of resistors,
3. The capacitor discharge circuit according to claim 1, wherein the delay circuit further includes a delay capacitor, and the delay capacitor is connected in parallel to a part of the plurality of resistors. The discharge path is made of a resistor,
3. The capacitor discharge circuit according to claim 1, wherein the delay circuit further includes a reactor, and the reactor is connected in series to the resistor.   The delay circuit includes an electronically controlled first opening / closing means for opening / closing an electric path connecting the capacitor and the delay capacitor, a member having a voltage lower than a charging voltage of the delay capacitor, and the delay capacitor 4. The capacitor discharge circuit according to claim 3, further comprising electronically controlled second opening / closing means for opening / closing an electric path connecting the two.   6. The capacitor discharging circuit according to claim 5, wherein the delay circuit further includes a resistor in a member having a voltage lower than a charging voltage of the delay capacitor and an electric path connecting the delay capacitor.   When the first opening / closing means is in the closed state and the second opening / closing means is in the open state, the output signal becomes the first threshold after the change of the output signal of the delay circuit is started. The output time of the delay circuit when the first open / close means is opened and the second open / close means is closed. The capacitor according to claim 6, further comprising an abnormality determination unit that determines whether there is an abnormality in the resistor as the discharge path based on a ratio to a time until the signal reaches the second threshold value. Discharge circuit.

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