JP2013038608A - Bias circuit and amplification circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a bias circuit and an amplification circuit that can operate in a wide voltage range down to a low voltage and can set a temperature coefficient of a bias current.SOLUTION: The bias circuit provided includes a current generation circuit and a voltage generation circuit. The current generation circuit generates a first current on the basis of a voltage difference between forward voltages of two PN junctions different in junction area, and generates a second current having a temperature coefficient different in polarity from that of the first current on the basis of the forward voltage of the PN junction smaller in junction area of the two PN junctions. The voltage generation circuit generates a reference voltage from a current combining the first current and the second current.

Description

  Embodiments described herein relate generally to a bias circuit and an amplifier circuit.

  The bias circuit is a circuit that supplies a bias current and a bias voltage to an electronic circuit such as an amplifier circuit. For example, in a low noise amplifier circuit (LNA), a stable bias that does not depend on a power supply voltage or temperature can be supplied. Required. In addition, with the reduction in the voltage of electronic devices, the amplifier circuit and the bias circuit are also required to operate with a power supply voltage lower than the conventional operating voltage.

JP 2001-274636 A

  Embodiments of the present invention provide a bias circuit and an amplifier circuit that can operate in a wide voltage range up to a low voltage and can set a temperature coefficient of a bias current.

  According to the embodiment, there is provided a bias circuit including a current generation circuit and a voltage generation circuit. The current generation circuit generates a first current based on a voltage difference between the forward voltages of two PN junctions having different junction areas, and the PN junction in the order of PN junctions having a smaller area of the junction of the two PN junctions. Based on the directional voltage, a second current having a temperature coefficient having a polarity different from that of the first current is generated. The voltage generation circuit generates a reference voltage from a current obtained by combining the first current and the second current.

FIG. 3 is a circuit diagram illustrating the configuration of an amplifier circuit including a bias circuit according to the first embodiment. FIG. 6 is a circuit diagram illustrating the configuration of an amplifier circuit including a bias circuit according to a second embodiment. FIG. 6 is a circuit diagram illustrating the configuration of an amplifier circuit including a bias circuit according to a third embodiment. FIG. 10 is a circuit diagram illustrating the configuration of an amplifier circuit including a bias circuit according to a fourth embodiment. FIG. 9 is a circuit diagram illustrating the configuration of an amplifier circuit including a bias circuit according to a fifth embodiment.

  Hereinafter, embodiments will be described in detail with reference to the drawings. Note that, in the present specification and each drawing, the same elements as those described above with reference to the previous drawings are denoted by the same reference numerals, and detailed description thereof is omitted as appropriate.

First, the first embodiment will be described.
FIG. 1 is a circuit diagram illustrating the configuration of an amplifier circuit including a bias circuit according to the first embodiment.
A bias circuit (portion surrounded by a broken line 1) includes a current generating circuit (portion surrounded by a broken line 2) that generates a current, a reference voltage generating circuit (portion surrounded by a broken line 3) that generates a reference voltage, and a reference voltage. An output buffer circuit (a portion surrounded by a broken line 4) is provided. The amplifier circuit 5 includes a bias circuit 1 and an amplifier element (a portion surrounded by a broken line 6) that is supplied with the reference voltage Vbias0 from the bias circuit 1 and amplifies the high-frequency signal RFin. FIG. 1 illustrates a configuration in which the amplifying element 6 includes an HBT (heterojunction bipolar transistor) Q4.

The current generation circuit 2 generates the first current _IE based on the voltage difference between the forward voltages of two PN junctions having different junction areas, and based on the forward voltage of the PN junction having a small junction area. generating a second current _{I R} Te. Note that the polarity of the temperature coefficient is different between the first current and the second current. The base-emitter between the base and emitter of the first NPN transistor Q1 is used as a PN junction having a relatively large area of the junction, and the base-emitter of the second NPN transistor Q2 having a smaller emitter area than the first NPN transistor Q1. The gap is used as a PN junction having a relatively large area of the junction.

  The base of the first NPN transistor Q1 is connected to the collector of the first NPN transistor Q1, and the first NPN transistor Q1 is diode-connected. The emitter of the first NPN transistor Q1 is grounded. The base of the second NPN transistor Q2 is connected to the collector of the second NPN transistor Q2, and the second NPN transistor Q2 is diode-connected. The emitter of the second NPN transistor Q2 is grounded.

  The base and collector of the first NPN transistor Q1 are connected to one end of the first resistor R2. The other end of the first resistor R2 is connected to the drain of a P-channel MOSFET (hereinafter referred to as PMOS) M3. The source of the PMOS M3 is connected to the power supply Vcc. The base and collector of the second NPN transistor Q2 are connected to the drain of the PMOS M4, and the source of the PMOS M4 is connected to the power supply Vcc.

  A second resistor R3 is connected in parallel to the base and emitter of the second NPN transistor Q2. A third resistor R4 is connected in parallel to the first NPN transistor Q1 and the first resistor R2 connected in series. That is, the third resistor R4 is connected to the emitter of the first NPN transistor Q1 and the other end of the first resistor R2. The second resistor R3 and the third resistor R4 are the same type of resistors, have the same temperature coefficient, and have the same resistance value. The first resistor R2 is the same type of resistor as the second resistor R3 and the third resistor R4, and has the same temperature coefficient.

The inverting input terminal of the first operational amplifier EA1 (-), the forward voltage V ₂ between the base and emitter of the second NPN transistor Q2 is inputted. The non-inverting input terminal of the first operational amplifier EA1 (+), the composite voltage V ₁ of the forward voltage between the base-emitter voltage across the first resistor R2 and the first NPN transistor Q1 Is entered. The output of the first operational amplifier circuit EA1 is connected to the gates of PMOS M3 and M4.

Voltage generating circuit 3 generates a reference voltage V ₃ from the current I1 obtained by combining the first current I _E and the second current I _R. The voltage generation circuit 3 includes PMOSs M3 and M4 in the current generation circuit 2, a PMOS M5 having a current mirror configuration, and a reference transistor Q3 of the same type as the HBT Q4 of the amplification element 6. The source of the PMOS M5 is connected to the power supply Vcc, the gate is connected to the output of the first operational amplifier circuit EA1 of the current generation circuit 2, and the drain is connected to the base of the reference transistor Q3. Reference transistor Q3 has a base and a collector connected, the emitter base potential of the reference transistor Q3 is grounded, as the reference voltage V _3, is output to the buffer circuit 4.

Buffer circuit 4 outputs a reference voltage Vbias0 equal to the reference voltage _{V 3.} In the buffer circuit 4, the second operational amplifier circuit EA2, the PMOS MPo, and the resistor R6 constitute a current output type voltage follower circuit. Inverting input terminal of the second operational amplifier EA2 (-), the reference voltage V ₃ generated by the voltage generating circuit 3 is input. The voltage at the drain of the PMOS MPo is fed back to the non-inverting input terminal (+). The gate of the PMOS MPo is connected to the output of the first operational amplifier circuit EA1, and the source is connected to the power supply Vcc.

The voltage at the drain of the PMOS MPo is negatively fed back to the second operational amplifier circuit EA2 via the resistor R6. As a result, the drain of the PMOS MPo as the output of the buffer circuit 4 outputs a reference voltage Vbias0 equal to the reference voltage _{V 3.} The resistor R6 is inserted between the drain of the PMOS MPo and the input of the first operational amplifier circuit EA1 as an input protection element of the first operational amplifier circuit EA2.

Next, the operation of the bias circuit 1 will be described.
The bias circuit 1 generates a first current I _E and the second current I _R in the current generating circuit 2, the voltage generating circuit 3, synthesis of the first current I _E and the second current I _R generating a reference voltage _{V 3} from the current I1. Further, it is output from the buffer circuit 4 as a reference voltage Vbias0.

PMOS M3, M4 of the current generating circuit 2 forms a current mirror, the current _{I 1} generated by the PMOS M3 is equal to the current _{I 2} PMOS M4 generates.

Further, as described above, the inverting input terminal of the first operational amplifier EA1 (-), the forward voltage V ₂ between the base and emitter of the second NPN transistor Q2 is inputted. The non-inverting input terminal of the first operational amplifier EA1 (+), the composite voltage V ₁ of the forward voltage between the base-emitter voltage across the first resistor R2 and the first NPN transistor Q1 Is entered. The first operational amplifier circuit EA1 amplifies the voltage difference V ₁ −V ₂ and outputs the output voltage to the gates of the PMOS M3 and M4.

Therefore, the first operational amplifier circuit EA1 decreases the currents I ₁ and I ₂ generated by the PMOS M3 and M4 when the voltage difference V ₁ −V ₂ is increased, and the voltage difference V ₁ −V ₂ is decreased. The currents I ₁ and I ₂ generated by the PMOS M3 and M4 are increased. Further, when the currents I ₁ and I ₂ decrease, the voltage drop of the first resistor R ₂ decreases. Therefore, the voltage difference V ₁ -V ₂ decreases, and when the currents I ₁ and I ₂ increase, the first Since the voltage drop across the resistor R2 increases, the voltage difference V ₁ −V ₂ increases.
Therefore, the first operational amplifier circuit EA1 controls the gate voltages of the PMOSs M3 and M4 so that the voltage difference V ₁ −V ₂ between the combined voltage V ₁ and the forward voltage V ₂ becomes zero.

As described above, the resistance value of the second resistor R3, for equal resistance value of the third resistor R4, the current I _R flowing through the second resistor R3 is equal to the current flowing through the third resistor R4. The emitter current I _E1 of the first NPN transistor Q1 is equal to the emitter current I _{E2 of} the second NPN transistor Q2. Therefore, the emitter current of the first NPN transistor Q1 and the emitter current of the second NPN transistor Q2 are set as the first current _IE . The first current _IE does not depend on the voltage of the power supply Vcc and the PMOS M3 and M4.

The voltage difference ΔVF between the base-emitter forward voltage V2 of the _second NPN transistor Q2 and the base-emitter forward voltage of the first NPN transistor Q1 is the voltage across the first resistor R2. equal.
Therefore, the current _IE is expressed by the following equation (1), where S _E1 / S _E2 is the emitter area ratio of the first NPN transistor Q1 and the second NPN transistor Q2, and R ₂ is the resistance value of the first resistor R2. become that way.

ここで、Ｖ_Ｔは、熱電圧であり、ボルツマン定数をｋ、温度をＴ、電子の電荷をｑとして、Ｖ_Ｔ＝ｋＴ／ｑである。

Here, V _T is a thermal voltage, V _T = kT / q, where Boltzmann constant is k, temperature is T, and electron charge is q.

Further, a second resistor R3 and the third resistor R4 equal resistance value, since the voltage V ₁ and V ₂ is equal according to both ends, the second current I _R flowing through each of the resistors, the the resistance value of the second resistor R3 as _{R3, I R = V 2 /} R 3 , and the current _I 1 which combines the first current _{I E} and the second current _{I R} (= _{I 2)} is (2 )

Therefore, the variation of the current I ₁ and the temperature coefficient are respectively expressed by the equations (3) and (4). The variation is the variation of the resistance value R ₃ of the second resistor R ₃ , and the temperature coefficient is the proportional constant. the value of K, is determined by the value of the forward voltage V _2.

The condition for canceling the temperature dependence that causes the temperature coefficient of the current I ₁ to be zero is as shown in equation (5).

Therefore, the emitter areas of the first NPN transistor Q1 and the second NPN transistor Q2, and the value of the base-emitter voltage V ₂ determined by the first current I _E (= ΔVF / R ₂ ) as the emitter current, By adjusting the resistance ratio R ₃ / R ₂ to the value of the proportionality constant K determined by the voltage V ₂ , the temperature coefficient of the current I ₁ can be made zero. In the case for example, a temperature coefficient of the second resistor R3 is positive, to be greater than the value determined the resistance ratio R _{3 /} R ₂ in (5), positively the temperature coefficient of the current I ₁ The temperature coefficient of the current I ₁ can be made negative by decreasing the resistance ratio R ₃ / R ₂ .

Thus, the voltage difference ΔVF between the base-emitter voltages of two transistors having different emitter areas has a positive temperature coefficient, and the base-emitter voltage V ₂ has a negative temperature coefficient. As a result, in the current generation circuit 2, the first current _IE is generated based on the voltage difference ΔVF of the forward voltage of the PN junctions having different junction areas, and the junction area of the two PN junctions is small. generating a second current I _R having a temperature coefficient and polarity different temperature coefficient of the first current I _E on the basis of the forward voltage V ₂ of the PN junction. The temperature coefficient of the current I1 can be set to positive, 0, or negative by setting each current value.

Further, as described above, the current _{I E,} the current _{I R,} the voltage fluctuation of the power source Vcc, PMOS M3, M4 of the circuit components, does not depend on the characteristic variation of the first and second NPN transistors Q1, Q2. Further, in the current generation circuit 2, the voltage of the power supply Vcc is higher than the combined voltage of the base-emitter voltage V2 of the _second NPN transistor Q2 and the saturation voltage Vdsat between the source and drain of the PMOS M4. If it is high, it can operate. For example, it can operate with a low power supply voltage of about 1V.

In the voltage generation circuit 3, the output voltage of the first operational amplifier circuit EA1 is input to the gate of the PMOS M5. As described above, the characteristics of the PMOS M5 are the same as those of the PMOS M3 and M4 of the current generation circuit 2. Accordingly, PMOS M5 generates a current _I 1 (= _{I 2)} size ratio times the current _{I 3} that is generated by PMOS M3, M4 of the current generating circuit 2. Current _{I 3} is an amplifying device 6 flows through the same type of transistors Q3, to generate a reference voltage _{V 3.}

Buffer circuit 4 is a voltage follower current output, and inputs the reference voltage V ₃ generated by the voltage generating circuit 3 outputs a reference voltage Vbias0 equal to the reference voltage V _3.
The reference voltage Vbias0 is supplied to the base of the HBT Q4 of the amplifying element 6. The HBT Q4 generates a bias current Ibias (= I ₃ × S _EQ4 / S _EQ3 ) corresponding to the emitter area ratio (S _EQ4 / S _EQ3 ) times of the HBT Q4 and the reference transistor Q3.

  When viewed from the amplification element 6 side, the buffer circuit 4 is controlled by the operational amplifier circuit EA2 having a large voltage gain in the low frequency range, and can be regarded as a DC voltage source having a very small impedance. On the other hand, in the high frequency range, the voltage gain of the operational amplifier circuit EA2 becomes very small, and the constant current characteristic of the PMOS MPo appears. As a result, the loss of the high-frequency input signal RFin on the bias circuit 1 side is reduced, and the performance such as NF and gain of the single element of the amplifying element 6 can be easily extracted.

As described above, in the bias circuit 1, the first current _IE is generated based on the forward voltage difference ΔVF of the PN junctions having different junction areas, and the forward direction of the PN junction having the small junction area. and it generates a second current I _R having a polarity temperature coefficient different from the temperature coefficient of the first current I _E on the basis of the voltage V _2. Then, and it generates a reference voltage Vbias0 from current I1 obtained by combining the first current _{I E} and the second current _{I R.} As a result, the temperature coefficient of the current I1 can be set to positive, 0, and negative. In the amplifier circuit 5, the temperature similar to that of the current I1 is supplied to the amplifier element 6 supplied with the reference voltage Vbias0 as a bias voltage. A bias current Ibias having a coefficient can be generated.

In the bias circuit 1, the forward voltage _{V 2} between the base and emitter of the second NPN transistor Q2, the voltage of the power supply Vcc than the combined voltage of the saturation voltage Vdsat between the source and the drain of the PMOS M4 high Operation is possible, and low voltage operation is possible.

  In the bias circuit 1, the first NPN transistor Q1 and the second NPN transistor having a smaller emitter area than the first NPN transistor Q1, which are diode-connected as two PN junctions having different junction areas, are used. Q2 is used. However, a PNP transistor or a PN junction diode may be used. For example, when configured with BiCMOS, the diode of the NPN transistor is superior in characteristics and variations compared to the single diode, and thus the current range can be expanded. Further, for example, when it is configured by a parasitic PNP transistor, it can be realized by a CMOS process. The same applies to other embodiments described below.

  Moreover, in the bias circuit 1, the structure in which the amplifying element 6 has HBT Q4 is illustrated. However, when the amplifying element has a FET such as an NMOS, the reference transistor can be constituted by a FET in accordance with the amplifying element. The same applies to other embodiments described below.

Next, a second embodiment will be described.
FIG. 2 is a circuit diagram illustrating the configuration of an amplifier circuit including a bias circuit according to the second embodiment.
In the bias circuit 1a, the voltage generation circuit 3 of the bias circuit 1 shown in FIG. 1 is replaced with a voltage generation circuit 3a. The current generation circuit 2 and the buffer circuit 4 are the same as those of the bias circuit 1 in FIG. The amplifier circuit 5a includes a bias circuit 1a and an amplifier element 6a that is supplied with the reference voltages Vbias0 and Vbias1 from the bias circuit 1a and amplifies the high-frequency signal RFin. The amplifying element 6a has a cascode-structured HBT Q4 and an NMOS M7. In FIG. 2, the same elements as those in FIG. 1 are denoted by the same reference numerals.

The voltage generation circuit 3a is similar to the voltage generation circuit 3 shown in FIG. 1 in the same type as the PMOS M6 constituting the current mirror with the PMOS M3 and M4 of the current generation circuit 2, the resistor R5, and the NMOS M6 of the amplification element 6a. A reference transistor M18 and a bypass capacitor are added.
The source of the PMOS M6 is connected to the power supply Vcc, the gate is connected to the output of the first operational amplifier circuit EA1, and the drain is connected to one end of the resistor R5. The other end of the resistor R5 is connected to the gate and drain of the quasi-transistor M18. The source of the reference transistor M18 is grounded.

Since the output voltage of the first operational amplifier circuit EA1 that is the same as that of the PMOS M3, M4, and M5 is supplied to the gate of the PMOS M6, the PMOS M6 is multiplied by the size ratio of the current I1 generated by the PMOS M3 and M4. to generate a current _{I 3.} Current _{I 3} flows into the resistor R5 and the reference transistor M18, and generates a reference voltage Vbias1 to a connection point between the resistor R5 and the PMOS M6.

  The reference voltage Vbias1 is supplied to the gate of the NMOS M7 of the amplifier element 6. The connection point between the resistor R5 and the PMOS M6 is grounded via a bypass capacitor, and the NMOS M7 is grounded.

As described above, the bias circuit 1a can supply the biases Vbias0 and Vbias1 to the amplifying element 6 having the cascode-structured HBT Q4 and the NMOS M7. Further, since the bias is generated independently for the HBT Q4 and the NMOS M7, the wraparound of the input high-frequency signal RFin to the NMOS M7 can be reduced.
Other configurations, operations, and effects of the bias circuit 1a are the same as those of the bias circuit 1.

  In the bias circuit 1a, a configuration in which the amplifying element 6a includes a cascode-structured HBT Q4 and an NMOS M7 is illustrated. However, the amplifying element 6a may have another element, for example, a cascode configuration of HBT and HBT, or a cascode configuration of NMOS and NMOS. In accordance with this, the reference transistors Q3 and M18 of the voltage generation circuit 3a can also be composed of HBT and HBT, NMOS and NMOS. The same applies to other embodiments described below.

  The bias circuit 1a generates the reference voltage Vbias0 and the reference voltage Vbias1 independently. However, it is also possible to connect the resistor R5 between the reference transistor Q3 and the NMOS M5 and generate the reference voltage Vbias0 and the reference voltage Vbias1 at both ends of the resistor R5, respectively. The same applies to other embodiments described below.

Next, a third embodiment will be described.
FIG. 3 is a circuit diagram illustrating the configuration of an amplifier circuit including a bias circuit according to the third embodiment.
A bias circuit (portion surrounded by a broken line 1b) is a current generating circuit (portion surrounded by a broken line 2a) that generates a current, a reference voltage generating circuit that generates a reference voltage (portion surrounded by a broken line 3b), and outputs a reference voltage A buffer circuit (a portion surrounded by a broken line 4).

The amplifier circuit 5b includes a bias circuit 1b and an amplifier element (a portion surrounded by a broken line 6) that is supplied with the reference voltage Vbias0 from the bias circuit 1b and amplifies the high-frequency signal RFin.
The buffer circuit 4 and the amplifying element 6 are the same as the buffer circuit 4 and the amplifying element 6 shown in FIG.

  The current generation circuit 2a includes a first NPN transistor Q5, a second NPN transistor Q6 having a smaller emitter area than the first NPN transistor Q5, a first resistor R2, and PMOSs M3 and M4. Yes. The first resistor R2 is connected in series with the first NPN transistor Q5.

  That is, the emitter of the first NPN transistor Q5 is connected to one end of the first resistor R2. The other end of the first resistor R2 is grounded. The collector of the first NPN transistor Q5 is connected to the drain and gate of the PMOS M3. The source of the PMOS M3 is connected to the power supply Vcc. The emitter of the second NPN transistor Q6 is set, and the collector is connected to the drain of the PMOS M4. The source of the PMOS M4 is connected to the power supply Vcc.

  The gate of the PMOS M3 is connected to the drain of the PMOS M3, the gate of the PMOS M4, and the non-inverting input terminal (+) of the first operational amplifier circuit EA1. The PMOS M3 and M4 constitute a current mirror CM1.

  The inverting input terminal (−) of the first operational amplifier circuit EA1 is connected to the drain of the PMOS M4 and the collector of the second NPN transistor Q6. The output of the first operational amplifier circuit EA1 is connected to the gate of the PMOS M8. The source of the PMOS M8 is connected to the power supply Vcc, and the drain is connected to the base of the first NPN transistor Q5, the base of the second NPN transistor Q6, and one end of the second resistor R3. The other end of the second resistor R3 is grounded.

  The voltage generation circuit 3b includes the PMOS M3 and M4 in the current generation circuit 2a, the PMOS M13 that forms the current mirror CM1, the PMOS M9 and the PMOS M9 that forms the current mirror, and the reference transistor of the same type as the HBT Q4 of the amplification element 6. Q3. The source of the PMOS M13 is connected to the power supply Vcc, and the gate is connected to the gate and drain of the PMOS M13. The source of the PMOS M9 is connected to the power supply Vcc, and the gate is connected to the output of the first operational amplifier circuit EA1. The drain of the PMOS M9 and the drain of the PMOS M13 are connected to the base and collector of the reference transistor Q3. The PMOS M13 is a PMOS having the same characteristics as the PMOS M3 and M4, and the PMOS M9 is a PMOS having the same characteristics as the PMOS M8.

Next, the operation of the bias circuit 1b will be described.
PMOS M3, M4 of the current generation circuit 2a, because it constitutes a current mirror is equal to the current _{I 2} generated by the current _{I 1} and PMOS M4 generated by the PMOS M3.
In addition, the first operational amplifier circuit EA1 includes a combined voltage obtained by combining the voltage across the first resistor R2 and the collector-emitter voltage of the first NPN transistor Q5, and the collector / emitter of the second NPN transistor Q6. The base voltage of the first NPN transistor Q5 and the base voltage of the second NPN transistor Q6 are controlled via the PMOS M8 and the second resistor R3 so that the voltage between the emitters becomes equal.

  That is, the first operational amplifier circuit EA1 combines the voltage across the first resistor R2 and the forward voltage between the base and emitter of the first NPN transistor Q5 and the second NPN transistor Q6. The common base voltage is controlled so that the forward voltage between the bases and the emitters becomes equal.

Accordingly, the current of the first NPN transistor Q5 and the first current _{I E} of the second NPN transistor Q6, the first current _{I E} and the second current _{I R} and the combined current through the second resistor R3 I ₁ (= I ₂ ) is expressed by equations (1) and (2) as in the bias circuit 1.

In the voltage generation circuit 3b, the gate of the PMOS M13 is connected to the gate of the PMOS M3, and the PMOS M13 forms a current mirror CM1 with the PMOS M3. Therefore, the PMOS M13 includes the first current I generated by the PMOS M3. A current that is twice the size ratio of _E is generated. The output voltage of the first operational amplifier circuit EA1 is input to the gates of the PMOS M8 and M9. Accordingly, PMOS M9 generates size ratio times the current of the current _{I R} of PMOS M8 generated.
Thus, the first current I _E and the second current I current and _R were synthesized I ₁ size ratio times the current I ₃ is the amplifier element 6 flows of the same type of reference transistors Q3, a reference voltage V ₃ Generate.

Buffer circuit 4a is a voltage follower current output, and inputs the reference voltage V ₃ generated by the voltage generating circuit 3b, and outputs the reference voltage Vbias0 equal to the reference voltage V _3.
The reference voltage Vbias0 is supplied to the base of the HBT Q4 of the amplifying element 6. The HBT Q4 generates a bias current Ibias (= I ₃ × S _EQ4 / S _EQ3 ) corresponding to the emitter area ratio (S _EQ4 / S _EQ3 ) times of the HBT Q4 and the reference transistor Q3.

  Therefore, the bias circuit 1b has the same effect as the bias circuit 1. In addition, since the resistance values of the second resistor R3 and the third resistor R4 in the bias circuit 1 define the bias current Ibias, high accuracy is required, and the circuit area increases. Therefore, since the bias circuit 1b does not have the third resistor R4 of the bias circuit 1, the circuit area can be reduced.

FIG. 4 is a circuit diagram illustrating the configuration of an amplifier circuit including a bias circuit according to the fourth embodiment.
The bias circuit (portion surrounded by a broken line 1c) outputs a current generation circuit (portion surrounded by a broken line 2b) that generates a current, a voltage generation circuit that generates a reference voltage (portion surrounded by a broken line 3c), and outputs a reference voltage. A buffer circuit (portion surrounded by a broken line 4) is provided.

The amplifier circuit 5c includes a bias circuit 1c and an amplifier element (a portion surrounded by a broken line 6a) that is supplied with the reference voltages Vbias0 and Vbias1 from the bias circuit 1c and amplifies the high-frequency signal RFin.
The buffer circuit 4 and the amplifying element 6a are the same as those in FIG.

  The current generation circuit 2b includes a first NPN transistor Q1, a second NPN transistor Q2 having a smaller emitter area (junction area) than the first NPN transistor Q1, PMOS M3, M4, M15, NMOS 14, , First and second resistors R2 and R3, and first and third operational amplifier circuits EA1 and EA3. The base of the first NPN transistor Q1 is connected to the collector of the first NPN transistor Q1, and the first NPN transistor Q1 is diode-connected. The emitter of the first NPN transistor Q1 is grounded. The base of the second NPN transistor Q2 is connected to the collector of the second NPN transistor Q2, and the second NPN transistor Q2 is diode-connected. The emitter of the second NPN transistor Q2 is grounded.

  The base and collector of the first NPN transistor Q1 are connected to one end of the first resistor R2. The other end of the first resistor R2 is connected to the drain of the PMOS M3. The source of the PMOS M3 is connected to the power supply Vcc. The base and collector of the second NPN transistor Q2 are connected to the drain of the PMOS M4, and the source of the PMOS M4 is connected to the power supply Vcc.

Inverting input terminal of the first operational amplifier EA1 (-), the forward voltage V ₂ between the base and emitter of the second NPN transistor Q2 is input. The non-inverting input terminal of the first operational amplifier EA1 (+), the composite voltage V ₁ of the forward voltage between the base-emitter voltage across the first resistor R2 and the first NPN transistor Q1 Entered. The output of the first operational amplifier circuit EA1 is connected to the gates of PMOS M3 and M4.

The third operational amplifier circuit EA3 constitutes a current output type voltage follower circuit through the NMOS M14. The non-inverting input terminal of the third operational amplifier EA3 (+), the forward voltage V ₂ between the base and emitter of the second NPN transistor Q2 is input. The inverting input terminal (−) of the third operational amplifier circuit EA3 is connected to the source of the NMOS M14 and one end of the second resistor R3, and the output of the third operational amplifier circuit EA3 is connected to the gate of the NMOS M14. The The drain of the NMOS M14 is connected to the drain and gate of the PMOS M15. The source of the PMOS M15 is connected to the power supply Vcc. The other end of the second resistor R2 is grounded. Third operational amplifier EA3 inputs the forward voltage V ₂ between the base and emitter of the second NPN transistor Q2, and outputs a voltage equal the forward voltage V ₂ to the second resistor R3.

  As described above, the current generation circuit 2b deletes the second resistor R3 and the third resistor R4 in the previous stage of the first operational amplifier circuit EA1 in the current generation circuit 2 illustrated in FIG. The second resistor R3 is connected via a voltage follower constituted by the operational amplifier circuit EA3.

  The voltage generation circuit 3c is configured by adding PMOS M16 and M17 to the voltage generation circuit 3a shown in FIG. The source of the PMOS M16 is connected to the power supply Vcc, the drain is connected to the drain of the PMOS M5, and the gate is connected to the gate and drain of the PMOS M15. The source of the PMOS M17 is connected to the power supply Vcc, the drain is connected to the drain of the PMOS M6, and the gate is connected to the gate and drain of the PMOS M15.

Next, the operation of the bias circuit 1c will be described.
The operation of the current generation circuit 2b is the same as that of the current generation circuit 2 shown in FIG. 1, and the current of the first NPN transistor Q1, the first current I _{E of} the second NPN transistor Q2, and the first current I _E and the current _I 1 obtained by synthesizing the second current _{I R} flowing through the second resistor R3 (= _{I 2),} similar to the bias circuit 1 (1) and (2) below.

The currents generated by the PMOS M3 and M4 are equal to the first current _IE of the first NPN transistor Q1 and the second NPN transistor Q2. The current flowing through the PMOS M15 is equal to the second current _{I R} flowing through the second resistor R3.

Voltage generator 3c generates the first current _{I E} and the second current _{I R} and the size ratio times the current I3 of the combined current _{I 1} to a PMOS M5, M16, is flowing in the reference transistor Q3 . Reference transistor Q3 generates the reference voltage _{V 3,} via a buffer circuit 4a, and outputs to the amplifying element 6a as the reference voltage VBIAS0. Further, to generate a first current _{I E} and the second current _{I R} and the size ratio times the current I3 of the combined current _{I 1} to a PMOS M6, M17, is flowing in the reference transistor M18 and the resistor R5. A reference voltage Vbias1 is generated in the resistor R5.

  Therefore, the bias circuit 1c has the same effect as the bias circuit 1a. Further, since the bias circuit 1c does not have the third resistor R4 like the bias circuit 1b, the circuit area can be reduced.

FIG. 5 is a circuit diagram illustrating the configuration of an amplifier circuit including a bias circuit according to the fifth embodiment.
The bias circuit 1d is configured by replacing the voltage generation circuit 3c of the bias circuit 1c shown in FIG. 4 with a voltage generation circuit 3d. The amplifying circuit 5d includes a bias circuit 1d and an amplifying element (a portion surrounded by a broken line 6b) that is supplied with the reference voltages Vbias0 and Vbias1 from the bias circuit 1d and amplifies the high-frequency signal RFin. The current generating circuit 2b, the buffer circuit 4, and the starting circuit 5a are the same as those in FIG.

The amplifying element 6b has cascode-structured HBTs Q4 and Q6. Therefore, the voltage generation circuit 3d is configured by replacing the NMOS M18 of the voltage generation circuit 3c with HBT Q7.
Therefore, the operation of the bias circuit 1d is the same as that of the bias circuit 1c, and the bias circuit 1d has the same effect as the bias circuit 1c.

  Although some embodiments of the present invention have been described, these embodiments are presented as examples, and the scope of the invention is not limited to these embodiments. These novel embodiments can be implemented in various other forms, and various omissions, replacements, and changes can be made without departing from the scope of the invention. These embodiments and modifications thereof are included in the scope and gist of the invention, and are included in the invention described in the claims and the equivalents thereof.

  1, 1a, 1b, 1c, 1d ... bias circuit, 2, 2a, 2b ... current generation circuit, 3, 3a, 3b, 3c, 3d ... voltage generation circuit, 4, 4a ... buffer circuit, 5, 5a, 5b, 5c, 5d ... amplifier circuit, 6, 6a, 6b ... amplifier element, CM1 ... current mirror, EA1 ... first operational amplifier circuit, EA2 ... second operational amplifier circuit, EA3 ... third operational amplifier circuit, M1- M6, M8 to M13, M15 to M17, MPO ... P-channel MOSFET (PMOS), M7, M14 ... N-channel MOSFET (NMOS), M18, Q3, Q7 ... Reference transistor, Q1, Q5 ... First bipolar transistor Q2, Q6 ... second bipolar transistor, Q4, Q8 ... HBT, R1, R6 ... resistor, R2 ... first resistor, R3 ... second Resistance, R4 ... the third resistor

Claims (8)

A first current is generated based on a voltage difference between forward voltages of two PN junctions having different junction areas, and based on a forward voltage of a PN junction having a smaller junction area of the two PN junctions. A current generation circuit for generating a second current having a temperature coefficient having a polarity different from that of the first current;
A voltage generation circuit that generates a reference voltage from a current obtained by combining the first current and the second current;
A bias circuit comprising: The current generation circuit includes:
A first bipolar transistor;
A first resistor connected in series to the first bipolar transistor;
A second bipolar transistor having a junction area smaller than that of the first bipolar transistor and having a current equal to that of the first bipolar transistor;
A second resistor for generating a second current by supplying a forward voltage between a base and an emitter of the second bipolar transistor at both ends;
Have
The combined voltage of the voltage across the first resistor and the forward voltage between the base and the emitter of the first bipolar transistor is equal to the forward voltage between the base and the emitter of the second bipolar transistor. The bias circuit according to claim 1, wherein the first current is generated by controlling a current value of a current flowing through the first bipolar transistor and the second bipolar transistor. A base of the first bipolar transistor is connected to a collector of the first bipolar transistor;
3. The bias circuit according to claim 2, wherein a base of the second bipolar transistor is connected to a collector of the second bipolar transistor. A base of the first bipolar transistor is connected to a base of the second bipolar transistor;
3. The bias circuit according to claim 2, wherein a forward voltage between a base and an emitter of the second bipolar transistor is controlled to make the first voltage equal to the second voltage.   5. The bias circuit according to claim 2, wherein the second resistor is connected to a base and an emitter of the second bipolar transistor.   5. The bias circuit according to claim 2, wherein the second resistor is connected to a base and an emitter of the second bipolar transistor via a voltage follower.   The voltage generation circuit further generates a voltage higher than the reference voltage from a current obtained by combining the first current and the second current. The bias circuit described. A bias circuit according to any one of claims 1 to 7,
An amplifying element supplied with the reference voltage as a bias;
An amplifier circuit comprising:

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