JP2015114815A - Reference voltage circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a reference voltage circuit which can improve rise characteristics.SOLUTION: A reference voltage circuit 101 includes a bandgap reference circuit 1, a comparator 2, and a start-up circuit 3. The comparator 2 compares an output voltage Vref of the bandgap reference circuit 1 with a predetermined voltage V1 set to a value lower than a desired reference voltage. The start-up circuit 3 generates a start-up current in the bandgap reference circuit 1 on the basis of the comparison result by the comparator 2.

Description

  Embodiments described herein relate generally to a reference voltage circuit.

Conventionally, as a reference voltage generation source of a reference voltage circuit, a band gap reference circuit using a difference in temperature characteristics between a base-emitter voltage V _BE and a thermal voltage Vt of a silicon (Si) bipolar transistor is used. When a silicon bipolar transistor is used, a reference voltage of about 1.2 V, which is close to the silicon band gap of about 1.2 eV, can be obtained.

In general, in a bandgap reference circuit, a difference in V _BE between two bipolar transistors having different emitter areas and a voltage drop caused by a resistance connected to the two transistors are amplified by a differential amplifier, and the input voltage of the differential amplifier is amplified. The current of the bipolar transistor is controlled so as to be equal.

  However, immediately after the power is turned on, no current flows through the bandgap reference circuit, and there is no difference in the input voltage of the differential amplifier. Therefore, the differential amplifier becomes stable, and the bandgap reference circuit cannot enter the original operation state. Therefore, in a reference voltage circuit using the band gap reference circuit as a reference voltage generation source, it is necessary to allow a current to flow through the band gap reference circuit at the time of startup.

JP 2010-160700 A

  The problem to be solved by the present invention is to provide a reference voltage circuit capable of improving the rising characteristics.

  The reference voltage circuit according to the embodiment includes a band gap reference circuit, a comparator, and a starting circuit. The comparator compares the output voltage of the bandgap reference circuit with a predetermined voltage set to a value lower than a desired reference voltage. The starting circuit generates a starting current in the band gap reference circuit based on the comparison result of the comparator.

FIG. 3 is a circuit diagram showing an example of a configuration of a reference voltage circuit according to the first embodiment. The figure which shows the mode of generation | occurrence | production of starting current, and the change of a reference voltage output. The circuit diagram which shows the example of a structure of the reference voltage circuit of 2nd Embodiment. The circuit diagram which shows the example of a structure of the reference voltage circuit of 3rd Embodiment.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. In the drawings, the same or corresponding parts are denoted by the same reference numerals, and the description thereof will not be repeated.

(First embodiment)
FIG. 1 is a circuit diagram illustrating an example of the configuration of the reference voltage circuit according to the first embodiment.

  The reference voltage circuit 101 of the present embodiment includes a band gap reference circuit 1 and a comparator 2 that compares the output voltage Vref of the band gap reference circuit 1 with a predetermined voltage V1 set to a value lower than a desired reference voltage. And a starting circuit 3 for generating a starting current Ist in the bandgap reference circuit 1 based on the comparison result of the comparator 2.

  The reference voltage circuit 101 includes a PMOS transistor Q1 and a current source I1 that generate a bias current to be supplied to the bandgap reference circuit 1, the comparator 2, and the starting circuit 3.

  The bandgap reference circuit 1 includes npn transistors T1 and T2 that are diode-connected together, a resistor R1 connected between the npn transistor T1 and the output terminal OUT, and an npn transistor T2 and the output terminal OUT. And resistors R2 and R3 connected to each other.

Here, the npn transistor T1 and the npn transistor T2 have an emitter area ratio of 1: N (N> 1). Further, since it is used as a diode, h _FE may be low and can be formed by a CMOS process.

  The bandgap reference circuit 1 includes a differential circuit 11 to which a potential at a connection point between the npn transistor T1 and the resistor R1 and a potential at a connection point between the resistors R2 and R3 are input, and an output of the differential circuit 11 And an NMOS transistor N1 connected between the input voltage power supply VIN and the output terminal OUT and whose conduction is controlled by the amplifier 12.

  Here, as an example of the differential circuit 11, a differential pair constituted by PMOS transistors P11 and P12 and NMOS transistors N11 and N12, a PMOS transistor Q1 and a current mirror circuit are formed, and a bias is applied to the differential pair. An example of a circuit having a PMOS transistor Q11 for supplying current will be shown.

  The NMOS transistors N11 and N12 form a current mirror, and the potential at the connection point between the npn transistor T1 and the resistor R1 is input to the gate terminal of the PMOS transistor P11, and the connection point between the resistors R2 and R3 is connected to the gate terminal of the PMOS transistor P12. Is input.

  As an example of the amplifier 12, an NMOS transistor N13 in which the output of the differential circuit 11 is input to the gate terminal, a PMOS transistor Q1 that forms a current mirror circuit with the PMOS transistor Q1, and a PMOS transistor Q12 that supplies a bias current to the NMOS transistor N13; An example of a circuit having

  The capacitor Cc and the resistor Rc connected between the output terminal and the input terminal of the amplifier 12 are a phase compensation circuit for preventing oscillation.

  In the above-described configuration, by appropriately setting the ratio of the resistors R1 and R2 and the ratio of the resistors R3 and R2, the bandgap reference circuit 1 can set the output voltage Vref to a voltage based on the silicon bandgap, approximately It can be controlled to 1.2V. As a result, the output voltage Vref of the bandgap reference circuit 1 becomes a constant voltage even if the potential of the input voltage power supply VIN varies.

  However, when the input voltage power supply VIN is activated, no current flows through the npn transistors T1 and T2, so that there is no voltage level difference between the differential inputs of the differential circuit 11, and the differential circuit 11 becomes stable. As a result, no operating current flows through the band gap reference circuit 1.

  Therefore, in the present embodiment, the comparator 2 and the starting circuit 3 are provided so that the starting current for starting operation flows in the band gap reference circuit 1 when the input voltage power source VIN is started.

  The comparator 2 forms a differential pair composed of PMOS transistors P21 and P22 and NMOS transistors N21 and N22, a PMOS transistor Q1 and a current mirror circuit, and supplies a bias current to the differential pair. Q21.

  The output voltage Vref of the bandgap reference circuit 1 is input to the gate terminal of the PMOS transistor P22, and the gate terminal of the PMOS transistor P21 is set to a voltage lower than the value during normal operation (about 1.2V). A predetermined voltage V1 is input.

  The predetermined voltage V1 is generated using, for example, a forward voltage of a diode. In this case, since the forward voltage of the diode is about 0.8V, V1≈0.8V.

  The PMOS transistor P21 has a source terminal connected to the drain terminal of the PMOS transistor Q21 and a drain terminal connected to the drain terminal of the NMOS transistor N21.

  The PMOS transistor P22 has a source terminal connected to the drain terminal of the PMOS transistor Q21, and a drain terminal connected to the drain terminal of the NMOS transistor N22.

  A connection point between the drain terminal of the PMOS transistor P22 and the drain terminal of the NMOS transistor N22 is an output terminal of the comparator 2.

  NMOS transistors N21 and N22 have their source terminals connected to ground terminal GND and their gate terminals connected to the drain terminal of NMOS transistor N21 to form a current mirror circuit.

  The startup circuit 3 includes an NMOS transistor N31 to which the output of the comparator 2 is input.

  The NMOS transistor N31 has a gate terminal connected to the output terminal of the comparator 2, a source terminal connected to the ground terminal GND, and a drain terminal serving as the output terminal of the starting circuit 3.

  In the present embodiment, the output terminal of the activation circuit 3 is connected to the gate terminal of the NMOS transistor N13 of the amplifier 12 of the bandgap reference circuit 1.

  Next, operations of the comparator 2 and the starting circuit 3 will be described.

  Immediately after the input voltage power supply VIN is activated, the output voltage Vref of the bandgap reference circuit 1 is lower than the predetermined voltage V1. For this reason, the PMOS transistor P22 of the comparator 2 is turned on, and an H (high) level signal is output from the comparator 2. As a result, the NMOS transistor N31 of the activation circuit 3 is turned on, and the output terminal of the activation circuit 3 becomes L (low) level.

  The output terminal of the activation circuit 3 is connected to the gate terminal of the NMOS transistor N13 of the amplifier 12 of the bandgap reference circuit 1. For this reason, the NMOS transistor N13 is forcibly turned off, and the output of the amplifier 12 becomes H level.

  As a result, the NMOS transistor N1 is turned on, and the starting current Ist is applied from the input voltage power source VIN to the npn transistors T1 and T2.

  By applying the starting current Ist, the bandgap reference circuit 1 starts operating, and the output voltage Vref gradually increases.

  Thereafter, when the value of the output voltage Vref reaches the predetermined voltage V1, the PMOS transistor P22 of the comparator 2 is turned off, and the output of the comparator 2 changes to the L level. As a result, the NMOS transistor N31 is turned off and no current flows through the starting circuit 3.

  As a result, the amplifier 12 of the bandgap reference circuit 1 is not controlled by the starting circuit 3 and the starting current Ist does not flow.

  FIG. 2 is a waveform diagram showing how the starting current Ist is generated after the input voltage power source VIN is started and how the output voltage Vref is changed.

  As shown in FIG. 2, a large current flows in the starting current Ist until the output voltage Vref reaches a predetermined voltage V1. On the other hand, after the output voltage Vref exceeds the predetermined voltage V1, only the current consumed by the bandgap reference circuit 1 flows.

  After the output voltage Vref exceeds the predetermined voltage V1, the bandgap reference circuit 1 performs an operation of keeping the output voltage Vref constant by internal feedback control.

  According to this embodiment, the band gap reference circuit is connected via the NMOS transistor N1 by forcibly operating the amplifier 12 by the starting circuit 3 until the value of the output voltage Vref reaches the predetermined voltage V1. The starting current Ist can be applied to 1. Thereby, the rising characteristic of the output voltage Vref can be improved.

  In addition, after the value of the output voltage Vref reaches the predetermined voltage V1, the starting current does not flow, and generation of extra current consumption can be suppressed.

(Second Embodiment)
FIG. 3 is a circuit diagram illustrating an example of the configuration of the reference voltage circuit according to the second embodiment.

  In the reference voltage circuit 102 according to the present embodiment, an amplification stage is added before the NMOS transistor N31 of the activation circuit 3 of the reference voltage circuit 101 according to the first embodiment to form an activation circuit 3A. In addition, since the signal level is inverted by the above-described amplification stage, the comparator 2 of the first embodiment is replaced with a comparator 2A in which the output level is inverted.

  The activation circuit 3A includes an amplification stage including an NMOS transistor N32 and a PMOS transistor Q31 in front of the NMOS transistor N31 of the activation circuit 3.

  In the NMOS transistor N32, the output of the comparator 2A is input to the gate terminal, and the drain terminal is connected to the drain terminal of the PMOS transistor Q31.

  The PMOS transistor Q31 forms a current mirror circuit with the PMOS transistor Q1, and supplies a bias current to the NMOS transistor N32.

  A connection point between the drain terminal of the NMOS transistor N32 and the drain terminal of the PMOS transistor Q31 is connected to the gate terminal of the NMOS transistor N31.

  In the comparator 2A, the gate terminals of the NMOS transistor N21 and the NMOS transistor N22 are both connected to the drain terminal of the NMOS transistor N22. A connection point between the drain terminal of the PMOS transistor P21 and the drain terminal of the NMOS transistor N21 is an output terminal.

  According to the present embodiment as described above, the output signal of the comparator 2A is amplified by the amplification stage of the activation circuit 3A, so that the change in the output of the activation circuit 3A is accelerated and the bandgap reference circuit 1 is activated earlier. be able to.

(Third embodiment)
In the first and second embodiments described above, the example in which the amplifier in the bandgap reference circuit is forcibly operated to generate the start-up current has been described. An example in which a starting current is generated by forcibly operating a dynamic circuit will be described.

  FIG. 4 is a circuit diagram illustrating an example of the configuration of the reference voltage circuit according to the third embodiment.

  The reference voltage circuit 103 of the present embodiment is different from the reference voltage circuit 101 of the first embodiment in that the start circuit 3 is replaced with a start circuit 3B, and the output terminal of the start circuit 3B is connected to the band gap reference circuit 1. This is the point that the connection to the differential circuit 11 is made.

  The starting circuit 3B includes a PMOS transistor Q31 having a drain terminal connected to the drain terminal of the NMOS transistor N31 constituting the starting circuit 3, a PMOS transistor P31 having a drain terminal connected to the gate terminal, and a PMOS transistor P31. A PMOS transistor Q32 having a drain terminal connected to the source terminal is added.

  The PMOS transistor Q31 forms a current mirror circuit with the PMOS transistor Q1, and supplies a bias current to the NMOS transistor N31.

  Similarly, the PMOS transistor Q32 forms a current mirror circuit with the PMOS transistor Q1, and supplies a bias current to the PMOS transistor P31.

  The drain terminal of the PMOS transistor P31 is connected to the drain terminal of the NMOS transistor N12 of the differential circuit 11 of the bandgap reference circuit 1 and the gate terminals of the NMOS transistors N11 and N12.

  Next, the operation of the startup circuit 3B of this embodiment will be described.

  Immediately after the input voltage power supply VIN is activated, while the output voltage Vref is lower than the predetermined voltage V1, the output of the comparator 2 is at the H level as in the first embodiment. As a result, the NMOS transistor N31 is turned on, the gate terminal of the PMOS transistor P31 becomes L level, and the PMOS transistor P31 is turned on.

  As a result, a current is forcibly supplied to the NMOS transistor N12 of the differential circuit 11 via the PMOS transistor Q32.

  When a current flows through the NMOS transistor N12, a current also flows through the NMOS transistor N11 that forms a current mirror circuit with the NMOS transistor N12.

  As a result, the gate terminal of the NMOS transistor N13 of the amplifier 12 becomes L level, and the NMOS transistor N13 is turned off. Thereby, the output of the amplifier 12 becomes H level.

  Therefore, the NMOS transistor N1 is turned on, and the starting current Ist is applied from the input voltage power source VIN to the npn transistors T1 and T2.

  Also in the present embodiment, the starting current Ist flows only during a period when the output voltage Vref is lower than the predetermined voltage V1.

  According to the present embodiment, since the current is forcibly supplied to the differential circuit 11 when the input voltage power supply VIN is started, the operation of the differential circuit 11 can be started quickly, and the bandgap reference circuit 1 The output voltage Vref can be quickly brought close to a desired reference voltage.

  According to the reference voltage circuit of at least one embodiment described above, the rising characteristics can be improved.

  Moreover, although some embodiment of this invention was described, these embodiment is shown as an example and is not intending limiting the range of invention. These novel embodiments can be implemented in various other forms, and various omissions, replacements, and changes can be made without departing from the scope of the invention. These embodiments and modifications thereof are included in the scope and gist of the invention, and are included in the invention described in the claims and the equivalents thereof.

1 Bandgap reference circuit 2, 2A Comparator 3, 3A, 3B Start-up circuit 11 Differential circuit 12 Amplifier 101, 102, 103 Reference voltage circuit OUT Output terminals N1, N11, N12, N13, N21, N22, N31, N32 NMOS Transistors P11, P12, P13, P21, P22, P31, Q1, Q11, Q12, Q21, Q31, Q32 PMOS transistor T1, T2 npn transistors R1, R2, R3, Rc Resistor Cc Capacitor I1 Current source V1 Predetermined voltage

Claims (5)

A band gap reference circuit;
A comparator for comparing the output voltage of the bandgap reference circuit with a predetermined voltage set to a value lower than a desired reference voltage;
A reference voltage circuit comprising: a start circuit for generating a start current in the band gap reference circuit based on a comparison result of the comparator. The starting circuit is
2. The reference voltage circuit according to claim 1, wherein when the comparator detects that the output voltage is lower than the predetermined voltage, the band gap reference circuit generates the starting current. The band gap reference circuit is:
And a MOS transistor connected between the input power supply terminal and the output terminal of the bandgap reference circuit, and supplying the starting current to the output terminal of the bandgap reference circuit according to the control of the starting circuit. The reference voltage circuit according to claim 1 or 2. The bandgap reference circuit comprises an amplifier for driving the MOS transistor;
The starting circuit is
4. The reference voltage according to claim 3, wherein when the comparator detects that the output voltage is lower than the predetermined voltage, the amplifier is forcibly operated to make the MOS transistor conductive. circuit. The bandgap reference circuit includes an amplifier that drives the MOS transistor, and a differential circuit connected to a previous stage of the amplifier,
The starting circuit is
5. The MOS transistor according to claim 4, wherein when the comparator detects that the output voltage is lower than the predetermined voltage, the differential circuit is forcibly operated to make the MOS transistor conductive. Reference voltage circuit.