JP2013034058A - Oscillator circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To solve the problem of a conventional technology based oscillator circuit composed of a current source, a comparison circuit and an external capacitance that the accuracy of an oscillation frequency is degraded depending on the capacitance value of the external capacitance, giving rise to the need for extending a delay time according to a discharge time of the external capacitance which is determined by the capacitance value and a time constant of a resistance component for pulling out electric charge, because the discharge time is extended as the capacitance value increases, and that, conversely, if the capacitance value is small, the delay time becomes large relative to the cycle of an oscillation frequency, resulting in degradation of the accuracy of the oscillation frequency.SOLUTION: An oscillator circuit is provided with two external capacitances, which are charged and discharged alternately, so that the accuracy of an oscillation frequency is unaffected by a discharge time of electric charge built up in the external capacitances. This means that the accuracy of an oscillation frequency will in no case change depending on capacitance values of the external capacitances.

Description

  The present invention relates to an oscillation circuit and an oscillation method using the oscillation circuit, and more particularly to an oscillation circuit that oscillates a rectangular wave and an oscillation method using the oscillation circuit.

  A signal used for a clock signal or the like is required to have high accuracy in its frequency. Conventional techniques are known in which an oscillating circuit for generating such a signal includes a current source, a comparator, and a capacitor. In this conventional oscillation circuit, an external capacitor is used, but there is a problem that the accuracy of the oscillation frequency is deteriorated depending on the capacitance value.

  In relation to the above, Patent Document 1 (Japanese Patent Laid-Open No. 2006-148515) discloses a description relating to an oscillation circuit to which a delay circuit is applied. FIG. 1 is a circuit diagram showing a configuration of an oscillation circuit 40 described in Patent Document 1. As shown in FIG.

Components of the oscillation circuit 40 of FIG. 1 will be described. The oscillation circuit 40 of FIG. 1 includes a delay circuit unit 10 and a monostable multivibrator circuit unit 30. The delay circuit unit 10 compares the current source I01, the first to third N-channel MOS transistors M01 to M03, the first and second fuses F01 and F02, the capacitor C01, and the reference voltage power supply Vref0. A device CMP01 and an output unit OUT0 are provided. The monostable multivibrator circuit unit 30 includes a monostable multivibrator MV01, a capacitor C02, and a current source I02.

The connection relationship of the components of the oscillation circuit 40 in FIG. 1 will be described. One end of the current source I02 is connected to the first power supply Vdd0. The other end of the current source I02 is connected to one end of the capacitor C02. Both ends of the capacitor C02 are connected to two control ends of the monostable multivibrator MV01, respectively. The input part of the monostable multivibrator is connected to the output part OUT0. The output portion of the monostable multivibrator is commonly connected to the gates of the first to third N-channel MOS transistors M01 to M03.

  One end of the current source I01 is connected to the first power supply Vdd0. The other end of the current source I01 is a drain of the first N-channel MOS transistor M01, one end of each of the first and second fuses F01 and F02, and one end of the capacitor C01. Are commonly connected to a non-inverting input section in the comparator CMP01. The other end of the first fuse F01 is connected to the drain of the second N-channel MOS transistor M02. The other end of the second fuse F02 is connected to the drain of the third N-channel MOS transistor M03. The inverting input end of the comparator CMP01 is connected to one end of the reference voltage power supply Vref0. The second power supply Vss0 is commonly connected to the sources of the first to third N-channel MOS transistors M01 to M03, the other end of the capacitor C01, and the other end of the reference voltage power supply Vref0. ing. The output unit in the comparator CMP01 is connected to the output unit OUT0.

  The operation of the oscillation circuit 40 in FIG. 1 will be described. The current source I01 charges the capacitor C01. The monostable multivibrator MV01 supplies a control voltage to the gates of the first to third N-channel MOS transistors M01 to M03 provided in parallel. The state of this control voltage repeats high level and low level.

  In the first to third N-channel MOS transistors M01 to M03, a leak current flows between the drain and source when the control voltage supplied to the gate is at a high level. Due to this leakage current, the capacitor C01 connected between the drain and source of the first to third N-channel MOS transistors M01 to M03 is discharged.

  The comparator CMP01 compares the voltage of the capacitor C01 with the reference voltage Vref0, and outputs the resulting output voltage. Here, when the voltage of the capacitor C01 is higher than the reference voltage Vref0, the output voltage becomes high level, and in the opposite case, the output voltage becomes low level.

  The control voltage output from the monostable multivibrator MV01 becomes high level when the output voltage of the capacitor C01 changes from low level to high level. The state of the monostable multivibrator MV01 is maintained for a predetermined time determined by the capacitance of the capacitor C02 and the current of the current source I02. It is assumed that the control voltage output from the monostable multivibrator MV01 automatically returns to the low level after a predetermined time has elapsed since it became the high level.

  By repeating the high and low levels of the voltage output from the oscillation circuit 40, a pulsed oscillation signal is obtained.

  The predetermined time during which the state of the monostable multivibrator MV01 is maintained is preferably adjusted appropriately so that the discharge time of the capacitor C01 is sufficiently secured. Here, if the capacitor C01 is not sufficiently discharged, the pulse width of the oscillation signal will vary. This phenomenon will be described.

  First, operations expected in the oscillation circuit 40 shown in FIG. 1 will be described. FIG. 2A is a graph group illustrating an operation example expected in the oscillation circuit 40 illustrated in FIG. FIG. 2A includes two graphs (a) and (b). A graph (a) in FIG. 2A shows an example of a time change of the voltage of the control signal output from the monostable multivibrator circuit MV01 in the operation expected in the oscillation circuit 40 in FIG. A graph (b) in FIG. 2A shows an example of a temporal change in voltage between both ends of the capacitor C01 in an operation expected in the oscillation circuit 40 in FIG.

  2A, the horizontal axis indicates the passage of time, the vertical axis indicates the voltage of the control signal output from the monostable multivibrator circuit MV01, the period TA1 indicates the period of this control signal, and the period TA2 indicates a delay time from when this control signal falls to when it next rises.

  2A, the horizontal axis indicates the passage of time, the vertical axis indicates the voltage between both ends of the capacitor C01, the period TA3 indicates the discharge time of the capacitor C01, and the period TA4 indicates the charging of the capacitor C01. The voltage Vref0 indicates the voltage of the reference voltage power supply Vref0.

  As shown in the two graphs (a) and (b) of FIG. 2A, in the operation expected in the oscillation circuit 40 shown in FIG. 1, the period TA2 is equal to the period TA3, and the period TA1 is equal to the period TA3 and the period TA4. Is equal to the sum of Here, the discharge of the capacitor C01 is completed before the period TA3 ends. As a result, the period TA1, that is, the oscillation frequency is constant.

  Next, an operation when a problem occurs in the oscillation circuit 40 shown in FIG. 1 will be described. FIG. 2B is a graph group illustrating an operation example when a problem occurs in the oscillation circuit 40 illustrated in FIG. 1. FIG. 2B includes two graphs (a) and (b). The graph (a) of FIG. 2B shows an example of the time change of the voltage of the control signal output from the monostable multivibrator circuit MV01 in the operation when the problem occurs in the oscillation circuit 40 of FIG. A graph (b) in FIG. 2B shows an example of a time change in voltage between both ends of the capacitor C01 in an operation when a problem occurs in the oscillation circuit 40 in FIG.

  In the graph (a) of FIG. 2B, the horizontal axis indicates the passage of time, the vertical axis indicates the voltage of the control signal output from the monostable multivibrator circuit MV01, the period TB1 indicates the period of the control signal, and the period TB2 indicates a delay time from when this control signal falls to when it next rises.

  As shown in the two graphs (a) and (b) of FIG. 2B, in the operation when a problem occurs in the oscillation circuit 40 shown in FIG. 1, the period TB2 is equal to the period TB3, and the period TB1 is equal to the period TB3. And equal to the sum of periods TB4. Here, when the period TB3 is switched to the period TB4, the discharge of the capacitor C01 is not completed. The voltage of the capacitor C01 at this moment is shown in the graph (b) of FIG. 2B as the voltage V0. That is, in the example of FIG. 2B, charging starts with the charge remaining in the capacitor C01. As a result, the pulse width of the control signal output from the monostable multivibrator circuit MV01 varies, and the pulse width of the output signal output from the oscillation circuit 40 also varies.

  In order to avoid such variation, the oscillation circuit 40 described in Patent Document 1 performs the following control. That is, when the current value of the current source I01 is large, the pulse width of the control signal output from the monostable multivibrator MV01 is shortened, and the current value of the current source increases the output pulse width. Thus, an appropriate discharge time is ensured with respect to the delay time, and an oscillation circuit with high frequency accuracy is realized.

  As another method for avoiding the above-described variation, a method using an astable multivibrator described in Non-Patent Document 1 (Data sheet of CMOS Timer part number LMC555 manufactured by National Semiconductor) is known. FIG. 3 is a circuit diagram showing a configuration of an astable multivibrator as a semiconductor integrated circuit according to the prior art, which includes a comparison circuit, a current source, and a capacitor. FIG. 4 is a circuit diagram showing a configuration of an astable multivibrator as a circuit in which an external element is connected to the semiconductor integrated circuit of FIG. In the conventional astable multivibrator shown in FIGS. 3 and 4, when the two resistors RA and RB operate as current sources to charge and discharge the external capacitor C, a triangular wave is generated in the external capacitor C. Is done. At this time, the inclination of the triangular wave is controlled by the capacitance value of the external capacitor C, and the oscillation frequency is set.

  FIG. 5 is a graph group showing an operation example of the astable multivibrator shown in FIGS. 3 and 4. FIG. 5 includes two graphs (a) and (b). The graph (a) in FIG. 5 shows an example of the time change of the voltage of the signal output from the astable multivibrator circuit shown in FIGS. 3 and 4. The graph (b) in FIG. 5 shows an example of the time change of the voltage of the external capacitor C shown in FIGS. In each of the two graphs (a) and (b) in FIG. 5, the horizontal axis indicates the passage of time, and the vertical axis indicates the voltage change of each signal.

  Each graph of FIG. 5 shows a case where the astable multivibrator of FIGS. 3 and 4 operates under the following conditions as an example. That is, the power supply voltage is 5 V, the resistance RA is 3.9 kΩ, the resistance RB is 9 kΩ, the capacitance value of the external capacitor C is 0.01 μF, the horizontal axis is 20 μsec per scale, and the vertical axis of the graph (a) is one scale. The vertical axis of graph (b) is 1 V per division.

  While the voltage of the signal shown in the graph (a) of FIG. 5 is at a high level, the voltage of the external capacitor C shown in the graph (b) of FIG. 5 rises. On the contrary, while the voltage of the signal shown in the graph (a) of FIG. 5 is at a low level, the voltage of the external capacitor C shown in the graph (b) of FIG. 5 decreases.

JP 2006-148515 A

Data sheet of CMOS Timer part number LMC555 manufactured by National Semiconductor

  As described above, the conventional oscillation circuit including the current source, the comparison circuit, and the external capacitor has a problem that the accuracy of the oscillation frequency is deteriorated depending on the capacitance value of the external capacitor. The discharge time of the external capacitor is determined by the capacitance value and the time constant of the resistance component that extracts the charge. Therefore, when the capacitance value is large, the discharge time becomes long, and it is necessary to set the delay time to be long according to the discharge time. On the other hand, when the capacitance value is small, the delay time is relatively large with respect to the period of the oscillation frequency, so that the accuracy of the oscillation frequency is deteriorated.

  In order to increase the frequency accuracy, the two known techniques described above are known. However, in the method according to Patent Document 1, it is necessary to use a monostable multivibrator, and power consumption and layout area increase accordingly. Also in the method according to Non-Patent Document 1, the LMC 555 has two comparators and has a large layout area.

  The means for solving the problem will be described below using the numbers used in the (DETAILED DESCRIPTION). These numbers are added to clarify the correspondence between the description of (Claims) and (Mode for Carrying Out the Invention). However, these numbers should not be used to interpret the technical scope of the invention described in (Claims).

  The oscillation circuit according to the present invention includes a constant current source (IDD), a first capacitor (C1), a second capacitor (C2), a switching circuit unit (COMP, INV1, FF, INV2), a switch group ( SW1 to SW4). Here, the constant current source (IDD) supplies a constant current (I). The first capacitor (C1) is charged in the first state (Type-A) supplied with the constant current (I), and discharged in the second state (Type-B) that is short-circuited. A constant current (I) is supplied and charged in the second capacitor (C2) and the second state (Type-B), and short-circuited and discharged in the first state (Type-A). The switching circuit unit (COMP, INV1, FF, INV2) is applied with the voltage (VA) of the first capacitor (C1) in the first state (Type-A), and in the second state (Type-B). The voltage (VB) of the second capacitor (C2) is applied to generate rectangular waves (OSCCLK_C, B_DRV). The switch group (SW1 to SW4) switches between the first and second states (Type-A, Type-B) according to the rectangular wave (OSCCLK_C, B_DRV).

  In the oscillation method according to the present invention, in the step of supplying a constant current (I) and in the first state (Type-A), the first capacitor (C1) is charged with the constant current (I), and the second capacitor In the step of short-circuiting (C2) and discharging, and in the second state (Type-B), the second capacitor (C2) is charged with a constant current (I), and the first capacitor (C1) is short-circuited. The first capacitor (C1) voltage (VA) in the first state (Type-A) and the second capacitor (C2) voltage (VB) in the second state (Type-B). ) In accordance with the rectangular wave (OSCCLK_C, B_DRV) and switching between the first and second states (Type-A, Type-B) in accordance with the rectangular wave (OSCCLK_C, B_DRV). .

  According to the oscillation circuit and the oscillation method of the present invention, the accuracy of the oscillation frequency is not affected by the discharge time of the charge accumulated in the external capacitor. That is, the accuracy of the oscillation frequency does not change depending on the capacitance value of the external capacitor.

FIG. 1 is a circuit diagram showing a configuration of an oscillation circuit described in the patent document. FIG. 2A is a graph group showing an operation example expected in the astable multivibrator of FIGS. 3 and 4. FIG. 2B is a graph group showing an operation example when a problem occurs in the astable multivibrator of FIGS. 3 and 4. FIG. 3 is a circuit diagram showing a configuration of an astable multivibrator as a semiconductor integrated circuit according to the prior art, which includes a comparison circuit, a current source, and a capacitor. FIG. 4 is a circuit diagram showing a configuration of an astable multivibrator as a circuit in which an external element is connected to the semiconductor integrated circuit of FIG. FIG. 5 is a graph group showing an operation example of the astable multivibrator of FIGS. 3 and 4. FIG. 6 is a circuit diagram showing a configuration of the oscillation circuit according to the embodiment of the present invention. FIG. 7A is a circuit diagram showing an operation example in the first state of the oscillation circuit according to the embodiment of the present invention. FIG. 7B is a circuit diagram illustrating an operation example in the second state of the oscillation circuit according to the embodiment of the present invention. FIG. 8 is a circuit diagram showing a configuration in which an NMOS transistor or a CMOS transistor is used as four switches of the oscillation circuit according to the embodiment of the present invention. FIG. 9A is a graph group showing temporal changes of respective signals in the oscillation circuit according to the embodiment of the present invention. FIG. 9B is a graph group showing in detail the time change of some signals in the oscillation circuit according to the embodiment of the present invention.

  With reference to the attached drawings, embodiments for carrying out an oscillation circuit and an oscillation method according to the present invention will be described below.

(Embodiment)
FIG. 6 is a circuit diagram showing a configuration of the oscillation circuit according to the embodiment of the present invention. The components of the oscillation circuit of FIG. 6 will be described. The oscillation circuit of FIG. 6 includes a power supply VDD, a current source IDD, a reference voltage source VREF, first and second capacitors C1 and C2, first and second connection portions P1 and P2, 4th switch SW1-SW4, comparison circuit part COMP, 1st and 2nd inverter INV1 and INV2, frequency dividing circuit FF, 1st output node N1, and 2nd output node N2 are provided. doing. Each of the first to fourth switches SW1 to SW4 has first and second end portions and a control signal input portion. Because of the symmetry described later, the first and second capacitors C1 and C2 have the same capacitance value, the first and third switches SW1 and SW3 have the same characteristics, and the second and fourth switches SW2 and SW4 preferably have the same characteristics.

  Here, the first and second capacitors C1 and C2 are preferably external capacitors connected to the semiconductor integrated circuit including other components from the outside. However, this is only an example and does not limit the present invention.

  The connection relationship of the components of the oscillation circuit in FIG. 6 will be described. One end of the first capacitor C1 is grounded. The other end of the first capacitor C1 is connected to the first connection portion P1. The first connection portion P1 is connected to the first end portion of the first switch SW1 and the first end portion of the second switch SW2. The second end of the first switch SW1 is grounded. A second end of the second switch SW2 is connected to the first output node N1.

  One end of the second capacitor C2 is grounded. The other end of the second capacitor C2 is connected to the second connection portion P2. The second connection portion P2 is connected to the first end portion of the third switch SW3 and the first end portion of the fourth switch SW4. The second end of the third switch SW3 is grounded. The second end of the fourth switch SW4 is connected to the first output node N1.

  One end of the current source IDD is connected to the power supply VDD. The other end of the current source IDD is connected to the output node N. The output node N is connected to a first input unit in the comparison circuit COMP. A second input unit in the comparison circuit COMP is connected to one end of the reference voltage source VREF. The other end of the reference voltage source VREF is grounded. An output unit in the comparison circuit COMP is connected to an input unit in the first inverter INV. The output unit in the first inverter INV is connected to the input unit in the frequency dividing circuit FF. The output unit in the frequency dividing circuit FF is connected to the second output node N2.

  The second output node N2 is connected to a control signal input unit in the first switch SW1, a control signal input unit in the fourth switch SW4, and an input unit in the second inverter INV2. The output section of the second inverter INV2 is connected to the control signal input section of the second switch SW2 and the control signal input section of the third switch SW3.

  The operation of the components of the oscillation circuit of FIG. 6, that is, the oscillation method according to the embodiment of the present invention will be described. First, the current source IDD outputs a constant current I toward the first output node N1. Since no current flows into the first input section of the comparison circuit COMP, the constant current I flows toward the conductive state of the second switch SW2 or the fourth switch SW4.

  Next, the frequency dividing circuit FF is a flip-flop circuit in which the output signal is switched when the input signal rises from the low state to the high state. Here, the output signal of the frequency dividing circuit FF is referred to as a control signal B_DRV. The inverted signal of the signal B_DRV, that is, the output signal of the second inverter INV2 is referred to as a control signal A_DRV.

  When the control signal A_DRV is in a high state, that is, in an on state, the control signal B_DRV is in a low state, that is, in an off state. This state is hereinafter referred to as a first state or a Type-A state. Conversely, when the control signal B_DRV is in a high state, that is, an on state, the control signal A_DRV is in a low state, that is, an off state. This state is hereinafter referred to as a second state or a Type-B state.

  FIG. 7A is a circuit diagram showing an operation example in the first state of the oscillation circuit according to the embodiment of the present invention. In the first state, the second switch SW2 is turned on, that is, turned on in response to the control signal A_DRV. In addition, the fourth switch SW4 is turned off in response to the control signal B_DRV, that is, becomes a cut-off ground. Therefore, the constant current I charges the first capacitor C1 via the second switch SW2 and the first connection part P1. The voltage of the first capacitor C1 is referred to as voltage VA.

  At this time, since the first switch SW1 is in an off state, that is, in a cut-off state in accordance with the control signal B_DRV, charging of the first capacitor C1 is not hindered. On the other hand, the third switch SW3 is in an on state, that is, in a conductive state in response to the control signal A_DRV. Therefore, while the first capacitor C1 is being charged, the second capacitor C2 is short-circuited via the third switch SW3 and discharged.

  Here, the third switch SW3 is preferably an N-channel MOS transistor or the like. This is because the N-channel MOS transistor has a resistance component between the drain and the source when a low state signal is input to the gate and becomes conductive.

  FIG. 7B is a circuit diagram illustrating an operation example in the second state of the oscillation circuit according to the embodiment of the present invention. In the second state, the fourth switch SW4 is turned on, that is, in a conductive state in response to the control signal B_DRV. Further, the second switch SW2 is turned off, that is, becomes a cut-off ground according to the control signal A_DRV. Therefore, the constant current I charges the second capacitor C2 via the fourth switch SW4 and the second connection part P2. The voltage of the second capacitor C2 is referred to as voltage VB.

  At this time, since the third switch SW3 is in an off state, that is, in a cut-off state in accordance with the control signal A_DRV, charging of the second capacitor C2 is not hindered. On the other hand, the first switch SW1 is in an on state, that is, in a conductive state in response to the control signal B_DRV. Therefore, while the second capacitor C2 is being charged, the first capacitor C1 is short-circuited via the first switch SW1 and discharged.

  Here, the first switch SW1 is also preferably an N-channel MOS transistor or the like, like the third switch SW3.

  The second and fourth switches SW2 and SW4 are preferably CMOS transistors or the like. In the first place, the second and fourth switches SW2 and SW4 only switch the voltage VA or VB of the first or second capacitor C1 or C2 as a connection destination to the input voltage CMP_IN of the comparison circuit COMP. Therefore, as the second and fourth switches SW2 and SW4, a switch circuit having a minimum transistor size and a large on-resistance can be used. However, when the power supply voltage VDD is low, a switch circuit having an excessively high on-resistance may not be in an on state, that is, a conductive state, and the circuit operation may become unstable. Even in such a case, by using a switch circuit composed of a CMOS transistor having a low on-resistance, the switching between the on state and the off state of the second and fourth switches SW2 and SW4, that is, the conduction state and the cutoff state can be determined.

  FIG. 8 is a circuit diagram showing a configuration in which an N-channel MOS transistor or a CMOS transistor is used as the four switches SW1 to SW4 of the oscillation circuit according to the embodiment of the present invention. In the circuit diagram of FIG. 8, N-channel MOS transistors are used as the first and third switches, and CMOS transistors are used as the second and fourth switches. Here, due to the characteristics of the CMOS transistor, two control signals A_DRV and B_DRV are used as control signals in the second and fourth switches SW2 and SW4, respectively.

  FIG. 9A is a graph group showing temporal changes of respective signals in the oscillation circuit according to the embodiment of the present invention. The graph group in FIG. 9A includes first to ninth graphs (a) to (i). The first graph (a) in FIG. 9A shows the time change of the states in the first and fourth switches SW1 and SW4. The second graph (b) in FIG. 9A shows the time change of the states in the second and third switches SW2 and SW3. The third graph (c) in FIG. 9A shows the time change of the voltage VA of the first capacitor C1. The fourth graph (d) in FIG. 9A shows the time change of the voltage VB of the second capacitor C2. A fifth graph (e) in FIG. 9A shows a time change of the input signal CMP_IN in the comparison circuit COMP. The sixth graph (f) in FIG. 9A shows the time change of the output signal CMP_OUT in the comparison circuit COMP. The seventh graph (g) in FIG. 9A shows the time change of the output signal CMP_OUTB of the first inverter INV1. The eighth graph (h) in FIG. 9A shows the time change of the control signal A_DRV. The ninth graph (i) in FIG. 9A shows the time change of the control signal B_DRV.

FIG. 9B is a graph group showing in detail the time change of some signals in the oscillation circuit according to the embodiment of the present invention. The graph group in FIG. 9B includes first to fifth graphs (e) to (i). The first graph (e) in FIG. 9B shows in detail the time change of the input signal CMP_IN in the comparison circuit COMP. The second graph (f) in FIG. 9A shows in detail the time change of the output signal CMP_OUT in the comparison circuit COMP.
The third graph (g) in FIG. 9A shows in detail the time change of the output signal CMP_OUTB of the first inverter INV1.
The fourth graph (h) in FIG. 9A shows the time change of the control signal A_DRV in detail.
The fifth graph (i) in FIG. 9A shows the time change of the control signal B_DRV in detail.

As shown in the first and second graphs (a) and (b) of FIG. 9A, in the oscillation circuit according to the present embodiment, the first state (Type-A) and the second state (Type-B) are Occur alternately.
As shown in the third graph (c) of FIG. 9A, the voltage VA of the first capacitor C1 increases at a constant speed at the same time as the first state starts, and decreases at the same time as the second state starts.
Conversely, as shown in the fourth graph (d) of FIG. 9A, the voltage VB of the second capacitor C2 increases at a constant speed at the same time as the second state starts, and at the same time as the first state starts. Descend.
Here, it is desirable that the voltage VA of the first capacitor C1 rises to a voltage higher than the reference voltage VREF. Further, it is desirable that the voltage VB of the second capacitor C2 also rises to a voltage higher than the reference voltage VREF.

  When the first and second states are alternately switched, the conduction cut-off state of the second and fourth switches SW2 and SW4 is also switched, so that the input signal CMP_IN supplied to the first input unit in the comparison circuit COMP is A so-called “sawtooth wave” as shown in the fifth graph (e) of FIG. This sawtooth wave is a combination of a portion where the voltage VA of the first capacitor C1 rises in the first state and a portion where the voltage VB of the second capacitor C2 rises in the second state.

  The comparison circuit COMP compares the input signal CMP_IN with the reference voltage VREF, binarizes the result, and generates and outputs the output signal CMP_OUT shown in the sixth graph (f) of FIG. 9A. The operation of the comparison circuit COMP will be described with reference to the first and second graphs (e) and (f) of FIG. 9B. While the input signal CMP_IN is lower than the reference voltage VREF, the output signal CMP_OUT is in a high state. Conversely, while the input signal CMP_IN is higher than the reference voltage VREF, the output signal CMP_OUT is in a low state.

  The first inverter INV1 receives the output signal CMP_OUT of the comparison circuit COMP and generates and outputs a signal CMP_OUTB. As shown in the seventh graph (g) of FIG. 9A and the third graph (g) of FIG. 9B, the output signal CMP_OUTB is an inverted signal of the output signal CMP_OUT of the comparison circuit COMP.

  The frequency divider FF, which is a flip-flop circuit, receives the output signal CMP_OUTB of the first inverter INV1, and generates and outputs the control signal B_DRV. Here, as shown in the ninth graph (i) of FIG. 9A and the fifth graph (i) of FIG. 9B, the control signal B_DRV switches from the high state to the low state when the signal CMP_OUTB rises. Alternatively, if the control signal B_DRV is in the low state immediately before the signal CMP_OUTB rises, the control signal B_DRV switches from the low state to the high state at the rising timing.

  The second inverter INV2 receives the control signal B_DRV that is an output signal of the frequency dividing circuit FF, and generates and outputs the control signal A_DRV. Here, the control signal A_DRV is an inverted signal of the control signal B_DRV as shown in the eighth graph (h) of FIG. 9A and the fourth graph (h) of FIG. 9B.

  Here, according to the above-described symmetry, that is, the first and second capacitors C1 and C2 have the same capacitance value, the first and third switches SW1 and SW3 have the same characteristics, and the second and fourth capacitors If the switches SW2 and SW4 have the same characteristics, the time for which the first state and the second state each continue is the same length. As a result, an ideal sawtooth wave as shown in the fifth graph (e) of FIG. 9A is obtained at the first output node N1 as the input signal CMP_IN supplied to the comparison circuit COMP. Furthermore, an ideal rectangular wave as shown in the ninth graph (i) of FIG. 9A is obtained at the second output node N2 as the control signal B_DRV or the clock signal OSCCLK_C.

  In the oscillation circuit according to the present embodiment, the charges charged in the first and second capacitors C1 and C2 are short-circuited by the first and third switches SW1 and SW3, respectively, and are extracted as in the prior art. No significant error can occur. Therefore, the capacitance values of the first and second capacitors C1 and C2 do not affect the accuracy of the oscillation frequency. As a result, the oscillation circuit according to the present embodiment can provide a wider oscillatable band than the conventional technique even in the use range where the accuracy of the oscillation frequency is the same.

  Furthermore, as a circuit for drawing out charges charged in the first and second capacitors C1 and C2, in this embodiment, the restriction on the time for discharging charges is relaxed. More specifically, the charge may be pulled out from the second capacitor C2 while the first capacitor C1 is charged. Therefore, it is not necessary to reduce the on-resistance of the N-channel MOS transistor, and the layout area as a semiconductor integrated circuit can be reduced as compared with the prior art.

DESCRIPTION OF SYMBOLS 10 Delay circuit part 30 Monostable multivibrator circuit part 40 Oscillation circuit A_DRV, B_DRV Control signal C01, C02 Capacitor C1, C2 Capacitance CMP01 Comparator CMP_IN (COMP) input signal CMP_OUT (COMP) output signal CMP_OUTB (INV1) output Signal COMP Comparison circuit F01, F02 Fuse FF Frequency division circuit I01, I02 Current source INV1, INV2 Inverter M01-M03 (First to third) N-channel MOS transistors MV01 Monostable multivibrator N1, N2 Output node OSCCLK_C Rectangular wave OUT0 output unit P1, P2 connection unit VA (C1) voltage VB (C2) voltage VDD power supply VREF reference voltage, reference voltage source Vref0 reference voltage, reference voltage power supply SW1 to SW 4 switch

Claims (5)

A constant current source for supplying a constant current;
A first capacity charged in the first state supplied with the constant current and discharged in a second state shorted;
A second capacity to be charged by being supplied with the constant current in the second state and short-circuited to be discharged in the first state;
A switching circuit unit configured to generate a rectangular wave by applying a voltage of the first capacitor in the first state and applying a voltage of the second capacitor in the second state;
An oscillation circuit comprising: a switch group that switches the first and second states according to the rectangular wave. The oscillation circuit according to claim 1,
The slope of the sawtooth wave that is the voltage applied to the switching circuit unit in the first state is controlled by the current value of the constant current and the capacitance value of the first capacitor,
The slope of the sawtooth wave, which is the voltage applied to the switching circuit in the second state, is controlled by the current value of the constant current and the capacitance value of the second capacitor. The oscillation circuit according to claim 1 or 2,
The switch group includes:
A first switch that short-circuits the first capacitor in the second state;
A second switch for conducting the first capacitor to the constant current source and the switching circuit in the first state;
A third switch for short-circuiting the second capacitor in the first state;
An oscillation circuit comprising: a fourth switch that conducts the second capacitor to the constant current source and the switching circuit unit in the second state. The oscillation circuit according to claim 3,
Each of the first to fourth switches is
Comprising an N-channel MOS transistor that conducts or cuts off between a drain and a source according to a voltage of a signal supplied to a gate;
The switching circuit unit includes:
An oscillation circuit further comprising an inverter that supplies an inverted signal of the rectangular wave to the gate of the first or third switch. Supplying a constant current;
Charging the first capacitor with the constant current and short-circuiting the second capacitor in the first state; and
In a second state, charging the second capacity with the constant current, short-circuiting the first capacity and discharging;
Generating a rectangular group according to the voltage of the first capacitor in the first state and the voltage of the second capacitor in the second state;
A step of switching between the first state and the second state according to the rectangular wave.

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