JP2013033945A - Detection device and detection system - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a detection device with pixels each including an amplification TFT and a selection TFT, in which off-leak of the selection TFT is sufficiently reduced.SOLUTION: A detection device comprises: a conversion element 100; a first thin film transistor 110 having a gate 114 connected to the conversion element 100; and a second thin film transistor 120 having a gate 124 connected to a drive wiring 150. The second thin film transistor 120 includes a polycrystalline semiconductor layer which is an intrinsic semiconductor region, and has a third region 121 allowing an orthographic projection of the gate 124 to be located between a first region 122 and a second region 123. One of the first region 122 and the second region 123 is connected to one 113 of source and drain of the first thin film transistor 110. The polycrystalline semiconductor layer has a fourth region 125 and a fifth region 126 each having a lower concentration of impurities than the first region 122 and the second region 123, between the first region 122 and the third region 121, and between the second region 123 and the third region 121.

Description

  The present invention relates to a detection apparatus and a detection system applied to a medical diagnostic imaging apparatus, a nondestructive inspection apparatus, an analysis apparatus using radiation, and the like.

  Thin film semiconductor manufacturing technology is also used for detection devices such as light detection devices and radiation detection devices having an array of pixels (pixel array) in which switch elements such as TFTs (thin film transistors) and conversion elements such as photoelectric conversion elements are combined. ing. Particularly in recent years, in order to meet the demand for higher speed and higher sensitivity of the device, a detection device having an array of pixels (pixel array) using a polycrystalline semiconductor TFT as a switching element has been studied.

  In Patent Document 1, a plurality of pixels are provided, and each of the plurality of pixels is selected from a conversion element, a polycrystalline semiconductor amplification TFT, an amorphous or polycrystalline semiconductor reset TFT, and a polycrystalline semiconductor. A detection device having a TFT for use is disclosed. The gate of the amplification TFT is connected to the conversion element, and one of the source and the drain is connected to one of the source and the drain of the selection TFT. One of the source and drain of the reset TFT is connected to the conversion element and the gate of the amplifier TFT, and the other of the source and drain is connected to the power supply line. A reset driving wiring is connected to the gate of the reset TFT, and a pixel selecting driving wiring is connected to the gate of the selection TFT. The selection TFT has an LDD structure in which the gate electrode is overlapped only on the drain side, and measures are taken to reduce hot carrier injection and not to reduce the operation speed.

JP 2001-298663 A

  In the configuration of the selection TFT of the conventional detection device described above, the resistance value in the state where the non-conducting potential is supplied to the gate cannot be secured sufficiently, and even when it is desired to be non-conductive, the carrier of the selection TFT is The countermeasure against so-called off-leakage that cannot completely prevent the movement is not sufficient. Therefore, the signal output from the pixel supplied with the non-conducting potential to the gate of the selection TFT is superimposed on the signal output from the pixel supplied with the conducting potential to the gate of the selection TFT. In other words, so-called crosstalk may occur.

  The present invention is intended to solve the problem of such a conventional configuration, and in the detection device having a pixel including an amplification TFT and a selection TFT, the countermeasure against off-leakage of the selection TFT is improved. An object of the present invention is to provide a detection device.

  The detection device of the present invention includes a conversion element that converts radiation or light into electric charge, a first thin film transistor having a gate connected to the conversion element, a gate connected to a drive wiring, a first region, a second region, An intrinsic semiconductor region having a lower impurity concentration than the first region and the second region, and a third region in which an orthogonal projection of the gate is located between the first region and the second region. And a second thin film transistor including a crystalline semiconductor layer, wherein one of the first region and the second region is connected to one of a source and a drain of the first thin film transistor, and the polycrystalline semiconductor layer Is between the first region and the third region, and between the second region and the third region, the fourth region having a lower impurity concentration than the first region and the second region. The first region and the front Containing a lower concentration fifth region of the impurity than the second region

  According to the present invention, it is possible to provide a detection device having an improved countermeasure against off-leakage of a selection TFT in a detection device having a pixel including an amplification TFT and a selection TFT.

It is a top view per pixel of the detection apparatus which concerns on the 1st Embodiment of this invention. It is sectional drawing of the detection apparatus which concerns on the 1st Embodiment of this invention. It is a schematic equivalent circuit of the detection apparatus which concerns on this invention. It is a top view per pixel of the detection apparatus which concerns on the 2nd Embodiment of this invention. It is sectional drawing of the detection apparatus which concerns on the 2nd Embodiment of this invention. It is a conceptual diagram of the radiation detection system using the detection apparatus of this invention.

  Hereinafter, embodiments of the present invention will be specifically described with reference to the accompanying drawings. In addition, in this specification, radiation is a beam having energy of the same degree or more, for example, X-rays, β-rays, γ-rays, etc., which are beams formed by particles (including photons) emitted by radiation decay, such as X Lines, particle beams, cosmic rays, etc. are also included.

(First embodiment)
First, the configuration of one pixel of the detection apparatus according to the first embodiment of the present invention will be described with reference to FIGS. 1 and 2A and 2B. FIG. 1 is a plan view of one pixel. In FIG. 1, only the first electrode 101 is shown for the conversion element 100 for simplification. 2A is a cross-sectional view taken along line AA ′ in FIG. 1, and FIG. 2B is a cross-sectional view taken along line BB ′ in FIG.
One pixel in the detection device of the present invention includes a conversion element 100 that converts radiation or light into electric charge, and a first thin film transistor (TFT) 110 that amplifies a signal corresponding to the electric charge of the conversion element 100. In addition, the pixel includes a second thin film transistor (TFT) 120 that selectively outputs a signal amplified according to the charge, a third thin film transistor (TFT) 130 for resetting the gates of the conversion element 100 and the first TFT 110, including.

  In the present embodiment, the conversion element 100 uses a PIN photodiode that is a photoelectric conversion element. The conversion element 100 is laminated and disposed on first to third TFTs provided on an insulating substrate 190 such as a glass substrate with an interlayer insulating layer 195 interposed therebetween. The conversion element 100 includes a first electrode 101, a first conductivity type impurity semiconductor layer 102, a semiconductor layer 103, and a second conductivity type, which are provided on the interlayer insulation layer 195 in this order from the interlayer insulation layer side. The impurity semiconductor layer 104 and the second electrode 105 are included. Here, the first conductivity type impurity semiconductor layer 102 has a higher concentration of the first conductivity type impurity than the semiconductor layer 103 and the second conductivity type impurity semiconductor layer 104. The second conductivity type impurity semiconductor layer 104 has a higher concentration of second conductivity type impurities than the first conductivity type impurity semiconductor layer 102 and the semiconductor layer 103. The first conductivity type and the second conductivity type are different from each other. For example, if the first conductivity type is n-type, the second conductivity type is p-type. An electrode wiring (not shown) is electrically connected to the second electrode 105. The first electrode 101 is electrically connected to the gate 114 of the first TFT 110 in a contact hole CH1 provided in the first passivation layer 193, the second passivation layer 194, and the interlayer insulating layer 195. In addition, the first electrode 101 is formed in the impurity semiconductor region 133 that is one of the source and the drain of the third TFT 130 in the contact hole CH2 provided in the first passivation layer 193, the second passivation layer 194, and the interlayer insulating layer 195. Electrically connected. In the present embodiment, the photodiode using the first conductivity type impurity semiconductor layer 102, the semiconductor layer 103, and the second conductivity type impurity semiconductor layer 104, which is mainly made of amorphous silicon, is used. The invention is not limited to this. For example, an element that directly converts radiation into electric charges using the first conductivity type impurity semiconductor layer 102, the semiconductor layer 103, and the second conductivity type impurity semiconductor layer 104 mainly containing amorphous selenium can be used. .

  The first TFT 110 includes, on the first insulating layer 191 provided on the substrate 190, a polycrystalline silicon layer as a polycrystalline semiconductor layer, a gate insulating layer 192, and a gate 114 in order from the substrate side. . The polycrystalline semiconductor layer of the first TFT 110 includes a channel region 111, an impurity region 112 having a higher impurity concentration than the channel region 111, and an impurity region 113 having a higher impurity concentration than the channel region 111. The channel region 111 is an intrinsic semiconductor region, and the orthogonal projection of the gate 114 is located in the intrinsic semiconductor region of the polycrystalline semiconductor layer that becomes the channel region 111. The impurity region 112 and the impurity region 113 are doped with impurities of the same conductivity type, and one is a source and the other is a drain. The gate 114 is electrically connected to the first electrode 101 of the conversion element 100 in a contact hole CH1 provided in the first passivation layer 193, the second passivation layer 194, and the interlayer insulating layer 195. In the present embodiment, the impurity region 112 is electrically connected to the first power supply wiring 140.

  The second TFT 120 includes a polycrystalline silicon layer as a polycrystalline semiconductor layer, a gate insulating layer 192, a gate 124, and a first semiconductor layer 191 provided on the substrate 190. ,including. The polycrystalline semiconductor layer of the second TFT 120 includes a channel region 121, an impurity region 122 having a higher impurity concentration than the channel region 121, and an impurity region 123 having a higher impurity concentration than the channel region 121. The channel region 121 corresponding to the third region of the present invention is an intrinsic semiconductor region, and the orthographic projection of the gate 124 is located in the intrinsic semiconductor region of the polycrystalline semiconductor layer that becomes the channel region 111. The impurity regions 122 and 123 correspond to the first region and the second region of the present invention. Here, the impurity doped in the impurity region 122 and the impurity doped in the impurity region 123 are impurities of the same conductivity type. In the present embodiment, the impurity region 113 of the first TFT 110 and the impurity region 122 of the second TFT are shared.

Note that the present invention is not limited thereto, and the impurity region 113 and the impurity region 122 may be separated from each other as long as the impurity region 113 and the impurity region 122 are electrically connected. Here, in the polycrystalline semiconductor layer of the present embodiment, the fourth region between the channel region 121 and the impurity region 122 has the same conductivity type as the impurity regions 122 and 123 and has a lower impurity concentration than the impurity regions 122 and 123. 125. The fourth region 125 has a higher impurity concentration than the channel region 121. In the polycrystalline semiconductor layer of this embodiment, the fifth region 126 between the channel region 121 and the impurity region 123 has the same conductivity type as the impurity regions 122 and 123 and has a lower impurity concentration than the impurity regions 122 and 123. Have The fifth region 126 has a higher impurity concentration than the channel region 121. The fourth region 125 and the fifth region 126 are so-called LDD (Lightly-Doped Drain) regions. Since the second TFT 120 of this embodiment has such an LDD structure, a sufficient resistance value (off resistance) in a state where a non-conducting potential is supplied to the gate 124 can be secured. As a result, crosstalk with the conversion elements of other pixels can be reduced. The concentration of the impurity in each of these regions is desirably set so that the mobility of the second TFT 120 is 10 to 600 (cm ² / Vs). Here, the mobility μ (cm ² / Vs) of the ^second TFT 120 is defined by the following equation (1).

Ids = μ × Ci × (Vgs−Vth) × Vds × W / L (1)
Here, W (cm) is the channel width, L (cm) is the channel length, Ci (F) is the capacitance per unit area of the channel, Vgs (v) is the gate-drain voltage of the entire second TFT 120, and Vth (v ) Is a threshold voltage. Vds (v) is the drain-source voltage of the entire second TFT 120, and Ids (A) is the drain-source current of the entire second TFT 120.

The mobility μc (cm ² / Vs) of the channel region 121 of the second TFT 120 is defined by the following formula (2).

Ids = μc × Ci × (vgs−Vth) × vds × W / L (2)
Here, vgs (v) is a gate-drain voltage of the channel of the second TFT 120, and vds (v) is a drain-source voltage of the channel of the second TFT 120.

  Further, Vgs and vgs, and Vds and vds are defined by the following equations (3) and (4).

Vgs = vgs + Ids × R _LDD (3)
Vds = vds + 2 × Ids × R _LDD (4)
Here, R _LDD (Ω) is the resistance value of the LDD region.

R _LDD is defined by the following equation (5).

R _LDD = R _□ × L _LDD / W (5)
Here, R _□ (Ω / sq) is the sheet resistance of the LDD region, and L _LDD (cm) is the length of the LDD region (LDD length).

  Further, the on-resistance Ron (Ω) of the entire second TFT 120 is defined by the following formula (6).

Ron = Vds / Ids (6)
The following formulas (7) and (8) are derived from the above formulas (1) to (6).

μ = μc × {(Vgs−Vth−Ids × R _□ × L _LDD / W) × (Ron−2 × R _□ × L _LDD / W)} / {(Vgs−Vth) × Ron} (7)
μc = 1 / {Ci × (Vgs−Ids × R _□ × L _LDD / W) × (Ron−2 × R _□ × L _LDD / W) × W / L} (8)
It is preferable to appropriately set the channel width W, the channel length L, the sheet resistance R _{□ of} the LDD region, and the LDD region length (LDD length) L _LDD so as to satisfy the expressions (7) and (8). . Further, in order to obtain the sheet resistance R _□ of the LDD region, it is more desirable to appropriately set the impurity concentration and thickness of the LDD region. The gate 124 is electrically connected to the selection drive wiring 150, and the impurity region 123 is electrically connected to the signal wiring 160. In the present embodiment, the first power supply wiring 140 is connected to the impurity region 112 of the first TFT 110 and the signal wiring 160 is connected to the impurity region 123 of the second TFT 120. However, the present invention is not limited to this. It is not something. The signal wiring 160 may be connected to the impurity region 112 of the first TFT 110, and the first power supply wiring 140 may be connected to the impurity region 123 of the second TFT 120.

  The third TFT 130 includes a polycrystalline silicon layer as a polycrystalline semiconductor layer, a gate insulating layer 192, a gate 134, and a first semiconductor layer 191 provided on the substrate 190. ,including. The polycrystalline semiconductor layer of the third TFT 130 includes a channel region 131, an impurity region 132 having a higher impurity concentration than the channel region 131, and an impurity region 133 having a higher impurity concentration than the channel region 131. The channel region 131 is an intrinsic semiconductor region where the orthographic projection of the gate 134 of the polycrystalline semiconductor layer is located. The impurity doped in the impurity region 132 and the impurity doped in the impurity region 133 are impurities of the same conductivity type. . Here, the polycrystalline semiconductor layer of the third TFT 130 includes an LDD region 135 having the same conductivity type as the impurity regions 132 and 133 and having a lower impurity concentration than the impurity regions 132 and 133 between the channel region 131 and the impurity region 132. Have. The LDD region 135 has a higher impurity concentration than the channel region 131. The polycrystalline semiconductor layer of the third TFT 130 has an LDD region 136 having the same conductivity type as the impurity regions 132 and 133 and having a lower impurity concentration than the impurity regions 132 and 133 between the channel region 131 and the impurity region 133. . The LDD region 136 has a higher impurity concentration than the channel region 131. Since the third TFT 130 of this embodiment has such an LDD structure, a sufficient resistance value (off resistance) in a state where a non-conducting potential is supplied to the gate 134 can be secured. Thereby, the certainty of holding the potential of the first electrode 101 of the conversion element 100 is improved. The gate 134 is electrically connected to the reset driving wiring 170, and the impurity region 133 is electrically connected to the second power supply wiring 180. The impurity region 132 is electrically connected to the first electrode 101 of the conversion element 100 in the contact hole CH2 provided in the first passivation layer 193, the second passivation layer 194, and the interlayer insulating layer 195. . Note that the off-resistance of the third TFT 130 is preferably higher than the off-resistance of the second TFT 120. This is because the second TFT 120 requires a speed corresponding to the signal output, but the third TFT 130 requires the certainty of holding the potential rather than the speed. Therefore, it is effective to make the impurity concentrations of the LDD regions 135 and 136 of the third TFT 130 lower than the impurity concentrations of the fourth region 125 and the fifth region 126 of the second TFT 120. Further, it is preferable that the W / L of the channel region 131 of the third TFT 130 is made larger than the W / L of the channel region of the second TFT 120, or the gates 134 of the third TFT are provided more than the gates 124 of the second TFT. The third TFT 130 may be formed of a TFT having an amorphous semiconductor layer such as amorphous silicon formed separately from the second TFT 120.

  The gate insulating layer 192 is provided so as to cover the polycrystalline semiconductor layer of each TFT, and the first passivation layer 193 is provided so as to cover the gate insulating layer 192 and each gate. The second passivation layer 194 is provided so as to cover each TFT, the first power supply wiring 140, the signal wiring 160, and the second power supply wiring 180, and the interlayer insulating layer 195 is provided so as to cover the second passivation layer 194. ing. The third passivation layer 196 is provided so as to cover the conversion element 110, and the fourth passivation layer 197 is provided so as to cover the third passivation layer 196. The gate insulating layer 192, the first passivation layer 193, the second passivation layer 194, and the third passivation layer 196 are preferably formed using an inorganic insulating material such as silicon nitride. The interlayer insulating layer 195 and the fourth passivation layer 197 are preferably formed using an organic insulating material that can be easily formed with a large thickness in order to ensure surface flatness.

  Next, a schematic equivalent circuit of the detection apparatus according to the present invention will be described with reference to FIG. 3 has a pixel array of n rows and m columns (n and m are natural numbers of 2 or more). In the detection apparatus according to the present embodiment, a pixel array includes a plurality of pixels 301 arranged in a row direction and a column direction on a substrate 190. Each pixel 301 includes a conversion element 100, a first TFT 110, a second TFT 120, and a third TFT 130. A scintillator (not shown) that converts the wavelength of radiation into visible light may be disposed on the surface of the conversion element on the second electrode 105 side. The bias power source 305 is connected in common to the second electrodes 105 of the plurality of conversion elements 100 and supplies the second electrode 105 with a potential Vs at which the conversion elements 100 are reversely biased. The selection drive wiring 150 is connected in common to the gates 124 of the plurality of second TFTs 120 arranged in the row direction, and is electrically connected to the selection drive circuit 302. By supplying drive pulses including conduction and non-conduction potentials sequentially or simultaneously to a plurality of selection drive wirings 150 in which a plurality of selection drive circuits 302 are arranged in the column direction, amplified signals are supplied in units of rows. The pixels are output in parallel to a plurality of signal lines 160 arranged in the row direction. The signal wiring 160 is commonly connected to the third region 121 of the plurality of second TFTs 120 arranged in the column direction, and is electrically connected to the readout circuit 304. The reset driving wiring 170 is connected in common to the gates 134 of the plurality of third TFTs 130 arranged in the row direction, and is electrically connected to the reset driving circuit 303. A driving pulse including a conduction potential and a non-conduction potential is sequentially or simultaneously supplied to a plurality of reset driving wirings 170 in which a plurality of reset driving circuits 303 are arranged in the column direction. Thereby, the initial potential Vss is supplied from the second power supply circuit 307 to the first electrode 101 of the conversion element 100 via the second power supply wiring 180. The potential Vdd is supplied from the first power supply circuit 306 to the second region 112 of the first TFT 110 via the first power supply wiring 140. Note that when the potential Vss and the potential Vdd are the same, each power supply and each power supply wiring may be shared.

(Second Embodiment)
Next, the configuration of one pixel of the detection apparatus according to the second embodiment of the present invention will be described with reference to FIGS. 4 and 5A and 5B. FIG. 4 is a plan view per pixel. In FIG. 4, only the first electrode 101 is shown for the conversion element 100 for simplification. 5A is a cross-sectional view taken along the line AA ′ in FIG. 4, and FIG. 5B is a cross-sectional view taken along the line BB ′ in FIG. Moreover, the same thing as what was demonstrated in 1st Embodiment is provided with the same number, and detailed description is omitted.

  The polycrystalline semiconductor layer of the second TFT 120 in the first embodiment has a fourth region 125 that is an LDD region and a fifth region 126 that is an LDD region. On the other hand, the polycrystalline semiconductor layer of the second TFT 120 ′ in this embodiment has a lower impurity concentration than the impurity regions 122 and 123 between the channel region 121 and the impurity region 122, and the channel region 121 and the impurity concentration. Are substantially equivalent and have a fourth region '127. Further, the polycrystalline semiconductor layer of the second TFT 120 ′ in this embodiment has a lower impurity concentration than the impurity regions 122 and 123 between the channel region 121 and the impurity region 123, and the concentration of the channel region 121 and the impurity. Have fifth regions 128 that are substantially equivalent. That is, the fourth region 125 ′ and the fifth region 126 ′ are intrinsic semiconductor regions that are not doped with impurities of the same conductivity type as the impurity regions 122 and 123, and exist outside the region where the orthogonal projection of the gate 124 is located. It is an intrinsic semiconductor region. On the other hand, the channel region 121 is an intrinsic semiconductor region existing inside the region where the orthographic projection of the gate 124 is located. The fourth region 125 ′ and the fifth region 126 ′ can further have higher off resistance than the fourth region 125 and the fifth region 126, which are LDD regions. Thereby, crosstalk can be further reduced as compared with the first embodiment.

  In addition, the polycrystalline semiconductor layer of the third TFT 130 ′ of this embodiment has an intrinsic semiconductor region 137 ′ between the channel region 131 and the impurity region 132, and the channel region 131 and the impurity region 133, as in the second TFT 120 ′. Intrinsic semiconductor regions' 138 are respectively provided therebetween. Thereby, the certainty of holding the potential of the first electrode 111 of the conversion element 110 is further improved as compared with the first embodiment.

(Application embodiment)
Next, a radiation detection system using the detection apparatus of the present invention will be described with reference to FIG.

  X-rays 6060 generated by an X-ray tube 6050 serving as a radiation source pass through the chest 6062 of the patient or subject 6061 and enter each conversion element 12 of the conversion unit 3 included in the radiation detection apparatus 6040. This incident X-ray includes information inside the body of the patient 6061. Corresponding to the incidence of X-rays, the conversion unit 3 converts the radiation into electric charges to obtain electrical information. This information is converted into digital data, image-processed by an image processor 6070 as a signal processing means, and can be observed on a display 6080 as a display means in a control room.

  Further, this information can be transferred to a remote place by transmission processing means such as a telephone line 6090, and can be displayed on a display 6081 serving as a display means such as a doctor room in another place or stored in a recording means such as an optical disk. It is also possible for a doctor to make a diagnosis. Moreover, it can also record on the film 6110 used as a recording medium by the film processor 6100 used as a recording means.

100 conversion element 101 first electrode 110 first TFT (for amplification)
111 Channel region 112, 113 Impurity region 114 Gate 120 Second TFT (for selection)
121 3rd area 122 1st area | region 123 2nd area | region 124 Gate 125,125 '4th area | region 126,126' 5th area | region 130 3rd TFT (for reset)

Claims (10)

A conversion element for converting radiation or light into electric charge;
A first thin film transistor having a gate connected to the conversion element;
An intrinsic semiconductor region having a gate connected to a drive wiring and having a lower impurity concentration than the first region, the second region, and the first region and the second region, and between the first region and the second region And a third region in which the orthogonal projection of the gate is located, and one of the first region and the second region is connected to one of a source and a drain of the first thin film transistor. Two thin film transistors;
A detection device comprising:
The polycrystalline semiconductor layer includes a fourth region having a lower impurity concentration than the first region and the second region between the first region and the third region, the second region, and the third region. And a fifth region having a lower impurity concentration than the first region and the second region.   The detection device according to claim 1, wherein the fourth region and the fifth region have a concentration of the impurity higher than that of the third region.   2. The detection device according to claim 1, wherein the fourth region and the fifth region are intrinsic semiconductor regions existing outside a region where the orthographic projection of the gate of the polycrystalline semiconductor layer is located.   The gate is connected to another drive wiring different from the drive wiring, and the impurity concentration from the first region and the second region is a region where the orthographic projection of the gate is located between the first region and the second region. The semiconductor device further includes a third thin film transistor including a semiconductor layer having a channel region which is a low intrinsic semiconductor region, and one of the first region and the second region is connected to a gate of the first thin film transistor. The detection device according to any one of the above.   The semiconductor layer of the third thin film transistor is a polycrystalline semiconductor layer, and the polycrystalline semiconductor layer is disposed between the first region of the third thin film transistor and the channel region, and the second region of the third thin film transistor. The detection device according to claim 4, wherein a region having a lower concentration of the impurity than the first and second regions of the third thin film transistor is included between the channel region and the channel region.   The detection device according to claim 5, wherein a region where the impurity concentration is lower than the first and second regions of the third thin film transistor has a higher impurity concentration than the channel region.   The region where the impurity concentration is lower than the first and second regions of the third thin film transistor exists outside the region where the orthogonal projection of the gate of the third thin film transistor of the polycrystalline semiconductor layer of the third thin film transistor is located. The detection device according to claim 5, wherein the detection device is an intrinsic semiconductor region.   The detection device according to claim 4, wherein the semiconductor layer of the third thin film transistor is an amorphous semiconductor layer.   9. The detection device according to claim 4, wherein the third thin film transistor has an off-resistance higher than that of the second thin film transistor. The detection device according to any one of claims 1 to 9,
Signal processing means for processing a signal from the detection device;
Recording means for recording a signal from the signal processing means;
Display means for displaying a signal from the signal processing means;
Transmission processing means for transmitting a signal from the signal processing means;
A detection system comprising:

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