JP2013005196A - Enable signal generation circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To surely control an enable circuit coupled to an output stage, and also configure so that current consumption does not increase even when a power source voltage increases.SOLUTION: An enable signal generation circuit includes: a transistor MN1 whose gate is connected to a control input terminal 1 and source is connected to ground via a transistor MN2; a resistor R2 connected between a drain of the transistor MN1 and a power supply VDD; a transistor MP1 whose source and drain are respectively connected to two terminals of the resistor R2; a resistor R3 connected between a gate and the source of the transistor MP1; and a transistor MP2 whose source is connected to the gate of the transistor MP1 and whose gate is connected to the drain of the transistor MP1 and whose drain is connected to a load circuit 3. The gate of the transistor MP2 is connected to a control output terminal 2.

Description

  The present invention relates to an enable signal generation circuit that generates an enable signal having a voltage slightly lower than a power supply voltage.

  For example, as shown in FIG. 2, the high-side side includes an output circuit 11 that operates between a power supply voltage VDD and a voltage that is about 6 V lower than that, and an enable circuit 12 that controls operation / stop of the output circuit 11. An output circuit 14 that operates between the circuit 13 and 6V and the ground potential GND, outputs an output signal also to the output circuit 11 of the high-side circuit 13, and an enable circuit 15 that controls the operation / stop of the output circuit 14; When the power supply voltage VDD is high, the high-side circuit 13 is connected to a high breakdown voltage element (for example, a source-drain voltage breakdown voltage of about 40 to 60 V, A source-to-source voltage of about 6 V is used, and a low breakdown voltage element (for example, a source-drain voltage withstand voltage of about 6 V) is used for the low side circuit 16.

  In such a circuit, if the enable circuit 15 is controlled by the enable signal for the low side generated by the enable signal generation circuit (not shown) so that only the low side circuit 16 can be turned on / off, The stop order is always the order from the low side circuit 16 to the high side circuit 13. Therefore, if the high-side circuit 13 is operating even for a short period of time even though the low-side circuit 16 is stopped, a malfunction may occur. In addition, it is not possible to perform the enable control of the high side circuit 13 first in the circuit operation.

  Against this background, the enable control in the high-side circuit 13 is also required, and the enable circuit 12 for inputting the high-side enable signal generated by the enable signal generating circuit, like the enable circuit 15 in the low-side circuit 16. Is provided.

  Incidentally, Patent Document 1 discloses an enable signal generation circuit. As shown in FIG. 3, the PMOS transistor MP22 is connected to the positive power supply side of the inverter 21 composed of the NMOS transistor MN21 and the PMOS transistor MP21, and the two-input NAND composed of the NMOS transistors MN22 and MN23 and the PMOS transistors MP23 and MP24. The circuit 22 is configured so that the enable signal appearing at the control output terminal 25 is switched by the control signal input to the first control input terminal 23 of “H” active and the second control input terminal 24 of “L” active. It is a thing. In this enable signal generation circuit, an enable signal that is set to “H” is output to the control output terminal 25 only when the control input terminal 23 is “H” and the control input terminal 24 is “L”.

  However, the enable signal generation circuit shown in FIG. 3 controls the enable circuit 12 for turning on / off the high-side circuit 13 of FIG. 2 when low breakdown voltage elements are used for the transistors MN21 to MN23 and MP21 to MP24. An enable signal cannot be generated. Further, even if some of the elements in FIG. 3 are configured using high breakdown voltage elements, if the breakdown voltage between the gate and the source of the high breakdown voltage element is limited to a certain low breakdown voltage (about 6V), It is the same.

  FIG. 4 is a circuit diagram showing another conventional enable signal generation circuit. In this circuit, the source of a high breakdown voltage NMOS transistor MN31 whose gate is connected to the control input terminal 31 via a protective resistor R31 is grounded, and its drain is connected to the power supply VDD via resistors R32 and R33, and the resistor R32 , R33 is connected to the gate of a high breakdown voltage PMOS transistor MP31. The transistor MP31 has a source connected to the power supply VDD, a drain connected to the load circuit 33, and a gate connected to the control output terminal 32. D3 and D4 are protective zener diodes.

  In this enable signal generation circuit, when the control input terminal 31 becomes “H”, the transistor MN31 is turned on, a current flows through the resistors R32 and R33, and the voltage Vgs between the gate and source of the transistor MP31 becomes the threshold value of the transistor MP31. When the voltage becomes equal to or higher than the voltage, the transistor MP31 is turned on, and an enable signal of “VDD-Vgs” is output from the control output terminal 32. Therefore, this enable signal generation circuit can generate a high-side enable signal necessary for the enable circuit 12 of the high-side circuit 13 described in FIG.

JP-A-7-183797

  However, in the enable signal generation circuit of FIG. 4, the potential of the enable signal output to the control output terminal 32 is not determined by the threshold voltage of the transistor MP32, the variation of the resistance values of the resistors R32 and R33, the temperature change, and the like. In some cases, the circuit cannot be reliably controlled, and it is difficult to select circuit constants to prevent this. While the enable signal is output from the control output terminal 32, the transistor MN31 is on, and a current continues to flow through the resistors R32 and R33. This current increases as the voltage of the power supply VDD increases. , Power consumption increases.

  An object of the present invention is to provide an enable signal generation circuit that can reliably control a subsequent stage enable circuit and that does not increase current consumption even when a power supply voltage increases.

In order to achieve the above object, an enable signal generation circuit according to a first aspect of the present invention is a first circuit in which a gate (or base) is connected to a control input terminal and a source (or emitter) is connected to a second power supply terminal. A first transistor of the conductivity type, a first resistor connected between the drain (or collector) of the first transistor and the first power supply terminal, and a source (or emitter) and drain (or collector) ) Is a second transistor of the second conductivity type connected across the first resistor, and a second transistor connected between the gate (or base) and source (or emitter) of the second transistor. The resistor and the source (or emitter) are connected to the gate (or base) of the second transistor, and the gate (or base) is connected to the drain (or collector) of the second transistor. And a third transistor of the second conductivity type whose drain (or collector) is connected to a load circuit, and the gate (or base) of the third transistor is connected to the control output terminal. .
According to a second aspect of the present invention, in the enable signal generating circuit according to the first aspect, a constant current source circuit is connected between the second power supply terminal of the first transistor.
According to a third aspect of the present invention, in the enable signal generation circuit according to the first or second aspect, a first Zener diode is connected between the gate (or base) of the first transistor and the second power supply terminal. A second Zener diode is connected between the source and drain (or emitter and collector) of the second transistor.

  According to the present invention, when the voltage of the enable signal output from the control output terminal is clamped by the second transistor and the third transistor, and the second and third transistors are PMOS transistors, -2Vgs "enable signal can be output. For this reason, if the enable circuit of the high-side circuit to which the enable signal is input is configured by a PMOS transistor, the on / off of the PMOS transistor can be reliably controlled. Further, if the transistor of the enable circuit is formed of the same element as the second and third transistors, the manufacturing variation and the temperature characteristic are also changed, so that it is less susceptible to the variation and temperature change. Further, if a constant current source circuit is connected to the first transistor, the current flowing through the first transistor is stabilized by the constant current source, so that the current consumption is prevented from increasing even if the power supply voltage increases. Is done.

It is a circuit diagram of the enable signal generation circuit of the Example of this invention. FIG. 6 is a circuit diagram of a circuit that is enable-controlled. It is a circuit diagram of a conventional enable signal generation circuit. It is a circuit diagram of another conventional enable signal generation circuit.

  FIG. 1 shows an enable signal generation circuit according to an embodiment of the present invention. Reference numeral 1 denotes a control input terminal, which is connected to the gate of the NMOS transistor MN1 through the protective resistor R1. A depletion type NMOS transistor MN2 having a source and a gate connected in common is connected as a constant current source circuit between the source of the transistor MN1 and the ground. A resistor R2 is connected between the drain of the transistor NM1 and the power supply VDD, and the source and drain of the PMOS transistor MP1 are connected between both ends of the resistor R2. A resistor R3 is connected between the gate of the transistor MMP1 and the power supply VDD. The source and gate of the PMOS transistor MP2 are connected to the gate and drain of the transistor MP1, the gate of the transistor MP2 is connected to the control output terminal 2, and the load circuit 3 is connected to the drain. The zener diode D1 is for protecting the transistors MN1 and MN2, and the zener diode D2 is for protecting the transistor MP1. The transistors MN1, MP1, and MP2 are for high breakdown voltage, and the transistor MN2 is for low breakdown voltage.

  In this embodiment, the first transistor described in the claims is realized by the transistor MN1, the second transistor by the transistor MP1, and the third transistor by the transistor MP2. Further, the first resistor described in the claims is realized by the resistor R2, and the second resistor is realized by the resistor R3.

  In the enable signal generation circuit of this embodiment, a voltage clamp circuit is configured by the transistors MP1 and MP2 and the resistor R3. Therefore, when the control input terminal 1 is set to “H”, the transistors MN1 and MN2 are turned on, the voltage at the control output terminal 2 is once lowered, and the transistor MP2 is turned on. As a result, a current flows through the resistor R3, whereby the gate potential of the transistor MP1 is lowered, and the transistor MP1 is turned on. Therefore, if the gate-source voltages of the transistors MP1 and MP2 are Vgs, an enable signal clamped to a voltage of “VDD−2Vgs” appears at the control output terminal 2.

  Therefore, for example, if the enable circuit 12 of the high-side circuit 13 of FIG. 2 is provided with a PMOS transistor having a threshold voltage approximately equal to the threshold voltage of the transistor MP2, the voltage “VDD−2Vgs” of the enable signal is supplied to the enable circuit 12. ”Is input, it is possible to reliably turn on the PMOS transistor of the threshold voltage and enable the high-side circuit 13 to be enabled. If the load circuit 3 is configured to generate a low-side enable signal when the transistor MP2 is turned on, the low-side enable signal can be output from the load circuit 3 to the enable circuit 15. . At this time, the enable signals are simultaneously input to the enable circuits 12 and 15 of FIG. 2, and the output circuits 11 and 14 are enabled at the same time.

  In the enable signal generation circuit of this embodiment, since the drain current of the transistor MN1 is made constant by the transistor MN2, the drain current does not increase even when the voltage of the power supply VDD becomes high. Thus, an increase in current consumption can be avoided.

  In the above embodiment, the case where the MOS transistor is used has been described. However, the same can be applied to the case where the bipolar transistor is used. In this case, the PMOS transistor may be replaced by an NPN transistor, the NMOS transistor may be replaced by a PNP transistor, the source may be replaced by an emitter, the drain may be replaced by a collector, and the gate may be replaced by a base.

1: control input terminal, 2: control output terminal, 3: load circuit 11: output circuit, 12: enable circuit, 13: high side circuit, 14: output circuit, 15: enable circuit, 16: low side circuit 21: Inverter, 22: 2-input NAND circuit, 23: “H” active first control input terminal, 24: “L” active second control input terminal, 25: Control output terminal 31: Control input terminal, 32: Control output terminal 33: Load circuit

Claims (3)

  A first transistor of the first conductivity type having a gate (or base) connected to a control input terminal and a source (or emitter) connected to a second power supply terminal, and a drain (or collector) of the first transistor; And a first resistor connected between the first power supply terminal and a second conductivity type second having a source (or emitter) and a drain (or collector) connected to both ends of the first resistor. Transistor, a second resistor connected between the gate (or base) and source (or emitter) of the second transistor, and a source (or emitter) connected to the gate (or base) of the second transistor. A third transistor of the second conductivity type having a gate (or base) connected to a drain (or collector) of the second transistor and a drain (or collector) connected to a load circuit. And a register, the third enable signal generating circuit, characterized in that it connects the gate (or base) to the control output terminal of the transistor. The enable signal generation circuit according to claim 1,
An enable signal generating circuit, wherein a constant current source circuit is connected between the first transistor and the second power supply terminal. The enable signal generation circuit according to claim 1 or 2,
A first Zener diode is connected between the gate (or base) of the first transistor and the second power supply terminal, and a second Zener diode is connected between the source / drain (or emitter / collector) of the second transistor. An enable signal generation circuit comprising a Zener diode connected thereto.

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