JP4724472B2 - Semiconductor integrated circuit - Google Patents

Description

  The present invention relates to a semiconductor integrated circuit including a protection circuit for protecting an internal circuit from an electrostatic discharge voltage applied to an external connection terminal.

  In a normal electronic device, in order to protect an internal circuit of a semiconductor integrated circuit from an electrostatic discharge voltage, a protection circuit is provided between an external connection terminal to which the electrostatic discharge voltage is applied and the internal circuit. FIG. 6 is a diagram showing a partial configuration of a semiconductor integrated circuit having a conventional protection circuit.

  1 is an external connection terminal, 2 is an internal circuit for outputting a signal to the external connection terminal 1 (only an output circuit is shown here), and 3 is connected between the external connection terminal 1 and the internal circuit 2 The first protection circuit. The internal circuit 2 includes a CMOS circuit of a PMOS transistor MP1 and an NMOS transistor MN1 as an output circuit, and a node N1 of the drain common connection of both transistors MP1 and MN1 is connected to the external connection terminal 1. The first protection circuit 3 includes a trigger element TR1 composed of a constant voltage diode (which may be composed of an NMOS transistor, a PMOS transistor, or the like) for controlling the snapback voltage, and a current flowing through the trigger element TR1. A current / voltage conversion resistor R1 for converting to a voltage, and an NMOS transistor MN2 (switching element) connected so that a voltage generated in the resistor R1 is applied between the gate and the source. D1 is a protective diode.

  In this semiconductor integrated circuit, when a positive electrostatic discharge voltage is applied to the external connection terminal 1 with respect to the ground, the trigger element TR1 is first turned on to pass a current through the resistor R1, and the voltage generated in the resistor R1 The transistor MN2 becomes conductive, and the electrostatic discharge voltage applied to the external connection terminal 1 is released to the ground. As a result, the internal circuit 2 is protected from the electrostatic discharge voltage. When a negative electrostatic discharge voltage is applied to the external connection terminal 1 with respect to the ground, an electrostatic discharge voltage current flows through the parasitic diodes of the transistors MN1 and MN2, and protection is performed. Further, when a positive electrostatic discharge voltage is applied to the external connection terminal 1 with respect to the VDD power supply line, an electrostatic discharge voltage current flows through the protective diode D1 to perform protection. At this time, the electrostatic discharge voltage current also flows through the parasitic diode of the transistor MP1.

  However, in the semiconductor integrated circuit described above, the internal circuit 2 and the first protection circuit 3 are independent, and when a positive electrostatic discharge voltage is applied to the external connection terminal 1 with respect to the ground, the first protection is usually performed. When the circuit 3 starts the operation first, the external connection terminal 1 is grounded and the protection operation is performed. However, depending on the configuration of the circuit portion (not shown) that drives the internal circuit 2, the internal circuit 2 may be the first protection circuit 3. May start working at the same time or earlier. In such a case, the internal circuit 2 cannot be completely protected by the first protection circuit 3, and the internal circuit 2 may be destroyed.

  An object of the present invention is to provide a semiconductor integrated circuit in which an internal circuit can be effectively protected even when the operation of a first protection circuit is slow.

  The present invention includes an internal circuit including a first conductivity type first transistor having a source or emitter connected to ground and a drain or collector connected to a node, an external connection terminal connected to the node, and the external connection terminal In a semiconductor integrated circuit comprising: a first protection circuit that conducts a trigger element when a static discharge voltage is applied to the first resistor, generates a voltage at a first resistor, and conducts a switching element to short-circuit the external connection terminal to ground. When a voltage is generated in the first resistor of one protection circuit, a second protection circuit that short-circuits between the gate and source of the first transistor or between the base and emitter, or between the gate and source of the first transistor or between the base and emitter When this voltage exceeds a predetermined value, this is detected and a current is passed through the second resistor, and the voltage generated by the current flowing through the second resistor is Wherein the third protection circuit wherein by generating a voltage to the first resistor to conduct the switching element of the first protection circuit, and the provided time exceeds the value.

  Here, the internal circuit further includes a second conductivity type second transistor having a source or emitter connected to the high potential power supply terminal and a drain or collector connected to the node, and the second protection circuit includes the second protection circuit. Preferably, when a voltage is generated in the first resistor of one protection circuit, the gate and source or the base and emitter of the first transistor and the second transistor are short-circuited.

  The internal circuit further includes a second transistor of a second conductivity type having a source or emitter connected to the high potential power supply terminal and a drain or collector connected to the node, and the third protection circuit includes the first protection circuit. When the voltage between the gate and source of the transistor or the second transistor or the base-emitter exceeds a predetermined value, this is detected and a current is passed through the second resistor, and a voltage generated by the current flowing through the second resistor Preferably, when the voltage exceeds a predetermined value, a voltage is generated in the first resistance of the first protection circuit to make the switching element conductive.

  According to the present invention, even when the internal circuit operates faster than the first protection circuit by applying an electrostatic discharge voltage to the external connection terminal, the gate-source between the transistors of the internal circuit and the base Since the emitters are short-circuited or the protection operation of the first operation circuit is promoted, the internal circuit can be completely protected.

  Examples of the present invention will be described in detail below.

  FIG. 1 shows a circuit configuration of a semiconductor integrated circuit according to the first embodiment. Reference numeral 1 denotes an external connection terminal, 2 denotes an internal circuit for outputting a signal to the external connection terminal 1, and 3 denotes a first protection circuit connected between the external connection terminal 1 and the internal circuit 2. The configuration is the same as that shown in FIG. In the first embodiment, in addition to such a configuration, the second protection circuit 4 including the NMOS transistor MN3 is connected. This transistor MN3 was connected so that the voltage generated in the resistor R1 was applied between its gate and source, and its drain was connected to the gate of the transistor MN1 in the internal circuit 2.

  Therefore, in the semiconductor integrated circuit of the first embodiment, when an electrostatic discharge voltage having a positive polarity with respect to the ground is applied to the external connection terminal 1 and the trigger element TR1 is turned on to generate a voltage higher than a predetermined value in the resistor R1, The transistor MN2 of the first protection circuit 3 is turned on and the node N1, that is, the external connection terminal 1 is connected to the ground for protection operation, and the transistor MN3 is turned on to forcibly cut off the transistor MN1 of the internal circuit 2. .

  For this reason, the electrostatic discharge voltage applied to the external connection terminal 1 is applied to the VDD power line via the diode D1 and the parasitic diode of the transistor MP1, and the gate of the transistor MN1 of the internal circuit 2 is driven by a circuit (not shown). Even if a situation occurs, the transistor MN2 of the first protection circuit 3 or the newly added transistor MN3 is protected by the faster one, and the protection becomes complete. That is, when the operation of the first protection circuit 3 is slow, the transistor MN1 protects the transistor MN1.

  FIG. 2 shows a circuit configuration of the semiconductor integrated circuit according to the second embodiment. In this semiconductor integrated circuit, the NMOS transistor MN4 is connected in addition to the NMOS transistor MN3 described in the first embodiment so that the voltage generated in the resistor R1 is applied between the gate and the source. A current mirror circuit composed of PMOS transistors MP2 and MP3 is configured to be on the reference side, and a second protection circuit 4A configured by connecting the drain of the transistor MP3 of the current mirror circuit to the gate of the transistor MP1 of the internal circuit 2 is provided. Provided.

  Therefore, in the semiconductor integrated circuit according to the second embodiment, when an electrostatic discharge voltage is applied to the external connection terminal 1 and the trigger element TR1 is turned on to generate a voltage higher than a predetermined value in the resistor R1, the transistor MN2 of the first protection circuit 3 is used. Conducts a protection operation, and the transistor MN3 also conducts to forcibly shut off the transistor MN1 of the internal circuit 2, and the transistor MN4 also conducts, and the transistor MP3 of the current mirror circuit conducts to turn on the transistor of the internal circuit 2. MP1 is forcibly shut off. Therefore, as in the first embodiment, when the operation of the first protection circuit 3 is slow, the transistors MN1 and MP1 are protected by the transistors MN3 and MP3.

  FIG. 3 shows a circuit configuration of a semiconductor integrated circuit according to the third embodiment. In this semiconductor integrated circuit, the gate of the NMOS transistor MN5 is connected to the gate of the transistor MN1 of the internal circuit 2, and a current mirror circuit composed of PMOS transistors MP4 and MP5 is configured so that the current flowing through the transistor MN5 is on the reference side. A comparator COMP comprising a Gm amplifier for connecting a resistor R2 for converting the current flowing through the transistor MP5 of the current mirror circuit into a voltage and increasing the output current by comparing the voltage generated at the resistor R2 with the reference voltage Vref. The third protection circuit 5 is configured such that the output current of the comparator COMP flows through the resistor R1 of the first protection circuit 3.

  Since the transistor MN5 operates in the same way during the normal operation of the transistor MN1, the reference voltage Vref is set so that the comparator COMP is not inverted in this normal operation. The diode D2 connected between both input terminals of the comparator COMP is used to protect the comparator COMP by clipping it when an excessive voltage is applied.

  When the electrostatic discharge voltage is applied to the external connection terminal 1, the first protection circuit 3 starts to operate, but an excessive voltage is applied to the VDD power line via the diode D1 and the parasitic diode of the transistor MP1, When a voltage of a predetermined level or higher is applied between the gate and source of the transistor MN1 by the operation of a circuit unit (not shown) that drives the circuit 2, the transistor MN1 of the internal circuit 2 starts to conduct, and the first protection circuit 3 performs a protection operation. There is a case where an excessive current flows through the transistor MN1 before destruction.

  In contrast, in the third embodiment, when the voltage applied between the gate and the source of the transistor MN1 in the internal circuit 2 exceeds a predetermined value, the transistor MN5 detects this, and a current mirror circuit composed of the transistors MP4 and MP5 is provided. A current flows through the resistor R2. At this time, if an excessive voltage exceeding VDD is applied to the VDD power supply line, the voltage generated at the resistor R2 exceeds the reference voltage Vref, and the output current from the comparator COMP becomes large, which is the first protection circuit. Since a predetermined voltage is generated through the resistor R1 of No. 3, the transistor MN2 becomes conductive, the node N1 of the internal circuit 2 is short-circuited to the ground, and the transistor MN1 of the internal circuit 2 is protected.

  In the above protection operation, a current also flows through the transistor MN1 of the internal circuit 2. Therefore, the permissible current value is grasped in advance, and the transistor MN2 of the first protection circuit 3 is turned on before reaching the permissible current value. The conditions must be set in advance. For this purpose, the inversion operation point of the comparator COMP is set by adjusting the threshold voltage and W / L of the transistors MN1, MN5, MP4, and MP5, the resistance value of the resistor R2, and the like. Note that the diode D2 can be omitted if the voltage generated in the resistor R2 does not become too high.

  FIG. 4 shows a circuit configuration of a semiconductor integrated circuit according to the fourth embodiment. In this semiconductor integrated circuit, in addition to the configuration of the third protection circuit 5 of the third embodiment described with reference to FIG. 3, the gate of the PMOS transistor MP5 is connected to the gate of the transistor MP1 of the internal circuit 2, and the drain thereof is connected to the resistor R2. A third protection circuit 5A configured to be connected to is provided.

  Therefore, in this semiconductor integrated circuit, in addition to the operation of the third embodiment, when the gate-source voltage of the transistor MP1 of the internal circuit 2 exceeds a predetermined value, the transistor MP6 detects this and becomes conductive, and the resistance R2 A current is passed to generate a voltage there. Accordingly, when the voltage between the gate and the source of the transistor MN1 exceeds a certain value or when the voltage between the gate and the source of the transistor MP1 exceeds a certain value, an excessive voltage is generated on the VDD power line at this time. If the voltage is applied, the comparator COMP operates and the first protection circuit 3 functions.

  Even in the above-described protection operation, when the gate-source voltage of the transistor MP1 exceeds a certain value, a current also flows through the transistor MP1 of the internal circuit 2. Therefore, the allowable current value is grasped and the allowable current value is reached. It is necessary to set conditions in advance so that the transistor MN2 of the first protection circuit 3 is turned on. Therefore, in addition to the case of the third embodiment, it is necessary to adjust the threshold voltages and W / L of the transistors MP1 and MP6 as the inverting operation point of the comparator COMP.

  Here, the third protection circuit 5A for detecting the voltage between the gates and the sources of both the transistors MN1 and MP1 of the internal circuit 2 and urging the operation of the first protection circuit 3 is provided. In the case where such a transistor exists, the third protection circuit is preferably configured to detect the voltage between the gate and the source so as to promote the operation of the first protection circuit 3.

  FIG. 5 shows a circuit configuration of a semiconductor integrated circuit according to the fifth embodiment. This semiconductor integrated circuit is provided with a fourth protection circuit 6 that combines the configurations of the second protection circuit 4A (FIG. 2) of the second embodiment and the third protection circuit 5A (FIG. 4) of the fourth embodiment.

  When an electrostatic discharge voltage is applied to the external connection terminal 1 and the first protection circuit 3 operates before the internal circuit 2, the transistor MN2 conducts first, so that the node N1 of the internal circuit 2 is grounded. Connected. Thereafter, the transistors MN3 and MP3 are turned on, whereby the transistors MN1 and MP1 of the internal circuit 2 are cut off.

  When an electrostatic discharge voltage is applied to the external connection terminal 1 and the internal circuit 2 operates before the first protection circuit 3, the operation of the first protection circuit 2 is prompted by the output current from the comparator COMP. The node N1 of the internal circuit 2 is connected to the ground. In the internal circuit 2, when the transistors MN3 and MP3 are turned on, the transistors MN1 and MP1 are cut off.

  A mode in which the electrostatic discharge voltage is applied to the external connection terminal 1 and the internal circuit 2 and the first protection circuit 3 operate simultaneously may occur instantaneously. In this case, the operation of the comparator COMP Since it takes time to start, the protection operation by the trigger element TR1 of the first protection circuit 3 has priority.

  Although the case where a MOS transistor is used has been described above, the same configuration can be obtained when a bipolar transistor is used. In this case, the NMOS transistor is replaced with an NPN transistor, the PMOS transistor is replaced with a PNP transistor, the gate is replaced with a base, the source is replaced with an emitter, and the drain is replaced with a collector. In the claims, the difference between the PMOS transistor and the NMOS transistor, or the difference between the NPN transistor and the PNP transistor is expressed as a difference in conductivity type.

1 is a circuit diagram of a main part of a semiconductor integrated circuit including a protection circuit of Example 1. FIG. FIG. 10 is a circuit diagram of a main part of a semiconductor integrated circuit including a protection circuit of Example 2. FIG. 10 is a circuit diagram of a main part of a semiconductor integrated circuit including a protection circuit of Example 3. FIG. 10 is a circuit diagram of a main part of a semiconductor integrated circuit including a protection circuit according to a fourth embodiment. FIG. 10 is a circuit diagram of a main part of a semiconductor integrated circuit including a protection circuit of Example 5. It is a circuit diagram of the principal part of a semiconductor integrated circuit provided with the conventional protection circuit.

Explanation of symbols

1: External connection terminal 2: Internal circuit (output circuit)
3: First protection circuit 4, 4A: Second protection circuit 5, 5A: Third protection circuit 6: Fourth protection circuit

Claims (3)

An internal circuit including a first transistor of a first conductivity type having a source or emitter connected to ground and a drain or collector connected to a node, an external connection terminal connected to the node, and an electrostatic discharge voltage applied to the external connection terminal In a semiconductor integrated circuit comprising: a first protection circuit that conducts a trigger element when a voltage is applied, generates a voltage in a first resistor, and conducts a switching element to short-circuit the external connection terminal to ground;
A second protection circuit for short-circuiting between a gate and a source or between a base and an emitter of the first transistor when a voltage is generated in the first resistor of the first protection circuit;
Alternatively, when the voltage between the gate and the source of the first transistor or between the base and the emitter exceeds a predetermined value, this is detected, a current is passed through the second resistor, and a voltage generated by the current flowing through the second resistor is predetermined. A third protection circuit for generating a voltage in the first resistance of the first protection circuit to make the switching element conductive when exceeding a value;
A semiconductor integrated circuit comprising: The semiconductor integrated circuit according to claim 1,
The internal circuit further includes a second transistor of a second conductivity type having a source or emitter connected to a high potential power supply terminal and a drain or collector connected to the node;
The second protection circuit is configured to short-circuit between the gate and the source or between the base and emitter of the first transistor and the second transistor when a voltage is generated in the first resistance of the first protection circuit. A semiconductor integrated circuit. The semiconductor integrated circuit according to claim 1,
The internal circuit further includes a second transistor of a second conductivity type having a source or emitter connected to a high potential power supply terminal and a drain or collector connected to the node;
The third protection circuit detects when the voltage between the gate and source or the base and emitter of the first transistor or the second transistor exceeds a predetermined value, and causes a current to flow through the second resistor, A semiconductor integrated circuit characterized in that, when a voltage generated by a current flowing through a second resistor exceeds a predetermined value, a voltage is generated in the first resistor of the first protection circuit to make the switching element conductive.

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