JP2012525011A - 非平面な基板表面を有する基板を処理する方法 - Google Patents
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
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- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/22—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities
- H01L21/223—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities using diffusion into or out of a solid from or into a gaseous phase
- H01L21/2236—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities using diffusion into or out of a solid from or into a gaseous phase from or into a plasma phase
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- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
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- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
- H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
- H01L29/66803—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET with a step of doping the vertical sidewall, e.g. using tilted or multi-angled implants
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Abstract
【選択図】図1a
Description
図1a〜1dには、本発明の一実施形態に係る非平面的な表面を有する基板を処理する方法が示されている。方法は、第1段階から第3段階までを含む。一実施形態において、これらの段階は連続的に実行され、1つの段階が完了した後に、別の段階が実行される。別の実施形態では、複数の段階の少なくとも一部は、同時に実行される。更なる別の実施形態では、2つ以上の段階の一部分が、平行して行われてもよい。一実施形態では、段階を実行する順番が規定されていてもよい。別の実施形態では、段階を実行する順番は特に決められず、段階をいかなる順番で実行してもよい。
図6には、本開示の一実施形態に係る非平面的表面を有する基板を処理するシステムの例が示されている。図に示されるシステム600は、スタンドアローンシステムであってもよい。これに替えて、システム600は、1以上のシステム600、1以上の基板監視システム、1以上のその他の基板処理システム、及び、基板を異なるシステムへと搬送する1以上の搬送システムを含むクラスタツールの一部であってもよい。
Claims (17)
- 第1面及び第2面を有する非平面的な基板を処理する方法であって、
前記基板の前記第1面を前記第2面より完全に処理する第1段階と、
前記第1面が更に処理されるのを制限する第2段階と、
前記第2段階の後に、前記第2面を前記第1面より完全に処理する第3段階と
を備える方法。 - 前記第1段階及び前記第3段階は、同じ処理工程を含む請求項1に記載の方法。
- 前記第1面と前記第2面とは、異なる角度に向けられている請求項1に記載の方法。
- 前記第1面及び前記第2面は、互いに実質的に直角を成している請求項3に記載の方法。
- 前記第1段階及び前記第3段階は、前記基板へのイオン注入工程を含む請求項2に記載の方法。
- 前記第1面は、前記基板に向かう粒子に対して、前記第2面よりも多く暴露される方向に向けられている請求項1に記載の方法。
- 複数の粒子が、前記基板に向かう粒子経路を移動し、前記第1面が、前記粒子経路に対して実質的に垂直である請求項1に記載の方法。
- 前記第2面は、前記粒子経路と平行又は実質的に平行である請求項7に記載の方法。
- 前記第2段階は、前記基板上に膜を堆積する工程を含む請求項1に記載の方法。
- 前記第1面の上に堆積される膜が、更なる処理を制限するのに十分な厚みになるまで、前記第2段階は継続する請求項8に記載の方法。
- 前記膜を、酸素を含有する原子、分子又はプラズマに暴露する段階を更に備える請求項8に記載の方法。
- 前記膜を、窒素を含有する原子、分子又はプラズマに暴露する段階を更に備える請求項8に記載の方法。
- 前記第2段階は、前記第1段階の前に実行される請求項1に記載の方法。
- 非平面的な基板にイオンを注入する方法であって、
前記イオンの流れに対して垂直又は実質的に垂直な第1面部分、及び、前記イオンの流れに対して平行又は実質的に平行な第2面部分を有する前記基板にイオン注入を行い、前記第1面部分には、前記第2面部分よりも多くイオンを注入する段階と、
前記第2面部分上よりも前記第1面部分上において膜厚が大きい膜を前記基板に堆積させる段階と、
前記第1面部分上の前記膜により、前記第1面部分への更なるイオン注入が制限されると同時に、前記第2面部分にはイオンが注入されるイオン注入を前記基板に行う段階と
を備える方法。 - 前記第1面部分上の前記膜は、イオンが前記膜を通過して前記第1面部分へと注入されるのを防ぐのに十分な膜厚を有する請求項14に記載の方法。
- 前記膜を、酸素を含有する原子、分子又はプラズマに暴露する段階を更に備える請求項14に記載の方法。
- 前記膜を、窒素を含有する原子、分子又はプラズマに暴露する段階を更に備える請求項14に記載の方法。
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US17236509P | 2009-04-24 | 2009-04-24 | |
US61/172,365 | 2009-04-24 | ||
US12/765,346 US8202792B2 (en) | 2009-04-24 | 2010-04-22 | Method of processing a substrate having a non-planar surface |
US12/765,346 | 2010-04-22 | ||
PCT/US2010/032247 WO2010124213A2 (en) | 2009-04-24 | 2010-04-23 | A method for processing a substrate having a non-planar substrate surface |
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JP2012525011A true JP2012525011A (ja) | 2012-10-18 |
JP6074796B2 JP6074796B2 (ja) | 2017-02-08 |
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US (2) | US8202792B2 (ja) |
JP (1) | JP6074796B2 (ja) |
KR (1) | KR101626079B1 (ja) |
CN (1) | CN102449731B (ja) |
TW (1) | TWI543239B (ja) |
WO (1) | WO2010124213A2 (ja) |
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JPH0735879A (ja) * | 1993-07-22 | 1995-02-07 | Yukiro Kawashima | 時刻・年月日信号を出力する電波時計 |
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US20110039034A1 (en) * | 2009-08-11 | 2011-02-17 | Helen Maynard | Pulsed deposition and recrystallization and tandem solar cell design utilizing crystallized/amorphous material |
US8679960B2 (en) * | 2009-10-14 | 2014-03-25 | Varian Semiconductor Equipment Associates, Inc. | Technique for processing a substrate having a non-planar surface |
US8598020B2 (en) * | 2010-06-25 | 2013-12-03 | Applied Materials, Inc. | Plasma-enhanced chemical vapor deposition of crystalline germanium |
US8664027B2 (en) | 2011-02-11 | 2014-03-04 | Varian Semiconductor Associates, Inc. | LED mesa sidewall isolation by ion implantation |
US8501605B2 (en) * | 2011-03-14 | 2013-08-06 | Applied Materials, Inc. | Methods and apparatus for conformal doping |
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KR102252647B1 (ko) | 2014-07-11 | 2021-05-17 | 삼성전자주식회사 | 이미지 센서의 픽셀 및 이미지 센서 |
CN106033715B (zh) * | 2015-03-11 | 2019-03-22 | 上海临港凯世通半导体有限公司 | FinFET的掺杂方法 |
CN106033728B (zh) * | 2015-03-11 | 2019-07-09 | 上海凯世通半导体股份有限公司 | FinFET的掺杂方法 |
CN106033729B (zh) * | 2015-03-11 | 2019-04-02 | 上海凯世通半导体股份有限公司 | FinFET的掺杂方法 |
CN106548958B (zh) * | 2015-09-18 | 2020-09-04 | 中微半导体设备(上海)股份有限公司 | 一种整合多功能腔以及基片处理系统 |
CN107437506B (zh) * | 2016-05-27 | 2020-08-07 | 中芯国际集成电路制造(上海)有限公司 | 半导体结构的形成方法 |
US10566242B2 (en) * | 2016-12-13 | 2020-02-18 | Taiwan Semiconductor Manufacturing Company, Ltd. | Minimization of plasma doping induced fin height loss |
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US20120295430A1 (en) | 2012-11-22 |
KR20120006550A (ko) | 2012-01-18 |
JP6074796B2 (ja) | 2017-02-08 |
US8507372B2 (en) | 2013-08-13 |
KR101626079B1 (ko) | 2016-05-31 |
TW201216332A (en) | 2012-04-16 |
TWI543239B (zh) | 2016-07-21 |
WO2010124213A2 (en) | 2010-10-28 |
CN102449731B (zh) | 2014-10-08 |
CN102449731A (zh) | 2012-05-09 |
US8202792B2 (en) | 2012-06-19 |
WO2010124213A3 (en) | 2011-01-20 |
US20100273322A1 (en) | 2010-10-28 |
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