JP2012524402A - Semiconductor nanowire array for photovoltaic device application and method for manufacturing the same - Google Patents

Abstract

The cost per watt of photovoltaic (PV) power is reduced.
The present invention relates to the fabrication of nanowires for electrical and electronic applications. Disclosed is a method of growing silicon nanowires using an alumina template such that the aluminum forming the alumina is used as a catalyst for growing silicon nanowires in a VLS (CVD) process as well as as a semiconductor dopant. In addition, various techniques have been disclosed for removing masking of portions of aluminum and alumina to maintain electrical shielding between device layers.
[Selection] Figure 1

Description

  The present invention relates to the growth and use of nanowires on a substrate for the production of electrical circuits including photovoltaic devices.

  Government use rights

  The U.S. Government grants licenses to others under reasonable conditions to the patent owner in limited circumstances as provided in the lump sum license for the present invention and the contract number DOE-DE-FG02-07ER86313 awarded by the U.S. Department of Energy. Have the right to claim

  Priority claim

  This patent application is a continuation-in-part of US patent application Ser. No. 12 / 185,773 (Patent Document 1), as well as US Patent Application No. 61 / 169,279 (Patent Document 2), US Pat. Claimed priority as a continuation of 177,265 (patent document 3), US patent application 61 / 242,212 (patent document 4) and US patent application 12 / 759,537 (patent document 5) To do. All of these US patent applications are hereby incorporated by reference.

  Single crystal or polycrystalline silicon solar cells are currently the leading commercial photovoltaic (PV) technology, accounting for over 90% of the commercial market. With advances in device design, crystalline silicon solar cells have already reached a module efficiency of 16-20%. While efforts are being made to bring solar cell efficiency closer to the 31% theoretical limit of single band gap silicon solar conversion devices, this clean alternative power generation method is primarily used to produce photovoltaic modules. The high module cost is hindered by the manufacturing cost of the silicon wafer used, which is not accepted by the market. Currently, solar power is less than 0.1% of the US energy supply.

US patent application Ser. No. 12 / 185,773 US Patent Application No. 61 / 169,279 US Patent Application No. 61 / 177,265 US patent application 61 / 242,212 US patent application Ser. No. 12 / 759,537

  In order to realize the potential of this clean and abundant power source, new technologies are needed that lower the cost per watt of PV power and at the same time make PV power more easily available to consumers.

  The unique approach to PV device engineering disclosed herein avoids the need for high purity silicon wafers by utilizing nanowire (NW) array arrays with pn junctions in the radial direction. . The nanowire approach reduces the amount of silicon used to the indispensable amount needed to construct active light converting nanostructured components. The radial pn junction improves carrier collection efficiency using the small diameter of the NW and enhances light absorption using the high aspect ratio of the nanostructure. In a radial pn junction, the direction of light absorption and the direction of carrier collection are separated by making these two relevant dimensions orthogonal. The NW is optically thick along the longitudinal axis and thus maximizes light absorption, but it is thin in the radial direction and thus shortens the light-generated carrier extraction distance. These geometric attributes increase device efficiency compared to planar structures. The NW typically has a p-type crystalline silicon core covered with an n-type shell, and the NW can be made as a pn junction or a pin junction as required. Here, i is intrinsic silicon.

  The bottom-up fabrication technique for single crystal semiconductor nanowire arrays enables a low cost fabrication process for producing crystalline Si solar cells. The silicon nanowire (SiNW) growth process is known as vapor-liquid-solid (VLS) growth and includes growing SiNW from the vapor atmosphere using metal nanoparticles as a catalyst. For PV devices or other device applications, similar VLS methods can be used to grow silicon, germanium (Ge), gallium antimonide (GaSb), gallium nitride (GaN) or other semiconductor NWs. An interesting aspect of applying NW arrays produced by the VLS process to solar cells is the high growth rate (1-10 microns / min) on low-cost amorphous substrates (substrates) such as glass and metal foil. In addition, a single crystal semiconductor NW can be obtained at a low temperature (400 to 600 ° C.) with minimal or no post-growth treatment. This offers the potential to save significant energy and material during manufacturing and reduce manufacturing costs compared to silicon wafer based approaches.

For the VLS growth of silicon nanowires, typically a gold (Au) seed is used, mainly due to the low Al-Si eutectic temperature (363 ° C) and favorable wettability, which is the nanowire. This leads to the formation of a stable liquid alloy phase at the tip of the steel. However, Au is taken into the lattice of SiNW during VLS growth at a high concentration of 5 × 10 ^{17 to} 1.5 × 10 ¹⁸ cm ⁻³ , and forms a deep level electronic state in the Si band gap, By acting as a center for recombination, the lifetime of the charge carriers is reduced. However, aluminum (Al) can be used instead as a catalyst in the VLS process.

  Aluminum is a very attractive material for catalyzing SiNW because it is routinely used in Si processing lines. Adding Al to the Si lattice creates a state close to the Si valence band, so Al is a p-type dopant suitable for semiconductor applications such as PV devices. The Al-Si phase diagram is similar to the Au-Si phase diagram and forms a fairly low temperature eutectic (577 ° C), which is suitable for VLS growth of SiNW when used in PV devices. Become a catalyst. Furthermore, a vapor phase-solid phase-solid phase can be used in the same manner to produce SiNW at a temperature lower than 500 ° C. using a vapor phase Si precursor. Processing technology that eliminates the catalyst seeding process, works with low-cost materials, and requires minimal processing steps is the path to be taken to realize all cost-effective manufacturing of NW devices and all associated benefits .

In one embodiment of the invention, a layer of Al metal is partially applied to form a nanoporous anodized aluminum (AAO) layer on an Al metal surface or other conductive substrate coated with aluminum. Anodizing and then using high-aspect from a gas phase atmosphere containing silane (SiH ₄ ) or other Si-containing (Si ₂ H ₆ , SiCl _4, etc.) gas by using Al metal as a catalyst using VLS technology Catalyzing the axial growth of the ratio SiNW. An Al metal substrate can be used as a starting material, or Al can be deposited as a coating or layer on another substrate material. The SiNW grown by this process nucleates at the Al / AAO interface through the formation of an Al-Si eutectic phase at the bottom of the nanopore, and grows from inside the AAO pores outward. , Extend to free space. Since SiNW contains Al atoms with a volume concentration of 10 ¹⁸ / cm ³ to 10 ²⁰ / cm ³ that serve as effective p-type dopants, no additional dopant gas source needs to be added during SiNW growth. When a properly constructed AAO / Al substrate is used, the NW is in ohmic contact with the Al metal that is the anode of the PV device. Subsequently, a conformal n-type Si layer is preferably epitaxially deposited in situ to create a number of pn diode junctions. In a preferred embodiment, the n-type layer is deposited without removing the device from the reactor. In order to maximize the junction region and provide electrical conduction to the diode region, a thin p-type layer covering the entire AAO surface can be formed prior to the n-type coating. This additional layer can also insulate the N layer from the substrate by filling the pores of AAO that are not blocked by silicon nanowires for any reason. If necessary, an intrinsic material layer to form a pin diode, or as a continuous layer between discrete p (n) -type nanowires and subsequent continuous n (p) -type coatings Can be added between the p and n layers. The porous AAO layer is multifunctional because it functions both as a template for controlling the diameter and spacing of the SiNW and as an insulator for insulating the n-type layer from the Al substrate. A transparent conductive film is deposited on the n-type Si layer to form a cathode. Therefore, one material Al consists of a catalyst for SiNW growth, a PV electrode (anode), a p-type SiNW dopant source, an insulating layer (in the form of porous AAO), an NW template (AAO), And a mechanical support structure of the device.

  This process for versatile SiNW fabrication can create new solar electrical devices with light weight, versatility, low cost and new design attributes. To conform to the established superior Si wafer-based PV device market, conformal Al foil finish or applied Al layer for PV coating on the body of electric vehicles, to apply to PV fiber products Nano PV power generation using a variety of easily fabricated implementations, including SiNW wound on Al yarns or simply Al deposited on glass panels or other insulating substrates Can be realized.

FIG. 2 is a conceptual diagram of a SiNW PV device showing an Al core, a p-type SiNW bonded to Al and growing through an insulating AAO coating, and a continuous N-type Si layer covering it. The n-type layer is covered with an Al core electrode (anode) and a counter electrode outer conductive electrode (cathode). AAO provides electrical insulation between the anode and the cathode. This figure shows a cross-sectional view of a porous anodized aluminum coating on Al metal. The SEM photograph which shows the porous AAO layer produced on the surface of Al wire, raising the magnification level. Schematic diagram of anodization process, (a) An as a formed AAO nanopore, anodized at high voltage, (b) Continuous step-down anodization at lower voltage, nanofinger at channel bottom (C) a phosphoric acid etching solution thins the anodized layer at the bottom of the pores and simultaneously enlarges the pores to the desired diameter. SEM photograph showing a low cost and effective substrate for SiNW growth. Details of SiNW grown on partially anodized Al on glass substrate showing glass / Al / AAO and SiNW structure overall (left, 30 min, growth), glass / Al / AAO / SiNW interface Intermediate magnification image (center, 5 minutes, growth) and high magnification image (right, 5 minutes) of the interface shown. Multipurpose SiNW PV device architectures on glass for rigid planar devices (left) and on bulk aluminum for conformal structures (right). SEM image of AAO on Al metal showing the barrier layer. Aluminum anodized in oxalic acid, malonic acid and tartaric acid (left or right). FIG. 3 is a diagram of an anodization cell used to grow a porous alumina template near the periphery of a yarn. The figure on the right shows a uniform electric field pattern that will ensure uniform porous layer growth. High-magnification SEM image (100,000 times) showing the tip of the nanowire with and without apparent residual Al catalyst material on the tip (left) and without (right). AAO on Al metal before (left) and after (right) pressure reduction and pore expansion. (A) Low magnification TEM image of radial pn Si nanowire showing uniform coating thickness along nanowire axis, (b) Radial direction pn Si showing crystalline p-Si core and polycrystalline n-Si shell layer High magnification TEM image of nanowires. SEM picture of non-porous aluminum oxide that can be made in regions of Al substrates (or other substrates coated with Al) where nanowire growth is undesirable. Nanowires do not nucleate through nonporous oxides. Process diagram for PV yarn production. Current-voltage schedule used for the “step-down” anodization process. Porous AAO on Al yarn before (left) and after (right) pore expansion after using the anodization step of FIG. An alternative “step-down” anodization procedure and the resulting AAO on the surface of the Al yarn are shown. The steps of the fabrication method are illustrated.

  The present invention includes the design of SiNW array-based PV devices, including the components that make up the PV device, and the basic process of phased fabrication of silicon nanowire arrays (SiNW) for PV or other device applications. In addition to techniques for incorporating constructed SiNW arrays into PV device designs, methods for making SiNW arrays on partially anodized Al or Al layers bonded to other material structures are shown. The methods and designs described herein are based on starting materials other than Al, active optoelectronic nanostructures made from materials other than Si, and metals and semiconductors for fabrication and function other than photovoltaic (solar power). One skilled in the art will readily appreciate that it can be extended to devices using nanoscale structures. In this application, the term nano (nanowire, nanoscale, nanopore, etc.) refers to a characteristic length scale of 1-1000 nm, either in form or function, in one or more related spatial dimensions (directions). , Has, utilizes, incorporates, or otherwise manifests a material structure.

  In one preferred embodiment, the invention features a method of making an optoelectronic device operating as an active component (active component) utilizing a semiconductor nanowire array.

  Substrate preparation-aluminum anodization

An aluminum (purity 99.8% or higher) part (foil, sheet, thread, coated substrate, or other shape) is first composed of ethyl alcohol (95%) and perchloric acid (ACS, 60-62%) 4: Electrolytically polish at a temperature below 5 ° C. in solution 1 and limit the current to 2 amperes to obtain a bright and smooth Al surface, and apply an anodic bias to Al at 10 volts for 3 minutes. In both electropolishing and anodic oxidation steps, it is essential to have a cathode (counter electrode) shape that is symmetrical to the anode in order to achieve a uniform surface. Symmetry ensures a uniform field configuration across the surface of the anodized structure. Therefore, in the case of Al yarn, the cathode has a cylindrical shape centered on the yarn anode, and in the case of a flat substrate (substrate), the cathode also has plane symmetry. The symmetry ensures a uniform electric field distribution on the anode surface and thus a uniform electropolishing (or anodization). The cathode used here is typically a stainless steel mesh. After electropolishing, rinse Al (substrate) with deionized water, then in acidic electrolyte (sulfuric acid, oxalic acid, glycolic acid, phosphoric acid, malonic acid, tartaric acid, malic acid, citric acid, or others) Anodize the anode. Before anodic oxidation (and electropolishing), the interface between the electrolyte and air of the Al part is coated with a polymer (General Chemical Coscoat ^™ ) to prevent electrochemical breakdown at the interface. ) To mask. By changing the kind and concentration of the electrolytic solution, the bath temperature, and the anodic oxidation voltage, nanoporous Al ₂ O ₃ having a pitch of 35 to 980 nm and a pore diameter of 2 to 900 nm can be formed. In a preferred embodiment, 1 mm diameter Al (99.999%) yarn is anodized in 3 M malonic acid solution at 5 ° C. and 130 volts. Anodization is performed using a computer controlled bipolar power supply. Anodization is first performed in a constant voltage (CV) mode while monitoring the current. The current starts at a low current and begins to rise as oxidation occurs and alumina pores nucleate across the aluminum surface. Porous AAO islands begin to nucleate randomly near the Al surface and penetrate laterally along the length until the entire surface is covered by this porous network. The current rises slowly at a constant voltage (CV), indicating the progress of island growth. When the current plateau (horizontal state) begins, this indicates a complete conversion or steady state of the Al metal surface to the porous AAO layer covering the underlying metal. At this point, the diameter and spacing of the pores are already set, so control to the constant current (CC) region (at the plateau level) where the AAO thickness (pore depth) increases with continued application of current. Made transitions are made. Then, anodic oxidation is continued until the pores reach a desired depth (1 to 100 μm). Thereafter, the anodization is returned to the CV mode, and subsequently, the voltage is successively applied by 1 to 10 volts at intervals of 1 to 5 minutes so that the smaller nanofinger protrusions extend from the bottom of the pores into the oxidation barrier layer. Lower. This “step-down” anodization method is characterized by a current drop-rise-plateau sequence in each series of steps, which results in a thin AAO barrier layer grown on the anodization front. In order to disrupt the integrity of the remaining AAO barrier layer and make the subsequent pore expansion process more effective in removing the barrier completely, an additional voltage blast (original An anodizing voltage (which increases to 130 volts for malonic acid in this specification) may be used. Etching AAO in 5 wt% phosphoric acid solution (37 ° C.) not only widens (increases) the pore diameter, but also reaches Al at the Al / AAO interface for the next step in the NW fabrication process Fully open the pores at the bottom so that it can. The barrier layer can be removed, but when exposed to air, a thin (4 nm) native oxide layer is formed at 100 ps on the Al surface. Another technique for thinning the barrier layer involves switching the anodizing bath and voltage to a schedule that creates much smaller pores at the growth front (for malonic acid (2M, 130V) above) Followed by a phosphoric acid pore expansion / barrier removal step followed by switching to 0.3 wt% oxalic acid at a voltage of 20-40 V for 1-10 minutes). At this point, the Al / AAO yarn substrate is rinsed thoroughly with deionized water to remove residual process chemicals and then dried in air to allow SiNW growth.

In another embodiment, the anodization process uses 3M malonic acid at a temperature of 5 ° C. with a 6-6V step until the process reaches about 80V and then a 6-3V step until the process reaches about 60V. It was. The process was run for 49 minutes and 35 seconds. The sample was then pore expanded in a H ₃ PO ₄ solution at a temperature of 37 ° C. for 23 minutes.

  Nanowire growth

A chemical vapor deposition (CVD) reactor is used to grow SiNW on alumite. VLS SiNW growth is typically performed in a isothermal quartz tube reactor at 550-650 ° C. and low pressure (-10-500 Torr) using SiH ₄ (10% in H ₂ ) as the silicon source. In a preferred embodiment, the reactor pressure is 38 Torr, the temperature is 600 ° C., the flow rate in the CVD reactor is 100 sccm, and the silane is 90 sccm (10% SiH ₄ in H ₂ ). NWs grown under these conditions are mostly single crystals with <110>, <111> or <112> growth directions due to random nucleation of Si within the pores of AAO. At a suitable pressure and a suitable temperature, SiH ₄ diffuses into the pores and preferably decomposes on the catalyst surface at the bottom of the pores rather than the pore surface or walls. Increasing the growth temperature or lowering the proportion of hydrogen in the reactor gas mixture results in an increased silicon film deposition rate compared to VLS growth. The parameter space of temperature, pressure, flow rate and associated gas concentration covers many possible situations that can produce a number of acceptable results, depending on the substrate, the nature of the catalyst and the desired result. The parameters described for this embodiment are suitable for the Al / AAO yarn or planar substrate (substrate) described in the previous section. As Si is decomposed from the silane molecules, a stable liquid alloy phase (Si / Al eutectic) is generated, and a SiNW crystal phase is generated when the Si concentration in the melt reaches a critical value. The only unconstrained spatial direction is a vector that starts perpendicularly to the surface of the substrate starting from the bottom of the pores, so that crystals form at the Al / AAO interface and eutectics form at the NW tips as the process proceeds. Finally, it appears from the opening on the outer surface of the AAO pore. This phase is an Al—Si eutectic phase occurring at ˜577 ° C. SiNW nucleates at the bottom of the AAO pores and then emerges beyond the pore boundary and continues to grow in free space under appropriate conditions while maintaining the AAO pore size. The Al-Si melt is present at the tip of the nanowire at the growth front and provides a means for continuous growth as long as Si is constantly replenished from the gas phase into the melt. Since a part of Al is taken into the silicon lattice, if the growth continues, the Al will eventually be used up, and the NW growth process ends. In addition to the thickness or presence of the AAO barrier layer at the bottom, by adjusting the diameter and depth of the AAO pores, the eutectic phase system can be mass sized and used to set the CVD parameters used in the SiNW growth process. The amount of Al emerging from the pores can be controlled by adjusting the size of the Si—Al eutectic phase at the NW growth front using systematic control as well. In one embodiment, the SiNW can nucleate even if there is a significant amount (10-200 nm thick) barrier layer at the bottom of the AAO pores. This CVD (VLS) process produces SiNW that emerges from Al metal (in ohmic contact), which grows upward through the pores of AAO and maintains the pore size (100-250 nm) However, it extends to free space with a length of 1 to 500 μm (preferably 10 to 30). SiNW is produced at an Al concentration of ˜1-5 × 10 ¹⁹ / cm ³ by the growth of SiNW using the Al catalyst as described above. A relatively high concentration of dopant is advantageous for making SiNW devices with pn junctions in the radial direction that require a highly doped wire core to reduce series resistance. High doping also reduces the minority carrier diffusion length, which is problematic for devices such as wafer PV systems with an intrinsic carrier extraction distance of 100 μm, but for the radial array shown here Since the radial carrier extraction distance is several orders of magnitude smaller, it still has a high carrier extraction rate over the inherent distance (100 nm) of this system, while allowing a high concentration doping profile.

  In the above-described NW growth process, a plurality of discrete SiNWs are formed in an array so that the NW and the pores ideally have a one-to-one correspondence so that the silicon nanowires emerge from one pore. Can be generated. In this case, these NWs are electrically connected in a parallel circuit via Al metal, and NW is nucleated from the Al metal. Although p-type silicon is not directly formed on the AAO outer peripheral surface with a certain surface area ratio, the effective surface area of NW is still 2 to 1000 times larger than the “footprint” surface area of AAO because of the large aspect ratio of NW. Furthermore, the NW is not perfectly straight and this non-linearity effectively guarantees that 100% of the incident radiation hits the Si before the AAO surface (even before n or in-type coating). To do.

  In another embodiment, a p-type coating (which would require the introduction of a dopant such as boron into the source gas) is intentionally deposited to ensure that any surface of AAO is deposited. A p-type coating film can be applied. A p-type coating will add additional electrical continuity to the outer surface of the structure (nanowire bonded to the coating).

  In another embodiment, an intrinsic silicon layer is deposited on a p-type (either in a discrete NW configuration or a situation coupled to a continuous film) to form a foundation, and an n-type layer is further formed. Many pin junctions are made at the time of film formation.

  Formation of pn junction

  A conformal N-type silicon film is deposited after VLS growth of the p-type NW, thereby depositing a pn (or pin) diode junction (optionally, after the nanowire growth, an intrinsic silicon layer on the periphery of the yarn or planar substrate A complete functional array can also be constructed. The n-type silicon layer is preferably deposited by CVD on the outer surface of the p-type NW in the reactor (in situ) without exposing the material to air immediately after the VLS growth. When an intrinsic layer or an additional p-type coating film is formed before the n-type layer, it is also preferable to execute these procedures without breaking the sealing state (vacuum) of the CVD system.

  This is desirable to avoid oxidation of the SiNW surface. This is because if there is an oxide layer on the NW surface that exists between the p layer and the n layer, the device performance will be reduced by creating an interface state that may cause carrier recombination. I will. Removal of the oxide layer after formation requires an oxide removal step by either chemical etching (BOE), plasma removal, or other oxide removal methods prior to n- (i-n-) type coating It will be. In addition, Si atom dangling bonds (surface states) on the NW surface can be passivated with hydrogen using in situ processing or by oxide film etching in BOE under appropriate conditions. If this is done prior to atmospheric (oxygen / oxidation) exposure, the surface can be protected for some time.

In-situ deposition of the n-type film is achieved by introducing a short rest period after the VLS growth of the p-type SiNW, during which the SiH is purged using a nitrogen (or other inert gas) purge. ₄ is switched from the reactor and then an n-type silicon thin film is grown using systematically determined (10 ⁻³ to 10 ⁻⁴ ) PH ₃ / SiH ₄ dopant levels to achieve the desired doping. Will be. In this step, the reactor temperature is set to 600 ° C to 650 ° C. As a result, by adjusting the growth conditions, it is possible to switch between a region where NW growth is dominant and a region where thin film deposition is dominant. The n-type Si shell is polycrystalline at these deposition temperatures, but exhibits a uniform thickness along the length of the nanowire. However, in another embodiment, disilane (Si ₂ H ₆ ) is a substitute for silane that can produce an epitaxial n-type film at lower temperatures. During the n-type thin film coating process, Si covers substantially the entire surface within the CVD reactor, so that after deposition, certain selected areas of the surface that will later be used in devices such as photovoltaic devices. In particular, appropriate measures must be taken to protect certain electrical contact portions on the substrate or vice versa (or to selectively remove the n-type coating later) Please keep in mind. In order to preserve the pre-CVD morphology, structure and physical properties of the surface, masking agents can be used to facilitate surface protection / cleaning. In a preferred embodiment, an excess of Al is consumed (on the tip of the nanowire) in the NW growth process, but if the excess Al needs to be removed from the NW tip or other parts, an etching purge step It is also possible to achieve the removal in situ by introducing an HCL gas mixture into it and etching the Al. It is also possible to evaporate excess Al from the tip of the NW by raising the reactor temperature.

  The use of various coating techniques for making photovoltaic devices, especially CVD, requires that the various electrically different layers do not stick together and are short-circuited for some reason. In this case, a masking technique is devised that limits the application of the coating to maintain proper electrical shielding. However, those skilled in the art will use etching techniques to remove unwanted coatings in order to maintain electrical contact that is electrically isolated from any other component of the device that requires discrete conduction and the coating film. It will be appreciated that the membrane can be removed.

  The technology for limiting the n-type coating film from the surface region on the substrate where no n-type coating film is required includes post-treatment removal using chemical etching, mechanical removal (polishing, ablation, reactive ion etching) ), Masking or suitable to have an intentional sacrificial edge in place (removed, ablated, etched, or otherwise removed after the final CVD coating is complete) Making a sized substrate is included. In another embodiment, after the device is formed, the planar substrate (substrate) is inspected to identify those parts that are completely covered with SiNW, and then these parts are separated and finished into a complete PV device. .

  In another embodiment, a p-type silicon layer is coated on the p-type nanowire. If there are AAO pores that are not occluded by the SiNW or other defects that would cause a short circuit in the substrate, the p-type layer covers the pores and / or defects and is coated on top. Insulate the bottom substrate from the n-type layer. In another embodiment, an insulating layer can be coated over the device, and then the insulating layer can be selectively etched from areas of the AAO layer that are free of pinholes. Regions of the substrate that are typically lacking SiNW can be masked so that no pores are created by the anodization process. These can be along the edges of the substrate. In yet another embodiment, the completed substrate is inspected to detect areas with defects or missing SiNWs and thus shorts. In this embodiment, the absorption characteristics of nanowires can be used to detect the presence or absence of nanowires using a photoelectron detector.

  Similar results can be achieved using plasma enhanced CVD (PE-CVD) techniques at low temperatures and other relevant parameters for SiNW growth or coating processes.

  Completion of PV device

  In order to complete the formation of the PV device (PV yarn in this embodiment), an outer conductive coating (cathode) must be deposited on the n-type layer. An ideal cathode would be one that transmits 100% of incident light while providing high electrical conductivity (such as that of metal). Therefore, there are various options for transparent conductors. HC Stark produces a product called Clevios 1000®, a liquid PEDOT suspension, which can be sprayed or dip coated. Yes, it has a maximum transmittance of 90% in the wavelength band of sunlight, and the sheet resistance is ˜100Ω / sq. Similarly, Eikos offers a product called Invisicon®, which is a carbon nanotube suspension, which can also be applied by spray or dip coating. Is. Spray or dip coating techniques are attractive from a cost and ease of application standpoint, but the coating uniformity and all nanometer-scale recesses and cracks between the SiNW and SiNW are complete with the material. There is a limit to the ability to be applied so as to be electrically coated. Another method of depositing cathodes where a uniform coating is highly promising is the application of CVD such as PEDOT coating developed by GVD Inc. Regardless of how it is deposited, the coating must provide sufficient conductivity and transparency to maximize the function of the PV device. The lack of electrical conductivity can be compensated by providing an “effective conductivity” that approximates the effective conductivity of the Al metal anode structure using a cathode bus that periodically intersects the transparent cathode. In this PV yarn embodiment, spiral wound high purity copper or aluminum wire is used. The planar embodiment can evaporate aluminum in a mesh or other pattern on the transparent conductor. After forming the transparent conductive film, a transparent protective layer in consideration of the environment is formed on the surface to complete the device. This material can be a silicon-based resin, Teflon, Parylene, polyimide, or other robust, transparent, inert, non-conductive layer that is flexible and resilient to environmental (UV) degradation. .

  In a preferred embodiment, a roll of Al metal yarn is anodized, pore expanded, and placed in a CVD reactor using a reel-to-reel process to create nanowires and reverse conductivity doping into NW Coating (in one step), removed, and possibly coated with an electrode (cathode) using a CVD process followed by a protective polymer. In the reel-to-reel process, the yarn is oriented vertically as it passes through the reactor to minimize material distortion and deformation when exposed to the temperature and processing strain inherent in the reel-to-reel process. obtain.

  Although the above embodiment has described a method of making a SiNW array on partially anodized Al yarn, those skilled in the art have performed the same basic procedure on another geometry of Al metal, namely, AAO fine details. Apply to a layer of Al metal that is thick enough (1-2 microns) to form an AAO layer on the Al metal with sufficient Al metal at the bottom of the hole, thereby allowing the SiNW to properly nucleate It will be appreciated that a formed and still sufficient conductive Al metal layer can be left for use as an anode in an optoelectronic device. In one embodiment, a borosilicate slide glass is used that is coated with Al, partially anodized, and then grown with Si nanowires with a remaining Al layer sufficient for electrical contact. In this embodiment, the nanowire can be grown for 5 minutes. The reactor parameters can be a silane flow rate of 50 sccm in a reactor at a temperature of 600 ° C. and a pressure of 38 Torr.

  In a glass substrate embodiment, a layer of Al (1-20 microns thick) is deposited on the surface by electron beam evaporation, thermal evaporation, or sputter deposition, electroplating, physical coating or other techniques. Is deposited. The glass can have another conductive layer (ITO, metal, etc.) on the glass surface prior to Al coating to provide additional conductivity or other electrical functions. Thereafter, the Al is partially anodized using the AAO fabrication technique already described above, with a sufficient amount of porous AAO layer on the Al metal and below the AAO using the VLS technique. In the state in which the Al metal is held, it is prepared so as to function as a conductor and as a catalyst for SiNW growth. The basic process for porous AAO layer formation and SiNW growth follows the same basic outline as described above. Depending on the desired pore size and center-to-center distance, the appropriate electrolyte type, concentration and anodizing voltage are used. The integrity of the AAO barrier layer that forms at the bottom of the pores is disrupted using a step-down or electrolytic modification technique, thereby partially or completely removing the barrier layer using a phosphoric acid (or other acid) etching method be able to. A similar CVD process is then used to grow NW using Al as a catalyst for the VLS process.

  As noted above, when depositing a Si film or coating, the material will coat most of the reactor surface. This may create a need to remove masking of certain areas of the substrate so that it can later reach the conductive surface and contact the conductive surface as the anode or cathode of the device. Further, in a layered arrangement (eg, Al / AAO / glass), a conductive (doped) Si coating may make electrical contact with the Al layer and short circuit the anode and cathode of the device. Therefore, sacrificial edges that are removed after full electrical contact has been made may be used, or masking techniques may be utilized. In SiNW arrays grown on metal threads or wire arrays, there are no sacrificial edges and electrical shorts can be avoided by continuously feeding the wire source into the reaction chamber. In this embodiment, the yarn ends are placed outside the reactor, thus solving some or all of the “full coverage” problems associated with n-type deposition. Alternatively, the ends can be mechanically or chemically trimmed to fully cover the yarn and expose the anode (cathode) for electrical contact. A similar technique is used for the foil. Insulating the edge of the foil by creating a non-porous aluminum oxide layer around the edge of the foil to prevent SiNW nucleation and free of exposed edges of conductive material it can. Another option in the foil example is to trim the edge after complete anode, SiNW, diode junction formation and final electrode deposition to eliminate possible shorts.

  In another embodiment, the nanowires will nucleate away from Al without pore expansion etching. That is, the AAO barrier layer is still at the bottom of the pores, but the nanowires nevertheless grow. Furthermore, the barrier layer can be made somewhat thinner by introducing hydrogen into the reactor to decompose AAO into Al metal and reduce AAO.

  In another embodiment, the temperature of the reactor during the deposition of the n-type material is reduced to a temperature well below the melting point of aluminum. For example, the melting point of aluminum is 660 ° C. Thus, the CVD temperature can be reduced to about 650 ° C., thereby coating the device (SiNW) with an n-type layer using silane, hydrogen and phosphine as dopants. A lower temperature of about 550 ° C. can also be used to make SiNW. It can also be seen that conformal n-type layers can be obtained epitaxially or in a polycrystalline structure at temperatures below the melting point of Al using other gases such as disilane and silicon tetrachloride commonly used for silicon deposition. .

  In another embodiment, the SiNW is made by a vapor-solid-solid (VSS) growth mechanism at a temperature below the eutectic temperature, as opposed to VLS technology.

  In another embodiment, the SiNW is made at a lower temperature using a plasma enhanced chemical vapor deposition (PECVD) process.

The manufacturing methods disclosed herein are many VLS methods for growing SiNW by template, typically an electrochemical deposition of gold catalyst seeds into commercially available AAO films. Is different. In the present invention, Al metal under AAO is used as a catalyst. Therefore, every pore has a catalyst and SiNW grows vigorously. The SiNW grown by this process nucleates at the Al / AAO interface due to the formation of an Al—Si eutectic phase, and grows up and out of the AAO pores while maintaining the diameter. Since SiNW contains 10 ¹⁸ / cm ³ to 10 ²⁰ / cm ³ Al as a p-type dopant source, the Al catalyst self-doped NW without the need for additional dopant gas source, and SiNW is an Al metal And ohmic contact. The remaining Al layer is used as the anode of the PV device. At the final stage of SiNW growth, the reactor conditions are adjusted to produce a thin film layer that covers the AAO surface and connects the NWs together. The thin film maximizes the photoactive surface area and increases the level of manufacturing redundancy. That is, in order to prevent a short circuit, an unintentional pinhole in the AAO layer is filled before the n-type coating. A material such as p-silicon can be used.

Using an optimized substrate and appropriate CVD reactor conditions (detailed in the work plan), Al emerging from the eutectic phase AAO pores at the SiNW growth front becomes a dopant during the SiNW growth process. As used up. Therefore, a conformal n-type silicon film will be deposited in situ immediately after the VLS growth of the p-type NW. This will be achieved by introducing a short growth pause after the VLS growth of the p-type SiNW, during which the SiH ₄ is switched from the reactor and the reactor temperature increases. become. An increase in the growth temperature leads to an increase in the silicon thin film deposition rate. As a result, by adjusting the growth conditions, it is possible to switch between a region where NW growth is dominant and a region where thin film deposition is dominant. The n-type Si shell is polycrystalline at these deposition temperatures, but exhibits a uniform thickness along the length of the wire.

  Finally, to complete the production of functional nanomaterials, a conformal transparent conductive film (TCC) must be deposited on the n-type layer to act as the cathode. Although there are many options for TCC, the first method is flexible conductive PEDOT (polyethylene-3,4-dioxy) which is applied using GVD Corporation's oxidative chemical vapor deposition (oCVD) technology. Thiophene) is used. The oCVD process is a novel, all-dry low temperature method for forming an intrinsically conductive polymer coating on a wide range of substrates. oCVD “shrink-wraps” a high surface area substrate such as nanowires with a conformal and highly permeable conductive polymer coating. The coating is chemically pure, mechanically flexible and intrinsically conductive. Note that the figure shows a TCC that completely fills all voids to the height of the nanowire. A more realistic situation is shown in the SEM picture and it can be seen that the PEDOT coating (concave texture) is continuous and conformal to the outer surface of the NW. The final device will also have a transparent environmentally friendly protective layer on the TCC. Thus, TCC needs to be conformal and continuous to be an effective anode, but any remaining gaps are filled or covered with an environmentally friendly coating. Will not affect device performance.

  The described embodiments of the invention are exemplary only, and many variations and modifications will be apparent to those skilled in the art. All such variations and modifications are considered to be within the scope of the present invention as defined by the appended claims. Although the invention has been described and illustrated in detail, it should be clearly understood that they are intended to be illustrative and exemplary only and should not be taken in a limiting sense. It should be understood that the various features of the invention described in the context of separate embodiments for clarity can be provided in combination in one embodiment. Conversely, the various features of the invention described in the context of one embodiment for the sake of brevity may also be provided separately or in any appropriate combination. It should be understood that the specific embodiments described herein or the drawings are only intended to provide a very detailed disclosure of the present invention and are not intended to be limiting in any way. The spirit and scope of the present invention shall be limited only by the appended claims.

Claims (20)

A silicon nanowire device,
A substrate having a surface;
An anodized metal layer provided adjacent to the surface and having an outer surface opposite the surface;
A plurality of silicon nanowires of a first charge carrier type having a first end bonded to the substrate and a second end extending at least to the outer surface of the anodized layer;
A device comprising: a second charge carrier type silicon layer covering a second end of the plurality of nanowires, whereby the silicon layer is not directly electrically connected to the substrate.   The device of claim 1, wherein the silicon nanowires are doped with aluminum.   The device of claim 1, wherein the anodized layer is anodized.   The device of claim 1, wherein the substrate is aluminum.   The device of claim 1, wherein the silicon nanowires are doped with aluminum, the anodized layer is anodized, and the substrate is aluminum.   The device of claim 1, wherein the silicon nanowires protrude beyond the outer surface of the anodized layer. A method of forming a plurality of silicon nanowires,
Growing silicon nanowires through a plurality of pores in the anodized layer adjacent to the aluminum layer using the VLS process with aluminum at the bottom of the anodized pores as a catalyst;
Coating the silicon nanowires with an N-type semiconductor.   8. The method of claim 7, further comprising anodizing the aluminum layer so as not to reach the surface of the substrate prior to forming a plurality of pores.   8. The method of claim 7, further comprising removing the masking of the predetermined region by forming an alumina layer having no pores in the predetermined region of the aluminum layer.   The method of claim 7, further comprising preventing electrical contact between the n-type layer and the substrate.   8. The method of claim 7, further comprising continuing the VLS process until the aluminum comprising the catalyst is used up as the dopant of the silicon nanowires. A method for forming a silicon nanowire device, comprising:
Anodizing the aluminum layer, and forming a plurality of pores extending from the outer surface of the anodized layer to a location in the interface region at the bottom surface of the anodized layer, and a part of the aluminum at the bottom of the plurality of pores The step of making the
Growing silicon nanowires using a VLS process such that the aluminum remaining at the bottom of the plurality of pores is used both as a catalyst at the eutectic tip and as the dopant of the silicon nanowires. A method characterized by that.   13. The method of claim 12, further comprising continuing the growth of the silicon nanowire until the aluminum catalyst at the eutectic tip is consumed as a dopant for the silicon nanowire.   The method of claim 12, further comprising removing the eutectic tips of the plurality of silicon nanowires to remove the remaining catalyst.   The method of claim 10, further comprising coating the device with a protective film to prevent the N-type layer and the substrate from being short-circuited through pores in which silicon nanowires are not grown. the method of.   The method of claim 7, further comprising the step of coating the nanowire with an intrinsic silicon layer before coating with the N-type silicon layer.   The method of claim 7, further comprising the step of coating the nanowire with a P-type silicon layer before coating with the N-type silicon layer.   8. The method of claim 7, further comprising etching the N-type silicon layer from a predetermined region of the anodized surface.   The device of claim 1, further comprising a layer of transparent conductor in functional contact with the N-type silicon layer.   20. The device of claim 19, further comprising a metallic conductive wire in functional contact with the transparent conductor layer.

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