JP2016157726A - Manufacturing device and manufacturing method of impurity semiconductor layer - Google Patents

Manufacturing device and manufacturing method of impurity semiconductor layer Download PDF

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JP2016157726A
JP2016157726A JP2015032857A JP2015032857A JP2016157726A JP 2016157726 A JP2016157726 A JP 2016157726A JP 2015032857 A JP2015032857 A JP 2015032857A JP 2015032857 A JP2015032857 A JP 2015032857A JP 2016157726 A JP2016157726 A JP 2016157726A
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electrode
impurity semiconductor
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semiconductor layer
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JP6525136B2 (en
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本間 敬之
Noriyuki Honma
敬之 本間
康博 福中
Yasuhiro Fukunaka
康博 福中
美紀子 齋藤
Mikiko Saito
美紀子 齋藤
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Waseda University
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Abstract

PROBLEM TO BE SOLVED: To provide a manufacturing device and a manufacturing method of an impurity semiconductor layer, which can easily manufacture an impurity semiconductor layer in a simple manufacturing process under the atmosphere.SOLUTION: An impurity semiconductor layer manufacturing device 11 comprises: an accumulation part 12 where either one of a p-type impurity ion or an n-type impurity ion and an electrolyte 13 containing a semiconductor ion are accumulated; a working electrode 14 immersed in the electrolyte 13 in the accumulation part 12; a counter electrode 15 arranged opposite to the working electrode 14; and a controlled-potential electrolysis part 17 which causes a current to flow between the working electrode 14 and the counter electrode 15 and causes p-type or n-type impurity semiconductor to be electrolytically deposited on a surface of the electrode layer 2 of the working electrode 14 to form an impurity semiconductor layer on the surface of the electrode layer 2. Only by flowing a current between the working electrode 14 and the counter electrode 15, the impurity semiconductor can be electrolytically deposited on the surface of the electrode layer 2 to form the impurity semiconductor layer by reduction reaction of the p-type impurity ion or the n-type impurity ion which is contained in the electrolyte 13 with the semiconductor ion.SELECTED DRAWING: Figure 2

Description

本発明は、不純物半導体層の製造装置及び製造方法に関する。   The present invention relates to an impurity semiconductor layer manufacturing apparatus and manufacturing method.

p型不純物又はn型不純物が半導体膜中に添加された不純物半導体層を製造する製造方法としては、例えば基板上に形成されたシリコンなどの半導体膜に、例えばホウ素などのp型不純物や、ヒ素などのn型不純物をイオン化して注入するイオン注入法が知られている。   As a manufacturing method for manufacturing an impurity semiconductor layer in which a p-type impurity or an n-type impurity is added to a semiconductor film, for example, a p-type impurity such as boron or arsenic is formed on a semiconductor film such as silicon formed on a substrate. An ion implantation method is known in which n-type impurities such as those are ionized and implanted.

例えば、特許文献1に開示されるイオン注入法により不純物半導体層を製造する製造方法では、まず始めに、イオン源ガスと、カソードフィラメントから放出された電子とを衝突させて、イオン源チャンバ内に複数種のイオンを生成し、引出電極によってイオン源チャンバから複数のイオンを引き出してイオンビームを生成する。   For example, in a manufacturing method for manufacturing an impurity semiconductor layer by an ion implantation method disclosed in Patent Document 1, first, an ion source gas and electrons emitted from a cathode filament are collided to enter an ion source chamber. A plurality of types of ions are generated, and a plurality of ions are extracted from the ion source chamber by the extraction electrode to generate an ion beam.

次いで、この従来の製造方法では、質量分離法によって、イオンビーム内に含まれる複数種のイオンを単一種のイオンに分離し、当該イオンを加速器で加速した後、四極レンズで収束させたイオンを、真空チャンバ内に設置した半導体膜に照射する。このようにして従来の製造方法では、p型不純物又はn型不純物が半導体膜内にイオン注入された不純物半導体層を製造し得る。   Next, in this conventional manufacturing method, a plurality of types of ions contained in the ion beam are separated into a single type of ions by mass separation, and the ions are accelerated by an accelerator, and then focused by a quadrupole lens. Irradiate the semiconductor film installed in the vacuum chamber. In this way, the conventional manufacturing method can manufacture an impurity semiconductor layer in which p-type impurities or n-type impurities are ion-implanted into the semiconductor film.

特開2006−19048号公報JP 2006-19048 A

しかしながら、このような従来の製造方法では、p型不純物又はn型不純物が半導体膜内に添加された不純物半導体層を製造する際、半導体膜に直接イオンを打ち込んでいるため、当該半導体膜が設置される真空チャンバ内を高真空状態に維持する必要があり、製造工程が煩雑であるという問題があった。   However, in such a conventional manufacturing method, when manufacturing an impurity semiconductor layer in which a p-type impurity or an n-type impurity is added to the semiconductor film, ions are directly implanted into the semiconductor film. There is a problem that the inside of the vacuum chamber to be maintained must be maintained in a high vacuum state, and the manufacturing process is complicated.

そこで、本発明は、上記のような問題に鑑みてなされたものであり、大気雰囲気下での簡易な製造工程によって不純物半導体層を容易に製造できる不純物半導体層の製造装置及び製造方法を提供することを目的とする。   Therefore, the present invention has been made in view of the above problems, and provides an impurity semiconductor layer manufacturing apparatus and a manufacturing method that can easily manufacture an impurity semiconductor layer by a simple manufacturing process in an air atmosphere. For the purpose.

本発明による不純物半導体層の製造装置は、p型不純物イオン又はn型不純物イオンのいずれか一方と、半導体イオンとを含有した電解液が貯留された貯留部と、前記貯留部内にて前記電解液に浸漬された作用電極と、前記貯留部内にて前記電解液に浸漬され、前記作用電極と対向配置された対電極と、前記作用電極と前記対電極との間に電流を流し、前記作用電極の電極層表面に、p型又はn型の不純物半導体を電解析出させ、該電極層表面に不純物半導体層を形成させる定電位電解部とを備えることを特徴とする。   An apparatus for manufacturing an impurity semiconductor layer according to the present invention includes a storage part in which an electrolytic solution containing either p-type impurity ions or n-type impurity ions and semiconductor ions is stored, and the electrolytic solution in the storage part. A working electrode immersed in the storage portion, a counter electrode immersed in the electrolytic solution in the reservoir, and disposed opposite to the working electrode, and passing a current between the working electrode and the counter electrode, and the working electrode And a constant-potential electrolysis unit for electrolytically depositing a p-type or n-type impurity semiconductor on the surface of the electrode layer and forming the impurity semiconductor layer on the surface of the electrode layer.

本発明による不純物半導体層の製造方法は、p型不純物イオン又はn型不純物イオンのいずれか一方と、半導体イオンとを含有した電解液が貯留された貯留部内に、前記電解液に浸漬させるように作用電極と対電極とを対向配置させ、定電位電解部によって、前記作用電極と前記対電極との間に電流を流し、前記作用電極の電極層表面に、p型又はn型の不純物半導体を電解析出させ、該電極層表面に不純物半導体層を形成することを特徴とする。   In the method of manufacturing an impurity semiconductor layer according to the present invention, the electrolytic solution is immersed in a storage part in which an electrolytic solution containing either p-type impurity ions or n-type impurity ions and semiconductor ions is stored. A working electrode and a counter electrode are arranged opposite to each other, and a current is passed between the working electrode and the counter electrode by a constant-potential electrolysis unit, and a p-type or n-type impurity semiconductor is formed on the electrode layer surface of the working electrode. An impurity semiconductor layer is formed on the surface of the electrode layer by electrolytic deposition.

本発明によれば、貯留部内にて電解液に浸漬させた作用電極と対電極との間に電流を流すだけで、電解液に含有しているp型不純物イオン又はn型不純物イオンと、半導体イオンとの還元反応により、電極層の表面に不純物半導体を電解析出させて不純物半導体層を形成でき、かくして、従来のような真空状態を維持する煩雑な製造工程が不要となり、大気雰囲気下での簡易な製造工程によって不純物半導体層を容易に形成できる。   According to the present invention, the p-type impurity ions or the n-type impurity ions contained in the electrolytic solution and the semiconductor can be obtained by simply passing a current between the working electrode and the counter electrode immersed in the electrolytic solution in the reservoir. Due to the reduction reaction with ions, an impurity semiconductor can be electrolytically deposited on the surface of the electrode layer to form an impurity semiconductor layer, thus eliminating the need for a complicated manufacturing process for maintaining a vacuum state as in the prior art. The impurity semiconductor layer can be easily formed by this simple manufacturing process.

本発明の製造方法で製造した不純物半導体層を備える不純物半導体素子を示す模式図である。It is a schematic diagram which shows an impurity semiconductor element provided with the impurity semiconductor layer manufactured with the manufacturing method of this invention. 本発明の製造装置を示す概略図である。It is the schematic which shows the manufacturing apparatus of this invention.

1.不純物半導体素子の構成
図1において1は、本発明による製造方法によって製造された不純物半導体層3を備える不純物半導体素子を示す。この場合、不純物半導体素子1は、例えば石英ガラスなどにより板状に形成された基板4と、当該基板4の表面に設けられた層状の電極層2と、当該電極層2の表面に形成された所定パターンの不純物半導体層3とを有する。電極層2は、例えばAuやCrなどの金属で形成されており、不純物半導体層3を形成するために後述する製造装置に設置された際に、当該製造装置の電極として機能し得る。不純物半導体層3は、電極層2の表面に配置された複数の不純物半導体部3aにより構成されている。
1. Configuration of Impurity Semiconductor Element In FIG. 1, reference numeral 1 denotes an impurity semiconductor element including an impurity semiconductor layer 3 manufactured by a manufacturing method according to the present invention. In this case, the impurity semiconductor element 1 is formed on the surface of the substrate 4 formed on the surface of the substrate 4, the layered electrode layer 2 provided on the surface of the substrate 4, for example. And an impurity semiconductor layer 3 having a predetermined pattern. The electrode layer 2 is formed of a metal such as Au or Cr, for example, and can function as an electrode of the manufacturing apparatus when it is installed in a manufacturing apparatus described later to form the impurity semiconductor layer 3. The impurity semiconductor layer 3 is composed of a plurality of impurity semiconductor portions 3 a disposed on the surface of the electrode layer 2.

これら複数の不純物半導体部3aは、全て同一構成を有しており、例えばSiなどの半導体と、Alなどのp型不純物とが混在した不純物半導体により形成されており、外郭が所定形状に形成されている。なお、この実施の形態の場合、不純物半導体部3aは、例えば円柱形状に形成されており、その底面が電極層2の表面に固着され、当該電極層2の表面に対して立設するように配置されている。また、この実施の形態の場合、不純物半導体層3は、互いに隣接する不純物半導体部3a同士が所定間隔を空けて規則的に配置され、所定のパターンを形成している。そして、このような複数の不純物半導体部3aからなる不純物半導体層3は後述する製造装置により形成し得る。   The plurality of impurity semiconductor portions 3a all have the same configuration, and are formed of an impurity semiconductor in which a semiconductor such as Si and a p-type impurity such as Al are mixed, and the outer shape is formed in a predetermined shape. ing. In the case of this embodiment, the impurity semiconductor portion 3a is formed in a columnar shape, for example, and its bottom surface is fixed to the surface of the electrode layer 2 so as to stand on the surface of the electrode layer 2 Has been placed. In the case of this embodiment, the impurity semiconductor layer 3 has a predetermined pattern in which the impurity semiconductor portions 3a adjacent to each other are regularly arranged at a predetermined interval. And the impurity semiconductor layer 3 which consists of such a some impurity semiconductor part 3a can be formed with the manufacturing apparatus mentioned later.

2.本発明の製造装置の構成
次に、不純物半導体層3を電極層2の表面に形成する本発明の製造装置について説明する。図2に示すように、本発明の製造装置11は、容器状の貯留部12を有しており、当該貯留部12内に所定量の電解液13が貯留されている。
2. Next, the manufacturing apparatus of the present invention for forming the impurity semiconductor layer 3 on the surface of the electrode layer 2 will be described. As shown in FIG. 2, the manufacturing apparatus 11 of the present invention has a container-like storage part 12, and a predetermined amount of electrolytic solution 13 is stored in the storage part 12.

貯留部12内には、作用電極14と対電極15と参照電極16とが電解液13に浸漬され得るように配置されている。この場合、対電極15は、例えばPtなどの金属で針金状に形成されており、貯留部12内にて作用電極14と対向配置されている。また、参照電極16は、例えばPtやAgなどの金属で針金状に形成されており、作用電極14及び対電極15間に配置されている。   In the storage part 12, the working electrode 14, the counter electrode 15, and the reference electrode 16 are arrange | positioned so that it can be immersed in the electrolyte solution 13. FIG. In this case, the counter electrode 15 is formed in a wire shape with a metal such as Pt, and is disposed opposite to the working electrode 14 in the reservoir 12. The reference electrode 16 is formed in a wire shape with a metal such as Pt or Ag, and is disposed between the working electrode 14 and the counter electrode 15.

作用電極14には、基板4の一方の表面に層状の電極層2が形成されており、当該電極層2の表面に所定パターンのフォトレジスト層14aが配置されている。この実施の形態の場合、フォトレジスト層14aは、厚みを貫通するように複数の貫通孔14bが穿設されており、各貫通孔14b内にて電極層2が外部に露出している。   In the working electrode 14, a layered electrode layer 2 is formed on one surface of the substrate 4, and a photoresist layer 14 a having a predetermined pattern is disposed on the surface of the electrode layer 2. In the case of this embodiment, the photoresist layer 14a has a plurality of through holes 14b penetrating its thickness, and the electrode layer 2 is exposed to the outside in each through hole 14b.

因みに、この実施の形態の場合、フォトレジスト層14aは、各貫通孔14bが全て同一の形状を有しており、隣接する貫通孔14b同士が所定間隔を空けて規則的に配置された構成を有する。なお、この実施の形態の場合、貫通孔14bは、フォトレジスト層14aを表面から見たとき、孔形状が円形状に形成されており、フォトレジスト層14aに円柱状の空間を形成し得るようになされている。   Incidentally, in the case of this embodiment, the photoresist layer 14a has a configuration in which all the through holes 14b have the same shape, and the adjacent through holes 14b are regularly arranged with a predetermined interval therebetween. Have. In the case of this embodiment, the through-hole 14b has a circular shape when the photoresist layer 14a is viewed from the surface, so that a cylindrical space can be formed in the photoresist layer 14a. Has been made.

因みに、このような作用電極14は、電子ビーム蒸着法などにより電極層2を基板4上に形成した後、UVナノインプリント法などのリソグラフィ技術を用いてフォトレジスト層14aを電極層2上に形成することで作製できる。例えばUVナノインプリント法を用いた場合は、まず表面に円柱形状の凸部が所定の間隔をあけて規則的に配置された原版を用意する。次に、電極層2の表面にフォトレジストを塗布した後、原版の凸部の先端が電極層2の表面に接触するまで原版を電極層2に押し付ける。この際、電極層2の表面と原版の表面との間は、フォトレジストで充満した状態となる。最後に、紫外線を、原版を介してフォトレジストに照射して、電極層2の表面と原版の表面との間のフォトレジストを固化させることで、原版の凸部形状に対応した形状の貫通孔14bが規則的に配置されたフォトレジスト層14aを形成できる。   Incidentally, in such a working electrode 14, after the electrode layer 2 is formed on the substrate 4 by an electron beam evaporation method or the like, a photoresist layer 14a is formed on the electrode layer 2 by using a lithography technique such as a UV nanoimprint method. Can be produced. For example, when the UV nanoimprint method is used, first, an original plate is prepared in which cylindrical convex portions are regularly arranged on the surface at predetermined intervals. Next, after applying a photoresist on the surface of the electrode layer 2, the original plate is pressed against the electrode layer 2 until the tip of the convex portion of the original plate contacts the surface of the electrode layer 2. At this time, the space between the surface of the electrode layer 2 and the surface of the original plate is filled with the photoresist. Finally, the photoresist is irradiated with ultraviolet rays through the original plate to solidify the photoresist between the surface of the electrode layer 2 and the surface of the original plate, thereby forming a through-hole having a shape corresponding to the convex shape of the original plate. A photoresist layer 14a in which 14b is regularly arranged can be formed.

これに加えて、この製造装置11には、定電位電解部17が設けられており、作用電極14の電極層2に接続された導線18aと、対電極15に接続された導線18bと、参照電極16に接続された導線18cとが、当該定電位電解部17にそれぞれ接続されている。定電位電解部17は、導線18a及び導線18bを介して電解液13内の作用電極14と対電極15との間に電流を流すとともに、導線18a及び導線18cを介して作用電極14と参照電極16との間の電位差を測定し得るようになされている。これにより、定電位電解部17は、参照電極16を基準としたときの作用電極14及び参照電極16間の電位差を、作用電極14の電位と見なし、当該電位が所定の値となるように、電解液13内にて作用電極14と対電極15との間に流す電流を調整し得る。   In addition to this, the manufacturing apparatus 11 is provided with a constant potential electrolysis unit 17, a conductive wire 18 a connected to the electrode layer 2 of the working electrode 14, a conductive wire 18 b connected to the counter electrode 15, and a reference Conductive wires 18c connected to the electrodes 16 are connected to the constant potential electrolysis unit 17, respectively. The constant potential electrolysis unit 17 allows a current to flow between the working electrode 14 and the counter electrode 15 in the electrolytic solution 13 through the conducting wire 18a and the conducting wire 18b, and the working electrode 14 and the reference electrode through the conducting wire 18a and the conducting wire 18c. A potential difference between 16 and 16 can be measured. Thereby, the constant potential electrolysis unit 17 regards the potential difference between the working electrode 14 and the reference electrode 16 when the reference electrode 16 is used as a reference as the potential of the working electrode 14, so that the potential becomes a predetermined value. The current flowing between the working electrode 14 and the counter electrode 15 in the electrolytic solution 13 can be adjusted.

ここで、作用電極14、対電極15及び参照電極16が浸漬される電解液13は、例えば、p型の不純物半導体層3を形成する場合、半導体イオン(Siイオン)とp型不純物イオン(Alイオン)とがイオン液体内に溶解された電解液13が用いられる。これにより、作用電極14には、作用電極14と対電極15との間に電流が流れることで、フォトレジスト層14aの各貫通孔14b内で電解液13に露出している電極層2の表面に、半導体イオン及びp型不純物イオンの還元反応によって、半導体及びp型不純物が混在したp型の不純物半導体が電解析出し得る。   Here, the electrolytic solution 13 in which the working electrode 14, the counter electrode 15, and the reference electrode 16 are immersed is, for example, when forming the p-type impurity semiconductor layer 3, semiconductor ions (Si ions) and p-type impurity ions (Al An electrolytic solution 13 in which ions are dissolved in an ionic liquid is used. As a result, a current flows between the working electrode 14 and the counter electrode 15 in the working electrode 14, so that the surface of the electrode layer 2 exposed to the electrolytic solution 13 in each through hole 14 b of the photoresist layer 14 a. In addition, the p-type impurity semiconductor in which the semiconductor and the p-type impurity are mixed can be electrolytically deposited by the reduction reaction of the semiconductor ions and the p-type impurity ions.

かくして、作用電極14には、フォトレジスト層14aの貫通孔14bごとに、p型の不純物半導体でなる不純物半導体部3aが形成され、これら複数の不純物半導体部3aが所定間隔で配置された不純物半導体層3が電極層2の表面に形成され得る。   Thus, in the working electrode 14, an impurity semiconductor portion 3a made of a p-type impurity semiconductor is formed for each through hole 14b of the photoresist layer 14a, and an impurity semiconductor in which the plurality of impurity semiconductor portions 3a are arranged at a predetermined interval. Layer 3 can be formed on the surface of electrode layer 2.

なお、この実施の形態の場合、電解液13は、例えば、トリメチルヘキシルアンモニウム‐ビス(トリフルオロメタンスルホニル)イミド(TMHA‐TFSI)などのイオン液体に、SiClなどの半導体化合物と、AlClなどのp型不純物化合物とを溶解することにより生成し得る。これにより、電解液13は、半導体化合物とp型不純物化合物とがイオン液体に溶解する過程でイオン化され、半導体イオンとp型不純物イオンとがイオン液体内に存在した状態となり得る。因みに、イオン液体へのp型不純物の添加量を調整することで、電解析出する不純物半導体でのp型不純物の含有量を調整できる。 In the case of this embodiment, the electrolytic solution 13 is made of, for example, an ionic liquid such as trimethylhexylammonium-bis (trifluoromethanesulfonyl) imide (TMHA-TFSI), a semiconductor compound such as SiCl 4 , and AlCl 3 or the like. It can be produced by dissolving a p-type impurity compound. As a result, the electrolytic solution 13 can be ionized in the process in which the semiconductor compound and the p-type impurity compound are dissolved in the ionic liquid, and the semiconductor ion and the p-type impurity ion can be in a state of being present in the ionic liquid. Incidentally, by adjusting the amount of p-type impurity added to the ionic liquid, the content of the p-type impurity in the impurity semiconductor that is electrolytically deposited can be adjusted.

ここで、p型不純物化合物としては、例えば塩化、臭化、フッ化又はよう化したAl、Ga、B、Tlを適用することができ、この場合、p型不純物イオンとして、Alイオン、Gaイオン、Bイオン、Tlイオンを電解液内に含有させることができる。   Here, as the p-type impurity compound, for example, chlorinated, brominated, fluorinated or iodide Al, Ga, B, Tl can be applied. In this case, as the p-type impurity ions, Al ions, Ga ions are used. , B ions, and Tl ions can be contained in the electrolyte.

また、半導体化合物としては塩化、臭化、フッ化又はよう化した、Si、Geを適用することができ、この場合、半導体イオンとしてSiイオン、Geイオンを電解液内に含有させることができる。   Further, as the semiconductor compound, Si or Ge that is chlorinated, brominated, fluorinated, or iodide can be applied. In this case, Si ions and Ge ions can be contained in the electrolyte as semiconductor ions.

因みに、上述した実施の形態においては、溶媒としてのイオン液体にp型不純物化合物を添加して、p型不純物イオンがイオン液体内に溶解した電解液13を適用する場合について述べたが、本発明はこれに限らず、イオン液体にn型不純物化合物を添加して、n型不純物イオンがイオン液体内に溶解した電解液を適用してもよい。   Incidentally, in the above-described embodiment, the case where the p-type impurity compound is added to the ionic liquid as the solvent and the electrolytic solution 13 in which the p-type impurity ions are dissolved is applied is described. However, the present invention is not limited to this, and an electrolytic solution in which an n-type impurity compound is added to an ionic liquid and the n-type impurity ions are dissolved in the ionic liquid may be applied.

このようなn型不純物イオンがイオン液体内に溶解した電解液を用いた場合には、フォトレジスト層14aの各貫通孔14b内の電極層2に、n型の不純物半導体を電解析出させることができ、かくして、n型の不純物半導体でなる複数の不純物半導体部が所定間隔で配置されたn型の不純物半導体層を電極層2の表面に形成できる。   When an electrolytic solution in which such n-type impurity ions are dissolved in an ionic liquid is used, an n-type impurity semiconductor is electrolytically deposited on the electrode layer 2 in each through hole 14b of the photoresist layer 14a. Thus, an n-type impurity semiconductor layer in which a plurality of impurity semiconductor portions made of an n-type impurity semiconductor are arranged at a predetermined interval can be formed on the surface of the electrode layer 2.

因みに、この場合、n型不純物化合物としては、塩化、臭化、フッ化又はよう化したP、Sb、Biを適用することができ、これにより、n型不純物イオンとして、Pイオン、Sbイオン、Biイオンを電解液内に含有させることができる。   Incidentally, in this case, as the n-type impurity compound, it is possible to apply P, Sb, Bi that is chlorinated, brominated, fluorinated, or iodide, and as a result, P ions, Sb ions, Bi ions can be contained in the electrolytic solution.

なお、上述した実施の形態のように、イオン液体としてTMHA‐TFSIを適用し、半導体化合物としてSiClを適用し、p型不純物化合物としてAlClを適用した場合には、TMHA‐TFSIに対して、SiClを0.5Mの濃度で混合し、AlClを8.8×10-4Mの濃度で混合することが好ましい。 As in the embodiment described above, when TMHA-TFSI is applied as the ionic liquid, SiCl 4 is applied as the semiconductor compound, and AlCl 3 is applied as the p-type impurity compound, the TMHA-TFSI is It is preferable to mix SiCl 4 at a concentration of 0.5M and AlCl 3 at a concentration of 8.8 × 10 −4 M.

3.本発明による不純物半導体層の製造方法
次に、上述の製造装置11を用いて不純物半導体層3を製造する製造方法について説明する。この場合、定電位電解部17により、貯留部12内の電解液13に浸漬された作用電極14及び対電極15間に流す電流を調整し、作用電極14の電位を負の所定の値にする。当該作用電極14の電位を所定時間維持し、フォトレジスト層14aの貫通孔14b内にて電解液13に露出している電極層2の表面に、半導体イオン及びp型不純物イオンの還元反応によって、半導体及びp型不純物が混在したp型の不純物半導体を電解析出させる。これにより、製造装置11では、作用電極14の貫通孔14bごとに不純物半導体部3aが形成され、これら複数の不純物半導体部3aが所定パターンで配置された不純物半導体層3を作製できる。
3. Next, a manufacturing method for manufacturing the impurity semiconductor layer 3 using the manufacturing apparatus 11 described above will be described. In this case, the constant potential electrolysis unit 17 adjusts the current flowing between the working electrode 14 and the counter electrode 15 immersed in the electrolytic solution 13 in the storage unit 12, and sets the potential of the working electrode 14 to a negative predetermined value. . By maintaining the potential of the working electrode 14 for a predetermined time and reducing the semiconductor ions and p-type impurity ions on the surface of the electrode layer 2 exposed to the electrolytic solution 13 in the through hole 14b of the photoresist layer 14a, A p-type impurity semiconductor in which a semiconductor and a p-type impurity are mixed is electrolytically deposited. Thereby, in the manufacturing apparatus 11, the impurity semiconductor part 3a is formed for every through-hole 14b of the working electrode 14, and the impurity semiconductor layer 3 by which these several impurity semiconductor parts 3a are arrange | positioned by the predetermined pattern can be produced.

上述の実施の形態の場合、作用電極14の電位を-4V以上-1V以下となるようにし、当該作用電極14の電位を0.01時間以上1時間以下の間維持する。因みに、作用電極14の電位の値を調整することで、不純物半導体層3のp型不純物の含有量を調整できる。   In the case of the above-described embodiment, the potential of the working electrode 14 is set to −4 V or more and −1 V or less, and the potential of the working electrode 14 is maintained for 0.01 hour or more and 1 hour or less. Incidentally, the content of the p-type impurity in the impurity semiconductor layer 3 can be adjusted by adjusting the value of the potential of the working electrode 14.

次いで、製造装置11の貯留部12から作用電極14を取り出した後、例えばプラズマアッシャーによって、作用電極14のフォトレジスト層14aを除去することにより、基板4上の電極層2の表面に、複数の不純物半導体部3aでなる不純物半導体層3が形成された不純物半導体素子1を製造できる。   Next, after the working electrode 14 is taken out from the storage unit 12 of the manufacturing apparatus 11, the photoresist layer 14a of the working electrode 14 is removed by, for example, a plasma asher, so that a plurality of surfaces are formed on the surface of the electrode layer 2 on the substrate 4. The impurity semiconductor element 1 in which the impurity semiconductor layer 3 including the impurity semiconductor portion 3a is formed can be manufactured.

また、この実施の形態に場合、最後に、真空中、又は例えばArなどの不活性ガス中に不純物半導体素子1を置き、不純物半導体素子1を100℃以上1500℃以下で0.1時間以上加熱して熱処理を行う。このような熱処理によって、不純物半導体素子1における不純物半導体層3の結晶性を向上できると共に、当該不純物半導体層3に含まれているCの量を低減できる。   In this embodiment, finally, the impurity semiconductor element 1 is placed in a vacuum or an inert gas such as Ar, and the impurity semiconductor element 1 is heated at 100 ° C. to 1500 ° C. for 0.1 hour or more. Heat treatment is performed. By such heat treatment, the crystallinity of the impurity semiconductor layer 3 in the impurity semiconductor element 1 can be improved, and the amount of C contained in the impurity semiconductor layer 3 can be reduced.

4.作用及び効果
以上の構成において、本発明の製造装置11では、溶媒としてのイオン液体中にp型不純物イオン及び半導体イオンを含有した電解液13が貯留された貯留部12と、貯留部12内で電解液13に浸漬されて対向配置された作用電極14及び対電極15と、作用電極14及び対電極15間に電流を流す定電位電解部17とを設けるようにした。
4). Operation and Effect In the above-described configuration, in the manufacturing apparatus 11 of the present invention, the storage unit 12 in which the electrolytic solution 13 containing p-type impurity ions and semiconductor ions is stored in the ionic liquid as the solvent, and the storage unit 12 A working electrode 14 and a counter electrode 15 which are immersed in the electrolytic solution 13 and arranged to face each other, and a constant-potential electrolysis unit 17 for passing a current between the working electrode 14 and the counter electrode 15 are provided.

そして、この製造装置11では、電解液13内に浸漬させた作用電極14と対電極15との間に、定電位電解部17により電流を流して作用電極14の電位を所定の値に設定するようにしたことにより、作用電極14に設けたフォトレジスト層14aの各貫通孔14b内にそれぞれ露出した電極層2の表面に、p型の不純物半導体が電解析出してゆき、当該電極層2の表面に不純物半導体層3を形成できる。   In this manufacturing apparatus 11, a current is passed by the constant potential electrolysis unit 17 between the working electrode 14 and the counter electrode 15 immersed in the electrolytic solution 13 to set the potential of the working electrode 14 to a predetermined value. By doing so, a p-type impurity semiconductor is electrolytically deposited on the surface of the electrode layer 2 exposed in each through-hole 14b of the photoresist layer 14a provided in the working electrode 14, and the electrode layer 2 The impurity semiconductor layer 3 can be formed on the surface.

このように、本発明の製造装置11では、貯留部12内にて電解液13に浸漬させた作用電極14と対電極15との間に電流を流すだけで、電解液13に含有しているp型不純物イオンと、半導体イオンとの還元反応により、電極層2の表面に不純物半導体を電解析出させて不純物半導体層3を形成でき、かくして、従来のような真空状態を維持する煩雑な製造工程が不要となり、大気雰囲気下での簡易な製造工程によって不純物半導体層3を容易に形成できる。   Thus, in the manufacturing apparatus 11 of the present invention, it is contained in the electrolytic solution 13 only by passing a current between the working electrode 14 immersed in the electrolytic solution 13 in the reservoir 12 and the counter electrode 15. The impurity semiconductor layer 3 can be formed by electrolytically depositing an impurity semiconductor on the surface of the electrode layer 2 by the reduction reaction between the p-type impurity ions and the semiconductor ions, and thus a complicated manufacturing process that maintains a vacuum state as in the prior art. A process becomes unnecessary, and the impurity semiconductor layer 3 can be easily formed by a simple manufacturing process in an air atmosphere.

また、本発明の製造装置11では、複数の貫通孔14bを所定パターンで形成したフォトレジスト層14aを、電極層2の表面に設け、各貫通孔14b内に露出した電極層2の表面に、電解析出により不純物半導体部3aをそれぞれ形成するようにした。これにより、本発明の製造装置11では、フォトレジスト層14aの貫通孔14bに対応した位置にそれぞれ不純物半導体部3aを形成し得、これら複数の不純物半導体部3aが所望のパターンで配置された不純物半導体層3を電極層2上に形成できる。   Further, in the manufacturing apparatus 11 of the present invention, a photoresist layer 14a in which a plurality of through holes 14b are formed in a predetermined pattern is provided on the surface of the electrode layer 2, and on the surface of the electrode layer 2 exposed in each through hole 14b, The impurity semiconductor portions 3a are formed by electrolytic deposition. Thereby, in the manufacturing apparatus 11 of this invention, the impurity semiconductor part 3a can be formed in the position corresponding to the through-hole 14b of the photoresist layer 14a, respectively, and these several impurity semiconductor parts 3a are arranged by the desired pattern The semiconductor layer 3 can be formed on the electrode layer 2.

従って、本発明の製造装置11では、最終的に形成したい不純物半導体層3の所望パターンに合わせて、複数の貫通孔14bを配置させたフォトレジスト層14aを単に電極層2の表面に形成しておくだけで、不純物半導体部3aが所望パターンに配置された不純物半導体層3を形成できるので、不純物半導体層3の形成工程と同時に、不純物半導体層3のパターニング工程をも行うことができ、その分、従来のように層状の不純物半導体層を形成した後にエッチング技術により層状の不純物半導体層を別途パターニングする場合に比して、製造工程を簡略化できる。   Therefore, in the manufacturing apparatus 11 of the present invention, a photoresist layer 14a having a plurality of through holes 14b is simply formed on the surface of the electrode layer 2 in accordance with a desired pattern of the impurity semiconductor layer 3 to be finally formed. Since the impurity semiconductor layer 3 having the impurity semiconductor portion 3a arranged in a desired pattern can be formed simply by placing the impurity semiconductor portion 3a, the impurity semiconductor layer 3 can be patterned simultaneously with the impurity semiconductor layer 3 formation step. The manufacturing process can be simplified as compared with the case where the layered impurity semiconductor layer is separately patterned by an etching technique after the layered impurity semiconductor layer is formed as in the prior art.

また、この製造装置11では、フォトレジスト層14aに形成する貫通孔14bの形状を変えるだけで、所望する形状の不純物半導体部3aを容易に形成できる。   Further, in this manufacturing apparatus 11, the impurity semiconductor portion 3a having a desired shape can be easily formed simply by changing the shape of the through hole 14b formed in the photoresist layer 14a.

5.検証試験
次に、上述の本発明による製造装置11を用いて不純物半導体層3を作製し、作製した不純物半導体層の特性について評価した。この検証試験では、半導体化合物としてSiClを用い、p型不純物化合物としてAlClを用い、溶媒としてTMHA‐TFSIを用いて電解液13を作製した。具体的には、SiClとAlClとをそれぞれ0.5M,8.8×10-4Mの濃度でTMHA‐TFSIに溶解させて、半導体イオンとしてSiイオンを含有し、かつp型不純物イオンとしてAlイオンを含有した電解液13を作製した。
5. Verification Test Next, the impurity semiconductor layer 3 was produced using the manufacturing apparatus 11 according to the present invention described above, and the characteristics of the produced impurity semiconductor layer were evaluated. In this verification test, an electrolytic solution 13 was prepared using SiCl 4 as a semiconductor compound, AlCl 3 as a p-type impurity compound, and TMHA-TFSI as a solvent. Specifically, SiCl 4 and AlCl 3 are dissolved in TMHA-TFSI at concentrations of 0.5M and 8.8 × 10 −4 M, respectively, contain Si ions as semiconductor ions, and Al ions as p-type impurity ions The electrolyte solution 13 containing was produced.

また、この検証試験では、石英ガラスでなる板状の基板4を用意し、電子ビーム蒸着によって、厚さ0.01μmのCr層と、厚さ0.2μmのAu層とを基板4上に順に積層して電極層2を作製した。次いで、UVナノインプリント法により、貫通孔14bが所定パターンで形成されたフォトレジスト層14aを、電極層2の表面に形成し、これを作用電極14として貯留部12内に設置した。   In this verification test, a plate-like substrate 4 made of quartz glass is prepared, and a Cr layer having a thickness of 0.01 μm and an Au layer having a thickness of 0.2 μm are sequentially laminated on the substrate 4 by electron beam evaporation. Thus, an electrode layer 2 was produced. Next, a photoresist layer 14 a in which through holes 14 b were formed in a predetermined pattern was formed on the surface of the electrode layer 2 by the UV nanoimprint method, and this was placed in the storage portion 12 as a working electrode 14.

なお、この場合、フォトレジスト層14aには、直径が0.3μmで、孔形状が円形状でなる複数の貫通孔を、1μmの間隔をあけて規則的に配置させた。なお、各貫通孔14b内には電極層2が露出している。さらに、この検証試験では、Ptでなる対電極15と、Agでなる参照電極16とを用意し、対電極15と作用電極14とを貯留部12内で対向配置させ、さらに、対電極15及び作用電極14間に参照電極16を配置させた。   In this case, in the photoresist layer 14a, a plurality of through holes having a diameter of 0.3 μm and a circular hole shape were regularly arranged with an interval of 1 μm. The electrode layer 2 is exposed in each through hole 14b. Further, in this verification test, a counter electrode 15 made of Pt and a reference electrode 16 made of Ag are prepared, the counter electrode 15 and the working electrode 14 are arranged to face each other in the storage portion 12, and the counter electrode 15 and A reference electrode 16 was placed between the working electrodes 14.

なお、これら作用電極14、対電極15及び参照電極16には、導線18a、18b、18cを用いて定電位電解部17を接続させた。そして、作用電極14と対電極15との間に流す電流を、定電位電解部17によって制御して作用電極14の電位を-2.5Vとし、0.1時間、当該電位を維持した。   In addition, the constant potential electrolysis part 17 was connected to these working electrode 14, the counter electrode 15, and the reference electrode 16 using conducting wire 18a, 18b, 18c. And the electric current sent between the working electrode 14 and the counter electrode 15 was controlled by the constant potential electrolysis part 17, the electric potential of the working electrode 14 was set to -2.5V, and the said electric potential was maintained for 0.1 hour.

これにより、作用電極14には、フォトレジスト層14aの各貫通孔14b内に電解析出物が出現していることが確認できた。その後、作用電極14を電解液13から取り出し、フォトレジスト層14aを除去した。これにより、電極層2の表面には、フォトレジスト層14aの各貫通孔14bの位置に、当該貫通孔14bの形状と同じ形状でなる電解析出物が形成されていることが確認できた。次に、電極層2の表面に形成された電解析出物のゼーベック係数をゼーベック係数測定装置を用いて測定した。その結果、電極層2の表面に形成された電解析出物は、ゼーベック係数が500〜700/μVK-1であり、正の値であった。よって、電極層2の表面に形成された電解析出物は、p型の不純物半導体層であることが確認できた。 Thereby, it was confirmed that electrolytic deposits appeared on the working electrode 14 in the respective through holes 14b of the photoresist layer 14a. Thereafter, the working electrode 14 was taken out from the electrolytic solution 13 and the photoresist layer 14a was removed. Thereby, it was confirmed that electrolytic deposits having the same shape as the through holes 14b were formed on the surface of the electrode layer 2 at the positions of the through holes 14b of the photoresist layer 14a. Next, the Seebeck coefficient of the electrolytic deposit formed on the surface of the electrode layer 2 was measured using a Seebeck coefficient measuring device. As a result, the electrolytic deposit formed on the surface of the electrode layer 2 had a Seebeck coefficient of 500 to 700 / μVK −1 and was a positive value. Therefore, it was confirmed that the electrolytic deposit formed on the surface of the electrode layer 2 was a p-type impurity semiconductor layer.

次に、このように電極層2上に不純物半導体層3を有した不純物半導体素子1に対して熱処理を行い、熱処理前と熱処理後での不純物半導体層3の炭素の量を調べた。なお、ここでは、熱処理として、Ar雰囲気中において250℃で1時間、不純物半導体素子1を加熱した。そして、炭素の量は、XPSにより測定した。これにより熱処理した不純物半導体層3では、炭素の量が低減していることが確認できた。また、熱処理後の不純物半導体層3は結晶性も向上することが確認できた。   Next, heat treatment was performed on the impurity semiconductor element 1 having the impurity semiconductor layer 3 on the electrode layer 2 in this manner, and the amount of carbon in the impurity semiconductor layer 3 before and after the heat treatment was examined. Here, as the heat treatment, the impurity semiconductor element 1 was heated at 250 ° C. for 1 hour in an Ar atmosphere. The amount of carbon was measured by XPS. Thus, it was confirmed that the amount of carbon was reduced in the impurity semiconductor layer 3 subjected to the heat treatment. It was also confirmed that the impurity semiconductor layer 3 after the heat treatment was improved in crystallinity.

6.変形例
なお、本発明は、上述した実施の形態に限定されるものではなく、本発明の要旨の範囲内で種々の変形実施が可能であり、例えば、電極層2、対電極15、参照電極16、及び基板4を形成する材料を適宜変更することができる。
6). The present invention is not limited to the above-described embodiment, and various modifications can be made within the scope of the present invention. For example, the electrode layer 2, the counter electrode 15, and the reference electrode 16 and the material forming the substrate 4 can be appropriately changed.

上述した実施の形態では、溶媒として、TMHA‐TFSIを用いて電解液13を作製した場合について説明したが、本発明はこれに限られず、TMHA‐TFSIにかえて1-butyl-1-methylpyrrolidiniumbis(trifluoromethylsulfonyl)amide、1-butyl-1-methylpyrrolidiniumtrifluoromethylsulfonate、1-butyl-1-methylpyrrolidiniumtris(pentafluoroethyl)-trifluorophosphateなどのイオン液体や、プロピレンカーボネート(PC)などの有機溶媒を、溶媒として用いて電解液を作製してもよい。   In the above-described embodiment, the case where the electrolytic solution 13 is prepared using TMHA-TFSI as a solvent has been described. However, the present invention is not limited to this, and instead of TMHA-TFSI, 1-butyl-1-methylpyrrolidiniumbis ( Prepare an electrolyte using an ionic liquid such as trifluoromethylsulfonyl) amide, 1-butyl-1-methylpyrrolidiniumtrifluoromethylsulfonate, 1-butyl-1-methylpyrrolidiniumtris (pentafluoroethyl) -trifluorophosphate, or an organic solvent such as propylene carbonate (PC) as the solvent. May be.

上述した実施の形態では、本発明の製造装置11及び製造方法を用いて、p型の不純物半導体層3、又はn型の不純物半導体層を製造する場合について説明したが、本発明はこれに限られず、本発明の製造装置11及び製造方法を用いて、pn接合を有する不純物半導体層を製造するようにしてもよい。この場合、製造装置11では、先ず始めにp型の不純物半導体を電極層2の表面に電解析出させてp型の不純物半導体部3aを形成し、次いで、貯留部12に貯留されているp型不純物イオンを含有した電解液13を、p型不純物イオンとは導電型が異なるn型不純物イオンを含有した別の電解液にかえて、n型の不純物半導体をp型の不純物半導体部3a上に電解析出させる。これにより、製造装置11は、電極層2上にあるp型の不純物半導体層3上に、n型の不純物半導体層を積層させた、pn接合の不純物半導体層を作製できる。   In the above-described embodiment, the case where the p-type impurity semiconductor layer 3 or the n-type impurity semiconductor layer is manufactured using the manufacturing apparatus 11 and the manufacturing method of the present invention has been described. However, the present invention is not limited thereto. Instead, an impurity semiconductor layer having a pn junction may be manufactured using the manufacturing apparatus 11 and the manufacturing method of the present invention. In this case, in the manufacturing apparatus 11, first, a p-type impurity semiconductor is electrolytically deposited on the surface of the electrode layer 2 to form the p-type impurity semiconductor portion 3 a, and then the p stored in the storage portion 12. Replacing the electrolytic solution 13 containing n-type impurity ions with another electrolytic solution containing n-type impurity ions having a conductivity type different from that of the p-type impurity ions, the n-type impurity semiconductor is replaced on the p-type impurity semiconductor portion 3a. To be electrolytically deposited. Thus, the manufacturing apparatus 11 can produce a pn junction impurity semiconductor layer in which an n-type impurity semiconductor layer is stacked on a p-type impurity semiconductor layer 3 on the electrode layer 2.

上述した実施の形態では、基板4上に電極層2を設けた作用電極14を適用した場合について説明したが、本発明はこれに限られず、基板4を設けずに、板状の電極層2を用いた作用電極を適用してもよい。   In the embodiment described above, the case where the working electrode 14 provided with the electrode layer 2 on the substrate 4 has been described. However, the present invention is not limited to this, and the plate-like electrode layer 2 is not provided without providing the substrate 4. You may apply the working electrode using.

上述した実施の形態では、所定の間隔をあけて規則的に配置させた円柱形状の不純物半導体部3aを電極層2上に形成する場合について説明したが、本発明はこれに限られず、フォトレジスト層14aに形成した貫通孔14bの形状や配置を変えることで、不純物半導体部3aの形状や配置を適宜変更するようにしてもよい。また、本発明の製造装置11及び製造方法では、フォトレジスト層14aを形成せずに、基板4上に電極層2のみが設けられた作用電極を用いて、電極層2上に層状の不純物半導体層を形成するようにしてもよい。   In the above-described embodiment, the case where the columnar impurity semiconductor portion 3a regularly arranged with a predetermined interval is formed on the electrode layer 2 has been described. However, the present invention is not limited to this and the photoresist is not limited thereto. You may make it change suitably the shape and arrangement | positioning of the impurity semiconductor part 3a by changing the shape and arrangement | positioning of the through-hole 14b formed in the layer 14a. Further, in the manufacturing apparatus 11 and the manufacturing method of the present invention, a layered impurity semiconductor is formed on the electrode layer 2 by using a working electrode in which only the electrode layer 2 is provided on the substrate 4 without forming the photoresist layer 14a. A layer may be formed.

上述した実施の形態では、フォトレジスト層14aを除去した後、不純物半導体層3を熱処理した場合について説明したが、本発明はこれに限られず、不純物半導体層3を熱処理しなくてもよい。   In the above-described embodiment, the case where the impurity semiconductor layer 3 is heat treated after removing the photoresist layer 14a has been described. However, the present invention is not limited to this, and the impurity semiconductor layer 3 may not be heat treated.

1 不純物半導体素子
2 電極層
3 不純物半導体層
11 製造装置
12 貯留部
13 電解液
14 作用電極
15 対電極
17 定電位電解部
DESCRIPTION OF SYMBOLS 1 Impurity semiconductor element 2 Electrode layer 3 Impurity semiconductor layer 11 Manufacturing apparatus 12 Storage part 13 Electrolytic solution 14 Working electrode 15 Counter electrode 17 Constant potential electrolysis part

Claims (6)

p型不純物イオン又はn型不純物イオンのいずれか一方と、半導体イオンとを含有した電解液が貯留された貯留部と、
前記貯留部内にて前記電解液に浸漬された作用電極と、
前記貯留部内にて前記電解液に浸漬され、前記作用電極と対向配置された対電極と、
前記作用電極と前記対電極との間に電流を流し、前記作用電極の電極層表面に、p型又はn型の不純物半導体を電解析出させ、該電極層表面に不純物半導体層を形成させる定電位電解部と
を備えることを特徴とする不純物半導体層の製造装置。
a reservoir in which an electrolyte containing either p-type impurity ions or n-type impurity ions and semiconductor ions is stored;
A working electrode immersed in the electrolyte in the reservoir;
A counter electrode immersed in the electrolyte in the reservoir and disposed opposite the working electrode;
A current is passed between the working electrode and the counter electrode, and a p-type or n-type impurity semiconductor is electrolytically deposited on the surface of the electrode layer of the working electrode, thereby forming an impurity semiconductor layer on the surface of the electrode layer. An apparatus for producing an impurity semiconductor layer, comprising: a potential electrolysis unit.
前記作用電極には、
複数の貫通孔を有するフォトレジスト層が前記電極層表面に形成されており、各前記貫通孔内で外部に露出している前記電極層表面に前記不純物半導体を電解析出させる
ことを特徴とする請求項1に記載の不純物半導体層の製造装置。
The working electrode includes
A photoresist layer having a plurality of through holes is formed on the surface of the electrode layer, and the impurity semiconductor is electrolytically deposited on the surface of the electrode layer exposed to the outside in each of the through holes. The apparatus for manufacturing an impurity semiconductor layer according to claim 1.
p型不純物イオン又はn型不純物イオンのいずれか一方と、半導体イオンとを含有した電解液が貯留された貯留部内に、前記電解液に浸漬させるように作用電極と対電極とを対向配置させ、定電位電解部によって、前記作用電極と前記対電極との間に電流を流し、前記作用電極の電極層表面に、p型又はn型の不純物半導体を電解析出させ、該電極層表面に不純物半導体層を形成する
ことを特徴とする不純物半導体層の製造方法。
A working electrode and a counter electrode are arranged opposite to each other so as to be immersed in the electrolytic solution in a storage part in which an electrolytic solution containing either p-type impurity ions or n-type impurity ions and semiconductor ions is stored, A constant-potential electrolysis unit allows a current to flow between the working electrode and the counter electrode, electrolytically deposits a p-type or n-type impurity semiconductor on the surface of the electrode layer of the working electrode, and impurities on the surface of the electrode layer A method for producing an impurity semiconductor layer, comprising forming a semiconductor layer.
前記作用電極には、複数の貫通孔を有するフォトレジスト層が前記電極層表面に形成されており、各前記貫通孔内で外部に露出している前記電極層表面に前記不純物半導体が電解析出する
ことを特徴とする請求項3に記載の不純物半導体層の製造方法。
In the working electrode, a photoresist layer having a plurality of through holes is formed on the surface of the electrode layer, and the impurity semiconductor is electrolytically deposited on the surface of the electrode layer exposed to the outside in each of the through holes. The method of manufacturing an impurity semiconductor layer according to claim 3.
前記p型不純物イオン又は前記n型不純物イオンを含有した一の前記電解液を用いて、前記p型又は前記n型でなる一の前記不純物半導体を前記電極層上に電解析出させた後、前記一の電解液に含まれる前記p型不純物イオン又は前記n型不純物イオンとは導電型が異なる前記n型不純物イオン又は前記p型不純物イオンを含有した別の前記電解液を用いて、前記n型又は前記p型でなる他の前記不純物半導体を前記一の不純物半導体上に電解析出させる
ことを特徴とする請求項3又は4に記載の不純物半導体層の製造方法。
After electrolytically depositing the p-type or n-type impurity semiconductor on the electrode layer using the p-type impurity ion or the n-type impurity ion-containing one electrolyte solution, The n-type impurity ions or the p-type impurity ions that are different in conductivity type from the p-type impurity ions or the n-type impurity ions contained in the one electrolytic solution, 5. The method for producing an impurity semiconductor layer according to claim 3, wherein the other impurity semiconductor of a p-type or the p-type is electrolytically deposited on the one impurity semiconductor.
前記不純物半導体層を熱処理する
ことを特徴とする請求項3〜5のいずれか1項に記載の不純物半導体層の製造方法。
The method for manufacturing an impurity semiconductor layer according to claim 3, wherein the impurity semiconductor layer is heat-treated.
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