JP2007250663A - Thin film transistor structure, display device and method of manufacturing same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a structure of a thin film transistor with small off-current, a display device of sufficient picture quality which uses the structure, and to provide a method of manufacturing the display device. <P>SOLUTION: The thin film transistor structure includes an insulating substrate 20, a gate electrode 30 arranged on the insulating substrate 20, a gate insulating film 41 disposed to cover the gate electrode 30, a p-type or n-type amorphous silicon semiconductor layer 42 installed just above the gate insulating film 41, an intrinsic amorphous silicon semiconductor layer 43 arranged just above the p-type or n-type amorphous silicon semiconductor layer 42, and a source electrode 50 and a drain electrode 51 which are electrically connected to the intrinsic amorphous silicon semiconductor layer 43. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a thin film transistor structure, a display device, and a method for manufacturing the display device.

  Transistors used in a liquid crystal display or the like require two types of transistors: a switching thin film transistor attached to each pixel and a thin film transistor with a low threshold voltage fluctuation width for controlling the entire screen.

  As such a pixel switch, an amorphous silicon thin film transistor is used in particular because it can be manufactured with a small amount of material and can be manufactured at a low cost because the manufacturing process is at a lower temperature than that of a crystal system. As shown in FIG. 5, an amorphous silicon thin film transistor generally has a gate electrode formed on an insulating substrate, and a gate insulating film, an intrinsic (non-doped) amorphous silicon film, and a p-type or n-type amorphous silicon film. The films are formed in this order. Then, after the unnecessary amorphous silicon film is partially removed, the source electrode and the drain electrode are formed on the p-type or n-type amorphous silicon film, respectively. Has various problems.

  First, an amorphous silicon thin film transistor uses an intrinsic amorphous silicon film as an active layer. Therefore, in order to generate charges on the gate electrode to obtain good thin film transistor characteristics, it is necessary to overlap the gate electrode and the source electrode and the gate electrode and the drain electrode as shown in FIG. However, when the electrodes are overlapped in this way, the parasitic capacitance between the electrodes increases. Therefore, when such a transistor is used for a liquid crystal display device or the like, there is a problem in that image quality is deteriorated due to an increase in signal delay.

  In addition, the overlapping region must be constant, but this requires high-precision positioning. Therefore, depending on the processing accuracy, this region changes, so that the parasitic capacitance varies, and this also causes a problem that the image quality is deteriorated.

  Furthermore, the amorphous silicon thin film transistor has a large amount of fluctuation of the threshold voltage with respect to the positive bias, and the drive current decreases with time. Therefore, such a thin film transistor cannot be used in a transistor integrated circuit for screen control (driver). For this reason, in order to obtain a transistor used in a liquid crystal display or the like, as shown in FIG. 6, the pixel thin film transistor formed on the amorphous silicon of the display unit (liquid crystal panel) has a simple threshold voltage variation amount. A method is adopted in which a driver transistor integrated circuit formed in crystalline silicon is bonded to or connected to the same substrate. However, such a method increases the number of parts, which increases the cost of the liquid crystal display.

In addition to enhancement-type transistors using amorphous silicon, as shown in Non-Patent Document 1, a depletion-type transistor using ITO (indium tin oxide) as an active layer as a transistor used in a liquid crystal display or the like. Can also be used. As shown in FIG. 7, this transistor uses a ferroelectric thin film for the gate insulating film and an oxide conductor made of ITO for the channel region. According to this, it is described that good thin film transistor characteristics can be obtained.
Takaaki Miyasakao, Masaru Senoo, and Eisuke Tokumitsu `` Ferroelectric-gate thin-film transistors using indium-tin-oxide channel with large controllability '', APPLIED PHYSICS LETTERS 86,162902 (2005)

  However, since such a transistor uses ITO as an active layer, a defect level is generated in a region corresponding to the back channel. For this reason, there is a problem that the off-current becomes large and the voltage applied to the display medium cannot be maintained when used in a liquid crystal display device or the like, and the image quality is deteriorated.

 The present invention has been made in view of these points, and an object of the present invention is to provide a structure of a depletion type thin film transistor having a small off-current, a display device with good image quality using the same, and manufacture of the display device. Is to provide a method.

  The thin film transistor structure according to the present invention includes an insulating substrate, a gate electrode provided on the insulating substrate, a gate insulating film provided so as to cover the gate electrode, and a p provided immediately above the gate insulating film. Type or n-type amorphous silicon semiconductor layer, an intrinsic amorphous silicon semiconductor layer provided immediately above the p-type or n-type amorphous silicon semiconductor layer, and a source electrode and a drain electrically connected to the intrinsic amorphous silicon semiconductor layer, respectively And an electrode.

  According to such a configuration, a so-called depletion in which a p-type or n-type amorphous silicon semiconductor layer is stacked on the channel side of a semiconductor layer which is an active layer, and an intrinsic amorphous silicon semiconductor layer is stacked on the back channel side. Type thin film transistor can be obtained. Therefore, since the channel region formed by the gate voltage is connected to the source electrode region and the drain electrode region, an overlap region between the gate electrode, the source electrode, and the drain electrode, which is necessary for the enhancement type transistor, is not necessary. Accordingly, since parasitic capacitance between these electrodes hardly occurs, even if this thin film transistor is used in a display device, the problem of image quality degradation due to signal delay does not occur.

  In addition, since it is not necessary to overlap each electrode as described above, high-precision positioning for forming the overlap region is not necessary, and image quality deterioration due to variations in processing accuracy when forming the overlap region is prevented. The problems that occur are eliminated and in addition the manufacturing costs are lower.

  Further, since the region corresponding to the back channel is formed of the intrinsic amorphous silicon semiconductor layer, no defect level is generated there. Therefore, the off-state current is reduced, and even when this is used for a display device, the voltage applied to the display medium can be maintained, and the performance of the device using such a transistor is further improved.

  In the thin film transistor structure according to the present invention, the intrinsic amorphous silicon semiconductor layer may have a thickness of 30 nm or less.

  According to such a configuration, the series resistance generated when the source electrode and the drain electrode are in direct contact with the intrinsic amorphous silicon semiconductor layer is reduced by reducing the thickness of the intrinsic amorphous silicon semiconductor layer to 30 nm or less. Can be reduced. Accordingly, it is possible to suppress the performance of the thin film transistor from being lowered.

  A display device according to the present invention includes a thin film transistor substrate in which a driver is formed on an insulating substrate, the driver including a driver thin film transistor, and the driver thin film transistor is provided on the insulating substrate. A gate insulating film provided to cover the gate electrode, a p-type or n-type amorphous silicon semiconductor layer provided immediately above the gate insulating film, and a p-type or n-type amorphous silicon semiconductor layer It has an intrinsic amorphous silicon semiconductor layer provided immediately above, and a source electrode and a drain electrode each electrically connected to the intrinsic amorphous silicon semiconductor layer.

  According to such a configuration, since the region corresponding to the back channel of the driver thin film transistor for display measures is formed of the intrinsic amorphous silicon semiconductor layer, no defect level is generated there. For this reason, the off-current is reduced, and even when this is used for a display device, the voltage applied to the display medium can be maintained, and the image quality of the display device is improved.

  In addition, since the driver thin film transistor does not apply a positive bias or does not need to apply a positive bias, a small amount of threshold voltage can be suppressed. Therefore, even if it is used as a screen control driver for a display device, a decrease in driving current is suppressed over time, so that it can be manufactured on the same substrate as a thin film transistor for a pixel in the same process, and so-called monolithic drivers and the like can be manufactured. Is possible.

  A method of manufacturing a display device according to the present invention is a method of manufacturing a display device including a thin film transistor substrate in which a pixel thin film transistor and a driver thin film transistor having the same structure are formed on an insulating substrate, the method comprising: Further, the pixel thin film transistor and the driver thin film transistor are formed at the same time.

  According to such a structure, the driver thin film transistor and the pixel thin film transistor of the display device can be manufactured over the same substrate by the same process. Therefore, a display device using a thin transistor including an amorphous silicon layer can be made monolithic, and thus manufacturing costs can be reduced.

  As described above, according to the present invention, it is possible to provide a structure of a depletion type thin film transistor with a small off-current, a display device with good image quality using the same, and a method for manufacturing the display device.

  Hereinafter, a thin film transistor 10, a liquid crystal display device, and a method of manufacturing the liquid crystal display device according to embodiments of the present invention will be described in detail with reference to the drawings. The present invention is not limited to the following embodiment.

(Configuration of Thin Film Transistor 10)
FIG. 1 shows a thin film transistor 10 according to this embodiment.

  The thin film transistor 10 includes an insulating substrate 20, a gate electrode 30 formed on the insulating substrate 20, a stacked structure 40 formed on the gate electrode 30, and an intrinsic amorphous silicon semiconductor layer 43 as the uppermost layer of the stacked structure 40. The source electrode 50, the drain electrode 51, and the protective film 60 are connected.

  Insulating substrate 20 is barium-aluminoborosilicate glass, alkaline earth-aluminoborosilicate glass, borosilicate glass, alkaline earth-zinc-lead-aluminoborosilicate glass, alkaline earth-zinc, which are high strain point glasses. -It is made of aluminoborosilicate glass or the like.

  The gate electrode 30 is formed on the insulating substrate 20 and is subjected to predetermined patterning. The gate electrode 30 is made of Ti, TiN, Mo, Ta, TaN, Al or the like.

  The laminated structure 40 is provided on the gate electrode 30 and includes a lowermost gate insulating film 41, an intermediate p-type or n-type amorphous silicon semiconductor layer 42, and an uppermost intrinsic amorphous silicon semiconductor layer 43. ing.

  The gate insulating film 41 is located in the lowermost layer of the laminated structure 40. The gate insulating film 41 is formed so as to cover the gate electrode 30. The gate insulating film 41 is formed of an inorganic insulating film such as SiO2 or SiNx or an insulating film made of an insulating material (such as polysiloxane containing an organic group) mainly composed of an inorganic component having an organic group.

  The p-type or n-type amorphous silicon semiconductor layer 42 is formed on the intermediate layer of the stacked structure 40, that is, on the gate insulating film 41. The thickness of the p-type or n-type amorphous silicon semiconductor layer 42 is not particularly limited, but is formed to be, for example, about 100 nm. The p-type or n-type amorphous silicon semiconductor layer 42 is formed by doping an impurity element into hydrogenated amorphous silicon. As the impurity element to be doped, phosphorus (P) is used in the n-type amorphous silicon semiconductor layer, and boron (B) is used in the p-type amorphous silicon semiconductor layer.

  The intrinsic amorphous silicon semiconductor layer 43 is formed on the uppermost layer of the laminated structure 40, that is, the p-type or n-type amorphous silicon semiconductor layer 42. The intrinsic amorphous silicon semiconductor layer 43 is composed of hydrogenated amorphous silicon that is not doped with an impurity element. The thickness of the intrinsic amorphous silicon semiconductor layer 43 is not particularly limited, but is formed to be, for example, 30 nm or less. If the thickness of the intrinsic amorphous silicon semiconductor layer 43 is 30 nm or less, the series resistance generated when the source electrode 50 and the drain electrode 51 and the intrinsic amorphous silicon semiconductor layer 43 are in direct contact can be further reduced. it can. Thereby, it can suppress that the performance of the thin-film transistor 10 falls. In addition, when the thin film transistor 10 is used in a display unit such as a liquid crystal display device, as shown in FIG. 2, such series resistance can be reduced by irradiation with light from a backlight or the like. Is not reduced.

  The source electrode 50 and the drain electrode 51 are respectively formed on the intrinsic amorphous silicon semiconductor layer 43 so as not to overlap the gate electrode 30. That is, when the thin film transistor 10 is viewed from the surface, the source electrode 50 and the drain electrode 51 are formed so as to be sandwiched with an interval so as not to overlap the gate electrode 30. The source electrode 50 and the drain electrode 51 are made of Ti, TiN, Mo, Ta, TaN, Al or the like, like the gate electrode 30.

  Thus, in the thin film transistor 10, the p-type or n-type amorphous silicon semiconductor layer 42 is stacked on the channel side of the semiconductor layer which is an active layer, and the intrinsic amorphous silicon semiconductor layer 43 is stacked on the back channel side. That is, the thin film transistor 10 constitutes a depletion type transistor. Therefore, since the channel region formed by the gate voltage is connected to the source electrode region and the drain electrode region, an overlap region between the gate electrode, the source electrode, and the drain electrode, which is necessary for the enhancement type transistor, is not necessary. Therefore, the parasitic capacitance between these electrodes hardly occurs, and even if this thin film transistor 10 is used in a display device, the problem of image quality deterioration due to signal delay does not occur. Further, since the region corresponding to the back channel is formed by the intrinsic amorphous silicon semiconductor layer 43, no defect level is generated there. Therefore, the off-state current is reduced, and even when this is used for a display device, the voltage applied to the display medium can be maintained, and the performance of the device using such a transistor is further improved.

  The protective film 60 is made of SiNx or the like and is formed so as to cover the source electrode 50, the drain electrode 51, and the intrinsic amorphous silicon semiconductor layer 43.

(Configuration of the liquid crystal display device 70)
As shown in FIG. 3, the liquid crystal display device 70 according to this embodiment includes a display unit 81 (liquid crystal panel) formed on a thin film transistor substrate 80 and a peripheral circuit 82 formed in a backlight unit (not shown). It is configured.

  In the thin film transistor substrate 80, a display unit 81 (liquid crystal panel) having pixel regions arranged in a matrix and a peripheral circuit 82 including a display controller, a gate driver, a data driver, and the like are formed.

  In the display unit 81, a plurality of pixel thin film transistors 85 are formed in each pixel region. Each pixel thin film transistor 85 is connected to a data driver by a source bus line connected to the source electrode 50 of the pixel thin film transistor 85, and is connected to a gate driver by a gate bus line connected to the gate electrode 30 of the pixel thin film transistor 85. It is connected.

  In addition, since the pixel thin film transistor 85 has a region corresponding to the back channel formed of the intrinsic amorphous silicon semiconductor layer 43, no defect level is generated there. For this reason, the off-current is reduced, and even when this is used in the liquid crystal display device 70, the voltage applied to the display medium can be maintained, and the image quality of the liquid crystal display device 70 is improved.

  Since the driver thin film transistor 86 does not apply a positive bias or does not apply a positive bias, a small amount of threshold voltage can be suppressed. Therefore, even when used as a screen control driver of the liquid crystal display device 70, a decrease in drive current is regulated over time, so that the pixel thin film transistor 85 can be manufactured on the same substrate in the same process, such as a so-called driver. It becomes possible to make it monolithic.

(Manufacturing method of the liquid crystal display device 70)
Next, a method for manufacturing the liquid crystal display device 70 will be described.

  First, a metal thin film such as Cr, Ta, MoTa, MoW, Ti, TiN, Al, which becomes the pixel gate electrode 30 and the driver gate electrode 30, is sputtered on the same insulating substrate 20 made of a glass substrate or the like. Form a film. In the sputtering method, a metal having a high melting point is discharged and melted as a discharge electrode, and the molten particles are sprayed at a high speed.

  Next, resist application, mask exposure, and development are performed, unnecessary portions are etched by dry etching or wet etching, and then the resist is removed to form a gate electrode pattern.

Subsequently, SiN _x is formed as a gate insulating film 41 so as to cover the gate electrode 30 by a plasma CVD method so as to have a thickness of about 400 nm. Since this CVD film formation can be performed without breaking the vacuum, the interface characteristics between the semiconductor layer and the gate insulating film 41 can be kept good.

Next, an n-type amorphous silicon semiconductor layer is formed directly on the gate insulating film 41 by plasma CVD so as to have a thickness of about 100 nm. At this time, phosphorus (P) is doped by decomposing and forming a mixed gas obtained by mixing 1% by volume of phosphine (PH ₃ ) with monosilane gas (SiH ₄ ) using high-frequency plasma. Thereby, an n-type amorphous silicon semiconductor layer is formed.

When forming a p-type amorphous silicon semiconductor layer, boron (B) is doped instead of phosphorus (P). Boron doping is performed by decomposing and film-forming a mixed gas obtained by mixing 1% by volume of diborane (B ₂ H ₆ ) with monosilane gas (SiH ₄ ) using high-frequency plasma.

  Next, hydrogenated amorphous silicon is formed as an intrinsic amorphous silicon semiconductor layer 43 directly on the p-type or n-type amorphous silicon semiconductor layer 42 by plasma CVD so as to have a thickness of about 30 nm.

Subsequently, the source electrode 50 and the drain electrode 51 are formed on the intrinsic amorphous silicon semiconductor layer 43 so as to sandwich the gate electrode 30 when viewed from the surface of the thin film transistor 10 in a region that does not overlap with the gate electrode 30. . Thereby, the source electrode 50 and the drain electrode 51 are each electrically connected to the intrinsic amorphous silicon semiconductor layer 43. Here, a pixel source electrode 50 and a drain electrode 51 are formed on the pixel gate electrode 30, and a driver source electrode 50 and a drain electrode 51 are formed on the driver gate electrode 30, respectively. The source electrode 50 and the drain electrode 51 are each formed by depositing a metal thin film such as Cr, Ta, MoTa, MoW, Ti, TiN, and Al by sputtering, and then dry etching using a BCl ₃ / Cl ₂ gas. Then, the source electrode 50, the drain electrode 51, and the wiring pattern are formed by patterning into a predetermined shape. At this time, since it is not necessary to overlap the source electrode 50 and the drain electrode 51 with the gate electrode 30, high-precision positioning for forming the overlap region is not necessary, and processing at the time of forming the overlap region is performed. The problem of image quality degradation due to variations in accuracy is eliminated, and the manufacturing cost is further reduced.

  Next, a protective film 60 is formed. Then, the thin film transistor 10 is completed by patterning the formed protective film 60 into a predetermined shape by etching.

  By the above manufacturing method, the pixel thin film transistor 85 and the driver thin film transistor 86 are formed as the thin film transistor 10 and simultaneously connected by the source bus line and the gate bus line, whereby the thin film transistor substrate 80 can be manufactured. Further, the liquid crystal display device 70 is manufactured by using the thin film transistor substrate 80.

  Thus, the driver thin film transistor 86 and the pixel thin film transistor 85 of the liquid crystal display device 70 can be manufactured on the same substrate by the same process. Accordingly, a display device using a thin film transistor including an amorphous silicon layer can be made monolithic, and thus manufacturing costs can be reduced.

  In the thin film transistor 10 according to the present embodiment, the uppermost intrinsic amorphous silicon semiconductor layer 43 of the laminated structure 40 covers the entire p-type or n-type amorphous silicon semiconductor layer 42 as an intermediate layer, but is not limited thereto. Instead, it is sufficient to cover at least the entire region on the gate electrode 30. That is, for example, as shown in FIG. 4, the intrinsic amorphous silicon semiconductor layer 43 does not extend to the lower regions of the source electrode 50 and the drain electrode 51, and the lower surfaces of the source electrode 50 and the drain electrode 51 are p-type or n-type amorphous silicon semiconductor. A structure connected to the layer 42 may be used.

  As the display device, an LCD (liquid crystal display) is shown in the present embodiment, but an organic EL (organic electroluminescence), FED (field emission display), or SED (surface-display) is used. A display device such as a conduction electron-emitter display (surface field emission display) may be used.

(Function and effect)
Next, operational effects will be described.

  The thin film transistor structure according to the present invention includes an insulating substrate 20, a gate electrode 30 provided on the insulating substrate 20, a gate insulating film 41 provided so as to cover the gate electrode 30, and a gate insulating film 41. A p-type or n-type amorphous silicon semiconductor layer 42 provided immediately above, an intrinsic amorphous silicon semiconductor layer 43 provided immediately above the p-type or n-type amorphous silicon semiconductor layer 42, and an intrinsic amorphous silicon semiconductor layer 43, respectively. A source electrode 50 and a drain electrode 51 which are electrically connected are provided.

  According to such a configuration, the p-type or n-type amorphous silicon semiconductor layer 42 is stacked on the channel side of the semiconductor layer that is the active layer, and the intrinsic amorphous silicon semiconductor layer 43 is stacked on the back channel side. A so-called depletion type thin film transistor can be obtained. For this reason, it is not necessary to overlap the source electrode 50 and the gate electrode 30 and the drain electrode 51 and the gate electrode 30 in order to generate charges on the gate electrode 30. Therefore, the parasitic capacitance between these electrodes hardly occurs, and even if this thin film transistor 10 is used in a display device, the problem of image quality deterioration due to signal delay does not occur.

  In addition, since it is not necessary to overlap each electrode as described above, high-precision positioning for forming the overlap region is not necessary, and image quality deterioration due to variations in processing accuracy when forming the overlap region is prevented. The problems that occur are eliminated and in addition the manufacturing costs are lower.

  Furthermore, since the region corresponding to the back channel is formed of the intrinsic amorphous silicon semiconductor layer 43, no defect level is generated there. Therefore, the off-state current is reduced, and even when this is used for a display device, the voltage applied to the display medium can be maintained, and the performance of the device using such a transistor is further improved.

  In the thin film transistor structure according to the present invention, the intrinsic amorphous silicon semiconductor layer 43 may have a thickness of 30 nm or less.

  According to such a configuration, the series resistance generated when the source electrode 50 and the drain electrode 51 are in direct contact with the intrinsic amorphous silicon semiconductor layer 43 is reduced to a thickness of the intrinsic amorphous silicon semiconductor layer 43 of 30 nm or less. , Can reduce the resistance more. Therefore, it can suppress that the performance of the thin-film transistor 10 falls.

  The display device according to the present invention is a display device including a thin film transistor substrate 80 in which a driver is formed on an insulating substrate 20, and the driver includes a driver thin film transistor 86, and the driver thin film transistor 86 is an insulating substrate. A gate electrode 30 provided on the gate electrode 20, a gate insulating film 41 provided so as to cover the gate electrode 30, a p-type or n-type amorphous silicon semiconductor layer 42 provided immediately above the gate insulating film 41, An intrinsic amorphous silicon semiconductor layer 43 provided immediately above the p-type or n-type amorphous silicon semiconductor layer 42, and a source electrode 50 and a drain electrode 51 that are electrically connected to the intrinsic amorphous silicon semiconductor layer 43, respectively. It is characterized by that.

  According to such a configuration, a positive bias is not applied to the gate electrode of the driver thin film transistor 86, or a small amount may be applied, so that the fluctuation range of the threshold voltage can be suppressed. Therefore, even if it is used as a screen control driver for a display device, a decrease in driving current is suppressed over time, so that it can be manufactured on the same substrate as a thin film transistor for a pixel in the same process, and so-called monolithic drivers and the like can be manufactured. Is possible.

  A method for manufacturing a display device according to the present invention is a method for manufacturing a display device including a thin film transistor substrate 80 in which a pixel thin film transistor 85 and a driver thin film transistor 86 having the same structure are formed on an insulating substrate 20. A pixel thin film transistor 85 and a driver thin film transistor 86 are formed on the insulating substrate 20 at the same time.

  According to such a configuration, the driver thin film transistor 86 and the pixel thin film transistor 85 of the display device can be manufactured on the same substrate by the same process. Accordingly, a display device using a thin film transistor including an amorphous silicon layer can be made monolithic, and thus manufacturing costs can be reduced.

  As described above, the present invention is useful for a thin film transistor structure, a display device, and a method for manufacturing the display device.

1 is a cross-sectional view of a thin film transistor 10. It is sectional drawing of the thin-film transistor 10 which receives the irradiation of the light from the backlight of a display apparatus. 4 is a plan view of a liquid crystal display device 70. FIG. FIG. 3 is a cross-sectional view of the thin film transistor 10 having a structure in which a source electrode 50 and a drain electrode 51 are connected to an intrinsic amorphous silicon semiconductor layer 43 on the side surfaces. It is sectional drawing of the conventional amorphous silicon thin-film transistor. It is a top view of the conventional liquid crystal display device with which the thin-film transistor for pixels manufactured by the separate process and the transistor integrated circuit for drivers were connected to the same board | substrate. It is sectional drawing of a depletion type transistor using ITO as an active layer.

Explanation of symbols

DESCRIPTION OF SYMBOLS 10 Thin-film transistor 20 Insulating substrate 30 Gate electrode 40 Laminated structure 41 Gate insulating film 42 P-type or n-type amorphous silicon semiconductor layer 43 Intrinsic amorphous silicon semiconductor layer 50 Source electrode 51 Drain electrode 60 Protective film 70 Liquid crystal display device 80 Thin-film transistor substrate 81 Display unit 82 Peripheral circuit 85 Thin film transistor for pixel 86 Thin film transistor for driver

Claims (4)

An insulating substrate;
A gate electrode provided on the insulating substrate;
A gate insulating film provided to cover the gate electrode;
A p-type or n-type amorphous silicon semiconductor layer provided immediately above the gate insulating film;
An intrinsic amorphous silicon semiconductor layer provided immediately above the p-type or n-type amorphous silicon semiconductor layer;
Each of a source electrode and a drain electrode electrically connected to the intrinsic amorphous silicon semiconductor layer;
Thin film transistor structure. The thin film transistor structure of claim 1,
The intrinsic amorphous silicon semiconductor layer has a thin film transistor structure having a thickness of 30 nm or less. A display device including a thin film transistor substrate in which a driver is formed on an insulating substrate,
The driver includes a driver thin film transistor,
The driver thin film transistor
A gate electrode provided on the insulating substrate;
A gate insulating film provided to cover the gate electrode;
A p-type or n-type amorphous silicon semiconductor layer provided immediately above the gate insulating film;
An intrinsic amorphous silicon semiconductor layer provided immediately above the p-type or n-type amorphous silicon semiconductor layer;
Each of a source electrode and a drain electrode electrically connected to the intrinsic amorphous silicon semiconductor layer;
A display device. A method of manufacturing a display device including a thin film transistor substrate in which a thin film transistor for a pixel and a thin film transistor for a driver having the same structure are formed on an insulating substrate,
A method for manufacturing a display device, in which a pixel thin film transistor and a driver thin film transistor are formed on an insulating substrate at the same time.

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