JP2012226195A - Electro-optical device, circuit board therefor and electronic apparatus - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an electro-optical device, a circuit board for the electro-optical device, and an electronic apparatus each having high cost performance.SOLUTION: The electro-optical device includes: a data line drive circuit 22 and a scan line drive circuit 24 provided on a first circuit board; transistors included in or connected to the data line drive circuit 22 and the scan line drive circuit 24; and a VDD power supply wiring line 71, a VSSX power supply wiring line 72 and a VSSY power supply wiring line 73 which are connected to the transistors and provided adjacent to each other on the same wiring layer. The ratio of the plane area of the VDD power supply wiring line 71 to the plane area of the VSSX power supply wiring line 72 or the VSSY power supply wiring line 73 is within 1.5 times.

Description

  The present invention relates to an electro-optical device, a substrate for an electro-optical device, and an electronic apparatus.

  As the electro-optical device, for example, there is an active matrix driving type liquid crystal device including a transistor for each pixel as an element for switching control of a pixel electrode. As a method of manufacturing this liquid crystal device, for example, an element-side mother substrate on which a plurality of element substrates on which a pixel circuit including the transistor is formed is provided and a counter substrate disposed opposite to the element substrate are also provided on the same surface. The opposite mother substrate is bonded through a liquid crystal layer. Thereafter, the pair of mother substrates are divided and individual liquid crystal devices are taken out.

  On the other hand, when the liquid crystal device is manufactured or inspected, a potential difference is generated between the wirings sandwiched through the insulating film, so that there is a case where electric discharge occurs between these wirings, resulting in dielectric breakdown of the insulating film. Therefore, for example, as disclosed in Patent Document 1, a method for reducing the breakdown by suppressing the discharge between the wirings by reducing the area difference between the wiring parts overlapped with the insulating film interposed therebetween is disclosed. Has been.

International Publication WO08 / 010342 Pamphlet

  However, there are various types of wirings in the liquid crystal device, and not only the dielectric breakdown of the insulating film sandwiched between the wirings disclosed in Patent Document 1 above, but problems related to other types of wirings may occur. For example, a power supply wiring to which a constant potential is applied is often formed wider than other wirings in order to minimize electrical loss. As a result, the charge amount of the electric charge is larger than that of the other wirings, so that in the manufacturing process of the liquid crystal device, the transistor connected to the power wiring is connected to the other wiring due to static electricity stored in the power wiring. There was a problem that it was more susceptible to electrostatic breakdown than a conventional transistor.

  SUMMARY An advantage of some aspects of the invention is to solve at least a part of the problems described above, and the invention can be implemented as the following forms or application examples.

  Application Example 1 An electro-optical device according to this application example includes a first terminal and a second terminal, a data line driving circuit and a scanning line driving circuit, and a semiconductor included in the data line driving circuit and the scanning line driving circuit. A first constant potential wiring electrically connected to the element, the first terminal and the semiconductor element, and supplied with a first potential; and electrically connected to the second terminal and the semiconductor element; A second constant potential wiring which is supplied adjacent to the first constant potential wiring and is provided adjacent to the first constant potential wiring; and an area of the first constant potential wiring and the second constant potential wiring It is characterized in that the ratio to the area is 1.5 times or less.

  According to this configuration, the difference in area between the adjacent first constant potential wiring and the second constant potential wiring is reduced, and the potential difference generated between the wirings can be reduced as compared with the conventional case. . This makes it difficult for a current to flow due to a difference in charge amount between the first constant potential wiring and the second constant potential wiring, and a semiconductor element (for example, a transistor) connected to the first constant potential wiring or the second constant potential wiring. ) Electrostatic breakdown can be suppressed.

  Application Example 2 In the electro-optical device according to the application example, the first terminal, the second terminal, and the third terminal, the data line driving circuit and the scanning line driving circuit, the data line driving circuit, and the scanning line driving circuit. , A first constant potential wiring electrically connected to the first terminal and the semiconductor element and supplied with a first potential, and the second terminal and the semiconductor element of the data line driving circuit And a second constant potential wiring provided adjacent to the first constant potential wiring, the third terminal, and the scanning line drive. A third constant potential wiring electrically connected to the semiconductor element of the circuit, supplied with the second potential, and provided adjacent to the second constant potential wiring; Ratio of area to the area of the second constant potential wiring There is within 1.5 times, and the area of the first constant potential wiring, the ratio between the area of the third constant potential wiring is equal to or is within 1.5 times.

  According to this configuration, the difference in area between the adjacent first constant potential wiring and second constant potential wiring, and between the adjacent first constant potential wiring and third constant potential wiring, is reduced. The potential difference generated between the wirings can be reduced as compared with the conventional case. This makes it difficult for the current due to the difference in charge amount between the first constant potential wiring and the second constant potential wiring and between the first constant potential wiring and the third constant potential wiring to flow. An electrostatic breakdown of a semiconductor element (for example, a transistor) connected to the second constant potential wiring or the third constant potential wiring can be suppressed.

  Application Example 3 In the electro-optical device according to the application example described above, it is preferable that the area of the first constant potential wiring and the area of the second constant potential wiring are substantially equal.

  According to this configuration, since the area ratio between the adjacent first constant potential wiring and the second constant potential wiring is substantially equal, the potential difference generated between the wirings can be substantially eliminated. Thereby, electrostatic breakdown of the semiconductor element connected to the first constant potential wiring or the second constant potential wiring can be suppressed.

  Application Example 4 In the electro-optical device according to the application example described above, it is preferable that the area of the first constant potential wiring and the area of the third constant potential wiring are substantially equal.

  According to this configuration, since the area ratio between the first constant potential wiring and the third constant potential wiring adjacent to each other is substantially equal, the potential difference generated between the wirings can be substantially eliminated. Thereby, the electrostatic breakdown of the semiconductor element connected to the first constant potential wiring or the third constant potential wiring can be suppressed.

  Application Example 5 The electro-optical device substrate according to this application example is an electro-optical device substrate on which a plurality of electro-optical devices are formed, and one of the plurality of electro-optical devices is a first electro-optical device. A terminal and a second terminal; a data line driving circuit and a scanning line driving circuit; a semiconductor element included in the data line driving circuit and the scanning line driving circuit; and the first terminal and the semiconductor element. A first constant potential wiring to which a first potential is supplied, and a second potential lower than the first potential is electrically connected to the second terminal and the semiconductor element of the data line driving circuit, The second constant potential wiring provided adjacent to the first constant potential wiring, and the extension disposed across the electro-optical device adjacent to the one electro-optical device and electrically connected to the second terminal And the first constant voltage And the wiring area, the second ratio of the total area of constant potential wiring and the extension wire is equal to or is within 1.5 times.

  According to this configuration, since the extension wiring electrically connected to the second constant potential wiring is provided across the one electro-optical device and the electro-optical device adjacent to the one electro-optical device, The area of the second constant potential wiring can be adjusted to increase by the area of the extended wiring provided in the region. Therefore, the potential difference generated between the first constant potential wiring and the second constant potential wiring can be adjusted to be reduced. Thereby, electrostatic breakdown of the semiconductor element connected to the first constant potential wiring or the second constant potential wiring can be suppressed. Furthermore, since the extension wiring is removed after the scribe break, the extension wiring is provided so that the first constant potential wiring and the second constant potential wiring can be flattened without affecting the arrangement of the other wiring. The area ratio can be adjusted.

  Application Example 6 An electro-optical device according to this application example is formed using the electro-optical device substrate described above.

  According to this configuration, the area of the second constant potential wiring can be adjusted to increase by the area of the extended wiring. Therefore, the potential difference generated between the first constant potential wiring and the second constant potential wiring can be adjusted to be reduced. Thereby, electrostatic breakdown of the semiconductor element connected to the first constant potential wiring or the second constant potential wiring can be suppressed.

  Application Example 7 An electronic apparatus according to this application example includes the electro-optical device described above.

  According to this configuration, the electrostatic breakdown of the transistor in the manufacturing process can be prevented, and the electro-optical device that can be manufactured with a high yield is provided. Therefore, an electronic device having high cost performance can be provided.

The schematic plan view which shows the structure of a mother board | substrate. The enlarged plan view which expands and shows the A section of the mother board | substrate shown in FIG. FIG. 2 is a schematic plan view illustrating a structure of a liquid crystal device. FIG. 4 is a schematic cross-sectional view taken along the line CC ′ of the liquid crystal device illustrated in FIG. 3. FIG. 3 is an equivalent circuit diagram illustrating an electrical configuration of the liquid crystal device. FIG. 3 is a schematic cross-sectional view illustrating a structure of a liquid crystal device. FIG. 3 is a schematic plan view specifically showing a structure of a mother substrate in FIG. 2. The enlarged plan view which expands and shows the B section of the mother board | substrate shown in FIG. FIG. 8 is an equivalent circuit diagram showing an electrical configuration of part B of the mother board in FIG. 7. FIG. 8 is an equivalent circuit diagram showing an electrical configuration of part B of the mother board in FIG. 7. The chart which shows the relationship between the area ratio of VDD power supply wiring and VSSX power supply wiring, the presence or absence of an electrostatic breakdown, and a defect rate. FIG. 3 is a schematic diagram illustrating a configuration of a liquid crystal projector as an example of an electronic apparatus including a liquid crystal device.

  DESCRIPTION OF EXEMPLARY EMBODIMENTS Hereinafter, embodiments of the invention will be described with reference to the drawings. Note that the drawings to be used are appropriately enlarged or reduced so that the part to be described can be recognized.

<Configuration of mother board>
FIG. 1 is a schematic plan view showing the configuration of the mother board. FIG. 2 is an enlarged plan view showing an A portion of the mother board shown in FIG. Hereinafter, the configuration of the mother board will be described with reference to FIGS. 1 and 2.

  As shown in FIG. 1, a mother substrate 100 as a substrate for an electro-optical device is used for manufacturing a liquid crystal device 11 (see FIG. 3), for example, and is a pair of substrates constituting the liquid crystal device 11. One of the substrates (for example, element substrates) is imposed in a matrix shape. The size of the mother substrate 100 is, for example, 8 inches. The thickness of the mother substrate 100 is, for example, 1.2 mm. The material of the mother substrate 100 is, for example, quartz.

  The mother substrate 100 is not limited to a circular shape in plan, and may have a shape having an orientation flat with a part of the circumference cut out.

  As shown in FIG. 2, in each liquid crystal device 11, a data line driving circuit 22, a scanning line driving circuit 24, and an external connection terminal 23 as peripheral circuits are formed around the display area 19. The data line driving circuit 22 and the scanning line driving circuit 24 and the external connection terminal 23 are electrically connected to each other by a signal wiring 29. Hereinafter, the structure of the liquid crystal device 11 that is finally formed by processing the mother substrate 100 will be described.

<Configuration of electro-optical device>
FIG. 3 is a schematic plan view showing the structure of a liquid crystal device as an electro-optical device. FIG. 4 is a schematic cross-sectional view taken along the line CC ′ of the liquid crystal device shown in FIG. Hereinafter, the structure of the liquid crystal device will be described with reference to FIGS.

  As shown in FIGS. 3 and 4, the liquid crystal device 11 is, for example, a TFT active matrix type liquid crystal device using a thin film transistor (hereinafter referred to as a “TFT (Thin Film Transistor) element”) as a pixel switching element. It is. In the liquid crystal device 11, an element substrate 200 and a counter substrate 300 constituting a pair of substrates are bonded together via a sealing material 14 having a substantially rectangular frame shape in plan view.

  The first substrate 12 constituting the element substrate 200 and the second substrate 13 constituting the counter substrate 300 are made of a translucent material such as glass or quartz, for example. The liquid crystal device 11 has a configuration in which a liquid crystal layer 15 is enclosed in a region surrounded by a sealing material 14. The sealing material 14 is provided with an injection port 16 for injecting liquid crystal, and the injection port 16 is sealed with a sealing material 17.

  As the liquid crystal layer 15, for example, a liquid crystal material having a positive dielectric anisotropy is used. In the liquid crystal device 11, a frame light shielding film 18 having a rectangular frame shape made of a light shielding material is formed on the second substrate 13 along the vicinity of the inner periphery of the sealing material 14, and a region inside the frame light shielding film 18. Is the display area 19.

  The frame light shielding film 18 is made of, for example, aluminum (Al), which is a light shielding material, and is provided so as to partition the outer periphery of the display region 19 on the second substrate 13 side.

  In the display area 19, pixel areas 21 are provided in a matrix. The pixel area 21 constitutes one pixel that is the minimum display unit of the display area 19. A data line driving circuit 22 and an external connection terminal 23 are formed along one side (the lower side in FIG. 3) of the first substrate 12 in a region outside the sealing material 14.

  Further, scanning line driving circuits 24 are formed in the inner region of the sealing material 14 along two sides adjacent to the one side. An inspection circuit 25 is formed on the remaining side of the first substrate 12 (upper side in FIG. 3). The frame light shielding film 18 formed on the second substrate 13 side is, for example, at a position facing the scanning line driving circuit 24 and the inspection circuit 25 formed on the first substrate 12 (in other words, a position overlapping in plane). Is formed.

  On the other hand, vertical conduction terminals 26 for providing electrical continuity between the element substrate 200 and the counter substrate 300 are disposed at each corner of the counter substrate 300 (for example, four corners of the sealing material 14). Has been.

  As shown in FIG. 4, a plurality of pixel electrodes 27 are formed on the liquid crystal layer 15 side of the first substrate 12, and a first alignment film 28 is formed so as to cover the pixel electrodes 27. . The pixel electrode 27 is a conductive film made of a transparent conductive material such as ITO (Indium Tin Oxide).

  On the other hand, on the liquid crystal layer 15 side of the second substrate 13, a lattice-shaped light shielding film (BM: black matrix) (not shown) is formed, and a flat solid common electrode 31 is formed thereon. A second alignment film 32 is formed on the common electrode 31. The common electrode 31 is a conductive film made of a transparent conductive material such as ITO.

  The liquid crystal device 11 is a transmissive type, and polarizing plates (not shown) or the like are disposed on the light incident side and the light emitting side of the element substrate 200 and the counter substrate 300, respectively. The configuration of the liquid crystal device 11 is not limited to this, and may be a reflective type or a transflective type.

  FIG. 5 is an equivalent circuit diagram showing an electrical configuration of the liquid crystal device. Hereinafter, the electrical configuration of the liquid crystal device will be described with reference to FIG.

  As shown in FIG. 5, the liquid crystal device 11 has a plurality of pixel regions 21 that constitute a display region 19. A pixel electrode 27 is disposed in each pixel region 21. A TFT element 33 is formed in the pixel region 21.

  The TFT element 33 is a switching element that controls energization of the pixel electrode 27. A signal line 34 is electrically connected to the source side of the TFT element 33. Image signals S1, S2,..., Sn are supplied to each signal line 34 from, for example, the data line driving circuit 22 (see FIG. 3).

  A scanning line 35 is electrically connected to the gate side of the TFT element 33. For example, scanning signals G1, G2,..., Gm are supplied to the scanning lines 35 in a pulsed manner at a predetermined timing from the scanning line driving circuit 24 (see FIG. 3). Further, the pixel electrode 27 is electrically connected to the drain side of the TFT element 33.

  .., Gm supplied from the scanning line 35 causes the TFT element 33 serving as a switching element to be in an ON state for a certain period, so that the image signals S1, S2,. , Sn are written to the pixel region 21 via the pixel electrode 27 at a predetermined timing.

  Image signals S1, S2,..., Sn written at a predetermined level in the pixel region 21 are held for a certain period by a liquid crystal capacitor formed between the pixel electrode 27 and the common electrode 31 (see FIG. 4). In order to prevent leakage of the held image signals S1, S2,..., Sn, a storage capacitor 37 is formed between the pixel electrode 27 and the capacitor line.

  Thus, when a voltage signal is applied to the liquid crystal layer 15, the alignment state of the liquid crystal molecules changes according to the applied voltage level. Thereby, the light incident on the liquid crystal layer 15 is modulated to generate image light.

  FIG. 6 is a schematic cross-sectional view showing the structure of the liquid crystal device. Hereinafter, the structure of the liquid crystal device will be described with reference to FIG. FIG. 6 shows the cross-sectional positional relationship of each component, and is represented on a scale that can be clearly shown. FIG. 6 shows only the element substrate among the element substrate and the counter substrate constituting the liquid crystal device.

  As shown in FIG. 6, the liquid crystal device 11 includes an element substrate 200 and a counter substrate 300 (not shown). A lower light shielding film 41 made of Ti (titanium), Cr (chromium), or the like is formed on the first substrate 12 of the element substrate 200. The lower light-shielding film 41 is planarly patterned in a lattice shape, and defines an opening area of each pixel area 21. A base insulating film 42 made of a silicon oxide film or the like is formed on the first substrate 12 and the lower light shielding film 41.

  On the base insulating film 42, a TFT element 33, a scanning line 35, and the like are formed. The TFT element 33 has, for example, an LDD (Lightly Doped Drain) structure, a semiconductor layer 43 made of polysilicon or the like, a gate insulating film 44 formed on the semiconductor layer 43, and a gate insulating film 44 on the gate insulating film 44. And a scanning line 35 made of a formed polysilicon film or the like. As described above, the scanning line 35 functions as a gate electrode.

  The semiconductor layer 43 includes a channel region 43a, a low concentration source region 43b, a low concentration drain region 43c, a high concentration source region 43d, and a high concentration drain region 43e. A channel is formed in the channel region 43 a by an electric field from the scanning line 35. A first interlayer insulating film 45 made of a silicon oxide film or the like is formed on the gate insulating film 44.

  The high concentration source region 43 d of the TFT element 33 is electrically connected to the relay layer 46 formed on the first interlayer insulating film 45 through the contact hole 47. On the other hand, the high-concentration drain region 43 e is electrically connected to a relay layer 51 formed in the same layer as the relay layer 46 through a contact hole 52.

  The relay layer 46 is electrically connected to the signal line 34 formed on the second interlayer insulating film 53 via the contact hole 54. On the other hand, the relay layer 51 is electrically connected to a relay layer 55 formed in the same layer as the signal line 34 via a contact hole 56.

  The relay layer 55 is further electrically connected via a contact hole 56 to a relay layer 58 provided in the same layer as a capacitor electrode 57 described later. The relay layer 58 is electrically connected to the pixel electrode 27 through the contact hole 59. That is, the high concentration drain region 43e of the TFT element 33 and the pixel electrode 27 are electrically relay-connected through the relay layer 51, the relay layer 55, and the relay layer 58 in this order.

  A storage capacitor 62 is formed on the upper side of the signal line 34 and the relay layer 55 via a third interlayer insulating film 61. By electrically connecting the storage capacitor 62 in parallel with the liquid crystal capacitor, it is possible to hold the voltage of the pixel electrode 27 for a time that is, for example, three digits longer than the time during which the image signal is actually applied. Since the retention characteristics of the liquid crystal element are improved, the liquid crystal device 11 having a high contrast ratio can be realized.

  The capacitor electrode 57 functions as one electrode of the storage capacitor 62 electrically connected in parallel to the liquid crystal capacitor, and is held at a fixed potential. The capacitive electrode 57 is made of a transparent electrode such as ITO. For this reason, even if the capacitor electrode 57 is formed so as to overlap the display region 19 including the opening region, it is possible to suppress a decrease in light transmittance in the opening region.

  A dielectric film 63 is formed on the capacitor electrode 57. The dielectric film 63 is formed in a solid shape so as to cover the capacitor electrode 57. Since the dielectric film 63 is made of a transparent dielectric material such as silicon nitride, even if the dielectric film 63 is formed widely in the display area 19 including the opening area, the light transmittance in the opening area is high. It can suppress that it falls. In addition, it is more preferable that the thickness of the dielectric film 63 is smaller in order to increase the capacitance value of the storage capacitor 62.

  A capacitor separation film 64 for separating the storage capacitor 62 from one pixel to another is formed on the capacitor electrode 57. The capacitance value of the storage capacitor 62 can be adjusted by increasing or decreasing the area of the capacitor separation film 64.

  A pixel electrode 27 is formed on the capacitor separation film 64. The pixel electrode 27 is formed in an island shape for each pixel divided in a matrix by the signal line 34 and the scanning line 35. Although not shown here, on the pixel electrode 27, a first alignment film 28 (see FIG. 4) for regulating the alignment state of the liquid crystal molecules contained in the liquid crystal layer 15 (see FIG. 4). ) Is formed.

  Since the storage capacitor 62 is composed of the transparent capacitor electrode 57, the dielectric film 63, and the pixel electrode 27, each of the storage capacitors 62 does not narrow the opening region, and the aperture ratio, which is the proportion of the pixel in the opening region, is reduced. I will not let you. In addition, according to such a storage capacitor 62, the storage capacitor 62 can be formed in the open region, so that the capacitance value can be increased compared to the case where the storage capacitor is formed only in the non-open region. is there.

Although not shown, a black matrix (BM) made of aluminum or the like is formed on the side of the counter substrate 300 facing the liquid crystal layer 15 of the second substrate 13, and a silicon oxide film (SiO ₂ ) is formed thereon. Is formed. Further, a transparent common electrode 31 (see FIG. 4) is formed on the entire surface of the silicon oxide film, and a second alignment film 32 (see FIG. 4) is formed to cover the common electrode 31 made of ITO or the like. ing.

  FIG. 7 is a schematic plan view specifically showing the structure of the mother substrate in FIG. FIG. 8 is an enlarged plan view showing an enlarged portion B (particularly around the scribe line) of the mother substrate shown in FIG. Hereinafter, the structure of the mother substrate and the structure around the scribe line will be described with reference to FIGS.

  As shown in FIG. 7, the mother substrate 100 has a plurality of liquid crystal devices 11 arranged in a matrix as described above. The external connection terminal 23 and the data line driving circuit 22 are a VDD power wiring 71 (first constant potential wiring to which a first potential is supplied, a driving voltage of about 15 V) and a VSSX power wiring that constitute the signal wiring 29 described above. 72 (second constant potential wiring to which a second potential lower than the first potential is supplied, a reference potential) is electrically connected. In addition, the external connection terminal 23 and the scanning line driving circuit 24 are connected via the VDD power supply wiring 71 and the VSSY power supply wiring 73 (third constant potential wiring to which the second potential is supplied) constituting the signal wiring 29 described above. Electrically connected.

  Although not shown, the VDD power wiring 71 is routed around the periphery of the liquid crystal device 11 so as to surround the peripheral circuit (the data line driving circuit 22 and the scanning line driving circuit 24) and the display area 19, and Electrically connected.

  A scribe line 70 is provided between the liquid crystal device 11 and the liquid crystal device 11 (a region outside the external connection terminal 23) for dividing the liquid crystal device 11 into a plurality of liquid crystal devices 11 by a scribe / break process in the manufacturing process. . Hereinafter, the structure around the scribe line 70 will be described in detail with reference to FIG.

  The external connection terminal 23 has a VDD power supply terminal 81 as a first terminal, a VSSX power supply terminal 82 as a second terminal, and a VSSY power supply terminal 83 as a third terminal. The VDD power supply terminal 81 is electrically connected to the transistors included in the data line driving circuit 22 and the scanning line driving circuit 24 through the VDD power supply wiring 71. The VSSX power supply terminal (reference potential) 82 is electrically connected to the transistor of the data line driving circuit 22 through the VSSX power supply wiring 72. The VSSY power supply terminal (reference potential) 83 is electrically connected to the transistor of the scanning line driving circuit 24 through the VSSY power supply wiring 73.

  Around the scribe line 70, the planar area of the VSSX power supply wiring 72 and the VSSY power supply wiring 73 (hereinafter referred to as “planar area”) is brought close to the flat area of the VDD power supply wiring 71. Dummy extended wiring is provided. Here, it is assumed that the plane area of the VDD power supply wiring 71 is larger than the plane area of the VSSX power supply wiring 72 and the VSSY power supply wiring 73.

  More specifically, as shown in FIG. 8, the extension wiring is connected via the VSSX power supply wiring 72 and the VSSX power supply terminal 82 via the VSSX power supply wiring 72 a, the VSSY power supply wiring 73 and the VSSY power supply terminal 83. And VSSY extended wiring 73a.

  Note that the wirings for comparing the plane areas are wirings provided in the same wiring layer and adjacent to each other in the liquid crystal device 11. The flat area is the total area of wirings connected by one stroke in this wiring. In other words, the plane area of the VSSX power supply wiring 72 (including the VSSX expansion wiring 72a) is made closer to the plane area of the VDD power supply wiring 71. Further, the plane area of the VSSY power supply wiring 73 (including the VSSY extension wiring 73a) is made closer to the flat area of the VDD power supply wiring 71.

  More specifically, the VSSX extended wiring 72a extends along the scribe line 70 so that the plane area of the VDD power supply wiring 71 is within a ratio of 1.5 times the plane area of the VSSX power supply wiring 72 and VSSX extended wiring 72a. Extended.

  Similarly, the VSSY extension wiring 73a also extends along the scribe line 70 so that the plane area of the VDD power supply wiring 71 is within a ratio of 1.5 times the plane area of the VSSY power supply wiring 73 and the VSSY extension wiring 73a. It has been expanded.

  It is desirable that the plane area of the VSSX power supply wiring 72 (including the VSSX extension wiring 72a) and the plane area of the VDD power supply wiring 71 are substantially equal. Further, it is desirable that the plane area of the VSSY power supply wiring 73 (including the VSSY extension wiring 73a) and the plane area of the VDD power supply wiring 71 are substantially equal.

  In this way, by making the total area of the VSSX power supply wiring 72 and the VSSSX extended wiring 72a close to the area of the VDD power supply wiring 71, the potential difference generated between the wirings in the manufacturing process of the liquid crystal device 11 can be reduced. For example, electrostatic breakdown of the transistors connected to the VDD power supply wiring 71 and the VSSX power supply wiring 72 can be suppressed.

  Further, by bringing the total area of the VSSY power supply wiring 73 and the VSSY extended wiring 73a close to the area of the VDD power supply wiring 71, it becomes possible to reduce a potential difference generated between the wirings in the manufacturing process of the liquid crystal device 11. For example, it is possible to suppress electrostatic breakdown of the transistors connected to the VDD power supply wiring 71 and the VSSY power supply wiring 73.

  In addition, as a result of the comparative experiment, the yield of electrostatic breakdown when the ratio was within 1.5 times was better than when the ratio was within 2.0 times.

  Further, when the mother substrate 100 is scribed and broken, the VSSX extended wiring 72a and the VSSY extended wiring 73a provided around the scribe line 70 are cut, but for the purpose of reducing the potential difference between the wirings in the process. The performance as the liquid crystal device 11 is not impaired.

  9 and 10 are equivalent circuit diagrams showing an electrical configuration of the B part (peripheral circuit) of the mother board in FIG. Hereinafter, an example of the structure of the peripheral circuit will be described with reference to FIGS.

  As shown in FIG. 9, for example, an electrostatic protection circuit 181 and an inverter circuit 182 that are used in an inspection circuit are provided in a portion B (peripheral circuit) of the liquid crystal device 11. The electrostatic protection circuit 181 includes a Pch transistor (PchTFT) and an Nch transistor (NchTFT).

  The source and gate of the Pch transistor are connected to a VDD power supply wiring 171 (71) as a constant potential wiring to which a driving potential for driving the liquid crystal device 11 and a reference potential are applied. The drain is connected to the signal potential wiring 174. The source and gate of the Nch transistor are connected to a VSS power supply wiring 172 (72, 73) as a constant potential wiring. The drain is connected to the signal potential wiring 174. Note that the signal potential wiring 174 is connected to the signal terminal 123c.

  Similarly, the inverter circuit 182 includes a Pch transistor and an Nch transistor. The source of the Pch transistor is connected to the VDD power wiring 171. The gate is connected to the signal potential wiring 174. The source of the Nch transistor is connected to the VSS power supply wiring 172. The gate is connected to the signal potential wiring 174.

  Further, the circuit including the transistors in the peripheral circuit is not limited to the electrostatic protection circuit 181 and the inverter circuit 182, and may be a NAND circuit 95 as shown in FIG. 10, for example.

  In this manner, by making the total area of the VSS power supply wiring 172 and the extended wiring 72a (73a) close to the area of the VDD power supply wiring 171, the potential difference generated between the wirings in the manufacturing process of the liquid crystal device 11 is reduced. For example, it is possible to suppress electrostatic breakdown of transistors connected to the VDD power supply wiring 171 and the VSS power supply wiring 172.

  FIG. 11 is a chart showing the relationship between the area ratio between the VDD power supply wiring and the VSSX power supply wiring (VSSY power supply wiring), the presence / absence of electrostatic breakdown, and the defect rate. Hereinafter, the relationship between the area ratio, the electrostatic breakdown, and the defect rate will be described with reference to the chart of FIG.

  11 shows a case where the area ratio between the area of the VDD power supply wiring 71 and the area of the VSSX power supply wiring 72 (including the area of the VSSX expansion wiring 72a) is set to five patterns of the liquid crystal device A to the liquid crystal device E. This is the result of determining the presence or absence of electrostatic breakdown and the defective rate. The area ratio between the area of the VDD power supply wiring 71 and the area of the VSSY power supply wiring 73 (including the area of the VSSY extended wiring 73a) may be used.

  In the liquid crystal device A, the area ratio between the VDD power supply wiring 71 and the VSSX power supply wiring 72 (including the VSSX expansion wiring 72a) is 1.31. In this case, there was no electrostatic breakdown and the defect rate was 1% or less.

  In the liquid crystal device B, the area ratio between the VDD power supply wiring 71 and the VSSX power supply wiring 72 is 1.72. In this case, there was almost no electrostatic breakdown, and the defect rate was 2% to 3%.

  In the liquid crystal device C, the area ratio between the VDD power supply wiring 71 and the VSSX power supply wiring 72 is 2.62. In this case, there was electrostatic breakdown, and the defect rate was 10% to 15%.

  In the liquid crystal device D, the area ratio between the VDD power supply wiring 71 and the VSSX power supply wiring 72 is 14.92. Also in this case, there was electrostatic breakdown, and the defect rate was 15%.

  In the liquid crystal device E, the area ratio between the VDD power supply wiring 71 and the VSSX power supply wiring 72 is 45.25. Also in this case, there was electrostatic breakdown, and the defect rate was 20% to 40%.

  In this way, the VSSX extension wiring 72a is provided so that the area ratio between the area of the VDD power supply wiring 71 and the total area of the VSSX power supply wiring 72 and the VSSSX extension wiring 72a is within 1.5 times. Thus, in the manufacturing process of the liquid crystal device 11, it is possible to reduce a potential difference generated between the wirings. For example, the transistors connected to the VDD power supply wiring 71 and the VSSX power supply wiring 72 are prevented from being electrostatically damaged. be able to.

<Configuration of electronic equipment>
FIG. 12 is a schematic diagram illustrating a configuration of a liquid crystal projector as an example of an electronic apparatus including the above-described liquid crystal device. Hereinafter, the configuration of the liquid crystal projector including the liquid crystal device will be described with reference to FIG.

  As shown in FIG. 12, the liquid crystal projector 901 has a structure in which three liquid crystal modules employing the above-described liquid crystal device 11 are arranged and used as RGB light valves 911R, 911G, and 911B, respectively.

  Specifically, when projection light is emitted from a lamp unit 912 of a white light source such as a metal hydrolamp, the light components R, G, and B corresponding to the three primary colors of RGB are generated by three mirrors 913 and two dichroic mirrors 914. Divided and led to light valves 911R, 911G, and 911B corresponding to the respective colors. In particular, the light component B is guided through a relay lens system 918 including an incident lens 915, a relay lens 916, and an exit lens 917 in order to prevent light loss due to a long optical path.

  The light components R, G, and B corresponding to the three primary colors modulated by the light valves 911R, 911G, and 911B are synthesized again by the dichroic prism 919, and then projected as a color image on the screen 921 through the projection lens 920. The

  As described above, the present invention is not limited to the liquid crystal projector 901 in which three liquid crystal modules are arranged, and may be applied to, for example, a liquid crystal projector in which one liquid crystal module is arranged.

  The liquid crystal projector 901 having such a configuration can be efficiently assembled by reducing the cost through the liquid crystal module in which the liquid crystal device 11 described above is employed. In addition to the above-described liquid crystal projector 901, the electronic device including the liquid crystal device 11 is a high-definition EVF (Electric View Finder), a mobile phone, a mobile computer, a digital camera, a digital video camera, a television, a display, an in-vehicle device, an audio It can be used for various electronic devices such as devices and lighting devices.

  As described above in detail, according to the liquid crystal device 11 and the electronic apparatus of the present embodiment, the following effects can be obtained.

  (1) According to the liquid crystal device 11 of the present embodiment, the difference in the planar area between wirings between the adjacent VDD power wiring 71 and VSSX power wiring 72 (including the VSSX expansion wiring 72a) is reduced (1.5 times). In addition, since the difference in plane area between wirings between adjacent VDD power supply wiring 71 and VSSY power supply wiring 73 (including VSSY expansion wiring 73a) becomes small (within 1.5 times), the potential difference generated between the wirings Can be made smaller than in the prior art. This makes it difficult for a current to flow due to a difference in charge amount between the wirings, and can suppress electrostatic breakdown of the transistors connected to the power supply wirings 71, 72, 73.

  (2) According to the liquid crystal device 11 of the present embodiment, the VSSSX expansion electrically connected to the VSSX power supply wiring 72 outside the external connection terminal 23, that is, the cutting region (scribe line 70) for performing the scribe / break. Since the wiring 72a is provided and the VSSY extension wiring 73a electrically connected to the VSSY power supply wiring 73 is further provided, the VSSSX power supply wiring corresponding to the area of the extension wirings 72a and 73a provided around the scribe line 70 is provided. 72 and the VSSY power supply wiring 73 can be adjusted to increase the area. Therefore, the potential difference generated between the VDD power supply wiring 71 and the VSSX power supply wiring 72 and the potential difference generated between the VDD power supply wiring 71 and the VSSY power supply wiring 73 can be adjusted to be reduced. Thereby, electrostatic breakdown of the transistors connected to the VDD power supply wiring 71, the VSSX power supply wiring 72, and the VSSY power supply wiring 73 can be suppressed.

  (3) According to the liquid crystal device 11 of the present embodiment, after the scribe / break, the extension wirings 72a and 73a provided around the scribe line 70 are removed. Therefore, by providing the extension wirings 72a and 73a, The area of the VSSX power supply wiring 72 and the VSSY power supply wiring 73 can be adjusted without affecting the wiring arrangement.

  (4) According to the electronic apparatus of the present embodiment, since it is possible to prevent the electrostatic breakdown of the transistor in the manufacturing process and the liquid crystal device 11 that can be manufactured with a high yield is provided, an electronic apparatus having high cost performance is provided. Can be provided.

  In addition, embodiment is not limited above, It can also implement with the following forms.

(Modification 1)
As described above, in order to apply a voltage to the data line driving circuit 22 and the scanning line driving circuit 24, the present invention is not limited to the provision of the two power supply wirings of the VSSX power supply wiring 72 and the VSSY power supply wiring 73. Either one of the VSS may be divided into two, and the VDD power supply wiring may be divided into two power supply wirings of a VDDX power supply wiring and a VDDY power supply wiring.

(Modification 2)
As described above, the relationship between the flat area of the VDD power supply wiring 71 and the flat area of the VSSX power supply wiring 72 (including the VSSX expansion wiring 72a) or the VSSY power supply wiring 73 (including the VSSY expansion wiring 73a) is related to the liquid crystal device 11. Therefore, the range in which the VSSX extension wiring or the VSSY extension wiring is provided may be changed according to the model.

(Modification 3)
As described above, the target transistors for preventing electrostatic breakdown are not limited to the transistors included in the data line driving circuit 22 and the scanning line driving circuit 24. For example, the transistors are connected to the data line driving circuit 22 and the scanning line driving circuit 24. It may be a transistor. Further, the present invention is not limited to a transistor, and may be applied to a semiconductor element such as a diode.

(Modification 4)
As described above, the plane area of the VDD power supply wiring 71 is not limited to be larger than the plane area of the VSSX power supply wiring 72 and the VSSY power supply wiring 73, and the plane area of the VSSX power supply wiring 72 and the VSSY power supply wiring 73 is VDD. It may be larger than the plane area of the power supply wiring 71. Even in this case, the potential difference between the wirings can be reduced by providing the extended wiring so that the wiring with a small planar area approaches the wiring with a large planar area.

  DESCRIPTION OF SYMBOLS 11, 111 ... Liquid crystal device as an electro-optical device, 12 ... 1st board | substrate, 13 ... 2nd board | substrate, 14 ... Sealing material, 15 ... Liquid crystal layer, 16 ... Injection port, 17 ... Sealing material, 18 ... Frame light shielding film , 19 ... Display area, 21 ... Pixel area, 22 ... Data line driving circuit, 23 ... External connection terminal, 24 ... Scanning line driving circuit, 25 ... Inspection circuit, 26 ... Vertical conduction terminal, 27 ... Pixel electrode, 28 ... 1st alignment film, 29 ... signal wiring, 31 ... common electrode, 32 ... 2nd alignment film, 33 ... TFT element, 34 ... signal line, 35 ... scanning line, 36 ... capacitance line, 37 ... storage capacitor, 41 ... bottom Side light-shielding film 42... Underlying insulating film 43... Semiconductor layer 43 a. Channel region 43 b. Low concentration source region 43 c. Low concentration drain region 43 d. High concentration source region 43 e. Gate insulating film, 45 ... first interlayer insulation Film, 46, 51, 55, 58 ... Relay layer, 47, 52, 54, 56, 59 ... Contact hole, 53 ... Second interlayer insulating film, 57 ... Capacitance electrode, 61 ... Third interlayer insulating film, 62 ... Storage Capacitance 63 ... Dielectric film 64 ... Capacitance separation film 70 ... Scribe line 71 71 VDD power supply wiring 72 ... VSSX power supply wiring 72a ... VSSSX extension wiring 73 ... VSSY power supply wiring 73a ... VSSY extension wiring 81 ... VDD power terminal as the first terminal 82. VSSSX power terminal as the second terminal 83 83 VSSY power terminal as the third terminal 95 95 NAND circuit 100 100 Mother substrate as the electro-optical device substrate 171 ... VDD power supply wiring, 172 ... VSS power supply wiring, 174 ... signal potential wiring, 181 ... static protection circuit, 182 ... inverter circuit, 200 ... element substrate, 3 0 ... counter substrate, 901 ... liquid crystal projector, 911R, 911G, 911B ... light bulb, 912 ... lamp unit, 913 ... mirror, 914 ... dichroic mirror, 915 ... incident lens, 916 ... relay lens, 917 ... exit lens, 918 ... Relay lens system, 919 ... dichroic prism, 920 ... projection lens, 921 ... screen.

Claims (7)

A first terminal and a second terminal;
A data line driving circuit and a scanning line driving circuit;
A semiconductor element included in the data line driving circuit and the scanning line driving circuit;
A first constant potential wiring electrically connected to the first terminal and the semiconductor element and supplied with a first potential;
A second constant potential wiring electrically connected to the second terminal and the semiconductor element, supplied with a second potential lower than the first potential, and provided adjacent to the first constant potential wiring; Prepared,
An electro-optical device, wherein a ratio of an area of the first constant potential wiring and an area of the second constant potential wiring is 1.5 times or less. A first terminal, a second terminal and a third terminal;
A data line driving circuit and a scanning line driving circuit;
A semiconductor element included in the data line driving circuit and the scanning line driving circuit;
A first constant potential wiring electrically connected to the first terminal and the semiconductor element and supplied with a first potential;
A second potential that is electrically connected to the second terminal and the semiconductor element of the data line driving circuit, is supplied with a second potential lower than the first potential, and is provided adjacent to the first constant potential wiring. Constant potential wiring;
A third constant potential wiring electrically connected to the semiconductor element of the third terminal and the scanning line driving circuit, supplied with the second potential, and provided adjacent to the second constant potential wiring; Prepared,
The ratio of the area of the first constant potential wiring and the area of the second constant potential wiring is within 1.5 times, and the area of the first constant potential wiring and the area of the third constant potential wiring The electro-optical device is characterized in that the ratio is 1.5 times or less. The electro-optical device according to claim 1 or 2,
An electro-optical device, wherein an area of the first constant potential wiring and an area of the second constant potential wiring are substantially equal. The electro-optical device according to claim 2,
An electro-optical device, wherein an area of the first constant potential wiring and an area of the third constant potential wiring are substantially equal. In an electro-optical device substrate on which a plurality of electro-optical devices are formed,
One electro-optical device of the plurality of electro-optical devices is
A first terminal and a second terminal;
A data line driving circuit and a scanning line driving circuit;
A semiconductor element included in the data line driving circuit and the scanning line driving circuit;
A first constant potential wiring electrically connected to the first terminal and the semiconductor element and supplied with a first potential;
A second potential that is electrically connected to the second terminal and the semiconductor element of the data line driving circuit, is supplied with a second potential lower than the first potential, and is provided adjacent to the first constant potential wiring. Constant potential wiring;
An extended wiring disposed across the electro-optical device adjacent to the one electro-optical device and electrically connected to the second terminal;
With
The ratio of the area of said 1st constant potential wiring and the total area of the said 2nd constant potential wiring and the said extension wiring is 1.5 times or less. The board | substrate for electro-optical apparatuses characterized by the above-mentioned.   An electro-optical device formed using the electro-optical device substrate according to claim 5.   An electronic apparatus comprising the electro-optical device according to any one of claims 1 to 4 and 6.

Images