JP2012221125A - Data transfer control device, data transfer system and data transfer method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To execute the access of a master whose access destination competes with DMA transfer while satisfying the transfer speed request of the DMA transfer under execution.SOLUTION: A data transfer control device 110 includes: a first IF 105 for accessing a first storage device 107 in response to requests from a CPU 101 and a first DMAC 102; a second IF106 for accessing a second storage device 108 in response to a request from the first DMAC 102; and a counter 109 for counting an elapsed time since a second IF 106 starts accessing the second storage device 108. When receiving an access request from the CPU 101 to the first storage device 107 during a continuous transfer operation, the first IF 105 permits access from the CPU 101 to the first storage device 107 when the elapsed time is equal to or less than a reference value.

Description

  The present invention relates to a data transfer control device and a data transfer system for controlling access contention in direct memory access (hereinafter referred to as DMA) transfer.

  In general, an information processing apparatus can perform data transfer efficiently without using a CPU by performing DMA transfer using a DMA controller (hereinafter referred to as DMAC). However, in general, a computer using a common bus for memory access has a problem that during DMA transfer, the DMAC occupies the bus, so that access by the CPU and other DMA transfers cannot be executed.

  Means for solving this problem is presented in Patent Document 1. The configuration described in Patent Document 1 includes a plurality of buses, a plurality of bus masters, a bus control unit, and a plurality of data storage units that are provided corresponding to the plurality of buses and store transfer data. The bus control unit performs arbitration independently for each bus, so that a plurality of transfer requests for different buses can be executed simultaneously. However, when two or more bus acquisition requests are generated for one bus, access conflicts, and the right to use the bus is given to the DMAC according to priority.

Japanese Patent Laid-Open No. 2003-091501

  However, in the technique presented in Patent Document 1, simultaneous access is possible when the buses do not compete, but when the access destinations compete, access by a master such as a CPU is awaited during the DMA transfer period. There was a problem.

  On the other hand, when the access of the master such as the CPU is permitted during the DMA transfer, the subsequent DMA transfer is delayed by the access of the master. For this reason, there is a problem that a required DMA transfer rate may not be satisfied due to a decrease in the DMA transfer rate.

  The present invention solves the above-described conventional problems, and satisfies the transfer rate requirement of the DMA transfer being executed, while enabling the master access in which the DMA transfer and the access destination compete with each other, the data transfer control device, and the data It is an object to provide a transfer system and a data transfer method.

  In order to achieve the above object, a data transfer device according to an aspect of the present invention is a data transfer control device that transfers data from one of a first storage device and a second storage device to the other. Data from one of the first storage device and the second storage device via the first bus that is independent from the master, the master that accesses one storage device, and the first bus In accordance with a request from a first DMAC (Direct Memory Access Controller) that performs a continuous transfer operation that repeatedly and continuously performs a data transfer operation that writes the read data to the other, and the master and the first DMAC, In accordance with a request from the first DMAC and the first DMAC that accesses the first storage device, the second storage A second interface unit that accesses a device, and a counter that counts a first elapsed time since the second interface unit started accessing the second storage device. When the access request to the first storage device is received from the master during the continuous transfer operation, (1) when the first elapsed time is less than or equal to a first reference value, Access to the first storage device is permitted, and (2) when the first elapsed time is greater than the first reference value, the master prohibits access to the first storage device. 1 access control unit.

  Here, the DMAC performs data transfer by alternately and continuously performing reading from the transfer source and writing to the transfer destination. Therefore, while one storage device is being accessed, the other storage device is in an empty state in which access is not performed until the subsequent DMA transfer starts.

  Therefore, the data transfer control device according to an aspect of the present invention estimates the free state period of access in the first storage device when the master and the first DMAC cause access contention to the first storage device, If the elapsed time of 1 is less than or equal to the first reference value, access to the master is permitted. As a result, the data transfer apparatus can execute the access of the master whose access destination conflicts with the DMA transfer even during the DMA transfer. Further, the data transfer control device prohibits access of the master when the first elapsed time is larger than the first reference value. Thereby, the data transfer apparatus can satisfy the transfer rate request of the DMA transfer being executed.

  The first interface unit further includes a first DMAC access time required for one access from the first DMAC to the second storage device, and a first storage device from the master. And a first register that holds a first master access time required for one access to the first access control unit, wherein the first access control unit starts from the first DMAC access time to the first master access time. The first reference value may be calculated by subtracting.

  According to this configuration, the data transfer control device according to an aspect of the present invention can calculate the first reference value from the first DMAC access time and the first master access time.

  In addition, the first register further holds a first delay allowable value of one data transfer operation, and the first access control unit performs the first DMAC access time from the first DMAC access time. The first reference value may be calculated by adding the first allowable delay value after subtracting the master access time.

  According to this configuration, the data transfer control device according to an aspect of the present invention can realize access to the first storage device by the master during DMA transfer while suppressing the delay amount of DMA transfer within the allowable delay value. .

  In addition, the first interface unit further includes a second register that holds a total delay allowable amount in one continuous transfer operation, and the first access control unit receives the first register from the master. When an access request to the storage device is generated, the first master access time is subtracted from the first DMAC access time, and then a first delay allowable value equal to or less than the total delay allowable amount is added. The first reference value is calculated, and when the first elapsed time is less than or equal to the first reference value, access from the master to the first storage device is permitted and the second reference value is When the total delay allowable amount held in the register is reduced and the total delay allowable extension held in the second register is equal to or less than a predetermined value, the first reference value is: in front It may be used a value obtained by subtracting the first master access time from the first DMAC access time.

  According to this configuration, the data transfer control device according to an aspect of the present invention can realize access to the first storage device by the master during DMA transfer while satisfying the overall time requirement in the continuous transfer operation.

  The first delay tolerance may be the total delay tolerance.

  According to this configuration, the data transfer control device according to one aspect of the present invention performs control for realizing access to the first storage device by the master during DMA transfer while satisfying the overall time requirement in the continuous transfer operation. It can be done easily.

  The first access control unit uses the first value as the delay allowable value when the total delay allowable amount is equal to or greater than a predetermined threshold, and the total delay allowable amount is less than the threshold. A second value smaller than the first value may be used as the allowable delay value.

  According to this configuration, the data transfer control device according to an aspect of the present invention can permit access from a larger number of masters when the overall delay allowance is sufficient.

  The first access control unit permits the master to access the first storage device when the first elapsed time is less than or equal to the first reference value, and the first elapsed time. The first delay time is calculated by adding the time and the first master access time, and subtracting the first DMAC access time from the added value, and is stored in the second register The total delay allowable amount held in the second register may be updated by subtracting the first delay time from the total delay allowable amount.

  According to this configuration, the data transfer control device according to an aspect of the present invention can realize access to the first storage device by the master during DMA transfer while satisfying the overall time requirement in the continuous transfer operation.

  The second register holds a partial delay allowance corresponding to each of a plurality of partial sections obtained by dividing one continuous transfer operation, and the first access control unit receives the first access from the master. When an access request to one storage device occurs, the first master access time is subtracted from the first DMAC access time, and then the partial delay amount of the corresponding partial section is added, When the first reference value is calculated and the first elapsed time is less than or equal to the first reference value, access from the master to the first storage device is permitted, and the second register is stored in the second register. When the partial delay allowable amount of the corresponding partial section held is reduced and the partial delay amount of the corresponding section held in the second register is equal to or less than a predetermined value, First As reference value, it may be used a value obtained by subtracting the first master access time from the first DMAC access time.

  According to this configuration, the data transfer control device according to an aspect of the present invention can uniformize access by the master during the continuous transfer operation.

  In addition, the first DMAC is a third register that holds the number of consecutive accesses indicating the number of times of continuous access to the first storage device or the second storage device in one data transfer operation. And a buffer for holding data read from the first storage device or the second storage device, and the first DMAC is configured to perform the first storage device in one data transfer operation. The data is continuously read from one of the second storage devices for the number of consecutive accesses, the continuously read data is stored in the buffer, and the data stored in the buffer is stored for the number of consecutive accesses. In the write operation, the second storage unit writes to the other of the first storage device and the second storage device, and the counter is the second interface unit. The time from the start of initial access of continuous access number of times of access to the storage device may be counted as the first elapsed time.

  According to this configuration, the data transfer control device according to an aspect of the present invention can be applied to a case where a plurality of accesses are continuously performed in one data transfer operation.

  The first interface unit further includes a first DMAC access time required for one access from the first DMAC to the second storage device, and a first storage device from the master. And a first register for holding a first master access time required for one access to the first access control unit, wherein the first access control unit is a product of the first DMAC access time and the number of consecutive accesses. The first reference value may be calculated by subtracting the first master access time from the first master access time.

  According to this configuration, the data transfer control device according to an aspect of the present invention can calculate the first reference value even when a plurality of accesses are continuously performed in one data transfer operation.

  Further, the first register further holds a first delay allowable value of one data transfer operation, and the first access control unit includes the first DMAC access time and the number of consecutive accesses. The first reference value may be calculated by subtracting the first master access time from the product and adding the first allowable delay value.

  According to this configuration, the data transfer control device according to an aspect of the present invention can realize access to the first storage device by the master during DMA transfer while suppressing the delay amount of DMA transfer within the allowable delay value. .

  The data transfer control device further includes a second bus independent of the first bus, and the master accesses the first storage device via the second bus. Two DMACs may be used.

  According to this configuration, the data transfer apparatus according to an aspect of the present invention can execute the access of the second DMAC in which the DMA transfer and the access destination compete with each other while satisfying the transfer speed request of the DMA transfer being executed. .

  The master accesses the first storage device and the second storage device via a second bus independent of the first bus, and the second interface unit further includes the second bus In accordance with an instruction from the master, the second storage device is accessed, and the counter further counts a second elapsed time since the first interface unit started accessing the first storage device. When the second interface unit receives an access request from the master to the second storage device during the continuous transfer operation, the second elapsed time is less than or equal to a second reference value. Permitting access from the master to the second storage device, and prohibiting access from the master to the second storage device when the second elapsed time is greater than the second reference value. It may comprise the access control unit.

  According to this configuration, in the data transfer control device according to one aspect of the present invention, the master and the first DMAC independently access the first and second storage devices, and any one of the storages When an access conflict occurs in the apparatus, it is possible to execute a master access in which the DMA transfer and the access destination compete with each other while satisfying the transfer rate request of the DMA transfer being executed.

  The first interface unit further includes a first DMAC access time required for one access from the first DMAC to the second storage device, and a first storage device from the master. And a first register that holds a first master access time required for one access to the first access control unit, wherein the first access control unit starts from the first DMAC access time to the first master access time. The second reference unit further calculates a second reference necessary for one access from the first DMAC to the first storage device. A second register for holding a DMAC access time and a second master access time required for one access from the master to the second storage device; Subtracts the second master access time from the second DMAC access time, it may calculate the second reference value.

  According to this configuration, the data transfer control device according to an aspect of the present invention can calculate the first reference value from the first DMAC access time and the first master access time, and can also calculate the second DMAC access time. And the second master access time can calculate the second reference value.

  In addition, the first register further holds a first delay allowable value of one data transfer operation, and the first access control unit performs the first DMAC access time from the first DMAC access time. After subtracting the master access time, the first reference value is calculated by adding the first delay tolerance, and the fourth register further performs the first transfer of the data transfer operation. 2, and the second access control unit subtracts the second master access time from the second DMAC access time and then adds the second delay allowable value. Thus, the second reference value may be calculated.

  According to this configuration, the data transfer control device according to one aspect of the present invention allows the master during DMA transfer to access the first and second storage devices while keeping the delay amount of DMA transfer within the allowable delay value. Can be realized.

  The data transfer control device further includes a second register that holds an overall delay allowable amount in one continuous transfer operation, and the first access control unit receives the first memory from the master. When an access request to the device is generated, by subtracting the first master access time from the first DMAC access time, and then adding a first delay allowable value less than the total delay allowable amount, When the first reference value is calculated and the first elapsed time is less than or equal to the first reference value, access from the master to the first storage device is permitted, and the overall delay allowable amount is set to When the total delay amount held in the second register is less than or equal to a predetermined value, the first reference value is used as the first reference value from the first DMAC access time. Using the value obtained by subtracting the access time, the second access control unit determines that the second master from the second DMAC access time when an access request from the master to the second storage device is generated. After subtracting the access time, the second reference value is calculated by adding a second delay allowable value equal to or less than the total delay allowable amount, and the second elapsed time is equal to or less than the second reference value. In this case, access from the master to the second storage device is permitted, the total delay allowable amount is reduced, and the total delay amount held in the second register is less than or equal to a predetermined value. In this case, a value obtained by subtracting the second master access time from the second DMAC access time may be used as the second reference value.

  According to this configuration, the data transfer control device according to an aspect of the present invention realizes access to the first and second storage devices by the master during DMA transfer while satisfying the overall time requirement in the continuous transfer operation. it can.

  The master may be a CPU (Central Processing Unit).

  According to this configuration, the data transfer apparatus according to an embodiment of the present invention can execute CPU access in which DMA transfer and access destination compete with each other while satisfying the transfer speed request of the DMA transfer being executed.

  The present invention can be realized not only as such a data transfer control device, but also as a data transfer method including steps of characteristic means included in the data transfer control device. It can also be realized as a program executed by a computer. Needless to say, such a program can be distributed via a non-transitory computer-readable recording medium such as a CD-ROM and a transmission medium such as the Internet.

  Further, the present invention can be realized as a semiconductor integrated circuit (LSI) that realizes part or all of the functions of such a data transfer control device, or as a data transfer system including such a data transfer control device. it can.

  As described above, the present invention provides a data transfer control device, a data transfer system, and a data transfer method capable of satisfying the transfer rate requirement of the DMA transfer being executed and enabling the access of the master whose access destination conflicts with the DMA transfer. it can.

1 is a block diagram of a data transfer control system according to a first embodiment of the present invention. It is a flowchart of 1st IF which concerns on Embodiment 1 of this invention. 4 is a timing chart showing an access state to each storage device during DMA transfer according to the first embodiment of the present invention. 4 is a timing chart when CPU access is permitted according to the first embodiment of the present invention. 4 is a timing chart when CPU access is not permitted according to the first embodiment of the present invention. It is a timing chart in the comparative example based on Embodiment 1 of this invention. It is a block diagram of the modification of the data transfer control system which concerns on Embodiment 1 of this invention. It is a block diagram of the data transfer control system which concerns on Embodiment 2 of this invention. It is a flowchart of 1st IF which concerns on Embodiment 2 of this invention. It is a timing chart at the time of CPU access permission based on Embodiment 2 of this invention. It is a timing chart at the time of CPU access non-permission based on Embodiment 2 of this invention. It is a timing chart at the time of CPU access permission based on Embodiment 2 of this invention. It is a timing chart at the time of CPU access non-permission based on Embodiment 2 of this invention. It is a block diagram of the data transfer control system which concerns on Embodiment 3 of this invention. It is a timing chart of the whole DMA continuous transfer based on Embodiment 3 of this invention. It is a flowchart of 1st IF which concerns on Embodiment 3 of this invention. It is a timing chart at the time of CPU access permission based on Embodiment 3 of this invention. It is a timing chart at the time of CPU access non-permission based on Embodiment 3 of this invention. It is a block diagram of the data transfer control system which concerns on Embodiment 4 of this invention. It is a flowchart of 1st IF which concerns on Embodiment 4 of this invention. It is a timing chart which shows the access state to each memory | storage device in DMA transfer based on Embodiment 4 of this invention. It is a timing chart at the time of CPU access permission based on Embodiment 4 of this invention. It is a timing chart at the time of CPU access non-permission based on Embodiment 4 of this invention. It is a block diagram of the data transfer control system which concerns on Embodiment 5 of this invention. It is a timing chart at the time of CPU access permission based on Embodiment 5 of this invention. It is a timing chart at the time of CPU access non-permission based on Embodiment 5 of this invention. It is a block diagram of the data transfer control system which concerns on Embodiment 6 of this invention. It is a block diagram of the data transfer control system which concerns on Embodiment 7 of this invention. It is a block diagram of the data transfer control system which concerns on Embodiment 8 of this invention. It is a block diagram of the data transfer control system which concerns on Embodiment 9 of this invention. It is a block diagram of the data transfer control system which concerns on Embodiment 10 of this invention. It is a block diagram of the data transfer control system which concerns on Embodiment 11 of this invention. It is a block diagram of the data transfer control system which concerns on Embodiment 12 of this invention.

  The best mode for carrying out the present invention will be described below with reference to the drawings. In addition, since the component which attached | subjected the same code | symbol in embodiment performs the same operation | movement, description may be abbreviate | omitted again.

(Embodiment 1)
In the data transfer control device according to the first embodiment of the present invention, when there is an access request from the CPU to the first storage device while the DMAC is accessing the second storage device, the DMAC is the second storage device. It is determined whether or not the first elapsed time from the time when access is started is less than or equal to the reference value. Then, the data transfer control device permits access from the CPU to the first storage device when the first elapsed time is equal to or less than the reference value.

  As a result, the data transfer control device can execute the access of the master in which the DMA transfer and the access destination compete with each other while satisfying the transfer rate request of the DMA transfer being executed.

  First, the configuration of the data transfer control device according to the first embodiment of the present invention will be described.

  FIG. 1 is a block diagram showing a configuration of a data transfer system 100 according to Embodiment 1 of the present invention. The data transfer system 100 illustrated in FIG. 1 includes a first storage device 107, a second storage device 108, and a data transfer control device 110.

  The data transfer control device 110 transfers data from one of the first storage device 107 and the second storage device 108 to the other. For example, the data transfer control device 110 reads and processes data from the first storage device 107 and transfers data from the second storage device 108 to the first storage device 107.

  The first storage device 107 is, for example, a volatile memory, and the second storage device 108 is a nonvolatile memory having a longer access time than the first storage device 107. Note that the types of the first storage device 107 and the second storage device 108 are not limited thereto.

  The data transfer control device 110 includes a CPU 101, a first DMAC 102, a first DMAC bus 104, a first IF 105, a second IF 106, and a counter 109.

  The CPU 101 is a master that accesses the first storage device 107.

  The first DMAC bus 104 corresponds to the first bus of the present invention and can transfer data independently from the CPU 101.

  The first DMAC 102 performs data transfer between the first storage device 107 and the second storage device 108 via the first DMAC bus 104. Specifically, the first DMAC 102 performs a continuous transfer operation via the first DMAC bus 104. Here, the continuous transfer operation is an operation in which a data transfer operation of reading data from one of the first storage device 107 and the second storage device 108 and writing the read data to the other is repeatedly performed continuously. In this continuous transfer operation, the operation of reading data from one of the first storage device 107 and the second storage device 108 and the operation of writing the read data to the other are performed exclusively in time series. Hereinafter, this continuous transfer operation is also referred to as DMA transfer or DMA transfer operation.

  The CPU 101 and the first DMAC 102 operate independently.

  The first IF 105 corresponds to the first interface unit of the present invention and controls access to the first storage device 107. Specifically, the first IF 105 accesses the first storage device 107 in accordance with requests from the CPU 101 and the first DMAC 102.

  The second IF 106 corresponds to the second interface unit of the present invention, and controls access to the second storage device 108. Specifically, the second IF 106 accesses the second storage device 108 in accordance with a request from the first DMAC 102. Further, the second IF 106 outputs an access start signal to the counter 109 when access to the second storage device 108 is started.

  The counter 109 counts a first elapsed time (count value) from when the second IF 106 starts accessing the second storage device 108. Specifically, when the counter 109 receives an access start signal from the second IF 106, the counter 109 starts counting. In addition, the counter 109 passes the count value to the access control unit 152.

  The first IF 105 includes a first register 151 and an access control unit 152.

  The first register 151 includes registers 153 and 154.

  The register 153 holds the DMAC access time T1. The DMAC access time T1 corresponds to the first DMAC access time of the present invention, and indicates the time required for one access from the first DMAC 102 to the second storage device 108. Specifically, the DMAC access time T1 indicates the number of clock cycles necessary for one access from the first DMAC 102 to the second storage device 108.

  The register 154 holds the CPU access time T2. The CPU access time T2 corresponds to the first master access time of the present invention, and indicates the time required for one access from the CPU 101 to the first storage device 107. Specifically, the CPU access time T2 indicates the number of clock cycles required for one access from the CPU 101 to the first storage device 107.

  The access control unit 152 corresponds to the first access control unit of the present invention, and determines whether or not the CPU 101 can access the first storage device 107 during the continuous transfer operation by the first DMAC 102.

  Specifically, when the access control unit 152 receives an access request from the CPU 101 to the first storage device 107 during the continuous transfer operation, the access control unit 152 receives the first reference value and the first count counted by the counter 109. The elapsed time (count value) is compared. Then, the access control unit 152 permits access from the CPU 101 to the first storage device 107 when the first elapsed time is equal to or less than the first reference value. In addition, when the first elapsed time is larger than the first reference value, the access control unit 152 prohibits access from the CPU 101 to the first storage device 107. Here, the first reference value is a value obtained by subtracting the CPU access time T2 from the DMAC access time T1. That is, the access control unit 152 calculates the first reference value by subtracting the CPU access time T2 from the DMAC access time T1.

  Hereinafter, the operation of the data transfer control device 110 configured as described above will be described.

  The present invention is characterized by operations during DMA transfer. Therefore, in the following, an operation during execution of DMA transfer will be described.

  First, the operation of the first DMAC 102 will be described. The first DMAC 102 performs continuous transfer operations by alternately and continuously accessing the transfer source storage device and the transfer destination storage device. Here, data transfer from the first storage device 107 to the second storage device 108 is considered. In this case, the first DMAC 102 first issues a data read request from the first storage device 107 to the first IF 105. When the data read from the first storage device 107 is completed, the first DMAC 102 issues a data write request to the second storage device 108 to the second IF 106 to read the data earlier. Data is written to the second storage device 108. When the data writing is completed, the first DMAC 102 continues to update the address and starts reading from the first storage device 107 again. Thereafter, the first DMAC 102 performs access alternately in the same manner. The first DMAC 102 ends the continuous transfer operation when the transfer of data to be finally transferred is completed.

  Next, the operation of the first IF 105 will be described.

  FIG. 2 is a flowchart of the operation performed by the first IF 105 when executing DMA transfer.

  First, the CPU 101 or the first DMAC 102 sets the DMAC access time T1 in the register 153, and sets the CPU access time T2 in the register 154 (S101). The DMAC access time T1 and the CPU access time T2 may be set in advance before the continuous transfer operation, or at least one of the DMAC access time T1 and the CPU access time T2 is set for each continuous transfer operation. May be.

  Hereinafter, access from the CPU 101 to the first storage device 107 is referred to as CPU access, and access from the first DMAC 102 to the first storage device 107 or the second storage device 108 is referred to as DMA access. A CPU access request is called a CPU access request, and a DMA access request is called a DMA access request.

  Here, if the CPU access is being executed by the first IF 105 at the time of step S102 shown in FIG. 2, the continuous transfer operation may be started after the CPU access is completed, or the CPU access is canceled. Then, the continuous transfer operation may be started.

  First, the operation when no CPU access occurs during the continuous transfer operation will be described with reference to FIGS.

  First, the first IF 105 receives an access request from the DMAC 102 (S102), and starts DMA access (S103). When the DMA access is completed (S104), the first DMAC 102 next accesses the second storage device 108. During this time, the first IF 105 does not perform processing. Thereafter, when the access to the second storage device 108 is completed (Yes in S106), and the continuous transfer operation is not completed in Step S110 (No in S110), the first IF 105 returns to Step S102 again. A DMA access request is received and DMA access is executed (S103). If the continuous transfer operation is finally completed in step S110 (Yes in S110), the DMA continuous transfer operation ends.

  FIG. 3 is a diagram showing an access status to the first storage device 107 and the second storage device 108 at this time. As shown in FIG. 3, in the continuous transfer operation, the first DMAC 102 alternately accesses the first storage device 107 and the second storage device 108.

  Next, the operation when the first DMAC 102 is accessing the first storage device 107, that is, when a CPU access request is issued during the period from step S102 to step S104 in FIG. 2, will be described.

  At this time, since the DMA access is being executed, the CPU access request is not accepted.

  Next, when the first DMAC 102 is not accessing the first storage device 107, that is, when a CPU access request is issued during step S110 after step S104 in FIG. 2, or The operation when the CPU access request issued and not accepted during the period from step S102 to step S104 is in a waiting state until the completion of the DMA access in step S104 will be described.

  First, after the DMA access ends (S104), the counter 109 starts counting simultaneously with the start of the DMA access to the second storage device 108 (S105).

  Thereafter, the first IF 105 determines whether or not a CPU access request has been issued for each predetermined period in a period until the DMA access to the first storage device 107 ends (No in S106) ( S107).

  When the CPU access request is issued (Yes in S107), the first IF 105 determines whether the CPU access is possible. Specifically, when the counter value by the counter 109 is equal to or smaller than the first reference value (Yes in S108), the first IF 105 executes CPU access (S109). Further, the first IF 105 does not accept the CPU access request when the counter value by the counter 109 is larger than the first reference value (No in S108).

  A specific example of this access determination operation will be described with reference to FIGS. 4 and 5, the count value is the first elapsed time from the start of access to the second storage device 108 by the first DMAC 102, and the value is output from the counter 109. The remaining period T3 indicates the period from the generation of the CPU access request to the start of the subsequent DMA access to the first storage device 107, which can be calculated by subtracting the count value from the DMAC access time T1.

  FIG. 4 is a diagram illustrating an operation example when the CPU access time T2 is shorter than the remaining period T3 until the start of the subsequent DMA access at the time when the CPU access request occurs. In this case, the CPU access request is accepted and CPU access is executed. Further, the DMA transfer operation itself is the same as that shown in FIG.

  FIG. 5 is a diagram illustrating an operation example when the CPU access time T2 is longer than the remaining period T3. In this case, if the CPU access is permitted, the CPU access conflicts with the subsequent DMA transfer to the first storage device 107. Therefore, in this case, CPU access is not permitted.

  FIG. 6 is a diagram for comparison, and is a diagram illustrating an operation example when the process according to the first embodiment of the present invention is not performed when the CPU access time T2 is longer than the remaining period T3. As shown in FIG. 6, in such a case, if the CPU access is permitted, the CPU access conflicts with the DMA transfer to the subsequent first storage device 107. This delays subsequent DMA transfers.

  As described above, the data transfer control device 110 according to the first embodiment of the present invention permits CPU access only when the CPU access time T2 is shorter than the remaining period T3 until the subsequent DMA access starts. Accordingly, the data transfer control device 110 can execute access to the first storage device 107 by the CPU 101 without delaying subsequent DMA access.

  In the above description, the example in which the first register 151 holds the DMAC access time T1 and the CPU access time T2 has been described. However, as illustrated in FIG. 7, the first register 151 stores the first reference value. A register 155 that holds (= T2−T1) may be included. In this case, the access control unit 152 performs access determination by comparing the first reference value with the count value.

  FIG. 4 shows an operation example in which the CPU access occurs once until the next DMA transfer is started. However, the condition that the CPU access time T2 is shorter than the remaining period T3 until the subsequent DMA access is started. If satisfied, the CPU access may be executed any number of times before the next DMA transfer is performed.

  In the example shown in FIG. 1, the data transfer system 100 includes only one CPU 101, but has an independent number of buses that have an independent bus from the first DMAC 102 and access the first storage device 107. The CPU may be included. In this case, the same effect can be realized by adding a simple function.

  In the example illustrated in FIG. 1, the example in which the first DMAC 102 can access two storage devices is shown. However, the first DMAC 102 is connected to three or more storage devices including the first storage device 107. It may be accessible. In this case, the same effect can be realized by adding a simple function.

  In the above description, the example in which data is mainly transferred from the first storage device 107 to the second storage device 108 has been described. However, the present invention can be applied to either the first storage device 107 or the second storage device 108. The present invention can be applied to a case where a continuous transfer operation is performed in which data transfer operation for reading data from and writing data to the other is repeated continuously.

  Further, as described above, the first storage device 107 is, for example, a volatile memory, and the second storage device 108 is a nonvolatile memory having a longer access time than the first storage device 107. In such a case, by using the data transfer control device 110 according to the first embodiment of the present invention, data held in the second storage device 108 having a long access time is sequentially transferred to the first storage device 107. In addition, since data can be read from the first storage device 107, processing can be executed efficiently.

  Note that the configuration of the connected storage device is not limited to the above as long as it is a data accessible device.

(Embodiment 2)
In the second embodiment of the present invention, a modification of the above-described first embodiment will be described. The data transfer control device 210 according to the second embodiment of the present invention further determines whether the CPU can be accessed using the delay allowable value T4.

  FIG. 8 is a block diagram showing the configuration of the data transfer system 200 according to Embodiment 2 of the present invention. The data transfer control device 210 shown in FIG. 8 differs from the data transfer control device 110 according to the first embodiment in the configuration of the first IF 205. Specifically, the first register 151 further includes a register 256 that holds a delay allowable value T4 that is a delay allowable value in one data transfer operation. This allowable delay value T4 corresponds to the first allowable delay value of the present invention. Further, the access control unit 252 uses the allowable delay value T4 for determining whether or not CPU access is possible. Other components are the same as those in the first embodiment.

  In the first embodiment, CPU access is permitted only when there is no conflict with DMA transfer. On the other hand, in the second embodiment of the present invention, the DMA transfer is allowed to be delayed up to a certain value, and even in the case of contention, the DMA access is delayed and the CPU access is executed.

  Specifically, the access control unit 252 calculates the first reference value by subtracting the CPU access time T2 from the DMAC access time T1 and adding the allowable delay value T4. Next, the access control unit 252 compares the calculated first reference value with the first elapsed time (count value) counted by the counter 109. Then, the access control unit 252 permits access from the CPU 101 to the first storage device 107 when the first elapsed time is equal to or less than the first reference value. In addition, when the first elapsed time is larger than the first reference value, the access control unit 252 prohibits access from the CPU 101 to the first storage device 107.

  FIG. 9 is a flowchart of the operation by the first IF 205 during DMA transfer according to the second embodiment of the present invention. 9 is different from the process shown in FIG. 2 in steps S201 and S208. Further, the process shown in FIG. 9 further includes the process of step S211.

  First, the CPU 101 or the first DMAC 102 sets the DMAC access time T1 in the register 153, the CPU access time T2 in the register 154, and the allowable delay value T4 in the register 256 (S201).

  In FIG. 9, when a DMA access request is issued (S102), if the CPU access is already being executed (Yes in S211), the DMA transfer is waited until the CPU access is completed. When the CPU access ends in step S211, DMA access is executed (S103). Other operations in the flowchart are the same as those in the first embodiment.

  Further, during the DMA access execution from step S103 to step S104, the CPU access request is not accepted as in the first embodiment.

  If there is a CPU access request after the completion of DMA access in step S104 (Yes in S107), the access control unit 252 determines access and determines whether or not CPU access is possible (S208).

  The access determination at this time will be described with reference to FIGS. 10 and 11, the allowable delay value T4 is an allowable delay time that can satisfy the required performance even if a delay occurs in the DMA transfer, and is held in the register 256.

  FIG. 10 is a diagram illustrating an operation example when the CPU access time T2 is smaller than the total value of the remaining period T3 until the start of the subsequent DMA access and the allowable delay value T4 when the CPU access request is generated. . In this case, the CPU access request is accepted and CPU access is executed. Further, since the CPU access is being executed when the DMA access request is issued as shown in FIG. 10, the subsequent DMA transfer is in a waiting state and a delay occurs. The delay of the DMA transfer at this time is a set delay allowable value. It is within T4.

  FIG. 11 is a diagram illustrating an operation example when the CPU access time T2 is longer than the total value of the remaining period T3 until the start of the subsequent DMA access and the allowable delay value T4. In this case, if the CPU access is permitted, the delay of the subsequent DMA transfer becomes larger than the set delay allowable value T4, so the CPU access is not permitted.

  As described above, the data transfer control device 210 according to the second embodiment of the present invention can execute CPU access while keeping the delay of DMA transfer within a set allowable delay value.

  In the first embodiment described above, CPU access can be performed only when the CPU access time T2 is smaller than the DMAC access time T1, but in the second embodiment, depending on the value of the allowable delay value T4, Even when the CPU access time T2 is longer than the DMAC access time T1, the CPU access can be realized. The operation at this time will be described with reference to FIGS.

  Similarly at this time, as shown in FIG. 12, if the DMA transfer delay falls within the set allowable delay value T4, CPU access can be executed. Similarly, as shown in FIG. 13, when the DMA transfer delay exceeds the allowable delay value T4, the CPU access is not permitted.

  Note that the same modification example as in the first embodiment may be applied to the data transfer control device 210 according to the second embodiment.

  For example, the first register 151 may hold a first reference value (= T1−T2 + T4) instead of the DMAC access time T1, the CPU access time T2, and the delay allowable value T4.

(Embodiment 3)
In the third embodiment of the present invention, a modification of the above-described first embodiment will be described. The data transfer control device 310 according to the third embodiment of the present invention further determines whether or not the CPU can be accessed using the total delay allowable amount T5.

  FIG. 14 is a block diagram showing a configuration of a data transfer system 300 according to Embodiment 3 of the present invention. The data transfer control device 310 shown in FIG. 14 differs from the data transfer control device 110 according to the first embodiment in the configuration of the first IF 305. Specifically, the first IF 305 further includes a second register 357. Further, the function of the access control unit 352 is different from that of the access control unit 152.

  The second register 357 includes a register 358 that holds an overall delay allowable amount T5 in one continuous transfer operation by the first DMAC 102. The overall delay allowable amount T5 will be described with reference to FIG.

  The first DMAC 102 performs a continuous transfer operation for continuously transferring a predetermined amount of data. At this time, the DMA transfer request time shown in FIG. 15 is an elapsed time until the time at which the DMA transfer needs to be completed, and is given at the time of design. The fastest DMA transfer completion time is a time when the DMA transfer can be completed at the fastest when the DMA transfer is not hindered by access competition, and can be calculated in advance from the time required for one access and the required number of accesses. . The total delay allowable amount T5 can be calculated from these values, and is an allowable amount of delay time that can complete the DMA transfer within the DMA transfer request time even if a delay occurs during the DMA transfer.

  The access control unit 352 performs the following processing when an access request from the CPU 101 to the first storage device 107 is generated.

  First, the access control unit 352 calculates the first reference value by subtracting the CPU access time T2 from the DMAC access time T1 and adding the total delay allowable amount T5. Then, the access control unit 352 determines whether or not the CPU can be accessed using the calculated first reference value.

  Further, when the count value is equal to or smaller than the first reference value and the CPU access is permitted, the access control unit 352 adds the counter value and the CPU access time T2, and subtracts the DMAC access time T1 from the added value. Thus, the delay time T6 is calculated. This delay time T6 corresponds to the first delay time of the present invention. Next, the access control unit 352 subtracts the delay time T6 from the total delay allowable amount T5 held in the second register 357, thereby obtaining the total delay allowable amount T5 held in the second register 357. Update.

  FIG. 16 is a flowchart of the operation by the first IF 305 during the DMA transfer in the third embodiment of the present invention. Note that the processing shown in FIG. 16 differs from the processing shown in FIG. 9 in steps S301 and S308. Further, the process shown in FIG. 16 further includes the process of step S312.

  First, the CPU 101 or the first DMAC 102 sets the DMAC access time T1 in the register 153, the CPU access time T2 in the register 154, and the total delay allowable amount T5 in the register 358 (S301).

  If there is a CPU access request after the completion of DMA access in step S104 (Yes in S107), the access control unit 352 performs access determination and determines whether or not CPU access is possible (S308).

  This access determination will be described with reference to FIGS. In the third embodiment, the values of the first register 151 and the second register 357 are updated simultaneously with the access determination. The operation will also be described.

  For explanation, it is assumed that the first register 151 has the same configuration as that of the first embodiment and holds the DMAC access time T1 and the CPU access time T2. The remaining period T3 is calculated by subtracting the count value from the DMAC access time T1.

  Note that these values do not limit the values set in the first register 151, and a first reference value for determining access permission may be held in the first register 151.

  FIG. 17 is a diagram illustrating an operation example when the total delay allowable amount T5 is a sufficiently large value. At this time, since the count value is equal to or smaller than the first reference value (= T1-T2 + T5) (Yes in S308), the CPU access request is accepted and the CPU access is executed (S109).

  Next, the access control unit 352 calculates a delay time T6. This delay time T6 is a delay value when a delay occurs in the subsequent DMA access due to the CPU access. At this time, since the DMA transfer is delayed by the delay time T6, the access control unit 352 subtracts the delay time T6 from the total delay allowable amount T5 held in the second register 357. Is held in the second register 357 as a new overall delay allowance T5 (S312).

  FIG. 18 is a diagram showing an operation example when the total delay allowable amount T5 held in the second register 357 becomes smaller than the CPU access time T2 as a result of delay in DMA transfer. At this time, if the DMA transfer is delayed due to the CPU access, the DMA transfer allowable delay may be exceeded in some cases and the DMA transfer request may not be satisfied. Accordingly, the access control unit 352 does not permit CPU access when the count value is larger than the first reference value (= T1−T2 + T5) (No in S308) and a delay occurs in the subsequent DMA transfer.

  As described above, the data transfer control device 310 according to the third embodiment of the present invention recalculates the total delay allowable amount T5 each time a DMA transfer delay occurs, and determines access based on the total delay allowable amount T5. Update the reference value. As a result, the data transfer control device 310 can flexibly execute access by the CPU while satisfying the completion time required for DMA transfer.

  Note that the same modification example as in the first or second embodiment described above may be applied to the data transfer control device 310 according to the third embodiment.

  Further, the access control unit 352 may not calculate the DMA transfer delay time T6, but may subtract a predetermined value from the total delay allowable amount T5 each time a delay occurs in the DMA transfer.

  In the above description, a value obtained by adding the total delay allowable amount T5 to the value obtained by subtracting the CPU access time T2 from the DMAC access time T1 is used as the first reference value. A value obtained by adding the delay allowable value T4 to the value obtained by subtracting the CPU access time T2 from the DMAC access time T1 using the value T4 may be used as the first reference value. In this case, the access control unit 352 calculates the delay time T6 as described above, and sequentially subtracts the delay time T6 from the total delay allowable amount T5. Then, when the total delay allowable amount T5 becomes equal to or smaller than the allowable delay value T4, the access control unit 352 calculates the first reference value using the total delay allowable amount T5.

  Further, the access control unit 352 may change the delay allowable value T4 in a stepwise manner in accordance with the remaining overall delay allowable amount T5. For example, when the initial value of the total delay allowable amount T5 is 100 cycles, the access control unit 352 sets the delay allowable value T4 to 10 cycles when the total delay allowable amount T5 is 30 cycles or more, and the total delay allowable amount If T5 is less than 30 cycles, the allowable delay value T4 is set to 5 cycles.

  In addition, the access control unit 352 may divide one continuous transfer operation into a plurality of periods, and set an overall delay allowable amount T5 for each period. In other words, the second register 357 holds a partial delay allowable amount corresponding to each of a plurality of partial sections obtained by dividing one continuous transfer operation. Further, the access control unit 352 may use a partial delay allowable amount corresponding to the partial section in place of the total delay allowable amount T5 in the above-described process in a certain partial section.

(Embodiment 4)
In the fourth embodiment of the present invention, a modification of the above-described first embodiment will be described. In the fourth embodiment of the present invention, a case where each storage device is continuously accessed in one data transfer operation will be described.

  FIG. 19 is a block diagram showing a configuration of a data transfer system 400 according to Embodiment 4 of the present invention. The data transfer control device 410 illustrated in FIG. 19 has functions of the first DMAC 402, the access control unit 452 included in the first IF 405, and the second IF 406 compared to the data transfer control device 110 according to the first embodiment. Is different.

  The first DMAC 402 includes a buffer 421 and a third register 422. The third register 422 holds a continuous access number 423 indicating the number of continuous accesses to the first storage device 107 or the second storage device 108 in one data transfer operation.

  The buffer 421 holds data read from the first storage device 107 or the second storage device 108.

  The first DMAC 402 continuously reads data from one of the first storage device 107 and the second storage device 108 for the number of consecutive accesses 423 minutes in one data transfer operation, and the continuously read data Is stored in the buffer 421. Thereafter, the first DMAC 402 writes the data stored in the buffer 421 to the other of the first storage device 107 and the second storage device 108 by a write operation for the number of consecutive accesses 423.

  Further, the counter 109 counts, as the first elapsed time, the time from the start of the first access among the continuous access count 423 minutes to the second storage device 108 by the second IF 406. Specifically, the second IF 406 issues an access start signal at the time of initial access of continuous access. Then, the counter 109 starts counting according to the access start signal.

  Hereinafter, the operation of the first DMAC 402 will be described. Here, an example in which a continuous transfer operation for transferring data from the first storage device 107 to the second storage device 108 is performed will be described. First, the first DMAC 402 performs data reading from the first storage device 107 and holds the read data in the buffer 421. Subsequently, the first DMAC 402 continuously accesses the first storage device 107 and sequentially holds the read data in the buffer 421. The first DMAC 402 repeats this operation for 423 consecutive access times held in the third register 422. It is assumed that the buffer 421 can hold data for one read data size × the number of consecutive accesses 423. Thereafter, the first DMAC 402 sequentially writes the data held in the buffer 421 to the second storage device 108. The first DMAC 402 also repeats this operation for 423 continuous accesses. Thereafter, the first DMAC 402 performs a continuous transfer operation by repeating these series of data transfer operations.

  FIG. 20 is a flowchart of the operation by the first IF 405 during DMA transfer in the fourth embodiment. The process shown in FIG. 20 differs from the process shown in FIG. 2 in steps S401, S406, and S408. Further, the process shown in FIG. 20 further includes the process of step S413.

  First, the CPU 101 or the first DMAC 102 sets the DMAC access time T1 in the register 153, the CPU access time T2 in the register 154, and the continuous access count 423 in the third register 422 (S401).

  The first IF 405, once accessed from step S102 to step S104, does not complete the access for the specified number of times (continuous access number 423) in step S413 (No in S413), and again. The processing from step S102 to step S104 is executed. On the other hand, after the access for the number of consecutive accesses is completed in step S413 (Yes in S413), the first IF 405 once ends the DMAC access. In the meantime, the first DMAC 402 continuously accesses the second storage device 108 for the designated number of times.

  After the access to the second storage device 108 by the first DMAC 402 is completed (Yes in S406), if the continuous transfer operation is not completed in Step S110 (No in S110), the first IF 405 again performs Step S102. The access request is received and DMA access is executed (S103). If the continuous transfer operation is finally completed in S110 (Yes in S110), the first IF 405 ends the continuous transfer operation.

  FIG. 21 is a diagram illustrating an operation example in the case where access by the CPU 101 does not occur during DMA transfer. FIG. 21 shows an example in which the number of consecutive accesses 423 is two. An arbitrary number may be set as the continuous access number 423.

  If there is a CPU access request after completion of the DMA access in step S413 (Yes in S107), the access control unit 452 performs access determination and determines whether or not CPU access is possible (S408).

  This access determination operation will be described with reference to FIGS. 22 and 23, the DMAC access time T1b indicates a period during which the first DMAC 402 is accessing the second storage device 108 for the number of consecutive accesses 423. The DMAC access time T1b is a product of the DMAC access time T1 and the number of consecutive accesses 423. The count value is a first elapsed time from the start of the initial access of the continuous access to the second storage device 108 by the first DMAC 402, and is output from the counter 109. The remaining period T3 indicates a period from the generation of the CPU access request to the start of the subsequent DMA access to the subsequent first storage device 107. This remaining period T3 can be calculated by subtracting the count value from the DMAC access time T1b.

  The access control unit 452 determines whether or not CPU access is possible using the above value, as in the first embodiment. As shown in FIG. 22, when the CPU access time T2 is shorter than the remaining period T3 when the CPU access request is generated, that is, when the count value is equal to or less than the first reference value (= T1b-T2) (Yes in S408). The access control unit 452 permits the CPU access (S109). As shown in FIG. 23, when the CPU access time T2 is longer than the remaining period T3 when the CPU access request is generated, that is, when the count value is larger than the first reference value (= T1b−T2) (S408). No), the access control unit 452 does not permit CPU access.

  As described above, the data transfer control device 410 according to the fourth embodiment of the present invention permits the CPU access only when the CPU access time T2 is shorter than the remaining period T3 until the subsequent DMA access starts. Thus, the data transfer control device 410 can execute access to the first storage device 107 by the CPU 101 without delaying subsequent DMA access.

  In the fourth embodiment, the first DMAC 402 performs continuous access to the same storage device, so that even if the CPU access time T2 is longer than the DMAC access time T1, the CPU 101 does not delay DMA transfer. Access to the first storage device 107 can be executed.

  Note that the same modification example as in the first to third embodiments may be applied to the data transfer control device 410 according to the fourth embodiment.

(Embodiment 5)
In the fifth embodiment of the present invention, an example will be described in which the data transfer control device 410 according to the above-described fourth embodiment is modified in the same manner as in the above-described second embodiment.

  FIG. 24 is a block diagram showing a configuration of a data transfer system 500 according to Embodiment 5 of the present invention. The data transfer control device 510 shown in FIG. 24 differs from the data transfer control device 410 according to the fourth embodiment in the configuration of the first IF 505. Specifically, the first register 151 further includes a register 256 that holds a delay allowable value T4. Further, the function of the access control unit 552 is different from that of the access control unit 452.

  Similar to the second embodiment, in the fifth embodiment, the CPU access is executed by allowing the DMA transfer delay to a certain value and delaying the DMA transfer in the case of contention.

  Access determination in the fifth embodiment will be described with reference to FIGS. 25 and 26. FIG. Note that whether access is possible is the same as in the second embodiment.

  As shown in FIG. 25, when the CPU access time T2 is shorter than the sum of the remaining period T3 and the allowable delay value T4, the CPU access is permitted. Further, as shown in FIG. 26, when the CPU access time T2 is longer than the sum of the remaining period T3 and the allowable delay value T4, the CPU access is not permitted.

  As described above, the data transfer control device 510 according to the fifth embodiment of the present invention keeps the DMA transfer delay within the set allowable delay value T4 even when the CPU access time T2 is longer than the DMAC access time T1. CPU access can be performed.

(Embodiment 6)
In the sixth embodiment of the present invention, an example in which the data transfer control device 610 includes the second DMAC 601 instead of the CPU 101 will be described.

  FIG. 27 is a block diagram showing a configuration of a data transfer system 600 according to the sixth embodiment of the present invention. A data transfer control device 610 shown in FIG. 27 includes a second DMAC bus 603 and a second DMAC 601 instead of the CPU 101 in contrast to the data transfer control device 110 described in the first embodiment. The second DMAC bus 603 corresponds to the second bus of the present invention, and can transfer data independently of the first DMAC bus 104. The second DMAC 601 accesses the first storage device 107 and the third storage device 611 via the second DMAC bus 603.

  In addition, it is assumed that the access to the first storage device 107 by the second DMAC 601 has a lower priority than the access to the first storage device 107 by the first DMAC 102.

  The operation of the data transfer control device 610 according to the sixth embodiment is such that the access request from the CPU 101 in the first embodiment is replaced with the access request from the second DMAC 601. This is the same as the first embodiment. That is, the same effect can be realized by replacing the CPU 101 in the first embodiment with the second DMAC 601 and adding a simple function.

  In each of the embodiments from the second embodiment to the fifth embodiment, the same effect can be realized by replacing the CPU 101 with the second DMAC 601.

  Although the example in which the data transfer control device 610 includes two DMACs has been described here, the data transfer control device 610 may include three or more DMACs. In this case, the same effect can be realized by adding a simple function. Further, the data transfer control device 610 may include an arbitrary number of CPUs and an arbitrary number of DMACs. In this case, the same effect can be realized by adding a simple function.

(Embodiment 7)
In the seventh embodiment of the present invention, a case where the second IF performs the same processing as the first IF will be described.

  FIG. 28 is a block diagram showing a configuration of a data transfer system 700 according to Embodiment 7 of the present invention. The data transfer control device 710 illustrated in FIG. 28 differs from the data transfer control device 110 illustrated in FIG. 1 in the functions of the counter 709 and the second IF 706. Further, the data transfer control device 710 includes a CPU bus 703 that can transfer data independently of the first DMAC bus 104. The CPU bus 703 corresponds to the second bus of the present invention.

  The CPU 101 accesses the first storage device 107 and the second storage device 108 via the CPU bus 703.

  The second IF 706 further accesses the second storage device 108 in accordance with an instruction from the CPU 101. The second IF 706 includes a fourth register 751 and an access control unit 752. The fourth register 751 includes a register 753 and a register 754. The register 753 holds a DMAC access time T1 (second DMAC access time) indicating the time required for accessing the second storage device 108 from the first DMAC 102. The register 754 holds a CPU access time T2 (second master access time) indicating the time required for the CPU 101 to access the second storage device 108.

  The counter 709 further counts a second elapsed time after the first IF 105 starts accessing the first storage device 107.

  When the access control unit 752 receives an access request from the CPU 101 to the second storage device 108 during the continuous transfer operation, and the second elapsed time is equal to or less than the second reference value, the access control unit 752 receives the second storage from the CPU 101. When access to the device 108 is permitted and the second elapsed time is greater than the second reference value, access from the CPU 101 to the second storage device 108 is prohibited.

  Specifically, the first IF 105 issues an access start signal at the start of access from the first DMAC 102 to the first storage device 107. The second IF 706 issues an access start signal at the start of access from the first DMAC 102 to the second storage device 108. When the counter 709 receives an access start signal from either the first IF 105 or the second IF 706, the counter 709 starts counting.

  That is, the function of the second IF 706 is the same as that in the case where the access destination is replaced from the first storage device 107 to the second storage device 108 in the first IF 105.

  The operation of the first IF 105 when the CPU 101 accesses the first storage device 107 during DMA transfer is when the counter 709 receives an access start signal from the second IF 706 and starts counting. This operation is the same as the operation of the first IF 105 in the first embodiment.

  The operation of the second IF 706 when the CPU 101 accesses the second storage device 108 during the DMA transfer is when the counter 709 receives the access start signal from the first IF 105 and starts counting. These operations are the same as when the first storage device 107 and the second storage device 108 are switched in the first IF 105, and are substantially the same as the operations of the first IF 105 of the first embodiment. is there.

(Embodiment 8)
In the eighth embodiment of the present invention, an example will be described in which the data transfer control device 710 according to the seventh embodiment is modified in the same manner as in the second embodiment.

  FIG. 29 is a block diagram showing a configuration of a data transfer system 800 according to Embodiment 8 of the present invention. The changes in the first IF 205 from the seventh embodiment with respect to the data transfer control device 810 according to the eighth embodiment are the same as the changes in the second embodiment with respect to the first embodiment. The change in the second IF 806 from the seventh embodiment is the same as the change in the second embodiment with respect to the first embodiment, except that the first storage device 107 and the second storage device 108 are switched. is there.

  Specifically, the fourth register 751 further includes a register 856 that holds a delay allowable value T4 (second delay allowable value). Further, the function of the access control unit 852 is different from that of the access control unit 752.

  The operation of the first IF 205 when the CPU 101 accesses the first storage device 107 during DMA transfer is the same as the operation of the first IF 205 in the second embodiment.

  The operation of the second IF 806 when the CPU 101 accesses the second storage device 108 during the DMA transfer is the same as that of the first IF 205 when the first storage device 107 and the second storage device 108 are exchanged. The operation is the same.

(Embodiment 9)
In the ninth embodiment of the present invention, an example will be described in which the data transfer control device 710 according to the seventh embodiment is modified in the same manner as in the third embodiment.

  FIG. 30 is a block diagram showing a configuration of a data transfer system 900 according to the ninth embodiment of the present invention.

  The first register 151 included in the first IF 305 is the same as the first register 151 of the third embodiment. The access control unit 352 is the same as the access control unit 352 of the third embodiment. In the third embodiment, the first IF 305 includes the second register 357. However, the data transfer control device 910 includes the second register 957 instead of the second register 357. .

  The fourth register 751 included in the second IF 906 is the same as the first register 151 when the first storage device 107 and the second storage device 108 are replaced. The access control unit 952 is the same as the access control unit 352 when the first storage device 107 and the second storage device 108 are replaced.

  Similar to the second register 357 of the third embodiment, the second register 957 holds the total delay allowable amount T5 in one continuous transfer operation. Here, the total allowable delay T5 held in the second register 957 is updated each time a delay occurs in the access control of the access control unit 352 and the access control unit 952.

  Further, the operation of the first IF 305 when the CPU 101 accesses the first storage device 107 during the DMA transfer is the same as the operation of the first IF 305 in the third embodiment.

  The operation of the second IF 906 when the CPU 101 accesses the second storage device 108 during the DMA transfer is the same as that of the first IF 305 when the first storage device 107 and the second storage device 108 are exchanged. The operation is the same.

(Embodiment 10)
In the tenth embodiment of the present invention, an example will be described in which the data transfer control device 710 according to the seventh embodiment is modified in the same manner as in the fourth embodiment.

  FIG. 31 is a block diagram showing a configuration of a data transfer system 1000 according to the tenth embodiment of the present invention.

  In the data transfer control device 1010 shown in FIG. 31, the first DMAC 402 is the same as the first DMAC 402 in the fourth embodiment.

  The first IF 405 is the same as the first IF 405 of the fourth embodiment. The operation of the first IF 405 when the CPU 101 accesses the first storage device 107 during DMA transfer is the same as the operation of the first IF 405 in the fourth embodiment.

  The fourth register 751 and the access control unit 1052 included in the second IF 1006 are the first register included in the first IF 405 when the first storage device 107 and the second storage device 108 are replaced. 151 and the access control unit 452. The operation of the second IF 1006 when the CPU 101 accesses the second storage device 108 during the DMA transfer is the first IF 405 when the first storage device 107 and the second storage device 108 are exchanged. It is the same as the operation of.

(Embodiment 11)
In the eleventh embodiment of the present invention, an example will be described in which the data transfer control device 710 according to the seventh embodiment is modified in the same manner as in the fifth embodiment.

  FIG. 32 is a block diagram showing a configuration of a data transfer system 1100 according to Embodiment 11 of the present invention.

  In the data transfer control device 1110 described in FIG. 32, the first DMAC 402 is the same as the first DMAC 402 in the fifth embodiment.

  The first IF 505 is the same as the first IF 505 in the fifth embodiment. The operation of the first IF 505 when the CPU 101 accesses the first storage device 107 during DMA transfer is the same as the operation of the first IF 505 in the fifth embodiment.

  The fourth register 751 and the access control unit 1152 included in the second IF 1106 are the first register included in the first IF 505 when the first storage device 107 and the second storage device 108 are replaced. 151 and the access control unit 552. The operation of the second IF 1106 when the CPU 101 accesses the second storage device 108 during the DMA transfer is the first IF 505 when the first storage device 107 and the second storage device 108 are exchanged. It is the same as the operation of.

(Embodiment 12)
In the twelfth embodiment of the present invention, an example will be described in which the data transfer control device 710 according to the seventh embodiment is modified in the same manner as the sixth embodiment.

  FIG. 33 is a block diagram showing a configuration of a data transfer system 1200 according to Embodiment 12 of the present invention. The data transfer control device 1210 shown in FIG. 33 includes a second DMAC 601 instead of the CPU 101, in contrast to the data transfer control device 710 described in the seventh embodiment. It is assumed that the access to each storage device by the second DMAC 601 has a lower priority than the access by the first DMAC 102.

  The operation of the twelfth embodiment is the same as that of the seventh embodiment except that the request from the CPU 101 in the seventh embodiment is replaced with the access request from the second DMAC 601. By replacing the CPU 101 in the seventh embodiment with the second DMAC 601, a similar effect can be realized by adding a simple function.

  In each of the embodiments from the eighth embodiment to the eleventh embodiment, the same effect can be realized even if the CPU 101 is replaced with the second DMAC 601.

  Although the data transfer control device according to the embodiment of the present invention has been described above, the present invention is not limited to this embodiment.

  Each processing unit included in the data transfer control device according to the above embodiment is typically realized as an LSI which is an integrated circuit. These may be individually made into one chip, or may be made into one chip so as to include a part or all of them.

  Typically, the data transfer control device is configured as a one-chip semiconductor integrated circuit. The circuit including the data transfer control device and the first storage device may be configured as a one-chip semiconductor integrated circuit.

  Further, the circuit integration is not limited to LSI, and may be realized by a dedicated circuit or a general-purpose processor. An FPGA (Field Programmable Gate Array) that can be programmed after manufacturing the LSI or a reconfigurable processor that can reconfigure the connection and setting of circuit cells inside the LSI may be used.

  Moreover, you may implement | achieve part or all of the function of the data transfer control apparatus based on embodiment of this invention, when processors, such as CPU, run a program.

  Furthermore, the present invention may be the above program or a non-transitory computer-readable recording medium on which the above program is recorded. Needless to say, the program can be distributed via a transmission medium such as the Internet.

  Moreover, you may combine at least one part among the functions of the data transfer control apparatus which concerns on the said Embodiments 1-12, and its modification.

  Moreover, all the numbers used above are illustrated for specifically explaining the present invention, and the present invention is not limited to the illustrated numbers.

  In addition, division of functional blocks in the block diagram is an example, and a plurality of functional blocks can be realized as one functional block, a single functional block can be divided into a plurality of functions, or some functions can be transferred to other functional blocks May be. In addition, functions of a plurality of functional blocks having similar functions may be processed in parallel or time-division by a single hardware or software.

  In addition, the order in which the steps included in the processing procedure shown in the flowchart are executed is for illustration in order to specifically explain the present invention, and may be in an order other than the above. Also, some of the above steps may be executed simultaneously (in parallel) with other steps.

  Further, various modifications in which the present embodiment is modified within the scope conceivable by those skilled in the art are also included in the present invention without departing from the gist of the present invention.

  Since the data transfer control device according to the present invention can perform processing including access to the storage devices in parallel while satisfying the transfer request in the data transfer between the storage devices, the external storage device or the built-in storage device It is effective for an information processing apparatus having a plurality of storage devices.

100, 200, 300, 400, 500, 600, 700, 800, 900, 1000, 1100, 1200 Data transfer system 101 CPU
102, 402 First DMAC
104 First DMAC bus 105, 205, 305, 405, 505 First IF
106, 406, 706, 806, 906, 1006, 1106 Second IF
107 First storage device 108 Second storage device 109, 709 Counter 110, 210, 310, 410, 510, 610, 710, 810, 910, 1010, 1110, 1210 Data transfer control device 151 First register 152, 252, 352, 452, 552, 752, 852, 952, 1052, 1152 Access control unit 153, 154, 155, 256, 358, 753, 754, 856 Register 357, 957 Second register 421 Buffer 422 Third register 423 Number of consecutive accesses 601 Second DMAC
603 Second DMAC bus 611 Third storage device 703 CPU bus 751 Fourth register T1, T1b DMAC access time T2 CPU access time T3 Remaining period T4 Delay tolerance T5 Overall delay tolerance T6 Delay time

Claims (20)

A data transfer control device for transferring data from one of a first storage device and a second storage device to the other,
A master that accesses the first storage device;
A first bus independent of the master;
A continuous transfer operation for repeatedly and continuously performing a data transfer operation of reading data from one of the first storage device and the second storage device and writing the read data to the other via the first bus. A first DMAC (Direct Memory Access Controller) to perform;
A first interface unit that accesses the first storage device in accordance with a request from the master and the first DMAC;
A second interface unit that accesses the second storage device in accordance with a request from the first DMAC;
A counter that counts a first elapsed time since the second interface unit started accessing the second storage device;
The first interface unit includes:
In the case of receiving an access request from the master to the first storage device during the continuous transfer operation, (1) when the first elapsed time is equal to or less than a first reference value, the master (2) a first access that prohibits access from the master to the first storage device when the first elapsed time is greater than the first reference value. A data transfer control device comprising a control unit. The first interface unit further includes:
A first DMAC access time required for one access from the first DMAC to the second storage device, and a first time required for one access from the master to the first storage device. A first register for holding a master access time;
The data transfer control device according to claim 1, wherein the first access control unit calculates the first reference value by subtracting the first master access time from the first DMAC access time. The first register further holds a first delay allowable value of one data transfer operation,
The first access control unit subtracts the first master access time from the first DMAC access time and then adds the first delay allowable value to obtain the first reference value. The data transfer control device according to claim 2. The first interface unit further includes:
A second register for holding an overall delay tolerance in one continuous transfer operation;
The first access control unit, when an access request from the master to the first storage device occurs,
Subtracting the first master access time from the first DMAC access time, and then adding a first delay tolerance that is less than or equal to the overall delay tolerance to calculate the first reference value;
When the first elapsed time is less than or equal to the first reference value, the master allows access from the master to the first storage device, and sets the total delay allowable amount held in the second register. Reduce,
When the total allowable delay amount held in the second register is equal to or less than a predetermined value, the first master access from the first DMAC access time is used as the first reference value. The data transfer control device according to claim 2, wherein a value obtained by subtracting time is used. The data transfer control device according to claim 4, wherein the first delay tolerance is the total delay tolerance. The first access control unit includes:
If the overall delay allowance is greater than or equal to a predetermined threshold, the first value is used as the delay allowance,
5. The data transfer control device according to claim 4, wherein when the total delay allowable amount is less than the threshold value, a second value smaller than the first value is used as the delay allowable value. The first access control unit includes:
When the first elapsed time is equal to or less than the first reference value, the access from the master to the first storage device is permitted, and the first elapsed time and the first master access time are The first delay time is calculated by adding and subtracting the first DMAC access time from the added value, and the first delay is calculated from the total delay allowable amount held in the second register. The data transfer control device according to claim 4, wherein the total delay allowable amount held in the second register is updated by subtracting time. The second register holds a partial delay allowance corresponding to each of a plurality of partial sections obtained by dividing one continuous transfer operation,
The first access control unit, when an access request from the master to the first storage device occurs,
Subtracting the first master access time from the first DMAC access time and then adding the partial delay amount of the corresponding partial section to calculate the first reference value,
When the first elapsed time is less than or equal to the first reference value, the access from the master to the first storage device is permitted and the corresponding partial section held in the second register Reduce the partial delay tolerance,
When the partial delay amount of the corresponding section held in the second register is equal to or less than a predetermined value, the first reference value is used as the first reference value from the first DMAC access time. The data transfer control device according to claim 4, wherein a value obtained by subtracting the master access time is used. The first DMAC is:
A third register that holds the number of consecutive accesses indicating the number of times of continuous access to the first storage device or the second storage device in one data transfer operation;
A buffer for holding data read from the first storage device or the second storage device,
The first DMAC continuously reads data from the one of the first storage device and the second storage device for the number of times of continuous access and continuously reads the data in one data transfer operation. The data stored in the buffer, and the data stored in the buffer is written to the other of the first storage device and the second storage device by the write operation for the number of times of continuous access,
The counter counts, as the first elapsed time, a time from when the first access is started among accesses for the number of continuous accesses to the second storage device by the second interface unit. Item 4. The data transfer control device according to Item 1. The first interface unit further includes:
A first DMAC access time required for one access from the first DMAC to the second storage device, and a first time required for one access from the master to the first storage device. A first register for holding a master access time;
The first access control unit calculates the first reference value by subtracting the first master access time from a product of the first DMAC access time and the number of consecutive accesses. The data transfer control device according to 1. The first register further holds a first delay allowable value of one data transfer operation,
The first access control unit subtracts the first master access time from the product of the first DMAC access time and the number of consecutive accesses, and then adds the first delay allowable value. The data transfer control device according to claim 10, wherein the first reference value is calculated. The data transfer control device further includes:
A second bus independent of the first bus;
The data transfer control device according to any one of claims 1 to 11, wherein the master is a second DMAC that accesses the first storage device via the second bus. The master accesses the first storage device and the second storage device via a second bus independent of the first bus;
The second interface unit further accesses the second storage device in accordance with an instruction from the master,
The counter further counts a second elapsed time since the first interface unit started accessing the first storage device,
When the second interface unit receives an access request from the master to the second storage device during the continuous transfer operation,
If the second elapsed time is less than or equal to a second reference value, permit access from the master to the second storage device;
The data transfer control device according to claim 1, further comprising: a second access control unit that prohibits access from the master to the second storage device when the second elapsed time is greater than the second reference value. The first interface unit further includes:
A first DMAC access time required for one access from the first DMAC to the second storage device, and a first time required for one access from the master to the first storage device. A first register for holding a master access time;
The first access control unit calculates the first reference value by subtracting the first master access time from the first DMAC access time,
The second interface unit further includes:
A second DMAC access time required for one access from the first DMAC to the first storage device, and a second DMAC access time required for one access from the master to the second storage device. A fourth register for holding a master access time;
The data transfer control device according to claim 9, wherein the second access control unit calculates the second reference value by subtracting the second master access time from the second DMAC access time. The first register further holds a first delay allowable value of one data transfer operation,
The first access control unit subtracts the first master access time from the first DMAC access time and then adds the first delay allowable value to obtain the first reference value. Calculate
The fourth register further holds a second delay allowable value for one data transfer operation,
The second access control unit subtracts the second master access time from the second DMAC access time and then adds the second delay allowable value to obtain the second reference value. The data transfer control device according to claim 14 to calculate. The data transfer control device further includes:
A second register for holding an overall delay tolerance in one continuous transfer operation;
The first access control unit, when an access request from the master to the first storage device occurs,
Subtracting the first master access time from the first DMAC access time and then adding a first delay tolerance less than or equal to the overall delay tolerance to calculate the first reference value;
When the first elapsed time is less than or equal to the first reference value, the access from the master to the first storage device is permitted, and the overall delay allowable amount is reduced,
When the total delay amount held in the second register is equal to or less than a predetermined value, the first master access time is calculated from the first DMAC access time as the first reference value. Use the subtracted value,
The second access control unit, when an access request from the master to the second storage device occurs,
Subtracting the second master access time from the second DMAC access time, and then adding a second delay allowable value equal to or less than the total delay allowable amount to calculate the second reference value;
When the second elapsed time is less than or equal to the second reference value, the access from the master to the second storage device is permitted, and the overall delay allowable amount is reduced,
When the total delay amount held in the second register is equal to or less than a predetermined value, the second master access time is calculated from the second DMAC access time as the second reference value. The data transfer control device according to claim 14, wherein a subtracted value is used. The data transfer control device according to any one of claims 1 to 11 and 13 to 16, wherein the master is a CPU (Central Processing Unit). A data transfer control device according to any one of claims 1 to 17,
The first storage device;
A data transfer system including the second storage device. An integrated circuit for transferring data from one of a first storage device and a second storage device to the other,
A master that accesses the first storage device;
A first bus independent of the master;
A continuous transfer operation for repeatedly and continuously performing a data transfer operation of reading data from one of the first storage device and the second storage device and writing the read data to the other via the first bus. A first DMAC (Direct Memory Access Controller) to perform;
A first interface unit that accesses the first storage device in accordance with a request from the master and the first DMAC;
A second interface unit that accesses the second storage device in accordance with a request from the first DMAC;
A counter that counts a first elapsed time since the second interface unit started accessing the second storage device;
The first interface unit includes:
In the case of receiving an access request from the master to the first storage device during the continuous transfer operation, (1) when the first elapsed time is equal to or less than a first reference value, the master (2) a first access that prohibits access from the master to the first storage device when the first elapsed time is greater than the first reference value. An integrated circuit including a control unit. A data transfer method in a data transfer control device for transferring data from one of a first storage device and a second storage device to the other,
The data transfer control device includes:
A master that accesses the first storage device;
A first bus independent of the master;
A continuous transfer operation for repeatedly and continuously performing a data transfer operation of reading data from one of the first storage device and the second storage device and writing the read data to the other via the first bus. A first DMAC (Direct Memory Access Controller) to perform,
The data transfer method includes:
Accessing the first storage device in accordance with requests from the master and the first DMAC;
Accessing the second storage device in accordance with a request from the first DMAC;
Counting a first elapsed time since starting to access the second storage device;
In the case of receiving an access request from the master to the first storage device during the continuous transfer operation, (1) when the first elapsed time is equal to or less than a first reference value, the master And (2) prohibiting access from the master to the first storage device when the first elapsed time is greater than the first reference value. Data transfer method.

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