JP2012212894A - Plasma processing method and plasma processing device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a plasma processing device capable of highly accurately etching a film structure having a step, or a dry etching method.SOLUTION: A plasma processing device comprises: a vacuum container 107; a lower electrode 113 which is disposed in a processing chamber inside the vacuum container and in which a wafer 112 to be etched is placed on the upper surface; bias application devices 118 and 120 which supply high-frequency power for forming a bias potential to the lower electrode 113; gas introduction means 111 for introducing a reactive gas into the processing chamber; electric field supply means 101 to 103 for supplying electric field for generating plasma into the processing chamber; and an adjustment device 127 which adjusts ion energy distribution in the plasma which enters the wafer 112 with the high-frequency power.

Description

  The present invention relates to a semiconductor manufacturing method, and in particular, has a metal gate / high-k structure, a step structure, and a three-dimensional structure, requires high selectivity for a base film and a mask layer, and requires a vertical shape. The present invention relates to a plasma processing method and apparatus for forming a gate electrode.

MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor) devices used in digital home appliances, personal computers, mobile phones and the like are continuously required to have high integration, high speed, and high functionality. In response to this demand, a new material and a gate electrode with a new structure are being studied along with miniaturization of a conventional poly-Si / SiO ₂ structure gate electrode.

  The principle of dry etching processing used as a method for forming a gate electrode of a planar type MOSFET or FIN-FET having such a metal gate / high-k structure is that a reactive gas is converted into plasma by electromagnetic waves, and the generated ions and medium Ion-assisted reaction using a reactive radical. Therefore, the plasma processing apparatus embodying this method controls the plasma generation mechanism, the reactive gas introduction mechanism, the pressure control mechanism, the lower electrode mechanism for installing the Si wafer, the Si wafer transport mechanism, the operation timing thereof, and the like. It consists of a mechanism to do. Among these, the lower electrode mechanism includes an electrostatic adsorption mechanism for fixing the Si wafer, a temperature control mechanism for the Si wafer, and a bias application mechanism.

  As a method for controlling ion energy distribution (IEDF) using a plasma processing apparatus having the above-described mechanism, it is known that the waveform and frequency of an applied bias also have an effect. For example, the selectivity of etching with respect to Si during the insulating film etching can be improved by applying a pulsed bias and applying a two-frequency bias having a low frequency of 25 kHz or less and a high frequency of 2 MHz or more. It has been proposed (see, for example, Patent Document 1). Further, it has been reported that the frequency output by the bias mechanism has IEDF depending on the time of passing through the plasma sheath (for example, see Non-Patent Document 1).

  On the other hand, with regard to the plasma state detection monitor, a technique has been proposed in which high-frequency voltage, current, and phase are monitored to detect abnormalities such as insulation deterioration of the insulating film on the inner wall of the chamber and the lower electrode (for example, Patent Documents). 2).

JP 2002-141341 A JP 2007-250755 A

Journal of Vacuum Science and Technology A Volume 20 p.1759

  When a conventional plasma processing apparatus is used to form a metal gate / high-k gate electrode having an STI step 310 and having a multilayer film structure shown in FIG. As shown in FIG. 3B, it has been difficult to prevent the under-extraction 312 of the high-k gate insulating film and to prevent the occurrence of the trailing shape 314 to obtain a vertical bottom shape. Similar problems such as base selectivity and vertical workability, and the occurrence of a density difference due to the density of wiring provided on the substrate are even more severe in the gate etching of FIN-FETs. This is because the shape difference in the vertical direction, such as the under-filling at the upper part of the step of FIN of about 50 nm, the side etching at the upper part of the gate length part, and the bottom of the lower part, causes variation in characteristics.

  An object of the present invention is to perform a dry etching process on a gate electrode material having a STI structure or a three-dimensional gate structure (FIN-FET, etc.) and composed of a plurality of layers including a metal material and a high-k material. An object of the present invention is to provide a plasma processing method or a plasma processing apparatus that has high selectivity to the ground film and that can realize vertical processing stably.

  The purpose is to supply a vacuum vessel, a lower electrode arranged in the processing chamber of the vacuum vessel, and a wafer to be etched on the upper surface thereof, and a plurality of frequencies of bias power for forming a bias potential on the lower electrode. A bias applying mechanism, a gas supply mechanism for introducing a reactive gas into the process chamber, a mechanism for adjusting a gas pressure in the process chamber, and an electromagnetic wave supply mechanism for generating plasma in the process chamber In the processing apparatus, this is achieved by a plasma processing apparatus including an IEDF control mechanism for independently changing the energy of ions incident on the wafer and IEDF, and a mechanism for detecting a plasma state with respect to a bias frequency.

  At this time, the IEDF control mechanism is composed of a power supply unit that oscillates a plurality of frequencies and each matching unit, and the mechanism that detects the plasma state detects the plasma impedance for each frequency from the bias applying mechanism side. This is achieved by a plasma processing apparatus equipped with a mechanism.

  Further, the above object is to place a wafer having a step structure on a surface of a lower electrode in a processing chamber inside a vacuum chamber, which is composed of a plurality of layers including a metal material on a high-k material. One or more frequencies for forming a bias potential on the wafer, a step of introducing an etching gas into the processing chamber, a step of adjusting a processing pressure, a step of generating plasma in the processing chamber, In the plasma processing method for etching the film structure by varying the output of the bias power, detecting the time change of the plasma impedance from the bias applying mechanism side, and the detection result And a step of independently controlling the ion energy incident on the wafer and the distribution thereof after the end point is determined. Is achieved by the plasma processing method characterized in that it comprises a.

  In addition, the step of independently controlling the ion energy incident on the wafer and its distribution changes the output of the bias power of multiple frequencies and their mixing ratio, and also detects the time change of the impedance of the plasma. Including a step of separating the impedance of the wall state component and the component immediately above the wafer after the step of performing a step of comparing the separated data with a database or a variation model, and a step of cleaning the wall according to the comparison result, or This can be realized by a plasma processing method having a step of changing the next wafer processing condition.

Sectional drawing of the plasma processing apparatus which concerns on the Example of this invention. The graph which shows IEDF in 400 kHz, 13.56 MHz, and 2 frequency mixing bias. Sectional drawing of planar type CMOS-FET which has a multilayer structure containing a level | step difference, a metal material, and a high-k material. (A) Before etching treatment, (b) Etching treatment by a conventional method, (c) Etching treatment using the present invention. The figure which shows the timing comparison by the figure which shows the time sequence of the electrical end point determination and 2 frequency bias which were used when processing the Si wafer of the cross-sectional structure of FIG. 3, and the conventional end point determination method. The flowchart which determines an end point by this invention. Immitance chart directly above the wafer for end point determination. (A) the present invention, (b) one frequency. FIG. 3 is a flowchart for stabilization and fluctuation correction in the present invention. Poly-Si rate distribution and poly-Si rate and SiO ₂ rate, shows a mixing ratio dependent selectivity. (A) When the mixing ratio of low frequency and high frequency is 0%, (b) When the mixing ratio of low frequency and high frequency is 20%, (c) When the mixing ratio of low frequency and high frequency is 100%, (d) poly-Si rate SiO ₂ rate, dependency of selectivity on mixing ratio. The figure which shows the mechanism which implement | achieves the flowchart of FIG. The schematic diagram of the cross-sectional shape of a hard mask sample. (A) Before etching, (b) After hard mask etching with high frequency bias of conventional method, (c) After gate etching with high frequency bias of conventional method, (d) Gate etching with multiple high frequency biases of the present invention After that. The figure which shows the time sequence of EPD and 2 frequency bias used when processing the Si wafer of the cross-sectional structure of Fig.10 (a). The bird's-eye view and sectional drawing of the sample of FIN-FET structure. (A) Before gate etch, (b) After gate etch processing using the present invention, (c) A sample of a FIN-FET structure processed using the present invention at line AA ′ in FIG. Sectional drawing. The figure which shows the timing sequence used when processing FIN-FET. (A) EPD waveform, (b) lower electrode temperature, (c) additive gas flow rate, (d) gas pressure, (e) incident UHF power, (f) IEDF control mechanism distribution ratio. The schematic diagram of the cross-sectional shape of a sample. (A) Before etching, (b) After etching the sample to the hard mask using the present invention, (c) Cross-sectional shape of the deep hole after etching the sample using the conventional technique, (d) The present invention The cross-sectional shape of the deep hole after etching the sample by using. The schematic diagram which shows the outline of a structure of the control apparatus of the plasma processing apparatus which concerns on the Example shown in FIG.

  Embodiments of the present invention will be described below with reference to the drawings. First, an example of the film structure targeted by the embodiment of the present invention will be described with reference to FIG. FIG. 3A is a cross-sectional view of a sample of a planar type CMOS having a metal gate / high-k structure before etching, FIG. 3B is a cross-sectional view after etching by a conventional method, and FIG. The sectional view after the etching process in the present invention is shown.

3A, the wafer includes an STI 308 formed on the Si substrate 309, an HfSiON (high-k) insulating film 307 formed on the Si substrate 309 and the STI 308, and a High-k insulating film 307. A metal gate electrode layer 306 formed on the gate cap layer 305, a gate cap layer 305 sequentially stacked thereon, a lower layer mask 304, an intermediate layer mask 303, a BARC (antireflection film) layer 302, and an upper layer thereof. And a resist 301 formed on the substrate. As shown in this figure, a planar type stacked metal / high-k gate electrode having an STI step 310 due to the formation of STI 308 is applied to a conventional gate etching apparatus having a single bias frequency of 400 kHz, and Cl ₂ / HBr gas is supplied. When etching is performed, as shown in FIG. 3B, the underfilling 312 of the HfSiON (high-k) film is generated in the gate electrode lower portion 311 of the active portion that becomes the MOS type FET. In addition, the remaining 313 of the gate electrode material of the STI stepped portion is formed in the corner portion of the STI stepped portion 310 so as to spread out at the bottom. On the other hand, under the gate of the field portion, which is the wiring portion, there is a bottoming shape 314 in which the shape is widened but the remaining 315 of the gate electrode material on the STI is generated on the STI surface.

  That is, it has been found that in the etching process of the laminated metal / high-k gate electrode, it is difficult to simultaneously improve the base high-k selectivity near the gate electrode and prevent the occurrence of the trailing shape.

  The reason why it is difficult to improve the substrate selectivity and prevent the occurrence of the trailing shape with the 400 kHz bias shown in FIG. 3B is that the ion energy distribution (IEDF) spreads around the average energy. This is because the determination of the etching end point of the thin film and optically opaque material is delayed.

First, FIG. 2 shows an example of such different ion energy distributions with the same time-average ion energy. FIG. 2 shows an RF of Vpp = 200 V on a wafer at a low frequency of 400 kHz and a high frequency of 13.56 MHz under a plasma having an electron temperature of 3 eV, a mass number of incident ions of 79.9, and a plasma density of 1 × 10 ¹⁰ cm ^−3. It is a schematic diagram which shows the example of several IEDF at the time of applying. In the 400 kHz IEDF 203, the distribution width 204 is about 200 eV with respect to the time average of 100 eV, and it has two peaks around 0V and 200V. On the other hand, the high-frequency 13.56 MHz IEDF 201 has a narrow distribution width 202 of about 50 eV. It can be seen that IEDF 205 in which two frequencies of low frequency and high frequency are mixed by 100 Vpp has an intermediate distribution. This is because the period of sheath voltage change for accelerating ions becomes faster as the high-frequency bias is applied, the sheath oscillation time is shorter than the time for ions to pass through the sheath, and the ions cannot follow the sheath fluctuation and are accelerated by the average value of the electric field. This is because

  In this way, when etching is performed at a frequency of 400 kHz, high energy ions that are about twice the time average ion energy deteriorate the selectivity, and at the same time, low energy ions of about 0 eV cause the trailing shape. It seems that it was difficult to balance the issues. Therefore, in order to achieve both selectivity and tail shape, it is preferable to narrow the ion energy distribution at a high frequency. On the other hand, a distribution having a large spread at low frequencies may be used, for example, when the altered layer on the surface is physically sputtered with high energy ions or when an insulating film is etched that requires high energy ions. In addition, by using a low frequency, it is possible to utilize high energy ions having a distribution that is broader than the average ion energy without affecting the dissociation and distribution of the plasma. Thus, when etching a multilayer film consistently, it is necessary to be able to control IEDF.

  On the other hand, the delay of the end point determination, which is another cause of the shape abnormality in FIG. 3B, is that the etching rate needs to be reduced in order to cope with the thinning of the gate electrode (about 10 to 30 nm). to cause. That is, in the conventional method using emission spectroscopy, when the etching rate is low, the composition ratio of the reaction product in the plasma is small, so the emission intensity in the plasma is weak and the change is small.

  In the case of determining the end point by the conventional film thickness interference method, it is difficult to find periodicity because the thickness of the gate electrode which is the material to be etched is smaller than the quarter wavelength of the light source wavelength (200 to 800 nm) to be detected. In many cases, the surface roughness of the gate electrode material is present, and the underlying high-k film is thin and inhomogeneous of about 2 nm, so the intensity of the interference waveform is reduced and the error in film thickness conversion is greatly reproduced. The nature is bad. Furthermore, since the intensity of the interference waveform depends on the area to be etched within the viewing angle of the interference light, it is further difficult to determine the end point with a patterned wafer.

  On the other hand, the method for detecting the electrical characteristics of plasma used in the present invention is sensitive to changes in the sheath part where the density of reaction products directly on the wafer is high, so even if the initial film thickness is thin, it can be detected regardless of roughness. It is. Furthermore, regarding the stable operation of the apparatus, it is possible to detect the end point by separating the change in the plasma wall state and the change directly above the wafer by detecting the impedance immediately above the wafer at a plurality of frequencies of low frequency and high frequency. .

In general, when an equivalent circuit is displayed for the bias applied in the plasma, not only the impedance (Z ₁ y, y = H, L) of the sheath immediately above the high frequency angular velocity ω _H and low frequency angular velocity ω _L wafer, but also on the chamber wall surface. The electric circuit composed of the impedance (Z ₂ y, y = H, L) of the formed sheath is expressed by the following equations (1) and (2). The voltage and current when high frequency high frequency bias power is supplied are V _H and I _H , respectively, and the voltage and current when low frequency high frequency bias power is supplied are V _L and I _L , respectively. The resistance component, reactance component, inductance component, and capacitance component of the component directly above the wafer are R ₁ , X ₁ , L ₁ , and C ₁ , respectively, and the resistance component, reactance component, inductance component, and capacitance component of the wall surface state component of the processing chamber are respectively Let R ₂ , X ₂ , L ₂ , C ₂ . That is, voltage (V1y, y = H, L), current (I1y, y = H, L), and phase monitor values at different frequencies are detected, and the high frequency side (1) equation, the low frequency side (2) By solving the simultaneous equations of the equation (3), which is the relationship between the impedance and the frequency, for the real part and the imaginary part, it is possible to separate the impedance information directly above the wafer and the chamber wall surface.

  The present invention has been conceived based on the knowledge that a plurality of types of impedances can be separated and detected by a plurality of frequencies, and in the embodiment described below, a multi-layered planar CMOSFET having a step structure is provided. Ion energy distribution (IEDF) with multiple frequencies, such as various shape abnormalities (dense shape difference, notching, side etching, damage to the underlying film, bottom, missing base, tapered shape, etc.) that occur when etching the structure gate This is solved by using a plasma processing apparatus having a bias applying mechanism having a control mechanism and a plurality of plasma impedance detectors.

[Example 1]
First, an embodiment of an apparatus embodying the present invention will be described. FIG. 1 is a longitudinal sectional view schematically showing the configuration of a plasma processing apparatus according to an embodiment of the present invention. In the plasma processing apparatus shown in this figure, a plasma is formed inside a processing chamber disposed inside a vacuum vessel, and this plasma is used to form a substrate that is a material to be etched such as a semiconductor wafer disposed in the processing chamber. This is a plasma processing apparatus for processing the sample. The plasma generation mechanism in this plasma processing apparatus includes a 450 MHz UHF power source 101, a high-speed response UHF matching unit 102 with an impedance detector, an antenna 103, and an electromagnet 104.

  An antenna 103 that emits UHF waves into an etching chamber 107 that constitutes a vacuum vessel is installed on the atmosphere side from a quartz plate 105 that maintains a vacuum. The etching gas is introduced into the etching chamber 107 from the shower plate 106 after mixing the etching gas through the fast response reactive gas introduction mechanism 111 that can change the gas flow rate composed of the mass flow controller and the stop valve in a few seconds. . The gas pressure during the etching can be controlled by a high-speed response pressure control mechanism 110 directly above the high vacuum pump 109.

  The lower electrode 113 on which the Si wafer 112 that is the material to be etched is provided includes a substantially ring-shaped susceptor 114 that is disposed on the upper surface of the lower electrode 113 so as to cover the outer peripheral side and the side wall of the mounting surface on which the Si wafer 112 is placed. Two or more concentric circles are formed to be thermally different regions, and the temperature control mechanism 115 can be used to control the temperature of the lower electrode to a predetermined value in each region. During the etching process, the wafer 112 is electrostatically adsorbed using a DC voltage of −2000 V to +2000 V generated by the DC power supply 116, and the gap between the Si wafer 112 and the lower electrode 113 is filled with He to perform pressure control. Yes. By using such an electrostatic adsorption technique, the temperature of the Si wafer 112 during etching is adjusted.

  The lower electrode 113 is connected to a bias application mechanism 117 for drawing ions from the plasma into the wafer 112 and controlling the ion energy distribution. The bias application mechanism 117 includes an IEDF control mechanism 127 that controls the incident ion energy distribution and a plasma state monitor (hereinafter also referred to as PIM) 126. In this embodiment, the IEDF control mechanism 127 includes a power source that transmits and supplies power of a plurality of frequencies, and includes a low frequency bias power source unit 120, a low frequency matching unit 121, and a high frequency bias power source unit. 118 and a high frequency matching unit 119 are used. 400 kHz is used for the frequency of the low-frequency bias power supply unit 120 and 13.56 MHz is used for the frequency of the high-frequency bias power supply unit 118, and each can output at a minimum power of about 1 W to a maximum power of about 150 W (continuous sine wave) / 12 inch diameter, A device having a time modulation (hereinafter, sometimes referred to as TM) function that performs on-off modulation in a range of 500 Hz to 3 kHz was used (maximum power during modulation is about 500 W).

  At this time, the high-frequency matching unit 119 and the low-frequency matching unit 121 need to have such a sensitivity that the matching can be performed from an output of 0.5% or more of the maximum output and an output of 1 W at the lowest output. On the other hand, by installing the plasma state detector 126 between the IEDF control mechanism 127 and the lower electrode 113 as the plasma state detector 126, the time change of voltage, current, and phase with respect to each frequency, that is, electron density, electron temperature. Changes in impedance, including changes over time, are detected.

  In the plasma processing apparatus according to the present embodiment, the light emitting / receiving unit 122 that receives the plasma emission during the etching process is disposed, for example, in the lower part of the container constituting the etching chamber 107. The output from the light emitting / receiving unit 122 is transmitted to the emission spectroscope 123.

  In addition, a film thickness interference monitor 124 that detects the film thickness of the surface of the Si wafer by receiving interference light from plasma or an external light source is provided facing the Si wafer 112 on the lower electrode 113. Further, a heater 108 is disposed on the outer peripheral surface of the side wall of the etching chamber 107 so as to cover it and to adjust the temperature of the side wall to an appropriate value before and after the plasma processing.

  Furthermore, the plasma processing apparatus of the present embodiment receives the output from the sensor that controls the output value and timing of each part based on a preset value, or detects the operation of each part arranged in each part. A control device 125 is provided that performs calculations using these received results, or reads out data from the storage device and sends commands for the operations of the respective units. The control device 125 includes the UHF power source 101, a high-speed response UHF matching unit 102 with an impedance detector, a heater 108, a vacuum pump 109, a high-speed response pressure control mechanism 110, a high-speed reactive gas introduction mechanism 111, a temperature control mechanism 115, The IEDF control mechanism 127 and the high-frequency bias power supply unit 118 and the like disposed inside the IEDF control mechanism 127 and the emission spectrometer 123, the film thickness interference monitor 124, and the plasma state detector 126 are configured to be communicable. An operation signal is transmitted to each of these parts. For example, an output from the plasma state detector 126, the emission spectroscope 123, or the film thickness interference monitor 124 is received to detect the processing state such as the film thickness of the Si wafer and the end point of the processing, and according to the detection result. IEDF control mechanism 127, UHF power source 101, high-speed response UHF matching unit 102 with impedance detector, heater 108, vacuum pump 109, high-speed response pressure control mechanism 110, high-speed response reactive gas introduction mechanism 111, and temperature control mechanism 115 Calculate and transmit signals to adjust operation. The high-speed response UHF matching unit 102 with an impedance detector functions as a matching device that records a plurality of matching points with respect to the UHF power supply 101 and selects and matches the matching paths.

  Using such a plasma processing apparatus of FIG. 1, the STI step 310 and the ArF resist 301 / BARC 302 / intermediate mask 303 / lower mask 304 / gate Cap layer 305 / metal gate electrode as shown in FIG. The time chart of FIG. 4 shows an example of etching a thin metal gate electrode layer 306 (TiN) portion of 10 to 30 nm of the planar type MOS having the layer 306 / HfSiON insulating film 307 structure using the present invention. This will be described below.

  After etching from the BARC 302 to the gate Cap layer 305 in the same chamber, a break-through (hereinafter referred to as BT) step of TiN (metal gate electrode layer) 306 is performed. The purpose of this BT step is to remove a TiO surface layer that inhibits TiN etching, which is formed by combining with oxygen during BARC 302 overetching (hereinafter sometimes referred to as OE). As conditions for the BT step, Ar 100 to 200 cc, pressure 1 Pa, UHF applied power 500 W, 400 kHz, and bias low frequency applied power 50 to 100 W were used. By using a 400 kHz low frequency bias, high energy necessary for removing TiO was easily obtained.

  FIG. 4A shows end point determination (EPD) based on a change in impedance over time as a result of detecting voltage, current, and phase in a plasma impedance monitor for 400 kHz in the plasma state detector 126. As the TiN BT step progresses, TiO on the surface is removed and Ti, N, etc. are released in the vicinity of the plasma sheath, resulting in changes in electrical characteristics such as electron density and sheath thickness. Thus, at time 401 when the impedance increases, the process shifts to main etching (hereinafter sometimes referred to as ME).

In the ME step of TiN 306, HBr, NF ₃ , CF ₄ , and SF ₆ are added based on Cl ₂ or HCl, and the pressure is 0.2 Pa and the UHF applied power is 500 W. For the bias of the TiN ME step, a low frequency bias of 400 KHz and a high frequency bias of 13.56 MHz were mixed by 50% (FIG. 4B, dual frequency mixing ratio 403 at the time of ME of TiN). The reason is that it is formed on the wall surface of the chamber in order to obtain the anisotropy due to the high energy ions, which is the advantage of the low frequency bias application, while suppressing the tail of the low energy ions with the narrow distribution width that is the advantage of the high frequency bias application. This is because the impedance of the sheath formed immediately above the wafer and the impedance of the sheath formed immediately above the wafer are separated so that the end point can be determined with high accuracy using the impedance directly above the wafer. The ME step end point is determined by switching to the TiN OE1 step at time 402 when the plasma impedance detected by the plasma state detector 126 starts to change, and processing the output 404 of the IEDF control mechanism 127 with 100% high-frequency bias power. did. This is because in the next OE1 step, it is necessary to prepare different etching amounts due to differences in STI step, film thickness, circuit pattern density difference, etched material difference, and wafer in-plane difference. This is because, in the pattern, it is necessary to etch a portion that does not reach the base while maintaining selectivity with the base high-k.

  At this time, by using the signal of the plasma state detector 126, it is 1 to 1 from the end point 406 obtained by the method of detecting the time change of the emission peak of the conventional reaction product or etchant shown in FIG. The end point of the ME can be acquired as early as about 5 seconds, and damage to the underlying high-k film due to ions can be reduced.

After that, the OE2 step was started at the time when the signal of the plasma state detector 126 was stabilized. The OE2 step plasma conditions are HBr / O ₂ , Ar dilution, total flow rate 200 to 400 cc, pressure 3 to 10 Pa, and UHF high frequency power supply 101 output 500 to 700 W. A mixed bias power having a high frequency bias power of 80% and a low frequency bias power of 20% was used (FIG. 4 (c), two-frequency mixing ratio 405 at the time of OE2 of TiN). The purpose of this is to reduce electronic shading damage while reducing the background selectivity and the bottom shape of the stepped portion and non-opening portion of the STI. That is, by slightly mixing the ratio of high ion energy that is nearly twice the average ion energy, it is possible to maintain the reduction and selectivity of the trailing shape and suppress physical damage due to ion bombardment. That is, the recession of the source and drain can be reduced. Then, it is possible to avoid notching due to electron shading by neutralizing electrons charged on the mask with low energy ions.

  As described above, by applying the present invention, in the metal gate electrode processing as shown in FIG.

In addition to the gate electrode structure of this embodiment, other high-k materials include insulating materials such as ZrO ₂ , Y ₂ O ₃ , La ₂ O ₃ , LaAlOx, LaSiOx, Al ₂ O ₃ , HfO ₂ , and HfAlO (N). The same effect can be obtained when the material is a metal material such as TaN, TaSiN, TaC, Ru, HfN, and MoN in addition to TiN.

  In the above embodiment, the IEDF control mechanism 127 uses a mechanism including power supply units 118 and 120 that oscillate two different frequencies and matching units 119 and 121. This method has an advantage that the structure of the oscillator and the matching device is simpler than other IEDF controls, for example, clip bias. When a clip bias power source is used as the bias applying mechanism 117, this is the same as the superposition of a plurality of continuous frequencies, so this is expensive, but it is possible to provide a plasma state detector 126 having a continuous frequency range. It becomes possible to do.

  In addition, in the present embodiment, the mixing ratio is controlled by using Vpp as an index of the voltage for accelerating ions. However, the mixing ratio may be controlled not only by Vpp but also by the ratio of output power. At this time, the output power is a product of the current and the voltage, and the Vpp value varies depending on the arrangement and area of the ground, so this point needs to be considered. Alternatively, a method of controlling the output of each power supply so as to obtain a desired energy distribution based on a calculation model as shown in FIG. 2 is also possible. In that case, it is possible to improve control accuracy by providing a mechanism for detecting plasma density, electron temperature, and the like necessary for calculating the energy distribution.

  Furthermore, this time, for the IEDF control, 13.56 MHz was used on the high frequency side and 400 kHz was used on the low frequency side as the bias power supply. Basically, the IEDF control range is larger when the difference between the two frequencies is wide. It is also preferable from the viewpoint of spreading and isolating the impedance directly above the chamber wall surface and the wafer. Also, it is better not to be an integral multiple of each other so that harmonics of each frequency can be used. At this time, in order to maintain independence from plasma generation and good in-plane distribution, the frequency on the high frequency side is preferably lower than the frequency of the plasma generation mechanism. For example, in the case of ECR, since independent controllability of ion energy and plasma density becomes difficult at 100 MHz or higher, 4 MHz or higher and 100 MHz or lower is desirable. On the other hand, if the frequency on the low frequency side is less than 100 kHz, charge-up is likely to occur in the insulating layer on Si, which is inappropriate. Therefore, it is desirable to combine a low frequency with a frequency difference of 100 kHz or more and less than 4 MHz, and a high frequency with a frequency of 1 MHz or more and less than 100 MHz with a frequency difference as large as possible. The frequency band to be mixed also depends on the plasma generation mechanism. For example, in this plasma generation mechanism that uses a magnetic field for distribution control, 13.56 MHz is used on the high frequency side in consideration of the influence of the cross impedance of E × B. For ICP, CCP, etc., 27.60 MHz or the like can be used after adjusting the balance with the plasma source frequency.

[Example 2]
In the first embodiment, the end point is obtained from the absolute value of the impedance in the single wafer processing on the assumption that the impedance of the wall surface state does not change. However, in wafer mass production processing, there may be a change with time due to the chamber wall surface state. An example of obtaining the end point by separating the chamber wall state fluctuation is shown below. In the case where the end point determination is performed with the two-frequency mixing ratio of 50% in the TiN ME described in the first embodiment, as shown in the end point determination flow of FIG. 5, after the step 501 of detecting impedance according to a plurality of frequencies. The step 502 for separating the impedances immediately above the wall surface and the wafer based on the equations (1), (2), and (3) is performed, the step 503 for determining the end point is performed, the IEDF control mechanism 127, the UHF power supply 101 Step 504 is performed to change the output of the fast response pressure control mechanism 110, the fast response reactive gas introduction mechanism 111, and the temperature control mechanism 115. A schematic diagram of end point determination used at this time is shown in FIG.

  FIG. 6A is a plot of the impedance change immediately above the wafer excluding the impedance change of the wall surface portion after the separation process on an immittance chart based on complex impedance. For example, consider a case where the impedance 602 before the end point determination shifts to the impedance 601 when the etching film is completely removed. When the matching path 603 is taken by the tuning capacitor or tuning coil depending on the matching device, the end point is determined at the time of the point 605 that has passed through the set complex impedance range 604.

  On the other hand, FIG. 6B is a schematic diagram in which impedance changes detected at a single bias frequency, which is a conventional method, are plotted on an immittance chart. If there is a change over time, the wall impedance of the chamber changes as the etching process time increases, and the set impedance range 604 is exceeded before the end point is determined. According to the method of detecting impedances of a plurality of frequencies according to the present invention and performing the process of separating the wall surface and the wafer directly above, this phenomenon can be stably acquired without affecting the wall surface state, and combined with IEDF control. Thus, it is possible to stably obtain an etching shape of a metal gate / high-k structure which does not cause a base removal and does not generate a tailing shape.

  The flow in FIG. 5 is executed by a control program in the control device 125 or by being described in the control software of the plasma state detector 126. In the present embodiment, the metal gate electrode layer (TiN) 306 having a large impact on the device characteristics is described among the layers of the cross-sectional structure sample of FIG. 3A. However, each BARC 302, intermediate layer mask 303, lower layer mask 304 is described. In addition, it may be used for end point determination in each layer such as the gate cap layer 305.

[Example 3]
Next, an example using the separated chamber wall surface and the impedance change immediately above the wafer will be described below. FIG. 7 shows a flowchart of the TiN ME end point determination step in the case where a plurality of metal gate / high-k gate electrode etching processes shown in FIG. After the step 501 of detecting the impedance corresponding to a plurality of frequencies in the manner of the second embodiment, the step 502 of separating the impedances immediately above the wall surface and the wafer based on the expressions (1), (2), and (3) A step 701 is performed in which the impedance of the separated chamber wall surface and the impedance directly above the wafer are compared with the state of the same step in the past (data such as past impedance change, variation model formula).

  In the comparison step 701, the impedance, current, voltage, and phase currently in progress are recorded in a database and compared with past data, thereby classifying changes over time for each wafer. According to the classification, the separated impedance information is obtained by executing the process 702 for determining the wall surface state and appropriately adjusting the value of each device output so as to correct the cleaning process and the change of the wall surface state. It can be used to suppress changes over time.

For example, if only the voltage, current, phase, or impedance on the high-frequency bias side changes drastically during this classification, it is determined that the bias uniformity in the wafer surface has changed, and the next wafer processing By adjusting the in-plane distribution of the bias so that the in-plane distribution of the bias is uniform, it is possible to feedback control the bias uniformity and suppress a decrease in yield. This bias uniformity correction method can be realized by adjusting the mixing ratio of the two frequency biases. For example, the Poly-Si etching rate when the mixing ratio (VppH / (VppH + VppL)) of the low frequency (400 kHz: VppL) and the high frequency (13.56 MHz: VppL) is changed to 0%, 20%, and 100%. Changes in the distribution are shown in FIGS. 8 (a), (b), and (c). The etching conditions were such that HBr / O ₂ was used as the processing gas, the pressure was 3 Pa, and the UHF power was 500 W.

  When the bias power is 13.56 MHz and the mixing ratio is 0%, the medium-high distribution of the etching rate of Poly-Si is 11% (FIG. 8A). When the bias power is 20.56 MHz and the mixing ratio is 20%, the medium-high distribution of the Poly-Si etching rate is 0% (FIG. 8B). When the bias power is 13.56 MHz and the mixing ratio is 100%, the middle-high distribution of the etching rate of Poly-Si is 12% (FIG. 8C). That is, as the high-frequency bias power 13.56 MHz mixing ratio increases, the wafer edge distribution increases, and the wafer distribution can be controlled with the mixing ratio of 97% and the edge height of 12%.

FIG. 8D shows a poly-Si etching rate on a 200 mm wafer by changing the mixing ratio of the monitor voltages VH and VL of the high frequency bias 13.56 MHz and the low frequency bias 400 kHz so that VH + VL is substantially constant. 801 is the result of measuring the SiO ₂ etching rate 802. The SiO ₂ etching rate 802 is shown 10 times. As the mixing ratio of the high-frequency bias 13.56 MHz increases, the poly-Si etching rate is constant with a decrease of about 20%, while the SiO ₂ etching rate decreases drastically and the selectivity (selection ratio) 803 to the oxide film increases. To do. As described above, when the in-plane rate of the wafer is controlled by changing the bias mixing ratio, if the control is performed at a mixing ratio of 30% or more, a highly selective region that can sufficiently withstand OE (line 804 or higher with a selection ratio of 200). It is preferable. In addition, as a means for correcting the in-plane distribution of the etching rate and shape, it is possible to control in combination with the output of the electromagnet 104, the gas flow distribution, the in-plane distribution of the wafer stage, and the like.

  In addition, as the number of wafers processed increases, if only the low-frequency impedance and high-frequency impedance of the chamber wall change in the same etching step, the observer determines that the chamber wall state has changed, or controls it. Based on a model that is determined by the apparatus 125 and automatically or manually performs plasma cleaning of the plasma processing apparatus, promotes replacement of parts, or corrects fluctuations, the IEDF control mechanism 127, the UHF power supply 101, and the fast response pressure control mechanism 110 The outputs of the fast response reactive gas introduction mechanism 111 and the temperature control mechanism 115 are changed.

  As mentioned above, the example of classifying the device state and the wafer processing state by the impedance of the wafer directly above or the chamber wall surface, the impedance of the low frequency bias or the impedance of the high frequency bias has been given, but further, the changing direction (for example, inductor side or conductor) By considering the information on the other side, more detailed classification, database construction and variation factor extraction are possible, and appropriate feedback control according to the variation factor can be performed.

  In this way, the IEDF control bias of two-frequency mixing is used for the etching step (ME step and end point determination step) that has a large influence on the processing shape, and the impedance is measured, recorded, and compared with past databases and fluctuation models. By this method, it is possible to automatically correct the etching characteristic variation.

  A mechanism that embodies this method is shown in FIG. A database 901 is connected to the control device 125. The input signal to the control device 125 is not limited to the output of the plasma state detector 126 in the bias applying mechanism 117 described in the first and second embodiments. That is, as an input signal to the control device 125, the output (emission spectrum) of the conventional plasma emission spectrometer 123 and the high-speed response UHF matching unit 102 with impedance detector (plasma impedance, current, voltage as seen from the plasma generation frequency). , Phase) and output of the film thickness interference monitor 124 (residual film on the wafer), and other mechanisms such as the UHF power source 101, the electromagnet 104, the heater 108, the fast response pressure control mechanism 110, and the fast response reactive gas. The monitor values of the introduction mechanism 111, the temperature control mechanism 115, and the DC power supply 116 can be used. The control device 125 stores each input data. The control device 125 compares or refers to the past data recorded in the database 901 and the newly input data, and based on the result of collating with the fluctuation model in the database 901 or the control device 125, IEDF Control signals of the control mechanism 127 and each control device are output. As described above, by referring not only to the information of the plasma state detector 126 corresponding to a plurality of frequencies of the present invention but also the monitor values of each control mechanism such as the emission spectrum, more detailed apparatus states and wafer processing states can be obtained. It becomes possible to classify and take appropriate measures.

[Example 4]
Next, referring to FIG. 10, a structure in which planar type ArF resist 301 / BARC302 / TEOS (hard mask) 1001 / Poly-Si1002 / HfSiO ₂ 307 shown in FIG. A description will be given of an embodiment in which a CMOS gate having a gate is processed using the present invention.

  10A shows a cross-sectional shape of a planar CMOS having a multilayer mask structure including a hard mask before etching, FIG. 10B shows a cross-sectional shape after hard mask etching with a high frequency bias of a conventional method, and FIG. c) shows the cross-sectional shape after gate etching with a high-frequency bias of the conventional method, and FIG. 10 (d) shows the cross-sectional shape after etching processing according to the present invention.

  A Si wafer having a cross-sectional structure in which a hard mask 1001 and a Poly-Si gate electrode layer 1002 are disposed below the BARC film 302 shown in FIG. 10A is formed at a relatively high frequency of 26 MHz or 13.56 MHz. FIG. 10B shows an example in which the hard mask pattern 1001 is etched using the conventional technique (single frequency bias power supply). As shown in this figure, a side wall protective film 1004 adheres to the hard mask 1001 portion, resulting in a tapered shape 1003. Further, as shown in FIG. 10C, notching 1005 occurs in the dense pattern side portion at the boundary between the lower portion of the Poly-Si gate electrode layer 1002 and the HfSiON insulating film 307, and a part of the underlying HfSiON insulating film 307 is formed. Dielectric breakdown is likely to occur.

  Hereinafter, an example of etching a 12-inch wafer having the cross-sectional structure shown in FIG. 10A by applying the plasma state detector 126 of the present invention and the IEDF control bias will be described. The Si wafer 112 having the cross section shown in FIG. 10A was placed on the lower electrode 113 of the etching apparatus of FIG. 1, and trimming and etching processes were performed.

  The operation of applying a two-frequency bias in the case of trimming or etching will be described with reference to FIG. FIG. 11 is a graph showing changes with time of the operation of the processing performed by the plasma processing apparatus according to the embodiment shown in FIG. This graph is a diagram showing a time sequence in which the operation is plotted on the vertical axis and the time is plotted on the horizontal axis. In this figure, the trigger of the operation of the plasma processing apparatus of FIG. 1 is the end point determination method using the present invention as described in Examples 1 and 2, and the waveform of the output from the emission spectrometer 123 from the plasma. The vertical axis of the emission intensity in FIG. 11A is a relative value. FIG. 11B shows the mixing ratio between the on / off state of the bias of two frequencies and the bias power on the high frequency side.

In the ME step of BARC 302, halogen-based (CF ₄ , CHF ₃ , CH ₂ F ₂ , CH ₂ Cl ₂ , Cl ₂ , HBr, HCl, etc.) gas is added to O ₂ / Ar gas, and the total gas flow rate is adjusted. A plasma generated with a UHF power output of 500 W to 800 W with a pressure adjusted to 100 to 400 cc and a pressure of about 0.8 Pa to 10 Pa was used. The plasma distribution within the surface of the 12-inch wafer is controlled by the current values of the plurality of electromagnets 104. After the plasma is ignited, as shown in FIG. 11B, a low frequency bias power source 120 of 400 kHz is applied at about 30 to 50 W, and the BARC layer 302 is etched while trimming the resist 301 (the BARC ME process). ). At this time, a high frequency bias of 13.56 MHz is not applied, and the mixing ratio of the high frequency bias is 0%.

  By using the low frequency IEDF of 400 kHz, low ions are easily incident on the side wall portion, and isotropic trimming is efficiently performed, and the line edge roughness (Line Edge Roughness: LER) can be scraped off to achieve both effects of reduction. The trimming amount at this time was appropriately controlled by the gas mixture ratio and pressure, the plasma source power (output of the UHF power supply 101), the temperature of the lower electrode, and the OE time. As the end point 1101 of the BARC ME, an inflection point of emission intensity of CN 387 nm in plasma was used.

  After detecting the BARC ME end point, the BARC is over-etched (OE). During OE, in order to improve the selectivity, the bias power is reduced by about 10 W, further switched to the high frequency bias of 13.56 MHz, the low frequency bias is 0, and the mixing ratio of the high frequency bias is 100% (BARC OE processing).

Next, in the ME step of TEOS 1001 which is a hard mask, an appropriate gas is mixed from SF ₆ , CF ₄ , CHF ₃ , CH ₂ F ₂ , O ₂ , Ar, and He, and the total gas flow rate is set to 100 cc. Plasma was generated with a pressure of 0.4 to 1.5 Pa, a pressure of 0.4 to 1.5 Pa, a UHF output of 500 to 800 W, and a lower electrode bias power of 80 W to 150 W (hard mask ME treatment). As the frequency of the bias power, the output of the low-frequency bias power supply unit that becomes a broad IEDF having a high energy peak was used at a mixing ratio of 100%. This is to prevent re-dissociation of the reaction product in the vicinity of the wafer even at high power necessary for TEOS etching. By suppressing this re-dissociation, a taper shape 1003 as shown in FIG. 10B was obtained, and it was possible to process vertically instead of a hard mask having a sparse shape difference (FIG. 10D). When this low-frequency bias and high power are used, ion bombardment occurs on the ground as well as on the wafer, so reaction products containing the grounded material adhere to the quartz surface, and etching characteristics change with time and foreign matter is generated. May cause. In this case, earth spatter can be reduced by increasing the high-frequency mixing ratio within a range that does not cause excessive dissociation and maintains the in-plane processing dimensions.

  At the end point 1102 of such hard mask etching, OE is switched. In the OE step, the frequency is switched to 100% for the purpose of improving the selectivity with the base Poly-Si 1002 so that the processing time is equivalent to the STI step (hard mask OE processing).

Thereafter, a breakthrough (BT) step of Poly-Si 1002 was started. As for the plasma conditions in the BT treatment of Poly-Si, a single gas such as Cl ₂ , HBr, O ₂ , Ar, or He or a mixed gas thereof is used as the gas system, the total flow rate is 200 to 300 cc, and the pressure is 0.4. -0.8 Pa, UHF output was 500-700W. The condition of the IEDF control mechanism 127 was that a 400 kHz low frequency bias was applied 100% (Poly-Si BT treatment). This is because pattern bottom carbon materials, oxides, and the like are removed with high energy ions, and the protective film on the side walls is easily removed with low energy ions. In Poly-Si etching, since the processed shape has a great influence on the device characteristics, the end point was determined by the method to which the present invention described in Examples 1 and 2 was applied.

  As the ME of Poly-Si 1002, IEDF having a high frequency ratio of 50% of 13.56 MHz was used (Poly-Si ME treatment). The end point 1104 of the Poly-Si ME was obtained by the method shown in Example 2 from the signal of the plasma state detector 126.

  After detecting the end point of the Poly-Si ME process, the OE process is performed. This OE process is performed in two steps, OE1 and OE2. In the OE1 step, low-pressure conditions are desirable in order to achieve both substrate selectivity and etching shape (perpendicularity, no skirt shape). In order to obtain substrate selectivity under low pressure conditions, it is generally necessary to reduce the ion energy. However, if low bias is applied at a low frequency of 400 kHz, the ion directivity further decreases. , Hem shape is likely to remain. Therefore, in the OE1 step, IEDF in which a high frequency bias of 13.56 MHz is mixed 100% using the same processing gas as that of ME (Poly-Si OE1 processing) was used. The bias power is 10 W to 50 W (Vpp 250 V or less).

And it shifted to OE2 step which removes Poly-Si resulting from a STI level difference part, an in-plane, p / n gate difference, and a density pattern difference. The OE2 step plasma condition is that the process gas is HBr / O ₂ diluted with Ar, the total flow rate is 200 to 400 cc, the pressure is 3 to 10 Pa, and the UHF output is 500 to 700 W. A two-frequency mixed bias of 80% high frequency bias and 20% low frequency bias was used (Poly-Si OE2 treatment). This is for the purpose of achieving both background selectivity and electronic shading reduction. That is, by reducing the ratio of high ion energy that is nearly twice the average ion energy, the substrate selectivity can be maintained and physical damage due to ion bombardment can be suppressed. Further, by neutralizing the electrons charged on the upper part of the mask by low energy ions, notching due to electron shading can be avoided.

  As described above, when the material to be etched is changed in an etching sample having a multilayer structure, IEDF control is performed when the plasma state detector 126, the emission spectroscope 123, or the film thickness interference monitor 124 is used as a trigger to move to the next step. The setting example of the mechanism 127 has been described. In FIG. 15, the output voltage (Vpp) of the IEDF control power supply overshoots at the time of step switching, and an excessive voltage is applied to the material to be etched, so that the selectivity is not lowered. The outline of the structure of the control apparatus for making it do is shown.

  FIG. 15 is a schematic diagram showing an outline of a functional configuration of the control device of the plasma processing apparatus according to the embodiment shown in FIG. According to the etching process conditions (recipe) set in advance, the control device 125 that controls the output value and timing of the plasma source power source (UHF power source 101), the fast response pressure control mechanism 110, and the fast response reactive gas introduction mechanism 111, The output voltage and timing of the IEDF control mechanism 127 are controlled. The IEDF control mechanism 127 includes the output setting value SVHx of the Xth high frequency bias power supply unit 118 and the output setting value SVLx of the low frequency bias power supply unit 120 and the Xth step during the X−1th etching step at the latest. The stable point set value SPHx of the high frequency matching unit 119 and the stable point set value SPLx of the low frequency matching unit 121 are set in advance by signals from the control device 125.

  At this time, the transient set value SPHy of the stable point of the X-th high frequency matching unit 119 and the stable set point SPLy of the stable point of the low-frequency matching unit 121 are also set as appropriate. Thus, when shifting to the Xth step, it is possible to respond smoothly without overshoot or the like. At this time, based on the transition monitor values MPHx and MPLx (incident power and reflected power from the load, matching state, etc.), the transient set point values SPHy and SPLy and the power supply output values SVHx and SVLx are output. Thus, feedback control is also possible. Further, not only the signals of the high-frequency matching unit 119 and the low-frequency matching unit 121 but also the voltage, current, phase, and impedance signals of the plasma state detector 126 may be monitored and feedback control may be performed. You may refer to past values. As described above, the mechanism and method for smoothly and monotonically changing the time for the next target point in the shortest time have been shown. However, like the transient control of the IEDF control mechanism 127, the UHF power supply 101, the fast response pressure control, and the like. The same can be applied to the mechanism 110, the fast response reactive gas introduction mechanism 111, and the temperature control mechanism 115.

[Example 5]
Next, an example of a processing method when forming the three-dimensional structure FIN-FET having a high step shown in FIG. 12 using the plasma processing apparatus of FIG. 1 will be described. 12A is a perspective view showing a film structure before etching, FIG. 12B is a perspective view showing a film structure after etching using this embodiment, and FIG. 12C is a perspective view showing FIG. It is the longitudinal cross-sectional view cut | disconnected by the surface which passes along the AA line shown in FIG.

In FIG. 12A and FIG. 12C, the film structure before the etching of the three-dimensional structure FIN-FET having a high step is as follows: SiO ₂ layer 1203 formed on the Si substrate 309; Si layer 1202; The TiN layer 1204, the BARC 302, and the resist 301 are included. On the SiO ₂ layer 1203, FIN portion 1201 is formed, further on the SiO ₂ layer 1203 and FIN portion 1201, high-k insulating film 1205 is formed. Reference numeral 1208 denotes a FIN portion 1201 and a portion near the gate electrode. In this example, the etching is started from the film structure of FIG. 12A using the resist 301 as a mask, and dry etching is performed to obtain the film structure shown in FIG. In FIG. 12B, reference numeral 1205 denotes a high-k insulating film, and 1206 denotes a TiN gate electrode formed by etching the TiN layer 1204. The Si layer 1202 includes a plurality of FIN portions 1201 located on both sides of the TiN gate electrode 1206 and extending toward the TiN gate electrode 1206. FIG. 12C shows a longitudinal section of the film structure of FIG. 12A having the FIN portion 1201.

  In the wafer having the structure as shown in FIG. 12A, the difference in the OE amount between the upper and lower steps of the FIN portion 1201 is large, and the gate length portion that greatly affects the device characteristics is in the vertical direction. In addition to the IEDF control described in Examples 1 to 4, the gas, pressure, matching unit, and electrode temperature are linked to control transients between steps related to reaction products, etchants, and ion fluxes. It becomes important.

  As a mechanism for following such a transient phenomenon of the etching process, the high-speed response UHF matching unit 102 has a monotonously increasing or monotonic decrease in plasma incident power without overshoot or undershoot during continuous discharge between steps. It is preferable to use one having the performance of stabilizing the change in about 1 second. The performance can be realized by, for example, having a function of setting a plurality of matching parameters such as ignition and stable point and an optimum value of the matching path. Monotonic increase is defined as the time derivative of the response curve is always positive and the time derivative of the monotonic decrease response curve is always negative.

  In addition, in order to follow the transient phenomenon of the flux of reaction products and etchants, the rapid response reactive gas introduction mechanism 111 has an excessive flow rate when a new gas is added or decreased during plasma discharge. This can be realized by using a mechanism that can prevent the chute and undershoot, for example, a mechanism that keeps the gas flowing for a waiting time so that the gas does not accumulate and burst.

  Furthermore, it is desirable to provide a fast response pressure control mechanism 110 that can stabilize the pressure in about 2 seconds following the pressure fluctuation of the plasma accompanying such a change in gas flow rate. Such a function can be realized, for example, by providing a gas piping structure in which a pressure difference does not occur as much as possible, or by optimizing a pressure control algorithm. And in order to respond to the change in the Si wafer surface distribution of the reaction product, the lower electrode 113 can increase and decrease the temperature between steps at the highest possible speed (1 ° C./sec or more), and It is desirable that the divided inner, outer, or more portions have the ability to be controlled independently. This can be realized, for example, by providing a temperature control mechanism 115 including a heater, a temperature sensor, and He gas pressure control inside the lower electrode portion.

  FIG. 13 shows a time sequence of an etching process when FINFET etching formed on an SOI (Si on Insulator) substrate is performed using the etching apparatus shown in FIG. 1 having a mechanism having such a function. 13A shows, for example, the time change of the signal for EPD using the emission intensity, FIG. 13B shows the temperature of the lower electrode 113 during processing, and FIG. 13C shows the additive gas supplied to the etching chamber 107. 13 (d) shows the pressure of the gas in the etching chamber 107, FIG. 13 (e) shows the value of UHF power introduced into the etching chamber from the antenna 103, and FIG. 13 (f) shows the IEDF control mechanism 127. It is a graph which shows the distribution ratio of the bias by the several frequency to perform.

As the initial setting value of the temperature control mechanism 115 for controlling the electrode temperature of the lower electrode 113, the temperatures of the inner peripheral portion 1311 and the outer peripheral portion 1312 started at 40 ° C. as shown in FIG. 13B. First, the ME step of the BARC layer 302 is performed using O ₂ / Cl ₂ / Ar / CF ₄ in accordance with the process procedure shown in Example 4 above, and at the time 1302 when the plasma emission intensity starts to decrease, the BARC It moved to OE step. During OE, since selectivity with the underlying TiN 1204 is required, lamp control was performed in which Cl _{2 serving} as the TiN etchant was gradually monotonically reduced within 1301 or less when the emission intensity dropped (1303). The gas flow control waveform 1304 of the prior art was instantaneously decreased because it was only opening / closing control of the Cl ₂ gas air operation valve. Further, the pressure fluctuation 1307 in the plasma according to the prior art suddenly decreased because the Cl ₂ gas stop valve was instantaneously closed, and then returned to the set pressure over about 5 seconds.

  On the other hand, in this embodiment, by using the fast response reactive gas introduction mechanism 111 and the fast response pressure control mechanism 110, the amount of the etchant is gradually decreased in accordance with the decrease in the reaction product, and the pressure fluctuation caused thereby is corrected. Can be constant. In addition, since the pressure is constant, it is possible to suppress the fluctuation 1309 of the plasma incident power and the fluctuation of Vpp generated in the UHF matching device of the prior art, and it is possible to suppress the shape abnormality.

  Further, the frequency of the IEDF control mechanism 127 in the BARC OE is switched from the low frequency of 400 kHz to the high frequency of 13.56 MHz as described in the first embodiment. The bias output was in the range of 30W to 50W. After performing the OE process for a time during which the FIN step 1207 can be etched, the process proceeds to the BT step of the TiN layer 1204. At this time, in order to replace the gas, the UHF wave output and the bias power are turned off once. Then, the electrode temperature 1311 in the inner peripheral part during the TiN etch is raised by 20 ° C. for 10 seconds during which the discharge is interrupted and the gas replacement is performed. This is in order to suppress reattachment of the reaction product incident again during the TiN etching. Further, the temperature 1312 at the outer peripheral portion of the lower electrode 113 is adjusted to be 10 to 20 ° C. lower than the inner peripheral portion in consideration of the difference in reaction product distribution due to the exhaust efficiency.

  The TiN layer is composed of BT, ME, OE1, and OE2, and BT and ME were subjected to the same endpoint determination method and etching conditions according to the present invention as in Example 1.

  In the case of the UHF matching device of the prior art, when the transition to BT step S, the fluctuation 1308 of the plasma incident power at the time of ignition appeared, but by using the fast response UHF matching device 102, the incident power is overshooted, Smooth transition without undershoot. This is because the matching path can be appropriately set when the high-speed response UHF matching unit 102 shifts to different matching parameters at the time of ignition and at the time of stabilization.

  In the BT step, the BT process gas is introduced, and UHF power is applied so that the bias is set to the low frequency side. When the end of the BT step 1310 is detected, the supply of the BT process gas is stopped, and the supply of the UHF power and the power multiplied by the low frequency is stopped.

  Next, in the ME step, the ME process gas is supplied and the supply of UHF power to the antenna is started, and the bias power is supplied so that the power on the low frequency side and the high frequency side are 1: 1. In the ME step, the TiN OE 1 step is switched to at time 1314 when the impedance of the plasma state detector 126 starts to drop.

The OE1 step has the role of aligning the etching amount due to steps, density, and in-plane differences. That is, a pattern that has reached the ground early and a pattern that has not yet reached the ground are mixed. Therefore, it is necessary to reduce the taper shape and the skirt shape in the portion that does not reach the base, particularly in the vertical gate length portion, while maintaining the selectivity to high-k in the pattern reaching the base. In order to improve the selectivity, as shown in FIG. 13 (c), an F-based gas is added so as to be controlled in accordance with the amount of reaction product that gradually decreases with a monotonous increase. As the additive gas, NF ₃ , SF ₆ , CF ₄ , O ₂ , N ₂ , CH ₂ Cl _2, or the like may be used in consideration of the base material and the gate material. In the case where the gate electrode / gate insulating film structure is Poly-Si / SiO ₂ , oxygen or nitrogen performs the same function. At this time, the gas flow overshoot 1305, pressure fluctuation 1306, incident UHF wave fluctuation 1308, and Vpp fluctuation are generated by the fast response reactive gas introduction mechanism 111, the fast response pressure control mechanism 110, and the fast response UHF matching unit 102. These gases can be added without causing them to occur. During OE1, the IEDF control mechanism 127 performs processing at a high frequency of 100% so as to have a narrow energy distribution to improve selectivity, so that there is no abnormality in the shape of the opening (side etching, base removal). It is possible to reduce the density pattern difference and the P / N gate part difference.

  In this example, the electrode temperature was lowered by 20 ° C. at the same time as the end point 1314 of the TiN ME, thereby increasing the adsorption probability of the reduced reaction product and increasing the amount of deposit adhering to the selectivity. . This is because the reaction product is reduced to suppress the side etch due to the increase in the etchant ratio.

  On the other hand, in OE2, it is necessary to remove TiN remaining in the portion 1208 between the FIN portion and the gate electrode. Since it becomes the gate length, high-precision control is required. For this reason, the high frequency 13.56 MHz of the two-frequency bias 1313 is 80% Vpp, and the value of the total power supply output is such that the average of IEDF is 50 V or less (100 Vpp or less). This is because high selectivity is required for the high-k insulating film above the FIN. In order to etch the edge portion 1208 between the gate electrode 1206 and the FIN portion 1201, the low energy energy ions are removed from the upper portion. By suppressing the total output of the bias to 100 Vpp or less, it was possible to achieve both selectivity and etching. The bias power at this time was about 1 W / 12 inches.

  In order to secure further OE time, it is more effective to use the ramp control waveform 1316 that increases the mixing ratio to the high selection side in conjunction with the height of the edge portion that gradually decreases in the middle of OE2. Further, the two-frequency mixing ratio at the time of the BARC etch and TiN etch needs to be adjusted as appropriate according to the pattern density and FIN height (step height).

  Also, the high-frequency matching unit 119 and the low-frequency matching unit 121 in the IEDF control mechanism 127 also have a process of appropriately setting a plurality of matching points and their matching paths, like the high-speed response UHF matching unit 102. It is preferable because hunting, overshoot, and undershoot of energy, Vpp, or output power can be prevented. In addition, the plasma internal parameters (radical species and density, ion density, incident ion energy, etc.) that affect etching shift smoothly (monotonically increasing or monotonically decreasing) so that the ion-assisted reaction of etching can smoothly transition. It is good to implement with the algorithm which controls each mechanism. The internal parameters of the plasma are quantities indicating the characteristics of the plasma. These quantities are the radical species, density, ion density, the emission spectrometer 123 and a new density detection probe, and the incident ion energy. With regard to the above, it is preferable to feedback control what is detected by the signal of the plasma state detector 126, or to prepare and control a plurality of transition points in a prior database. At that time, since it is necessary to simultaneously change the setting values of the respective mechanisms during the step transition, it is necessary to prevent the control from diverging.

[Example 6]
Next, FIG. 14 shows an example in which a film structure other than the gate electrode is processed and formed in the plasma processing apparatus using the μ-wave ECR apparatus. In this example, a case where deep holes are formed in the Si substrate 309 as shown in FIG. In this case, the etching step includes an etching step of the BARC 302, the hard mask 1001, and the Si 309. The BARC layer 302 and the hard mask 1001 etching step are performed by the ME and OE processes as described in the fourth embodiment. Then, F-containing gas such as SF ₆ , CF ₄ , CHF ₃ , CH ₂ F ₂ , SiCl ₄ , SiF _4, and oxygen are mixed to obtain a gas flow rate of 100 cc to 300 cc, a pressure of 0.4 to 1.5 Pa, Plasma is generated at a microwave output of 500 to 800 W, which is a plasma generation mechanism, and the Si layer is etched by increasing the inside / outside electrode temperature from 5 ° C. to about 20 ° C. inside. 1401 shown in FIG. 14B is a trench after the hard mask etching.

In the present embodiment, the IEDF control mechanism 127 uses a component having a high frequency of 13.56 MHz that is 100% so that the ion energy distribution becomes narrow. This is to suppress the low energy ion energy existing in the low frequency IEDF from promoting the bowing 1402 of the Si layer shown in FIG. In addition, since the energy distribution is uniform, the facet angle of the resist can be prevented from increasing, and the hole can be formed with high precision as shown in FIG. It becomes. By performing timing control with such a deposition gas such as oxygen, SiF ₄ , and SiCl ₄ , finer and higher aspect processing can be performed.

  In the etching process of gate electrodes such as planar CMOS-FETs and three-dimensional structures (FiN-FETs) having a multi-layer structure including steps, metal materials, and high-k materials by the methods and mechanisms described above, abnormal shapes (dense / dense) It is possible to stably realize an etching process having no difference in shape, notching, side etching, damage to the underlying film, bottom, missing base, tapered shape, and the like.

  These mechanisms and examples are implemented in the semiconductor processing of the Si wafer, but can be applied to plasma etching processes such as plasma display, liquid crystal, and MEMS manufacturing by making the shape of the lower electrode 113 correspond.

DESCRIPTION OF SYMBOLS 101 UHF power supply 102 High-speed response UHF matching device with impedance detector 103 Antenna 104 Electromagnet 105 Quartz plate 106 Shower plate 107 Etching chamber 108 Heater 109 High vacuum pump 110 High-speed response pressure control mechanism 111 High-speed reactive gas introduction mechanism 112 Si wafer 113 Lower electrode 114 Susceptor 115 Temperature control mechanism 116 DC power supply 117 Bias application mechanism 118 High frequency bias power supply section 119 High frequency matching section 120 Low frequency bias power supply section 121 Low frequency matching section 122 Light emitting / receiving section 123 Light emission spectroscope 124 Film thickness interference monitor 125 Control Device 126 Plasma State Detector 127 IEDF Control Mechanism 201 High Frequency (13.56 MHz) IEDF
202 Distribution width at high frequency 203 Low frequency (400 kHz) Vpp200V IEDF
204 Distribution width at low frequency 205 IEDF when mixing low frequency (400 kHz) Vpp100V and high frequency (13.56 MHz) Vpp100V
301 resist 302 BARC
303 Intermediate layer mask 304 Lower layer mask 305 Gate Cap layer 306 Metal gate electrode layer 307 HfSiON insulating film 308 STI
309 Si substrate 310 STI step 311 Lower part of gate electrode in active part 312 Underlayer of HfSiON film 313 Remaining gate electrode material in STI step part 314 Footing shape 315 Remaining gate electrode material on STI 316 Gate electrode processed in the present invention 401 BT end point (time when impedance increases)
402 TiN ME end point (time when impedance began to change)
403 TiN FE dual frequency mixing ratio 404 TiN OE1 dual frequency mixing ratio 405 TiN OE2 dual frequency mixing ratio 406 TiN ME end point due to conventional emission peak 407 TiN BTME based on film thickness interference monitor Output waveform 408 Ti end point of TiN by thickness interference monitor 601 Impedance when etching film is completely removed 602 Impedance before end point determination 603 Matching path 604 Point where matching path passes through set complex impedance range 605 604 606 Impedance before end point determination when there is a change 607 Impedance after end point determination when there is a change over time 801 poly-Si rate 802 SiO ₂ rate 803 Selectivity of oxide film 804 Line of selectivity ratio 901 Database 1 001 Hard mask 1002 Poly-Si gate electrode layer 1003 Hard mask with taper shape density difference 1004 Reaction product adhering to side wall 1005 Notching 1101 End point of BARC 1102 End point of hard mask etching 1103 End point of BT step of Poly-Si 1104 End point of Poly-Si ME step 1105 Two-frequency mixing ratio during BARC etching 1106 Two-frequency mixing ratio during hard mask etching 1107 Two-frequency mixing ratio during Poly-Si etching 1108 2 during Poly-Si OE etching frequency mixing ratio 1201 FIN portion 1202 Si layer 1203 SiO ₂ layer 1204 TiN layer 1205 High-k insulating film 1206 etched TiN gate electrode 1207 FIN step 208 FIN portion and the gate electrode portion 1301 Time when emission intensity decreases 1302 Start time when CN emission intensity starts decreasing 1303 Lamp control 1304 Gas flow control waveform of prior art 1305 Gas flow overshoot 1306 Pressure fluctuation 1307 During plasma in prior art 1308 Fluctuation of plasma incident power during ignition 1309 Fluctuation of plasma incident power 1310 Time when emission intensity sufficiently rises 1311 Electrode temperature of inner peripheral part during TiN etching 1312 Temperature of outer peripheral part during TiN etching 1313 TiN ME step 2 Frequency bias of 1314 Time when Ti emission intensity starts to decrease 1315 F-system additive gas flow rate controlled to increase monotonously by the fast response reactive gas introduction mechanism 1316 Ramp control waveform 1401 Training after hard mask etching Ji 1402 Boeing

Claims (7)

A vacuum vessel, a lower electrode disposed in a processing chamber of the vacuum vessel, on which a wafer can be placed, a bias applying mechanism for supplying bias power of a plurality of different frequencies to the lower electrode, and a reactive gas in the processing chamber A gas supply mechanism to be introduced; a pressure adjustment mechanism for adjusting a pressure in the processing chamber; an electromagnetic wave supply mechanism for supplying an electromagnetic wave for generating plasma in the processing chamber; the bias application mechanism; the gas supply mechanism; In a plasma processing apparatus comprising a pressure adjustment mechanism and a control device for controlling the electromagnetic wave supply mechanism,
The bias application mechanism includes an ion energy distribution control mechanism that controls the distribution of incident ion energy to the wafer, and a plasma state detector that detects a plasma state, and the plasma state detector includes a plurality of the plasma state detectors on the wafer. The impedance of the plasma when a high frequency bias power having a different frequency is supplied is detected, and the detected impedance of the plasma is separated into a wall surface state component of the processing chamber and an impedance of a component directly above the wafer, and the control device includes: The plasma processing apparatus state is compared by comparing the impedance of the separated component directly above the wafer and the impedance of the separated processing chamber wall state component with reference data stored in the database in advance or a variation model formula stored in the database in advance. Plas characterized by judging Processing apparatus. The plasma processing apparatus according to claim 1,
The bias applying mechanism includes: a power supply unit that oscillates a plurality of different frequencies; a matching unit that corresponds to a plurality of different frequencies; and an impedance detector for a plurality of different frequencies, or a power supply unit that oscillates a plurality of different frequencies. A plasma processing apparatus comprising: a matching unit corresponding to a plurality of different frequencies; and a mechanism for detecting current, voltage, and phase with respect to the plurality of different frequencies. The plasma processing apparatus according to claim 1,
The plasma state detector has voltages V _H , I _H , Z _1H , Z _2H respectively for the voltage, current, impedance of the component directly above the wafer, and impedance of the wall state component of the processing chamber when high frequency high frequency bias power is supplied. And the voltage, current, impedance of the component directly above the wafer, and impedance of the wall state component of the processing chamber when the low-frequency high-frequency bias power is supplied are V _L , I _L , Z _1L , Z _2L , and the high frequency high frequency bias angular velocity and the low frequency high frequency bias angular velocity ω _H and ω _L respectively, and the impedance of the component immediately above the wafer when the high frequency high frequency bias power is supplied. The impedance of the component directly above the wafer and the resistance component and reactor of the component directly above the wafer when a low frequency high frequency bias power is supplied. Nsu component and an inductance component and a capacitance component, respectively _{Z 1H, Z 1L, R 1} , X 1, L 1, C 1 and to the impedance of the wall surface state components of the processing chamber when the RF bias power of a high frequency is supplied low The impedance of the wall surface state component of the processing chamber when the high frequency bias power of the frequency is supplied, the resistance component, the reactance component, the inductance component, and the capacitance component of the wall surface state component of the processing chamber are respectively _expressed as Z _2H , Z _2L , R ₂ , X ₂ , L ₂ , and C ₂ are used to separate the detected time variation of the detected plasma impedance into the wall state component of the processing chamber and the impedance of the component directly above the wafer. Processing equipment.

The plasma processing apparatus according to claim 1,
The electromagnetic wave supply mechanism includes a power source that supplies electric power of the electromagnetic wave, and a matching device that records a plurality of matching points with respect to the power source and selects and matches the matching path. Processing equipment. In a plasma processing method of forming a gate electrode having a metal gate / high-k structure on a wafer having a high-k material and a metal material provided on the high-k material by plasma etching,
Detecting a time change in plasma impedance while supplying a plurality of high-frequency bias powers having different frequencies to the wafer; and detecting the time change in the detected plasma impedance based on the wall surface state component of the processing chamber and the impedance of the component directly above the wafer And comparing the impedance of the wall state component of the separated processing chamber and the impedance of the component immediately above the separated wafer with reference data stored in a database in advance or a variation model formula stored in a database in advance. And a step of determining the state of the plasma processing apparatus. The plasma processing method according to claim 5, wherein
In the separating step, the voltage, current, impedance of the component directly above the wafer, and impedance of the wall surface state component of the processing chamber when the high-frequency high-frequency bias power is supplied are V _H , I _H , Z _1H , Z _2H , respectively. And the voltage, current, impedance of the component directly above the wafer, and impedance of the wall surface state component of the processing chamber when the low frequency high frequency bias power is supplied are V _L , I _L , Z _1L , Z _{2L, respectively.} (2) and the angular velocity of the high-frequency high-frequency bias and the low-frequency high-frequency bias are ω _H and ω _L , respectively, and the impedance of the component directly above the wafer when the high-frequency high-frequency bias power is supplied and low Impedance of the component directly above the wafer and resistance component and reactance of the component directly above the wafer when the high frequency bias power of the frequency is supplied Min and an inductance component and a capacitance component, respectively _{Z 1H, Z 1L, R 1} , X 1, L 1, C 1 and impedance and low frequency wall state components of the processing chamber when the RF bias power is supplied in the high frequency Z _2H , Z _2L , R ₂ , and X _{2 represent} the impedance of the wall state component of the processing chamber, the resistance component, the reactance component, the inductance component, and the capacitance component of the wall state component of the processing chamber when high frequency bias power is supplied. , L ₂ , and C _2, and the time variation of the detected plasma impedance is separated into the wall state component of the processing chamber and the impedance of the component directly above the wafer. Method.

The plasma processing method according to claim 5, wherein
The plasma processing method, wherein the gate electrode is a gate electrode of a FIN-FET.

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