WO2010095196A1 - Plasma treatment method and plasma treatment device - Google Patents

Plasma treatment method and plasma treatment device Download PDF

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Publication number
WO2010095196A1
WO2010095196A1 PCT/JP2009/006226 JP2009006226W WO2010095196A1 WO 2010095196 A1 WO2010095196 A1 WO 2010095196A1 JP 2009006226 W JP2009006226 W JP 2009006226W WO 2010095196 A1 WO2010095196 A1 WO 2010095196A1
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plasma
film
etching
gas
processing
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PCT/JP2009/006226
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French (fr)
Japanese (ja)
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島美希
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パナソニック株式会社
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31127—Etching organic layers
    • H01L21/31133—Etching organic layers by chemical means
    • H01L21/31138—Etching organic layers by chemical means by dry-etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01J—ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
    • H01J37/00—Discharge tubes with provision for introducing objects or material to be exposed to the discharge, e.g. for the purpose of examination or processing thereof
    • H01J37/32—Gas-filled discharge tubes
    • H01J37/32917—Plasma diagnostics
    • H01J37/32935—Monitoring and controlling tubes by information coming from the object and/or discharge
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31105—Etching inorganic layers
    • H01L21/31111—Etching inorganic layers by chemical means
    • H01L21/31116—Etching inorganic layers by chemical means by dry-etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31105—Etching inorganic layers
    • H01L21/31111—Etching inorganic layers by chemical means
    • H01L21/31116—Etching inorganic layers by chemical means by dry-etching
    • H01L21/31122—Etching inorganic layers by chemical means by dry-etching of layers not containing Si, e.g. PZT, Al2O3
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
    • H01L21/32135—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only
    • H01L21/32136—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only using plasmas
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
    • H01L21/32135—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only
    • H01L21/32136—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only using plasmas
    • H01L21/32137—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only using plasmas of silicon-containing layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32139—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer using masks

Definitions

  • the present invention relates to a method for manufacturing a semiconductor device having a multilayer film structure, and more particularly to processing of a fine structure in a semiconductor device having a multilayer film structure of a metal gate / high dielectric constant film. More specifically, the present invention relates to a plasma processing method and plasma processing apparatus for forming a gate electrode in a semiconductor device, and a control program for the processing sequence.
  • the high dielectric constant material film is referred to as a High-k material film.
  • plasma processing has become an indispensable technique for manufacturing ultra-high integrated circuit devices, particularly for applications such as microfabrication and thin film formation.
  • the need for plasma treatment in semiconductor device manufacturing methods is increasing in situations where the resist film thickness is becoming thinner.
  • the transistor structure is a multi-layer film of metal gate / high-k material film in which the oxide insulating film is changed to a high-k material film and the gate electrode is changed from only polysilicon to a metal gate film. It has changed to a laminated structure.
  • a more complicated multilayer film etching technique will be required in the semiconductor device manufacturing method in the future.
  • a film to be etched requires high selectivity with respect to the upper film serving as a mask and high vertical shape accuracy.
  • plasma processing is indispensable, and further, there is a demand for a plasma etching processing method and a plasma etching processing apparatus that are optimal for a gate electrode formation process and the like.
  • the processing principle of the dry etching process is that the reactive gas is converted into plasma by electromagnetic waves, and etching is performed by an ion-assisted reaction using the generated ions and neutral radicals.
  • a plasma processing apparatus embodying such dry etching processing includes a plasma generation mechanism, a reactive gas introduction mechanism, a pressure control mechanism, a lower electrode mechanism for installing a Si semiconductor substrate, and an operation control mechanism thereof. With.
  • the bias power to be applied As a method for grasping the ion energy distribution (Ion Energy Distribution Function; IEDF) using the plasma processing apparatus having the above-described mechanism (that is, a method for measuring and controlling the self-bias potential), the bias power to be applied. Or there is a method of controlling the frequency.
  • IEDF ion Energy Distribution Function
  • FIG. 5 is a schematic configuration diagram showing an example of a conventional plasma processing apparatus whose structure is disclosed in Patent Document 1.
  • This plasma processing apparatus includes a vacuum processing chamber 101 configured to be decompressed.
  • a workpiece (semiconductor substrate) 104 is placed on a lower electrode 103 provided in the vacuum processing chamber 101.
  • An upper electrode 106 is provided at a position facing the lower electrode 103.
  • the dry etching process of the workpiece 104 by this plasma processing apparatus is performed as follows. That is, first, an etching gas (process gas) is introduced from the gas introduction unit 105 into the vacuum processing chamber 101. At this time, the internal pressure of the vacuum processing chamber 101 is maintained at a predetermined pressure by the process gas exhaust adjustment of the vacuum exhaust device 102. In this state, for example, when the high frequency power source 107 applies high frequency power to the upper electrode 106 via the matching unit 108, plasma is generated by an electric field generated between the lower electrode 103 and the upper electrode 106. When the high frequency power source 111 applies high frequency power to the lower electrode 103 via the matching unit 115, the workpiece 104 exposed to the plasma is etched by the action of the plasma.
  • an etching gas (process gas) is introduced from the gas introduction unit 105 into the vacuum processing chamber 101.
  • the internal pressure of the vacuum processing chamber 101 is maintained at a predetermined pressure by the process gas exhaust adjustment of the vacuum exhaust device 102.
  • plasma is generated by an electric field generated
  • the self-bias potential of the bias power at this time is measured by the monitor 126, and the processing condition calculation unit 125 calculates the processing condition of the next workpiece 104 based on the measured value, and then the applied power control unit 128. Adjusts the ion energy distribution in the plasma incident on the workpiece 104 by the high frequency power.
  • the shape of the workpiece 104 after etching is predicted based on various data obtained in the workpiece processing 104 in which the etching processing proceeds while adjusting the ion energy distribution, and the bias during the etching processing is based on the prediction.
  • the optimum values of the applied power and the applied frequency by the applying device are determined, and the processing conditions for the next workpiece 104 are changed based on the determined optimal values. According to this dry etching method, the etching process can be performed with high accuracy even in a film structure having a step.
  • the conventional technique it is possible to indirectly grasp the amount of ions colliding with the workpiece 104 based on the measured value of the monitored self-bias potential.
  • various types of by-products such as metal, organic matter, Si polymer, etc. are processed because different types of film are processed during etching.
  • 114 will adhere to the chamber wall. Therefore, the density of each ion species in the plasma is changed by the change in the gas species (oxygen and fluorine components) supplied into the chamber due to the impedance change of the chamber due to these by-products 114 and the degas from the by-products 114. It is expected to change.
  • the processing conditions of the semiconductor substrate 104 to be processed next are changed based on the measurement information of the self-bias potential obtained at the time of processing one semiconductor substrate. Therefore, since there is no information to be fed back for the first (first) processed semiconductor substrate 104, processing must be performed under processing conditions without preset correction information. Unlike the predetermined size and shape, there is a problem that the size and shape may be finished in a soaking shape (a shape in which the etching side surface is slanted without rising vertically).
  • the present invention has been proposed in view of the above-described conventional circumstances, and it is a main object of the present invention to provide a plasma processing method or a plasma processing apparatus capable of stably controlling processing into a vertical shape with high base film selectivity. It is said.
  • the present invention employs the following technical means.
  • the present invention The workpiece having the laminated film on the surface is placed on the lower electrode in the vacuum processing chamber, and the vacuum power is supplied to the vacuum processing chamber while supplying bias power for forming a bias potential to the workpiece.
  • the vacuum power is supplied to the vacuum processing chamber while supplying bias power for forming a bias potential to the workpiece.
  • a plasma processing method for plasma-etching the film for each film while adjusting the plasma to a state suitable for each of the films to be configured A first step of detecting a time change of the plasma state for each plasma etching treatment of the film; For each plasma etching process of the film, the processing shape of the film is predicted based on the distribution of ion energy incident on the object to be processed and the density of each ion species in the plasma.
  • the present invention has the following aspects. That is, The second step includes A measurement step of measuring a physical quantity that varies according to an amount of electric charge between the inner wall of the vacuum processing chamber and the plasma, and an emission intensity of light emission generated in the plasma due to each ion species based on the etching gas.
  • a prediction step of predicting the processed shape of the film Further includes.
  • a physical quantity that varies in accordance with the amount of charge between the vacuum processing chamber wall and the plasma generated in the vacuum processing chamber is acquired. Furthermore, the emission intensity of a wavelength peculiar to each ion species, which varies depending on each ion species generated in the plasma, is acquired as a physical quantity.
  • the obtained physical quantity (self-bias potential or emission intensity of each ion species in the plasma, or emission intensity ratio) is calculated as a statistical value such as an average value or a median value, and from the statistical values, metal, high-k, oxide film, For each etching process of each film type such as polysilicon, the pattern dimension after etching is calculated (predicted) by a preset model.
  • the etching conditions gas flow rate of the next layer continuously performed in the same chamber so that the workpiece has a preset processing dimension in a preset model.
  • the mixing ratio and the bias applied power are calculated. Based on the etching conditions calculated by the above-described method, etching for the next layer processing is performed.
  • the present invention can also be provided as a recording medium on which a program for causing a computer to execute the procedure of the plasma processing method described above is recorded.
  • the processing shape or processing dimension is determined according to a preset model. It is possible to calculate the next laminated film processing condition by using the same model. Therefore, at the time of the etching process of the next film type, it is possible to perform the etching process while supplying the previously calculated processing conditions as feedback information to the control unit of the plasma etching apparatus. Thus, it is possible to always perform the etching process with the same processing accuracy by correcting the processing dimension and shape for each etching of each film type, without going through the troublesome process of measuring the dimension after etching.
  • FIG. 1 is a schematic configuration diagram showing a plasma processing apparatus in an embodiment of the present invention.
  • FIG. 2 is a diagram showing the relationship between the dimension after etching and the average value of the bias potential and the emission intensity during etching in the embodiment of the present invention.
  • FIG. 3A is a schematic cross-sectional view showing a first shape of a semiconductor substrate on which a plasma etching method according to an embodiment of the present invention is performed.
  • FIG. 3B is a schematic cross-sectional view showing a second shape of the semiconductor substrate on which the plasma etching method of the embodiment of the present invention is performed.
  • FIG. 3C is a schematic cross-sectional view showing a third shape of the semiconductor substrate on which the plasma etching method of the embodiment of the present invention is performed.
  • FIG. 3A is a schematic cross-sectional view showing a first shape of a semiconductor substrate on which a plasma etching method according to an embodiment of the present invention is performed.
  • FIG. 3B is a schematic cross-sectional
  • FIG. 3D is a schematic cross-sectional view showing a fourth shape of the semiconductor substrate on which the plasma etching method of the embodiment of the present invention is performed.
  • FIG. 3E is a schematic cross-sectional view showing a fifth shape of the semiconductor substrate on which the plasma etching method of the embodiment of the present invention is performed.
  • FIG. 3F is a schematic cross-sectional view showing a sixth shape of the semiconductor substrate on which the plasma etching method of the embodiment of the present invention is performed.
  • FIG. 3G is a schematic cross-sectional view showing a seventh shape of the semiconductor substrate on which the plasma etching method of the embodiment of the present invention is performed.
  • FIG. 4 is a flowchart of dimensional control in the embodiment of the present invention.
  • FIG. 5 is a schematic configuration diagram showing a conventional plasma processing apparatus.
  • ECR electron cyclotron resonance
  • FIG. 1 is a schematic configuration diagram showing a plasma processing apparatus of the present embodiment.
  • the plasma processing apparatus includes a vacuum processing chamber 1 configured to be depressurized.
  • An object to be processed (hereinafter simply referred to as a semiconductor substrate) 4 such as a semiconductor substrate is placed on a lower electrode 3 provided in the vacuum processing chamber 1.
  • one semiconductor substrate 4 is placed on the lower electrode 3.
  • An upper electrode 6 is disposed at a position facing the lower electrode 3.
  • a process gas which is an etching gas, is introduced into the vacuum processing chamber 1 from a gas introduction device 5 that supplies a plurality of reactive gases connected to the side walls of the vacuum processing chamber 1 while changing the flow rates thereof.
  • the internal pressure of the vacuum processing chamber 1 is maintained at a predetermined pressure by the process gas exhaust adjustment of the vacuum exhauster 2.
  • the high frequency power supply 7 supplies high frequency power in the UHF band or VHF band to the upper electrode (plasma excitation electrode) 6 via the impedance matching unit 8.
  • a magnetic field is formed in the vacuum processing chamber 1 by the coil 12 disposed on the outer periphery of the vacuum processing chamber 1.
  • the plasma 13 is excited and held between the lower electrode 3 and the upper electrode 6 by the action of the high frequency power and the magnetic field.
  • the surface of the semiconductor substrate 4 is exposed to the plasma 13 thus excited, whereby the semiconductor substrate 4 is etched.
  • the high frequency power supply 11 is supplied with high frequency power in the UHF band or VHF band via the impedance matching unit 15 in order to generate a substrate bias potential to the lower electrode 3 on which the semiconductor substrate 4 is placed.
  • the plasma processing apparatus includes a measurement circuit 26 that measures a bias potential of the lower electrode 3 (hereinafter referred to as a lower bias potential) between the matching unit 15 and the lower electrode 3 during the plasma processing.
  • the measurement circuit 26 measures the lower bias potential by measuring a high frequency signal applied to the lower electrode 3 during plasma processing.
  • the plasma processing apparatus includes a measuring circuit 9 between the matching unit 8 and the upper electrode 6 that measures a bias potential of the upper electrode 6 (hereinafter referred to as an antenna bias potential) during the plasma processing.
  • the measurement circuit 9 measures the antenna bias potential by measuring a high frequency signal applied to the upper electrode 6 during plasma processing.
  • the measurement circuit 26 obtains the lower bias potential by obtaining at least one period of the high-frequency voltage applied to the lower electrode 3 and calculating the DC component of the high-frequency voltage.
  • the measurement circuit 26 acquires the lower bias potential in real time at a predetermined sampling period (for example, 1 Hz).
  • the lower bias potential indicates the potential of the lower electrode 3 with respect to the semiconductor substrate 4 during the plasma processing, and the ion energy in the plasma incident on the semiconductor substrate 4 is simply measured by the measurement.
  • the measurement circuit 9 measures the potential of the upper electrode 6 with respect to the inner wall of the vacuum processing chamber 1.
  • the plasma processing apparatus of this embodiment includes an emission spectral intensity measuring device 30 that can simultaneously measure the emission intensity of plasmas having different wavelengths. Thereby, the intensity
  • plasma light having different wavelengths is generated for each active species such as radicals and ions in the plasma 13, and the emission intensity of each plasma light is , Depending on the state of the corresponding active species (mainly ionic species density). Therefore, by measuring the emission intensity of each plasma light with the emission spectral intensity measuring device 30, the ion density of each ion in the plasma can be easily grasped.
  • the self-bias potential indicates a potential generated in the semiconductor substrate 4 during plasma processing, and by measuring the self-bias potential, ions of each ion species in the plasma incident on the semiconductor substrate 4 are measured. Energy can be easily grasped. The ion energy of each ion species becomes an equipment parameter indicating the amount of the ion species in the plasma.
  • the inventor of the present application paid attention to the fluctuation of equipment parameters having such characteristics. Then, by analyzing the fluctuations of the equipment parameters, we have obtained the knowledge that the current processing dimensions at the time of processing the semiconductor substrate by plasma can be known and the processing dimensions after the current time can be predicted.
  • the mutual emission intensity ratio in an inert gas group such as Ar in the plasma is measured, and the ion density of Cl + , F ⁇ and the like which are ion species of ion etching is grasped based on the emission intensity ratio.
  • the self-bias potential in the semiconductor substrate 4 or the like is measured, and the amount (ion energy) of each ion species in the plasma incident on the semiconductor substrate 4 is grasped based on the self-bias potential.
  • the self-bias potential measured for grasping the ion energy does not necessarily need to be measured on the semiconductor substrate 4, and may be measured on the side wall or the ceiling in the vacuum processing chamber 1.
  • the self-bias potential measured at these sites indicates the amount (ion energy) of each ion species incident on the chamber wall surface or the like.
  • a proportional relationship is established between the amount of each ion species incident on the chamber wall surface and the like and the amount of the ion species incident on the semiconductor substrate 4. It is possible to estimate the amount of ion species incident on 4.
  • plasma light having a wavelength corresponding to the radical of the element acting on the chemical reaction etching may be measured simultaneously. Then, the density of ion species in the plasma that affects the etching rate can be easily grasped. Thereby, it becomes possible to easily grasp the action of chemical reaction etching together with ion etching (plasma etching).
  • Chemical reaction etching acts as isotropic etching on the semiconductor substrate 4, while plasma etching acts as anisotropic etching. Therefore, if the quantitative ratio between the plasma etching and the chemical reaction etching is grasped through the measurement of the emission intensity ratio, which etching is isotropic etching or anisotropic etching in this etching process? It becomes possible to grasp whether it is dominant.
  • the degree of etching anisotropy that fluctuates according to the generation of the pattern side wall protective film based on the equipment parameters. That is, when a polymer starting from a substance such as CF 3 , SiCOx, SiO and carbide is formed as a deposit film during etching processing and formed on the etching side wall, the generated deposit film functions as a pattern side wall protective film. . Therefore, the amount of the polymer produced on the etching side wall varies the degree of etching anisotropy.
  • the amount of polymer production during etching can be predicted by grasping the density of each radical generated in the plasma through measurement of the emission intensity ratio. Therefore, the degree of etching anisotropy can be indirectly grasped by predicting the production amount of the polymer through measurement of the emission intensity ratio.
  • FIG. 2 shows an average value of the CD shift amount during etching of the oxide film (difference value between the dimension of the resist pattern formed in advance on the semiconductor substrate 4 and the dimension of each film type processed by plasma etching). It is a figure which shows the correlation between self-bias potential and the emitted light intensity of CF, O, and CO.
  • the self-bias potential and the emission intensity are the average value of the emission intensity for each ion species, and the bias potential (these are 1 (Obtained during one plasma treatment).
  • the average value is used as a value representing the self-bias potential and the emission intensity ratio, but a median value or the like may be used.
  • the CD shift amount uses a statistical value such as an average value of a plurality of points (here, 13 points in the plane) within the semiconductor substrate surface.
  • FIG. 2A shows the pattern dimensions of the semiconductor substrate 4 after the oxide film etching
  • FIGS. 2B, 2C, and 2D show CO, O, and CF, respectively.
  • FIG. 2 (e) shows the self-bias potential of the lower electrode 3 in which the emission intensity in the plasma of each ion species is normalized by the emission intensity of Ar.
  • the horizontal axis in FIG. 2 indicates the processing date of the semiconductor substrate 4.
  • ⁇ indicates the date and time when maintenance of the vacuum processing chamber 1 was performed
  • ⁇ indicates the actual measurement value of the dimension value
  • ⁇ indicates the calculated value of the dimension value
  • ⁇ indicates the predicted value of the dimension value. Show.
  • the actual measurement value ( ⁇ ) of the dimension value means the actual measurement value of the resist pattern
  • the calculated value ( ⁇ ) of the dimension value is a multiple regression from the self-bias value and the emission intensity ratio in the period A.
  • the calculated value calculated by fitting with an equation is the estimated value ( ⁇ ) of the dimension value, which is the value of the estimated dimension value of the period B in the multiple regression equation created in the period A.
  • the ratio of the emission intensity of each ion species and the self-bias potential of the lower electrode 3 are changed in the same manner as the trend of the dimension value. These data are shifted every time the vacuum vessel is internally cleaned by the maintenance of the vacuum processing chamber 1 five times in total. For these reasons, the state change in the vacuum processing chamber 1 due to the generation (attachment etc.) of the reaction product on the inner wall of the vacuum processing chamber 1 and the change in the plasma atmosphere due to the gas generated from these by-products 14 are emitted. This is linked to changes in the intensity ratio and the self-bias potential of the lower electrode 3.
  • the dimensional data in FIG. 2A is expressed using multiple regression equations for the emission intensity ratio of each ion species, the self-bias potential of the lower electrode 3, the emission intensity of all wavelengths, and the etching time using the data of period A. Then, the following formula (1) is obtained.
  • y a + V + b * X1 + c * X2 + d * X3 + e * X4 + f * Z1 + g * T
  • y indicates the dimension value after oxide film etching
  • V indicates the resist dimension value
  • X1 indicates the emission intensity ratio (CO / Ar)
  • X2 indicates the emission intensity ratio (O / Ar)
  • X3 indicates the emission intensity ratio (CF / Ar)
  • X4 indicates the emission intensity of all wavelengths
  • Z1 indicates Vpp (self-bias potential) T represents the etching processing time.
  • the predicted value ( ⁇ ) is changed to the actual measurement value ( ⁇ ) and calculated value ( ⁇ ) of the dimension value in period B in FIG.
  • the pattern dimension of the actual measurement value ( ⁇ ), the calculated value ( ⁇ ), and the predicted value ( ⁇ ) are almost the same, and it is confirmed that the dimension is sufficiently predicted. it can.
  • an oxide film is used as a predictive model in which dimensional changes are caused by etching.
  • a predictive model other film types to be etched, such as polysilicon, a high-k material film, and a metal to be etched may be used. In these other predictive models, the same as described above. By creating a multiple regression analysis model, pattern dimensions can be predicted.
  • the average value is used as a statistical value representing each parameter to be used (self-bias potential, emission intensity ratio, etc.).
  • the statistical value for each parameter to be used is one plasma treatment. What is necessary is just to calculate and use the representative value of each parameter measured inside. For example, a median value may be used instead of the average value.
  • the emission intensity of plasma has a peculiar peak wavelength for each ion species.
  • the above-described pattern dimensions are predicted on the assumption that the emission intensity of each ion species used for model creation of the present embodiment has the following peak wavelength for each ion species. . That is, the peak wavelength is 260 to 265 nm for CF, 515 to 520 nm for CO, 775 to 780 nm for O, and 415 to 420 nm for Ar.
  • the light emission generated in the plasma according to each ion species has a plurality of wavelengths.
  • the light emission according to Ar 415.8, 451.1, 484.8, 549.5, 603.2, 696.5, 706.7, 750.4 (nm )
  • Each have a wavelength. Therefore, in the plasma in which a plurality of ion species emit light simultaneously, there is a possibility that the emission wavelengths overlap in a plurality of ion species that need to be measured. Therefore, in this embodiment, the measurement wavelengths set for each of a plurality of ion species that need to be measured are set to wavelengths that do not overlap each other.
  • This control includes the function of the calculation unit 25, the function of the upper power control unit 28, the function of the lower power control unit 29, the function of the information processing device 31, the function of the production system 32, and the gas introduction amount control device 33. It is executed by the function.
  • FIG. 3A to 3G show the pattern shapes of the etching films in the respective steps of the manufacturing method of this embodiment for manufacturing a semiconductor film having a stacked structure such as a metal gate / High-k structure.
  • FIG. 4 shows a flow in the present embodiment.
  • FIG. 3A shows an example of a material to be etched having a laminated structure.
  • the material to be etched functions as a semiconductor substrate 47, a high-k material film 46, a metal material 45 such as titanium nitride, a gate electrode material 44 such as polysilicon, a lower resist material 43, and a hard mask.
  • An intermediate layer (made of silicon oxide, silicon nitride or the like) 42 and a resist material 41 patterned by ArF lithography technology or the like are provided.
  • a pattern is formed on the resist material 41 by ArF lithography technology or the like, and the created pattern dimension is measured by a dimension measuring instrument or the like.
  • the measured dimension value in the pattern of the resist material 41 after the lithography process is used as a calculated value ( ⁇ ) in the pattern of the resist material 41 after the etching process.
  • the calculated value ( ⁇ ) is a value that functions as a design value (preset value) for etching when calculating the etching dimension difference ( ⁇ - ⁇ ) after completion of etching.
  • the above-described etching dimension difference ( ⁇ ⁇ ) is calculated by comparing the predicted value ( ⁇ ) of the pattern, which is the result of predicting the shape after the etching process.
  • a plasma etching process is performed on the pattern of the resist material 41 described above.
  • This plasma etching process ⁇ Set the vacuum processing chamber 1 to a low pressure of about 0 to 10 mTorr. ⁇ Apply electric power of about 0 to 500W to the upper electrode 6. ⁇ No power is applied to the lower electrode 3; Introduce into the vacuum processing chamber 1 a mixed gas of halogen gas (Cl 2 etc.) and O 2 gas, or a mixed gas of organic halide gas (CHF 3 etc.) and O 2 gas. It is carried out while satisfying the above conditions.
  • the pattern dimension of the resist material 41 is controlled to a predetermined value. At that time, the pattern dimension is controlled by appropriately changing the etching time and the mixing ratio in the mixed gas. The reason why the dimensions of the resist material 41 can be controlled by changing these parameters is as follows.
  • the etching time is increased or the O 2 gas flow rate in the vacuum processing chamber 1 is increased and the O ion concentration is increased, the decomposition of the resist material 41 is promoted and the pattern dimension is reduced.
  • an organic halide gas (CHF 3 or the like) is used as a constituent gas of the above mixed gas, a reaction byproduct is generated when the amount of organic halide gas is increased to increase the C and H concentration in the vacuum processing chamber 1.
  • the size of the resist material 41 is apparently thickened. With such a control method, the pattern size of the resist material 41 can be controlled.
  • the ratio of the gas introduced into the vacuum processing chamber 1 and the conditions for the power applied to the upper and lower electrodes 3 and 6 are as follows: plasma etching in the resist material 41 of another semiconductor substrate 47 performed immediately before the current plasma etching process
  • the following data measured in the process (hereinafter referred to as the previous process) and the following data set in the plasma etching process (hereinafter referred to as the current process) of the resist material 41 of the semiconductor substrate 47 are set in advance. It is determined by substituting it into the model formula (formula (1) etc. described above) (step S62).
  • Step S62 is performed by an APC (Advanced Process Control) process.
  • APC processing is based on changes in parameters in equipment obtained by monitoring, grasping (estimating) the processing state of the semiconductor substrate 47, and controlling the recipe (processing conditions) of the apparatus to change the state of the semiconductor substrate 47. It is a form of production in which the production is controlled by always maintaining a constant state.
  • the emission intensity and self-bias potential of light emission generated in the plasma due to Cl ions, O ions, and CO ions are measured.
  • the measurement data and the dimension value data (calculated value ( ⁇ )) of the resist material 41 measured in step S51 are substituted into a preset model formula (formula (1), etc.).
  • various conditions in the plasma discharge are determined (step S62), and the resist material 41 is etched according to the determined conditions (step S52).
  • the emission intensity and the self-bias potential in light emission caused by Cl ions, O ions, and CO ions are further measured (step S63).
  • the dimension of the resist material 41 after the etching process is predicted by substituting the processing time and the data of the resist dimension value measured in advance into a preset model formula (formula (1), etc.) (step) S64).
  • the intermediate layer 42 made of silicon oxide, silicon nitride, or the like is performed using the resist material 41 after the etching process as a mask.
  • the intermediate layer 42 made of silicon oxide will be described as an example.
  • ⁇ Set the vacuum processing chamber 1 to a low pressure of about 0 to 10 mTorr.
  • ⁇ Apply electric power of about 0 to 500W to the upper electrode 6.
  • -A mixed gas composed of an organic halide gas (such as CF 4 or CHF 3 ) and O 2 gas is introduced into the vacuum processing chamber 1.
  • plasma discharge is generated in the vacuum processing chamber 1 to generate an ion assist reaction using ions and neutral radicals, thereby etching the intermediate layer 42.
  • the predicted dimension value ( ⁇ ) of the resist material 4 calculated after the etching process of the resist material 41 is compared with the calculated value ( ⁇ ) of the intermediate layer 42 set in advance, and the dimension difference ( ⁇ ⁇ ⁇ ) is calculated.
  • the following corrections are made so that the calculated dimensional difference ( ⁇ - ⁇ ) becomes a preset value.
  • the self-bias potential, Cl ion, O ion, and CO ion emission intensity values during the intermediate layer processing of the previous processing performed immediately before the current processing of the semiconductor substrate 47 and the intermediate layer plasma etching during the current processing By substituting the processing time in processing and the resist material dimension predicted value ( ⁇ ) into a preset model formula (formula (1), etc.), -Gas flow rate introduced into the vacuum processing chamber 1, High frequency power applied to the lower electrode 3 and the upper electrode 6; Is determined (step S65).
  • the etching time and the flow rate ratio (mixing ratio) in the mixed gas (organic halide gas + O 2 gas) are changed so that the dimension after etching of the intermediate layer 42 becomes a predetermined value.
  • control is performed to adjust the pattern shape variation of the intermediate layer 42 after etching and to reduce the dimension after etching.
  • a mixed gas of organic halide gas (CHF 3 or the like) and O 2 gas, H 2 gas, N 2 , He, or the like is applied without applying a bias potential to the lower electrode 3.
  • the emission intensity and the self-bias potential in light emission caused by F ions, CFx ions, O ions, CO ions, etc. are further measured (step S66). .
  • FIG. 3C plasma etching of the lower resist material 43 is performed.
  • ⁇ Set the vacuum processing chamber 1 to a low pressure of about 0 to 10 mTorr.
  • ⁇ Apply electric power of about 0 to 500W to the upper electrode 6.
  • Introducing into the vacuum processing chamber 1 a gas type similar to the processing with the resist material 41 or a mixed gas of CO 2 and an inert gas such as Ar.
  • plasma discharge is generated in the vacuum processing chamber 1, and an ion assist reaction using ions and neutral radicals is generated to etch the lower resist material 43 (step S54).
  • the predicted dimension value ( ⁇ ) of the intermediate layer 42 calculated after the etching of the intermediate layer 42 is compared with the preset pattern calculation value ( ⁇ ) of the lower layer resist material 43, and the dimensional difference ( ⁇ - ⁇ ) is calculated.
  • the following correction is performed so that the calculated dimension difference ( ⁇ - ⁇ ) becomes a preset dimension.
  • the etching time and the flow rate of the mixed gas so that the dimension after etching of the lower resist material 43 becomes a predetermined value.
  • control is performed to reduce the size of the lower layer resist material 43 after the etching process.
  • a mixed gas organic halide (CHF 3 or the like), O 2 gas is mixed
  • H 2 gas without applying a bias potential to the lower electrode 3 are used.
  • FIG. 3D plasma etching of the gate electrode material 44 is performed.
  • ⁇ Set the vacuum processing chamber 1 to a low pressure of about 0 to 10 mTorr.
  • ⁇ Apply electric power of about 0 to 500W to the upper electrode 6.
  • the gate electrode material 44 (polysilicon film) is etched to about 80% of its film thickness.
  • the predicted size ( ⁇ ) of the lower resist material 43 calculated after the etching of the lower resist material 43 is compared with the preset calculated value ( ⁇ ) of the gate electrode material 44, and the dimensional difference ( ⁇ - ⁇ ) is calculated.
  • the following corrections are made so that the calculated dimensional difference ( ⁇ - ⁇ ) becomes a preset dimension.
  • the etching time and the flow rate ratio (mixing ratio) of each gas type (Cl 2 , HBr, CF 4 , O 2, etc.) so that the dimension after etching of the gate electrode material 44 becomes a predetermined value.
  • the bias power applied to the lower electrode 3 are controlled to reduce the size of the gate electrode material 44 after the etching process.
  • a mixed gas of organic halide (CHF 3 or the like) and O 2 gas, H 2 gas, or N 2 , He is applied without applying a bias potential to the lower electrode 3.
  • An organic polymer material is generated by generating a plasma discharge in the vacuum processing chamber 1 again in a state where an inert gas such as is introduced into the vacuum processing chamber 1, and a by-product made of the organic polymer material is formed in the lower resist material 43. It adheres to a side wall part and the side wall part of the intermediate
  • the emission intensity and self-bias potential in the light emission caused by each ion species such as organic halide (H, Br, CF, etc.), halide (F, etc.), O, CO, etc. Measurement is performed (step S72).
  • step S73 By substituting the processing time and the predicted dimension value ( ⁇ ) of the lower resist material 43 calculated by the above-described method (step S70) into a preset model formula (formula (1), etc.), after plasma etching The processing dimension after etching of the gate electrode material 44 is predicted (step S73).
  • the gate electrode material 44 remaining after the etching process is referred to as the remaining gate electrode material 44 ′ and is distinguished from the gate electrode material 44.
  • the vacuum processing chamber 1 is made into a low-pressure state, although power is also applied to the lower electrode 3, the power applied to the upper electrode 3 or the lower electrode 6 is set to be lower than that of the plasma etching process of the gate electrode material 44 performed earlier.
  • the predicted size ( ⁇ ) of the gate electrode material 44 calculated after the etching of the remaining gate electrode material 44 ′ and a preset gate
  • the calculated value ( ⁇ ) of the electrode material 44 is compared, and the dimensional difference ( ⁇ - ⁇ ) is calculated. The following corrections are made so that the calculated dimensional difference ( ⁇ - ⁇ ) becomes a preset dimension.
  • the bias power applied to the lower electrode 6 are controlled to reduce the dimension of the gate electrode material 44 after the etching process.
  • a mixed gas of organic halide (CHF 3 or the like) and O 2 gas, H 2 gas, or inert without applying a bias potential to the lower electrode 6
  • the gas (N 2 , He, etc.) introduced into the vacuum processing chamber 1 plasma discharge is generated again in the vacuum processing chamber 1 to generate an organic polymer material, and a by-product made of the organic polymer material is generated. It is made to adhere to the side wall part of the lower layer resist material 43 and the side wall part of the intermediate layer 42. Thereby, the etching dimension is controlled to become thicker.
  • the etching conditions are changed so that the gate electrode material 44 has a predetermined size and a vertical shape, and an etching process is performed (step S56).
  • Step S75 Measurement of emission intensity and self-bias potential in light emission caused by ion species such as H, Br, organic halides (CF, etc.), halides (F, etc.), O, CO, etc. during processing of the gate electrode material 44 (Step S75).
  • ion species such as H, Br, organic halides (CF, etc.), halides (F, etc.), O, CO, etc.
  • FIG. 3F plasma etching of the metal material film 45 is performed.
  • ⁇ Set the vacuum processing chamber 1 to a low pressure of about 0 to 10 mTorr.
  • ⁇ Apply electric power of about 0 to 150W to the upper electrode 6.
  • plasma discharge is generated in the vacuum processing chamber 1, and an ion assist reaction using ions and neutral radicals is generated to etch the metal material film 45 (step S57).
  • the estimated dimension value ( ⁇ ) of the gate electrode material 44 calculated after the etching of the gate electrode material 44 is compared with a preset calculated value ( ⁇ ) of the metal material film 45, and the dimension difference ( ⁇ - ⁇ ) is calculated.
  • the following correction is performed so that the calculated dimension difference ( ⁇ - ⁇ ) becomes a preset dimension.
  • the self-bias potential during processing and the emission intensity in light emission caused by ion species such as Cl, O, and CO are measured (step S78), and these measured values and metal material film plasma etching in this processing are measured.
  • Plasma etching is performed by substituting the processing time of the processing and the predicted size ( ⁇ ) of the gate electrode material 44 calculated by the above-described method (step S76) into a preset model formula (formula (1), etc.).
  • a processing dimension of the metal material film 45 after processing is predicted (step S77).
  • the organic halide (CHF 3) is applied without applying a bias potential to the lower electrode 3 after the etching of the metal material film 45 so that the pattern dimension after the etching of the metal material film 45 becomes a predetermined value.
  • Etc. a mixed gas of O 2 gas, H 2 , inert gas (N 2 , He, etc.) is introduced into the vacuum processing chamber 1, and plasma discharge is generated again in the vacuum processing chamber 1, thereby organic A polymer material is generated, and a by-product made of the organic polymer material is attached to the side wall portion of the metal material film 45.
  • the metal material film 45 is controlled to have a predetermined size by performing control such that the etching size of the metal material film 45 is apparently thickened.
  • the emission intensity and the self-bias potential in the luminescence generated due to the ion species such as Cl, O, and CO are measured (step S78).
  • Vacuum processing chamber 1 is in a low pressure state of about 0-100mTorr.
  • ⁇ Apply electric power of 0-1500W to the upper electrode 6.
  • plasma discharge is generated in the vacuum processing chamber 1, and an ion-assisted reaction using ions and neutral radicals is generated to etch the high-k material film 46 (step S58).
  • step S80 the self-bias potential during the etching process of the high-k material film 46 and the luminescence intensity in the luminescence caused by B ions, Cl ions, CO ions, etc. are measured (step S80).
  • step S57 the predicted dimension value of the metal material film 45 calculated by the above-described method
  • step S81 the processing dimension of the k material film 46 is predicted (step S81).
  • the dimension difference value ( ⁇ - ⁇ ) was calculated by comparing the predicted dimension value ( ⁇ ) after processing with a preset calculation value ( ⁇ ).
  • the predicted size data of the high-k material film 46 eg, the size difference ( ⁇ - ⁇ )
  • the processing dimensional accuracy of the high-k material film 46 can be further improved.
  • polysilicon is used as the gate electrode material 44.
  • the present invention is not limited to this, and other examples include TiSi, CoSi, PtSi, NiSi, and WSi.
  • Ti nitride is exemplified as the metal material film 45, but the present invention is not limited to this, and other examples include metals such as W, Ta, Pt, Ni, Co, and Al or alloys thereof. .
  • a program command is expressed by an electrical signal, an optical signal, a magnetic signal, etc.
  • the program is provided on a transmission medium such as a coaxial cable, copper wire, or optical fiber by transmitting the signal on a carrier wave.
  • a computer-readable recording medium optical media such as CD-ROM and DVD-ROM, magnetic media such as a flexible disk, and semiconductor memory such as flash memory and RAM can be used.
  • the present invention provides plasma processing that stably controls processing into a vertical shape with high base film selectivity when a gate electrode material composed of a plurality of layers including a metal material or a high-k material is dry-etched. Useful as a method.

Abstract

Provided is a plasma treatment method including a first step for determining the changes over time in the status of the plasma with each plasma etching treatment of a film, and a second step for estimating the finished shape of the film on the basis of the distribution of the ion energy to which the object to be treated is exposed and the density of each type of ion in the plasma with each plasma etching treatment of the film, and then controlling the bias power and etching gas mixture ratio such that the estimation results become a predetermined worked shape.

Description

プラズマ処理方法およびプラズマ処理装置Plasma processing method and plasma processing apparatus
　本発明は、多層膜構造を有する半導体装置の製造方法に関し、特にメタルゲート/高誘電率膜の多層膜構造を有する半導体装置における微細構造の加工に関する。さらに具体的には、半導体装置におけるゲート電極形成を行うプラズマ処理方法およびプラズマ処理装置と、その処理シーケンスの制御プログラムに関する。以下、高誘電率材料膜をＨｉｇｈ－ｋ材膜と称する。 The present invention relates to a method for manufacturing a semiconductor device having a multilayer film structure, and more particularly to processing of a fine structure in a semiconductor device having a multilayer film structure of a metal gate / high dielectric constant film. More specifically, the present invention relates to a plasma processing method and plasma processing apparatus for forming a gate electrode in a semiconductor device, and a control program for the processing sequence. Hereinafter, the high dielectric constant material film is referred to as a High-k material film.
　近年、プラズマ処理は、微細加工,薄膜形成等の用途として、特に超高集積回路装置を製造する上で必要不可欠な技術となっている。特に、半導体装置の微細化に伴い、レジストの膜厚がより薄くなってきている状況においてプラズマ処理は半導体装置の製造方法において必要性が高まっている。 In recent years, plasma processing has become an indispensable technique for manufacturing ultra-high integrated circuit devices, particularly for applications such as microfabrication and thin film formation. In particular, with the miniaturization of semiconductor devices, the need for plasma treatment in semiconductor device manufacturing methods is increasing in situations where the resist film thickness is becoming thinner.
　またＭＯＳトランジスタの微細化によりそのトランジスタ構造は、酸化絶縁膜をＨｉｇｈ－ｋ材膜に、ゲート電極をポリシリコンのみからメタルゲート膜にそれぞれ変更してなるメタルゲート/Ｈｉｇｈ－ｋ材膜の多層膜積層構造に変わってきている。そのような構造変更を受けて、今後半導体装置の製造方法では、より複雑な多層膜エッチング技術が必要とされると考えられる。例えば、メタルゲート/Ｈｉｇｈ－ｋ材膜の多層膜構造を有する半導体装置の加工においては、エッチングされる被エッチング膜は、マスクとなる上層の膜に対する高い選択性と、高い垂直形状精度が要求される。このようなトランジスタ構造の製造方法においてプラズマ処理は必須となっており、さらには、ゲート電極形成工程等に最適となるプラズマエッチング処理方法およびプラズマエッチング処理装置が要望されている。 Further, by miniaturization of MOS transistors, the transistor structure is a multi-layer film of metal gate / high-k material film in which the oxide insulating film is changed to a high-k material film and the gate electrode is changed from only polysilicon to a metal gate film. It has changed to a laminated structure. In view of such a structural change, it is considered that a more complicated multilayer film etching technique will be required in the semiconductor device manufacturing method in the future. For example, in the processing of a semiconductor device having a multilayer structure of metal gate / High-k material film, a film to be etched requires high selectivity with respect to the upper film serving as a mask and high vertical shape accuracy. The In such a transistor structure manufacturing method, plasma processing is indispensable, and further, there is a demand for a plasma etching processing method and a plasma etching processing apparatus that are optimal for a gate electrode formation process and the like.
　ドライエッチング処理の加工原理は、電磁波で反応性ガスをプラズマ化し、生じたイオンと中性ラジカルを用いたイオンアシスト反応によりエッチングを行うというものである。このようなドライエッチング加工を具現化したプラズマ処理装置は、プラズマ発生機構と、反応性ガス導入機構と、圧力制御機構と、Ｓｉ半導体基板を設置するための下部電極機構と、それらの動作制御機構とを備える。 The processing principle of the dry etching process is that the reactive gas is converted into plasma by electromagnetic waves, and etching is performed by an ion-assisted reaction using the generated ions and neutral radicals. A plasma processing apparatus embodying such dry etching processing includes a plasma generation mechanism, a reactive gas introduction mechanism, a pressure control mechanism, a lower electrode mechanism for installing a Si semiconductor substrate, and an operation control mechanism thereof. With.
　以上のような機構を持つプラズマ処理装置を用いて、イオンエネルギ分布（Ion Energy Distribution Function；ＩＥＤＦ）を把握する方法（すなわちセルフバイアス電位の測定およびそれを制御する方法）として、印加するバイアスの電力または周波数を制御する方法がある。 As a method for grasping the ion energy distribution (Ion Energy Distribution Function; IEDF) using the plasma processing apparatus having the above-described mechanism (that is, a method for measuring and controlling the self-bias potential), the bias power to be applied. Or there is a method of controlling the frequency.
　図５は、特許文献１にその構造が開示される従来のプラズマ処理装置の一例を示す概略構成図である。このプラズマ処理装置は、減圧可能に構成された真空処理室１０１を備える。被処理物（半導体基板）１０４は、真空処理室１０１内に設けられた下部電極１０３上に載置される。下部電極１０３と対向する位置には、上部電極１０６が設けられる。 FIG. 5 is a schematic configuration diagram showing an example of a conventional plasma processing apparatus whose structure is disclosed in Patent Document 1. In FIG. This plasma processing apparatus includes a vacuum processing chamber 101 configured to be decompressed. A workpiece (semiconductor substrate) 104 is placed on a lower electrode 103 provided in the vacuum processing chamber 101. An upper electrode 106 is provided at a position facing the lower electrode 103.
　このプラズマ処理装置による被処理物１０４のドライエッチング処理は次のようにして実施される。すなわち、まず真空処理室１０１内にガス導入部１０５からエッチングガス（プロセスガス）が導入される。このとき、真空処理室１０１の内圧は、真空排気器１０２のプロセスガス排気調整によって所定圧に維持される。当該状態で、例えば、高周波電源１０７が整合器１０８を介して上部電極１０６に高周波電力を印加すると、下部電極１０３と上部電極１０６との間で発生する電界によりプラズマが発生する。そして、高周波電源１１１が整合器１１５を介して下部電極１０３に高周波電力を印加すると、当該プラズマに曝された被処理物１０４は、プラズマの作用によりエッチングされる。このときのバイアス電力のセルフバイアス電位をモニタ１２６で測定し、その測定値に基づいて処理条件演算部１２５が次の被処理物１０４の処理条件の演算を行ったうえで、印加電力制御部１２８が高周波電力によって被処理物１０４に入射するプラズマ中のイオンエネルギ分布を調節する。イオンエネルギ分布の調節を行いながらエッチング処理が進行する被処理物処理１０４で得られる各種データに基づいて、エッチング後の被処理物１０４の形状を予測し、その予測に基づいてエッチング処理時におけるバイアス印加装置による印加電力および印加周波数の最適値を決定し、さらに決定した最適値に基づいて次の被処理物１０４の処理条件を変更する。このドライエッチング方法によれば、段差を有する膜構造においても高精度にエッチング処理を実施することができる。 The dry etching process of the workpiece 104 by this plasma processing apparatus is performed as follows. That is, first, an etching gas (process gas) is introduced from the gas introduction unit 105 into the vacuum processing chamber 101. At this time, the internal pressure of the vacuum processing chamber 101 is maintained at a predetermined pressure by the process gas exhaust adjustment of the vacuum exhaust device 102. In this state, for example, when the high frequency power source 107 applies high frequency power to the upper electrode 106 via the matching unit 108, plasma is generated by an electric field generated between the lower electrode 103 and the upper electrode 106. When the high frequency power source 111 applies high frequency power to the lower electrode 103 via the matching unit 115, the workpiece 104 exposed to the plasma is etched by the action of the plasma. The self-bias potential of the bias power at this time is measured by the monitor 126, and the processing condition calculation unit 125 calculates the processing condition of the next workpiece 104 based on the measured value, and then the applied power control unit 128. Adjusts the ion energy distribution in the plasma incident on the workpiece 104 by the high frequency power. The shape of the workpiece 104 after etching is predicted based on various data obtained in the workpiece processing 104 in which the etching processing proceeds while adjusting the ion energy distribution, and the bias during the etching processing is based on the prediction. The optimum values of the applied power and the applied frequency by the applying device are determined, and the processing conditions for the next workpiece 104 are changed based on the determined optimal values. According to this dry etching method, the etching process can be performed with high accuracy even in a film structure having a step.
特開２００８－２４４４２９号JP 2008-244429 A
　従来の技術によれば、モニタしたセルフバイアス電位の測定値に基づいて被処理物１０４に衝突させるイオンの量を間接的に把握することができる。しかしながら、メタルゲート/Ｈｉｇｈ－ｋ構造のような積層構造の半導体膜を有する被処理物１０４では、エッチング時に、異なる膜種の処理を行うため、メタル,有機物,Ｓｉポリマ等の様々な副生成物１１４が、チャンバ壁面に付着することになる。そのため、これら副生成物１１４によるチャンバのインピーダンス変化および、副生成物１１４からのデガス等により、チャンバ内へ供給されるガス種（酸素やフッ素成分）の変化によってプラズマ中の各イオン種の密度が変化することが想定される。しかしながら、セルフバイアス電位の測定情報だけでは、これらイオン種の密度変化を把握することは困難である。つまりセルフバイアス電位の測定値情報だけでは、被処理物１０４に衝突させるイオンの量を間接的に把握することができるものの、エッチング中のチャンバ内の各イオン種密度を、正確に把握することができない。そのため被処理物（半導体基板）１０４の寸法の予測および制御を正確に行うことは困難であると推測される。 According to the conventional technique, it is possible to indirectly grasp the amount of ions colliding with the workpiece 104 based on the measured value of the monitored self-bias potential. However, in the object to be processed 104 having a semiconductor film having a laminated structure such as a metal gate / high-k structure, various types of by-products such as metal, organic matter, Si polymer, etc. are processed because different types of film are processed during etching. 114 will adhere to the chamber wall. Therefore, the density of each ion species in the plasma is changed by the change in the gas species (oxygen and fluorine components) supplied into the chamber due to the impedance change of the chamber due to these by-products 114 and the degas from the by-products 114. It is expected to change. However, it is difficult to grasp the density change of these ion species only by the measurement information of the self-bias potential. That is, only the measured value information of the self-bias potential can indirectly grasp the amount of ions colliding with the workpiece 104, but can accurately grasp the density of each ion species in the chamber during etching. Can not. Therefore, it is estimated that it is difficult to accurately predict and control the dimension of the workpiece (semiconductor substrate) 104.
　また従来の技術では、一枚の半導体基板処理時に得られたセルフバイアス電位の測定情報に基づいて、次に処理を行う半導体基板１０４の処理条件を変更している。そのため、最初（一枚目）に処理される半導体基板１０４については、フィードバックすべき情報がないため、予め設定された補正情報のない処理条件で加工を行わなければならず、エッチング加工されたものの寸法および形状が、所定の寸法および形状と異なり、すそ引き形状（エッチング側面が垂直に立ち上がることなく斜めに傾斜した形状）等に仕上がる可能性があるという課題がある。 In the conventional technique, the processing conditions of the semiconductor substrate 104 to be processed next are changed based on the measurement information of the self-bias potential obtained at the time of processing one semiconductor substrate. Therefore, since there is no information to be fed back for the first (first) processed semiconductor substrate 104, processing must be performed under processing conditions without preset correction information. Unlike the predetermined size and shape, there is a problem that the size and shape may be finished in a soaking shape (a shape in which the etching side surface is slanted without rising vertically).
　本発明は、上記従来の事情を鑑みて提案されたものであって、下地膜選択性が高く垂直な形状への加工を安定に制御できるプラズマ処理方法またはプラズマ処理装置を提供することを主たる目的としている。 The present invention has been proposed in view of the above-described conventional circumstances, and it is a main object of the present invention to provide a plasma processing method or a plasma processing apparatus capable of stably controlling processing into a vertical shape with high base film selectivity. It is said.
　上記課題を解決するために、本発明は以下の技術的手段を採用している。 In order to solve the above problems, the present invention employs the following technical means.
　本発明は、
　積層膜を表面に有する被処理物を真空処理室内の下部電極上に載置したうえで、前記被処理物にバイアス電位を形成するためのバイアス電力を前記真空処理室に供給しながら、当該真空処理室に複数のガスを含むエッチングガスを供給することで前記比処理物上にプラズマを発生させ、かつ前記エッチングガスの混合比と、前記バイアス電力とを適宜調整することで、前記積層膜を構成する膜それぞれに適した状態に前記プラズマを調整しつつ前記膜を膜毎にプラズマエッチング処理するプラズマ処理方法であって、
　前記膜のプラズマエッチング処理毎に、前記プラズマの状態の時間変化を検知する第１の工程と、
　前記膜のプラズマエッチング処理毎に、前記被処理物上に入射するイオンエネルギ分布と前記プラズマ中の各イオン種の密度とに基づいて前記膜の加工形状を予測したうえで、その予測結果が所望加工形状になるように前記バイアス電力と前記エッチングガスの混合比とを制御する第２の工程と、
　を含む。 The present invention
The workpiece having the laminated film on the surface is placed on the lower electrode in the vacuum processing chamber, and the vacuum power is supplied to the vacuum processing chamber while supplying bias power for forming a bias potential to the workpiece. By supplying an etching gas containing a plurality of gases into the processing chamber, plasma is generated on the specific processing object, and the mixing ratio of the etching gas and the bias power are adjusted as appropriate, whereby the stacked film is formed. A plasma processing method for plasma-etching the film for each film while adjusting the plasma to a state suitable for each of the films to be configured;
A first step of detecting a time change of the plasma state for each plasma etching treatment of the film;
For each plasma etching process of the film, the processing shape of the film is predicted based on the distribution of ion energy incident on the object to be processed and the density of each ion species in the plasma. A second step of controlling the mixing ratio of the bias power and the etching gas so as to obtain a processed shape;
including.
　本発明には、以下の態様がある。すなわち、
　前記第２の工程は、
　前記真空処理室の内壁と前記プラズマとの間の電荷量に応じて変動する物理量と、前記エッチングガスに基づく各イオン種に起因して前記プラズマ内で生じる発光の発光強度とを測定する測定工程と、
　前記測定工程の測定結果を、あらかじめ設定しておいたモデル式に代入することで、前記膜の前記加工形状を予測する予測工程と、
　をさらに含む。 The present invention has the following aspects. That is,
The second step includes
A measurement step of measuring a physical quantity that varies according to an amount of electric charge between the inner wall of the vacuum processing chamber and the plasma, and an emission intensity of light emission generated in the plasma due to each ion species based on the etching gas. When,
By substituting the measurement result of the measurement step into a model equation set in advance, a prediction step of predicting the processed shape of the film,
Further includes.
　この態様によれば、例えば、まず真空処理室内壁と真空処理室内に生成されたプラズマとの間の電荷量に応じて変動する物理量を取得する。さらに、プラズマ中で発生している各イオン種に応じて変動する、各イオン種特有の波長の発光強度を物理量として取得する。得られた物理量(セルフバイアス電位かプラズマ中の各イオン種の発光強度、又は発光強度比)を平均値や中央値等の統計値として算出し、統計値からメタルやＨｉｇｈ－ｋおよび酸化膜やポリシリコン等の各膜種のエッチング処理毎に、エッチング後のパターン寸法を予め設定されたモデルにより計算（予測）する。計算された寸法値を元に、予め設定されているモデルにて、被処理物が予め設定されている加工寸法となるように、同一チャンバで連続して行う次の層のエッチング条件(ガス流量の混合比、バイアス印加電力)を算出する。前述の方法にて算出されたエッチング条件を元に、次の層加工時のエッチングを行う。 According to this aspect, for example, first, a physical quantity that varies in accordance with the amount of charge between the vacuum processing chamber wall and the plasma generated in the vacuum processing chamber is acquired. Furthermore, the emission intensity of a wavelength peculiar to each ion species, which varies depending on each ion species generated in the plasma, is acquired as a physical quantity. The obtained physical quantity (self-bias potential or emission intensity of each ion species in the plasma, or emission intensity ratio) is calculated as a statistical value such as an average value or a median value, and from the statistical values, metal, high-k, oxide film, For each etching process of each film type such as polysilicon, the pattern dimension after etching is calculated (predicted) by a preset model. Based on the calculated dimension value, the etching conditions (gas flow rate) of the next layer continuously performed in the same chamber so that the workpiece has a preset processing dimension in a preset model. The mixing ratio and the bias applied power) are calculated. Based on the etching conditions calculated by the above-described method, etching for the next layer processing is performed.
　本発明は、上述のプラズマ処理方法の手順をコンピュータに実行させるプログラムが記録された記録媒体として提供することもできる。 The present invention can also be provided as a recording medium on which a program for causing a computer to execute the procedure of the plasma processing method described above is recorded.
　本発明によれば、多層レジストや、メタルゲート/Ｈｉｇｈ－ｋ等からなる積層膜を一つの加工設備で連続エッチング加工する場合において、その加工形状または加工寸法を、予め設定されたモデルに従って膜種毎に推定し、さらに同様のモデルを用いて次の積層膜処理条件を算出することが可能になる。そのため、次の膜種のエッチング処理時において、先に算出しておいた処理条件をフィードバック情報としてプラズマエッチング装置の制御部に供与しながらエッチング加工を行うことが可能となる。これにより、各膜種のエッチング毎に加工寸法や形状の補正を行って常に同じ加工精度でエッチング処理を行うことが、エッチング後の寸法測定という面倒な工程を踏むことなく可能となる。 According to the present invention, when a multi-layered resist or a laminated film made of metal gate / High-k or the like is continuously etched by one processing facility, the processing shape or processing dimension is determined according to a preset model. It is possible to calculate the next laminated film processing condition by using the same model. Therefore, at the time of the etching process of the next film type, it is possible to perform the etching process while supplying the previously calculated processing conditions as feedback information to the control unit of the plasma etching apparatus. Thus, it is possible to always perform the etching process with the same processing accuracy by correcting the processing dimension and shape for each etching of each film type, without going through the troublesome process of measuring the dimension after etching.
　また、真空処理室壁へデポ物を多く付着させるガス種(HBr,CHF3)やエッチングするガス種（Cl）等が混在するエッチング条件により、真空処理室内のパーツおよび側壁デポ物の変化による、側壁部からのエッチャントの変化で、被処理物の加工の形状制御が経時変化するような場合であっても、各層の寸法等の変動を最小限に抑えることができる。 In addition, due to the etching conditions in which gas species (HBr, CHF 3 ) and gas species to be etched (Cl) that attach a lot of deposits to the vacuum processing chamber wall are mixed, due to changes in parts and sidewall deposits in the vacuum processing chamber, Even when the shape control of the processing of the object to be processed changes with time due to the change of the etchant from the side wall, the variation of the dimensions of each layer can be minimized.
図１は本発明の実施形態におけるプラズマ処理装置を示す概略構成図である。FIG. 1 is a schematic configuration diagram showing a plasma processing apparatus in an embodiment of the present invention. 図２は本発明の実施形態におけるエッチング後の寸法と、エッチング時のバイアス電位および発光強度の平均値との関係を示す図である。FIG. 2 is a diagram showing the relationship between the dimension after etching and the average value of the bias potential and the emission intensity during etching in the embodiment of the present invention. 図３Ａは本発明の実施形態のプラズマエッチング方法を実施した半導体基板の第１の形状を示す概略断面図である。FIG. 3A is a schematic cross-sectional view showing a first shape of a semiconductor substrate on which a plasma etching method according to an embodiment of the present invention is performed. 図３Ｂは本発明の実施形態のプラズマエッチング方法を実施した半導体基板の第２の形状を示す概略断面図である。FIG. 3B is a schematic cross-sectional view showing a second shape of the semiconductor substrate on which the plasma etching method of the embodiment of the present invention is performed. 図３Ｃは本発明の実施形態のプラズマエッチング方法を実施した半導体基板の第３の形状を示す概略断面図である。FIG. 3C is a schematic cross-sectional view showing a third shape of the semiconductor substrate on which the plasma etching method of the embodiment of the present invention is performed. 図３Ｄは本発明の実施形態のプラズマエッチング方法を実施した半導体基板の第４の形状を示す概略断面図である。FIG. 3D is a schematic cross-sectional view showing a fourth shape of the semiconductor substrate on which the plasma etching method of the embodiment of the present invention is performed. 図３Ｅは本発明の実施形態のプラズマエッチング方法を実施した半導体基板の第５の形状を示す概略断面図である。FIG. 3E is a schematic cross-sectional view showing a fifth shape of the semiconductor substrate on which the plasma etching method of the embodiment of the present invention is performed. 図３Ｆは本発明の実施形態のプラズマエッチング方法を実施した半導体基板の第６の形状を示す概略断面図である。FIG. 3F is a schematic cross-sectional view showing a sixth shape of the semiconductor substrate on which the plasma etching method of the embodiment of the present invention is performed. 図３Ｇは本発明の実施形態のプラズマエッチング方法を実施した半導体基板の第７の形状を示す概略断面図である。FIG. 3G is a schematic cross-sectional view showing a seventh shape of the semiconductor substrate on which the plasma etching method of the embodiment of the present invention is performed. 図４は本発明の実施形態における寸法制御のフローチャートである。FIG. 4 is a flowchart of dimensional control in the embodiment of the present invention. 図５は従来のプラズマ処理装置を示す概略構成図である。FIG. 5 is a schematic configuration diagram showing a conventional plasma processing apparatus.
　以下、本発明の実施形態について、図面を参照して詳細に説明する。以下の実施形態では、ＥＣＲ（電子サイクロトロン共鳴）型のドライエッチング装置により、本発明を具体化している。 Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. In the following embodiments, the present invention is embodied by an ECR (electron cyclotron resonance) type dry etching apparatus.
　以下、本発明に係る実施形態を、図１,図２,図３Ａ～図３Ｇ,図４を参照して詳細に説明する。図１は、本実施形態のプラズマ処理装置を示す概略構成図である。このプラズマ処理装置は、減圧可能に構成された真空処理室１を備える。半導体基板等の被処理物（以下、単に半導体基板という）４は、真空処理室１内に設けられた下部電極３上に載置される。本実施形態では、下部電極３上に、１枚の半導体基板４が載置される構成になっている。 Hereinafter, embodiments according to the present invention will be described in detail with reference to FIGS. 1, 2, 3A to 3G, and 4. FIG. FIG. 1 is a schematic configuration diagram showing a plasma processing apparatus of the present embodiment. The plasma processing apparatus includes a vacuum processing chamber 1 configured to be depressurized. An object to be processed (hereinafter simply referred to as a semiconductor substrate) 4 such as a semiconductor substrate is placed on a lower electrode 3 provided in the vacuum processing chamber 1. In the present embodiment, one semiconductor substrate 4 is placed on the lower electrode 3.
　下部電極３と対向する位置には、上部電極６が配置される。真空処理室１へは、真空処理室１の側壁に接続された複数の反応ガスの流量を変更して供給するガス導入器５からエッチングガスであるプロセスガスが導入される。このとき、真空処理室１の内圧は、真空排気器２のプロセスガス排気調整によって所定圧に維持される。当該状態で、高周波電源７がインピーダンス整合器８を介して上部電極（プラズマ励起電極）６へＵＨＦ帯やＶＨＦ帯の高周波電力を供給する。このとき、真空処理室１の外周に配設されたコイル１２により真空処理室１内に磁場が形成される。すると高周波電力と磁場との作用により、下部電極３と上部電極６との間にプラズマ１３が励起されて保持される。このようにして励起されたプラズマ１３に半導体基板４の表面が曝されることにより、半導体基板４のエッチング処理が行われる。なおプラズマ処理中、半導体基板４を載置した下部電極３には、基板バイアス電位を発生させるために、高周波電源１１がＵＨＦ帯やＶＨＦ帯の高周波電力が、インピーダンス整合器１５を介して供給される。 An upper electrode 6 is disposed at a position facing the lower electrode 3. A process gas, which is an etching gas, is introduced into the vacuum processing chamber 1 from a gas introduction device 5 that supplies a plurality of reactive gases connected to the side walls of the vacuum processing chamber 1 while changing the flow rates thereof. At this time, the internal pressure of the vacuum processing chamber 1 is maintained at a predetermined pressure by the process gas exhaust adjustment of the vacuum exhauster 2. In this state, the high frequency power supply 7 supplies high frequency power in the UHF band or VHF band to the upper electrode (plasma excitation electrode) 6 via the impedance matching unit 8. At this time, a magnetic field is formed in the vacuum processing chamber 1 by the coil 12 disposed on the outer periphery of the vacuum processing chamber 1. Then, the plasma 13 is excited and held between the lower electrode 3 and the upper electrode 6 by the action of the high frequency power and the magnetic field. The surface of the semiconductor substrate 4 is exposed to the plasma 13 thus excited, whereby the semiconductor substrate 4 is etched. During the plasma processing, the high frequency power supply 11 is supplied with high frequency power in the UHF band or VHF band via the impedance matching unit 15 in order to generate a substrate bias potential to the lower electrode 3 on which the semiconductor substrate 4 is placed. The
　プラズマ処理装置は、プラズマ処理中に下部電極３のバイアス電位（以下、下部バイアス電位という。）を計測する測定回路２６を、整合器１５と下部電極３との間に備えている。測定回路２６は、プラズマ処理中の下部電極３に印加される高周波信号を計測することにより、下部バイアス電位を計測する。同様に、プラズマ処理装置は、プラズマ処理中に上部電極６のバイアス電位（以下、アンテナバイアス電位という）を計測する測定回路９を、整合器８と上部電極６との間に備えている。測定回路９は、プラズマ処理中の上部電極６に印加される高周波信号を計測することにより、アンテナバイアス電位を計測する。 The plasma processing apparatus includes a measurement circuit 26 that measures a bias potential of the lower electrode 3 (hereinafter referred to as a lower bias potential) between the matching unit 15 and the lower electrode 3 during the plasma processing. The measurement circuit 26 measures the lower bias potential by measuring a high frequency signal applied to the lower electrode 3 during plasma processing. Similarly, the plasma processing apparatus includes a measuring circuit 9 between the matching unit 8 and the upper electrode 6 that measures a bias potential of the upper electrode 6 (hereinafter referred to as an antenna bias potential) during the plasma processing. The measurement circuit 9 measures the antenna bias potential by measuring a high frequency signal applied to the upper electrode 6 during plasma processing.
　例えば、測定回路２６は、下部電極３に印加されている高周波電圧を少なくとも１周期分取得し、当該高周波電圧の直流成分を算出することにより、下部バイアス電位を取得する。測定回路２６は、下部バイアス電位の取得を所定のサンプリング周期（例えば１Ｈｚ）で、リアルタイムに行う。なお、下部バイアス電位は、プラズマ処理中の半導体基板４に対する下部電極３の電位を示し、その測定によって、半導体基板４に入射するプラズマ中のイオンエネルギが簡易的に測定されることになる。同様に測定回路９では真空処理室１の内壁に対する上部電極６の電位を測定することになる。 For example, the measurement circuit 26 obtains the lower bias potential by obtaining at least one period of the high-frequency voltage applied to the lower electrode 3 and calculating the DC component of the high-frequency voltage. The measurement circuit 26 acquires the lower bias potential in real time at a predetermined sampling period (for example, 1 Hz). The lower bias potential indicates the potential of the lower electrode 3 with respect to the semiconductor substrate 4 during the plasma processing, and the ion energy in the plasma incident on the semiconductor substrate 4 is simply measured by the measurement. Similarly, the measurement circuit 9 measures the potential of the upper electrode 6 with respect to the inner wall of the vacuum processing chamber 1.
　本実施形態のプラズマ処理装置は、波長の異なるプラズマの発光強度を同時に測定することができる発光分光強度測定器３０を備える。これにより、イオン種毎に異なる波長の強度を同時に測定することができて、プラズマ中の各イオン種密度を簡易的に測定することが可能になる。なお、本実施形態のプラズマ処理装置が有する演算部２５、上部電力制御部２８、下部電力制御部２９、ガス導入量制御装置３３、情報処理装置３１（予め測定された半導体基板４上のレジストのパターン寸法の測定値データ情報を演算部２５に与える機能を有する）、および生産システム３２（半導体基板４の処理開始の指示信号と処理条件の情報を演算部２５に与える機能を有する）における機能の詳細については後述する。 The plasma processing apparatus of this embodiment includes an emission spectral intensity measuring device 30 that can simultaneously measure the emission intensity of plasmas having different wavelengths. Thereby, the intensity | strength of a different wavelength for every ion seed | species can be measured simultaneously, and it becomes possible to measure each ion seed | species density in plasma simply. Note that the calculation unit 25, the upper power control unit 28, the lower power control unit 29, the gas introduction amount control device 33, the information processing device 31 (information of the resist on the semiconductor substrate 4 measured in advance) included in the plasma processing apparatus of the present embodiment. And a function of providing measurement value data information of the pattern dimension to the arithmetic unit 25) and a function of the production system 32 (having a function of providing an instruction signal for starting processing of the semiconductor substrate 4 and information of processing conditions to the arithmetic unit 25). Details will be described later.
　以上の構成を有するプラズマ処理装置において、半導体基板４のエッチング処理過程においては、プラズマ１３中のラジカルやイオン等の活性種毎に異なる波長を有するプラズマ光が生じ、さらに各プラズマ光の発光強度は、対応する活性種の状態（主としてイオン種密度）に応じて変動する。そのため、各プラズマ光の発光強度を発光分光強度測定器３０で測定することで、プラズマ中の各イオンのイオン密度を簡易的に把握することができる。 In the plasma processing apparatus having the above configuration, in the etching process of the semiconductor substrate 4, plasma light having different wavelengths is generated for each active species such as radicals and ions in the plasma 13, and the emission intensity of each plasma light is , Depending on the state of the corresponding active species (mainly ionic species density). Therefore, by measuring the emission intensity of each plasma light with the emission spectral intensity measuring device 30, the ion density of each ion in the plasma can be easily grasped.
　また、前述したように、セルフバイアス電位は、プラズマ処理中に半導体基板４に生じる電位を示しており、セルフバイアス電位を測定することで、半導体基板４に入射するプラズマ中の各イオン種のイオンエネルギを簡易的に把握することができる。各イオン種のイオンエネルギは、プラズマ中におけるそのイオン種の量を示す設備パラメータとなる。 Further, as described above, the self-bias potential indicates a potential generated in the semiconductor substrate 4 during plasma processing, and by measuring the self-bias potential, ions of each ion species in the plasma incident on the semiconductor substrate 4 are measured. Energy can be easily grasped. The ion energy of each ion species becomes an equipment parameter indicating the amount of the ion species in the plasma.
　本願発明者は、このような特徴を有する設備パラメータの変動に着目した。そして、設備パラメータの変動を分析すれば、プラズマによる半導体基板加工時における現時点での加工寸法を知ることや現時点以降の加工寸法の予測を行うことができる、という知見を得た。 The inventor of the present application paid attention to the fluctuation of equipment parameters having such characteristics. Then, by analyzing the fluctuations of the equipment parameters, we have obtained the knowledge that the current processing dimensions at the time of processing the semiconductor substrate by plasma can be known and the processing dimensions after the current time can be predicted.
　例えば、プラズマ中におけるAr等の不活性ガス群における相互の発光強度比を測定し、その発光強度比に基づいてイオンエッチングのイオン種であるCl+、F-等のイオン密度を把握する。さらには、半導体基板４等におけるセルフバイアス電位を測定し、そのセルフバイアス電位に基づいて半導体基板４に入射するプラズマ中における各イオン種の量（イオンエネルギ）を把握する。なお、イオンエネルギを把握するために測定するセルフバイアス電位は、必ずしも半導体基板４において測定しなくてもよく、真空処理室１内の側壁や天井部において測定してもよい。これらの部位において測定するセルフバイアス電位は、チャンバ壁面等に入射する各イオン種の量（イオンエネルギ）を示している。チャンバ壁面等に入射する各イオン種の量と半導体基板４上に入射するイオン種の量との間には比例関係が成立しており、チャンバ壁面等に入射する各イオン種の量から半導体基板４上に入射するイオン種の量を推測することが可能である。 For example, the mutual emission intensity ratio in an inert gas group such as Ar in the plasma is measured, and the ion density of Cl + , F − and the like which are ion species of ion etching is grasped based on the emission intensity ratio. Further, the self-bias potential in the semiconductor substrate 4 or the like is measured, and the amount (ion energy) of each ion species in the plasma incident on the semiconductor substrate 4 is grasped based on the self-bias potential. Note that the self-bias potential measured for grasping the ion energy does not necessarily need to be measured on the semiconductor substrate 4, and may be measured on the side wall or the ceiling in the vacuum processing chamber 1. The self-bias potential measured at these sites indicates the amount (ion energy) of each ion species incident on the chamber wall surface or the like. A proportional relationship is established between the amount of each ion species incident on the chamber wall surface and the like and the amount of the ion species incident on the semiconductor substrate 4. It is possible to estimate the amount of ion species incident on 4.
　なお、発光強度比の測定において、化学反応エッチングに働く元素のラジカルに対応する波長を有するプラズマ光も同時に測定してもよい。そうすれば、エッチング速度へ影響を及ぼすイオン種のプラズマ中の密度も簡易的に把握することができるようになる。これにより、イオンエッチング（プラズマエッチング）ととともに化学反応エッチングの作用についても簡易的に把握することができるようになる。化学反応エッチングは半導体基板４に対して等方性エッチングとして作用する一方、プラズマエッチングは異方性エッチングとして作用する。そのため、発光強度比の測定を通じて、プラズマエッチングと化学反応エッチングとの間の量的比率を把握すれば、今回のエッチング処理において、等方性エッチングと異方性エッチングとのうちでどちらのエッチングが支配的になっているかを把握することが可能になる。 In the measurement of the emission intensity ratio, plasma light having a wavelength corresponding to the radical of the element acting on the chemical reaction etching may be measured simultaneously. Then, the density of ion species in the plasma that affects the etching rate can be easily grasped. Thereby, it becomes possible to easily grasp the action of chemical reaction etching together with ion etching (plasma etching). Chemical reaction etching acts as isotropic etching on the semiconductor substrate 4, while plasma etching acts as anisotropic etching. Therefore, if the quantitative ratio between the plasma etching and the chemical reaction etching is grasped through the measurement of the emission intensity ratio, which etching is isotropic etching or anisotropic etching in this etching process? It becomes possible to grasp whether it is dominant.
　またパターンの側壁保護膜の生成に応じて変動するエッチング異方性の度合いを設備パラメータに基づいて間接的に把握することが可能となる。すなわち、CF3,SiCOx,SiOといった物質と炭化物とを出発材料とするポリマがエッチング処理時にデポジット膜となってエッチング側壁に生成されると、生成されたデポジット膜がパターンの側壁保護膜として機能する。そのため、エッチング側壁における上記ポリマの生成量がエッチング異方性の度合いを変動させる。エッチング中におけるポリマ生成量は、発光強度比の測定を通じてプラズマ中に発生している各ラジカルの密度を把握することで予測することができる。そこで、上記ポリマの生成量を発光強度比の測定を通じて予測することで、エッチング異方性の度合いを間接的に把握することができる。 Further, it is possible to indirectly grasp the degree of etching anisotropy that fluctuates according to the generation of the pattern side wall protective film based on the equipment parameters. That is, when a polymer starting from a substance such as CF 3 , SiCOx, SiO and carbide is formed as a deposit film during etching processing and formed on the etching side wall, the generated deposit film functions as a pattern side wall protective film. . Therefore, the amount of the polymer produced on the etching side wall varies the degree of etching anisotropy. The amount of polymer production during etching can be predicted by grasping the density of each radical generated in the plasma through measurement of the emission intensity ratio. Therefore, the degree of etching anisotropy can be indirectly grasped by predicting the production amount of the polymer through measurement of the emission intensity ratio.
　図２は、酸化膜エッチング時のCDシフト量（半導体基板４上に予め形成されたレジストパターンの寸法と、プラズマエッチング加工された各膜種の寸法との間の差分値）の平均値と、セルフバイアス電位と、CF,O,COの発光強度との間の相互関係を示す図である。ここで、セルフバイアス電位と発光強度（Arの発光強度比として各イオン種毎に規格化）とは、各イオン種毎の発光強度の平均値であり、下部電極３におけるバイアス電位（これらは１回のプラズマ処理中に取得する）の平均値である。ここでは、セルフバイアス電位と発光強度比とを表わす値としてそれらの平均値を使用しているが、メジアン値等を用いても構わない。またCDシフト量は半導体基板面内の複数ポイント（ここでは面内１３ポイント）の平均値といった統計値を用いている。 FIG. 2 shows an average value of the CD shift amount during etching of the oxide film (difference value between the dimension of the resist pattern formed in advance on the semiconductor substrate 4 and the dimension of each film type processed by plasma etching). It is a figure which shows the correlation between self-bias potential and the emitted light intensity of CF, O, and CO. Here, the self-bias potential and the emission intensity (standardized for each ion species as Ar emission intensity ratio) are the average value of the emission intensity for each ion species, and the bias potential (these are 1 (Obtained during one plasma treatment). Here, the average value is used as a value representing the self-bias potential and the emission intensity ratio, but a median value or the like may be used. The CD shift amount uses a statistical value such as an average value of a plurality of points (here, 13 points in the plane) within the semiconductor substrate surface.
　図２の（ａ）は酸化膜エッチング後の半導体基板４のパターン寸法を示し、図２の（ｂ）,図２の（ｃ）,図２の（ｄ）は、それぞれCO,O,CFの各イオン種のプラズマ中の発光強度をArの発光強度で規格化した値を示し、図２の（ｅ）は下部電極３のセルフバイアス電位を示す。なお、図２における横軸は半導体基板４の処理日付を示す。また、図２において、▽は、真空処理室１のメンテナンスを実施した日時を示し、◇は寸法値の実測値を示し、□は寸法値の計算値を示し、△は寸法値の予測値を示す。ここで、寸法値の実測値（◇）とは、レジストパターン測定実測値のことをいい、寸法値の計算値（□）とは、期間Ａにてセルフバイアス値と発光強度比とから重回帰式にてフィッティングして算出した計算値のことをいい、寸法値の予測値（△）とは、期間Ａで作成した重回帰式で期間Ｂの寸法値を予想した値のことをいう。 2A shows the pattern dimensions of the semiconductor substrate 4 after the oxide film etching, and FIGS. 2B, 2C, and 2D show CO, O, and CF, respectively. FIG. 2 (e) shows the self-bias potential of the lower electrode 3 in which the emission intensity in the plasma of each ion species is normalized by the emission intensity of Ar. Note that the horizontal axis in FIG. 2 indicates the processing date of the semiconductor substrate 4. In FIG. 2, ▽ indicates the date and time when maintenance of the vacuum processing chamber 1 was performed, ◇ indicates the actual measurement value of the dimension value, □ indicates the calculated value of the dimension value, and Δ indicates the predicted value of the dimension value. Show. Here, the actual measurement value (◇) of the dimension value means the actual measurement value of the resist pattern, and the calculated value (□) of the dimension value is a multiple regression from the self-bias value and the emission intensity ratio in the period A. The calculated value calculated by fitting with an equation is the estimated value (Δ) of the dimension value, which is the value of the estimated dimension value of the period B in the multiple regression equation created in the period A.
　図２から明らかなように、各イオン種の発光強度の比および下部電極３のセルフバイアス電位が寸法値のトレンドと同様に変化している。またこれらのデータは計５回の真空処理室１のメンテナンスによる真空容器の内部洗浄毎にシフトしている。これらのことから、真空処理室１の内壁に反応生成物が発生（付着等）することによる真空処理室１内の状態変化およびこれら副生成物１４から発生するガスによるプラズマ雰囲気の変化が、発光強度比および下部電極３のセルフバイアス電位の変化に連動している。 As is clear from FIG. 2, the ratio of the emission intensity of each ion species and the self-bias potential of the lower electrode 3 are changed in the same manner as the trend of the dimension value. These data are shifted every time the vacuum vessel is internally cleaned by the maintenance of the vacuum processing chamber 1 five times in total. For these reasons, the state change in the vacuum processing chamber 1 due to the generation (attachment etc.) of the reaction product on the inner wall of the vacuum processing chamber 1 and the change in the plasma atmosphere due to the gas generated from these by-products 14 are emitted. This is linked to changes in the intensity ratio and the self-bias potential of the lower electrode 3.
　図２の（ａ）における寸法データを、期間Ａのデータを用いて、各イオン種の発光強度比,下部電極３のセルフバイアス電位,全波長の発光強度,およびエッチング時間を重回帰式で表現すると、以下の式（１）となる。 The dimensional data in FIG. 2A is expressed using multiple regression equations for the emission intensity ratio of each ion species, the self-bias potential of the lower electrode 3, the emission intensity of all wavelengths, and the etching time using the data of period A. Then, the following formula (1) is obtained.
　ｙ＝ａ＋V＋ｂ×X1＋ｃ×X２＋ｄ×X３＋e×X4＋f×Z1＋g×T・・・（１）
式（１）において、
ｙは酸化膜エッチング後寸法値を示し、
Vはレジスト寸法値を示し、
X1は発光強度比（CO/Ar）を示し、
X2は発光強度比（O/Ar）を示し、
X3は発光強度比（CF/Ar）を示し、
X4は全波長の発光強度を示し、
Z1はVpp(セルフバイアス電位)を示し、
Tはエッチング処理時間を示す。 y = a + V + b * X1 + c * X2 + d * X3 + e * X4 + f * Z1 + g * T (1)
In equation (1),
y indicates the dimension value after oxide film etching,
V indicates the resist dimension value,
X1 indicates the emission intensity ratio (CO / Ar)
X2 indicates the emission intensity ratio (O / Ar)
X3 indicates the emission intensity ratio (CF / Ar)
X4 indicates the emission intensity of all wavelengths,
Z1 indicates Vpp (self-bias potential)
T represents the etching processing time.
　期間Ａにおいてこれらのパラメータを用いて重回帰分析を行い、定数ａ～ｇを算出し、寸法予測モデルを作成する。 During period A, multiple regression analysis is performed using these parameters, constants ag are calculated, and a dimension prediction model is created.
　作成した予測モデルに基づいて期間Ｂにおける各寸法を予測したうえで、その予測値（△）を図２の(ａ)の期間Ｂにおける寸法値の実測値（◇）や計算値（□）に重ねてプロットしたうえで各値間の相関係数Ｒを算出した。それによると、モデル作成時でＲ＝０．８となり、期間Ｂの予測時にはＲ＝０．６となり、全期間を通してはＲ＝０．７７となった。このように本実施の形態によれば実測値（◇）のパターン寸法と計算値（□）と予測値（△）とがほぼ一致しており、寸法の予測が十分にできていることが確認できる。 After predicting each dimension in period B based on the created prediction model, the predicted value (Δ) is changed to the actual measurement value (◇) and calculated value (□) of the dimension value in period B in FIG. The correlation coefficient R between each value was calculated after plotting. According to this, R = 0.8 when the model was created, R = 0.6 when the period B was predicted, and R = 0.77 throughout the entire period. As described above, according to the present embodiment, the pattern dimension of the actual measurement value (◇), the calculated value (□), and the predicted value (△) are almost the same, and it is confirmed that the dimension is sufficiently predicted. it can.
　さて、上述した説明では、エッチングにより寸法変更が生じる予測モデルとして酸化膜を用いた。しかしながら、予測モデルとしては、エッチングする他の膜種であるポリシリコン、Ｈｉｇｈ－ｋ材膜、メタル等の被エッチング材を用いてもよく、これらの他の予測モデルにおいても、上述したのと同様の重回帰分析モデルを作成することで、パターン寸法の予測をすることができる。 In the above description, an oxide film is used as a predictive model in which dimensional changes are caused by etching. However, as a predictive model, other film types to be etched, such as polysilicon, a high-k material film, and a metal to be etched may be used. In these other predictive models, the same as described above. By creating a multiple regression analysis model, pattern dimensions can be predicted.
　また、上述した分析モデルでは、使用する各パラメータ（セルフバイアス電位,発光強度比等）を表わす統計値としてそれらの平均値を使用したが、使用する各パラメータの統計値は、１回のプラズマ処理中に計測された各パラメータの代表値を算出して用いれば良い。例えば、平均値に代えて、中央値を用いてもよい。 In the analysis model described above, the average value is used as a statistical value representing each parameter to be used (self-bias potential, emission intensity ratio, etc.). The statistical value for each parameter to be used is one plasma treatment. What is necessary is just to calculate and use the representative value of each parameter measured inside. For example, a median value may be used instead of the average value.
　なお、プラズマの発光強度はイオン種毎に特有のピーク波長を有する。例として、本実施形態のモデル作成に用いた各イオン種の発光強度は、各イオン種毎に以下のピーク波長を有していることを前提にして、上述したパターン寸法の予測を行っている。すなわち、CFでは260～265nmに、COでは515～520nmに、Oでは775～780nmに、Arでは415～420nmにそれぞれピーク波長を有する。 The emission intensity of plasma has a peculiar peak wavelength for each ion species. As an example, the above-described pattern dimensions are predicted on the assumption that the emission intensity of each ion species used for model creation of the present embodiment has the following peak wavelength for each ion species. . That is, the peak wavelength is 260 to 265 nm for CF, 515 to 520 nm for CO, 775 to 780 nm for O, and 415 to 420 nm for Ar.
　なお、各イオン種に応じてプラズマ中で発生する発光は複数の波長を有しており、例えはArに応じた発光では、415.8、451.1、484.8、549.5、603.2、696.5、706.7、750.4(nm)にそれぞれ波長を有している。そのため、複数のイオン種が同時に発光するプラズマでは、計測が必要な複数のイオン種において発光波長が重複する可能性がある。そのため、本実施の形態では、計測が必要となる複数のイオン種それぞれに設定する測定波長を互いに重複しない波長に設定している。 The light emission generated in the plasma according to each ion species has a plurality of wavelengths.For example, in the light emission according to Ar, 415.8, 451.1, 484.8, 549.5, 603.2, 696.5, 706.7, 750.4 (nm ) Each have a wavelength. Therefore, in the plasma in which a plurality of ion species emit light simultaneously, there is a possibility that the emission wavelengths overlap in a plurality of ion species that need to be measured. Therefore, in this embodiment, the measurement wavelengths set for each of a plurality of ion species that need to be measured are set to wavelengths that do not overlap each other.
　次に本実施形態における寸法の制御について説明する。この制御は、演算部２５の機能と、上部電力制御部２８の機能と、下部電力制御部２９の機能と、情報処理装置３１の機能と、生産システム３２の機能と、ガス導入量制御装置３３の機能とにより実行される。 Next, control of dimensions in this embodiment will be described. This control includes the function of the calculation unit 25, the function of the upper power control unit 28, the function of the lower power control unit 29, the function of the information processing device 31, the function of the production system 32, and the gas introduction amount control device 33. It is executed by the function.
　図３Ａ～図３Ｇは、メタルゲート/Ｈｉｇｈ－ｋ構造等の積層構造を有する半導体膜を製造する本実施形態の製造方法の各工程における各エッチング膜のパターン形状を示す。図４は本実施形態におけるフローを示す。 3A to 3G show the pattern shapes of the etching films in the respective steps of the manufacturing method of this embodiment for manufacturing a semiconductor film having a stacked structure such as a metal gate / High-k structure. FIG. 4 shows a flow in the present embodiment.
　図３Ａは、積層構造の被エッチング材の例を示す。この被エッチング材は、半導体基板４７に、Ｈｉｇｈ－ｋ材膜４６と、チタン窒化物等のメタル材４５と、ポリシリコン等のゲート電極材４４と、下層レジスト材４３と、ハードマスクとして機能する中間層（酸化珪素,窒化珪素等からなる）４２と、ArFリソグラフィ技術等によってパターン形成されたレジスト材４１とを備える。 FIG. 3A shows an example of a material to be etched having a laminated structure. The material to be etched functions as a semiconductor substrate 47, a high-k material film 46, a metal material 45 such as titanium nitride, a gate electrode material 44 such as polysilicon, a lower resist material 43, and a hard mask. An intermediate layer (made of silicon oxide, silicon nitride or the like) 42 and a resist material 41 patterned by ArF lithography technology or the like are provided.
　まず、ArFリソグラフィ技術等によってレジスト材４１にパターン形成し、さらに作成したパターン寸法を寸法測定器等によって測定する。（ステップＳ５１,Ｓ６１）。測定したリソグラフィ処理後のレジスト材４１のパターンにける寸法値は、エッチング処理後のレジスト材４１のパターンにおける計算値（□）として用いられる。計算値（□）は、エッチング完了後においてエッチング寸法差（□－△）を算出する際におけるエッチングの設計値（予め設定された値）として機能する値であって、この計算値（□）と、エッチング処理後の形状を予測した結果であるパターンの予測値（□）とが比較されることで前述したエッチング寸法差（□－△）が算出される。 First, a pattern is formed on the resist material 41 by ArF lithography technology or the like, and the created pattern dimension is measured by a dimension measuring instrument or the like. (Steps S51 and S61). The measured dimension value in the pattern of the resist material 41 after the lithography process is used as a calculated value (□) in the pattern of the resist material 41 after the etching process. The calculated value (□) is a value that functions as a design value (preset value) for etching when calculating the etching dimension difference (□ -Δ) after completion of etching. Then, the above-described etching dimension difference (□ −Δ) is calculated by comparing the predicted value (□) of the pattern, which is the result of predicting the shape after the etching process.
　次に上述したレジスト材４１のパターンをプラズマエッチング処理する。このプラズマエッチング処理は、
・真空処理室１を0～10mTorr程度の低圧状態にする、
・上部電極６に0～500W程度の電力を印加する、
・下部電極３には電力を印加しない、
・ハロゲンガス（Cl2等）とO2ガスとの混合ガス、または有機ハロゲン化物ガス（CHF3等）とO2ガスとの混合ガスを真空処理室１に導入する、
以上の条件を満たして実施される。 Next, a plasma etching process is performed on the pattern of the resist material 41 described above. This plasma etching process
・ Set the vacuum processing chamber 1 to a low pressure of about 0 to 10 mTorr.
・ Apply electric power of about 0 to 500W to the upper electrode 6.
・ No power is applied to the lower electrode 3;
Introduce into the vacuum processing chamber 1 a mixed gas of halogen gas (Cl 2 etc.) and O 2 gas, or a mixed gas of organic halide gas (CHF 3 etc.) and O 2 gas.
It is carried out while satisfying the above conditions.
　なお、このプラズマエッチング処理においては、レジスト材４１のパターン寸法が所定の値になるように制御される。その際、エッチング時間と、上記混合ガスにおける混合比とをそれぞれ適宜変更することでパターン寸法の制御が実施される。これらのパラメータを変更することでレジスト材４１の寸法を制御できるのは次の理由による。 In the plasma etching process, the pattern dimension of the resist material 41 is controlled to a predetermined value. At that time, the pattern dimension is controlled by appropriately changing the etching time and the mixing ratio in the mixed gas. The reason why the dimensions of the resist material 41 can be controlled by changing these parameters is as follows.
　エッチング時間が長くなる、または真空処理室１内のO2ガス流量が増加してOイオン濃度が高くなると、レジスト材４１の分解が促進されてパターン寸法が縮小する。一方、上記混合ガスの構成ガスとして有機ハロゲン化物ガス（CHF3等）を用いた場合では、有機ハロゲン化物ガス量を増加させて真空処理室１内のCおよびH濃度が高くなると、反応副生成物として生成されてレジストパターンの側壁に付着する有機ポリマ量が増大する結果、レジスト材４１の寸法が見かけ上、太くなる。このような制御手法により、レジスト材４１のパターン寸法制御を行うことができる。 When the etching time is increased or the O 2 gas flow rate in the vacuum processing chamber 1 is increased and the O ion concentration is increased, the decomposition of the resist material 41 is promoted and the pattern dimension is reduced. On the other hand, when an organic halide gas (CHF 3 or the like) is used as a constituent gas of the above mixed gas, a reaction byproduct is generated when the amount of organic halide gas is increased to increase the C and H concentration in the vacuum processing chamber 1. As a result of the increase in the amount of organic polymer produced as a product and adhering to the sidewall of the resist pattern, the size of the resist material 41 is apparently thickened. With such a control method, the pattern size of the resist material 41 can be controlled.
　真空処理室１内への導入ガスの比率および上部、下部電極３,６への印加電力条件は、今回のプラズマエッチング処理の直前に実施されたもう一つの半導体基板４７のレジスト材４１におけるプラズマエッチング処理（以下、前回処理という）において測定された以下のデータと、今回の半導体基板４７のレジスト材４１のプラズマエッチング処理（以下、今回処理という）において設定された以下のデータとを、予め設定したモデル式（前述した式（１）等）に代入することで決定する（ステップＳ６２）。 The ratio of the gas introduced into the vacuum processing chamber 1 and the conditions for the power applied to the upper and lower electrodes 3 and 6 are as follows: plasma etching in the resist material 41 of another semiconductor substrate 47 performed immediately before the current plasma etching process The following data measured in the process (hereinafter referred to as the previous process) and the following data set in the plasma etching process (hereinafter referred to as the current process) of the resist material 41 of the semiconductor substrate 47 are set in advance. It is determined by substituting it into the model formula (formula (1) etc. described above) (step S62).
　（前回処理時のデータ）
・レジスト材４１処理中におけるセルフバイアス電圧
・Clイオン,Oイオン,COイオンの発光強度
　（今回処理時のデータ）
・レジスト材４１処理における処理時間
・ArFリソグラフィ技術等によるパターン形成後において測定されたレジスト材４１のレジスト寸法値（計算値（□））
　ステップＳ６２は、APC(Advanced Process Control)処理によって実施される。APC処理とは、モニタリングによって得られる設備におけるパラメータの変化に基づいて、半導体基板４７の処理状態を把握(推測)し、装置のレシピ(処理条件）を制御することで、半導体基板４７の状態を常に一定に調整して保たれた状態をコントロールして生産する生産形態のことである。 (Data from previous processing)
・ Self-bias voltage during resist material 41 processing ・ Luminescence intensity of Cl ions, O ions, and CO ions (data during this processing)
-Processing time in resist material 41 processing-Resist dimension value of resist material 41 (calculated value (□)) measured after pattern formation by ArF lithography technology, etc.
Step S62 is performed by an APC (Advanced Process Control) process. APC processing is based on changes in parameters in equipment obtained by monitoring, grasping (estimating) the processing state of the semiconductor substrate 47, and controlling the recipe (processing conditions) of the apparatus to change the state of the semiconductor substrate 47. It is a form of production in which the production is controlled by always maintaining a constant state.
　以上のようにして実施されるレジスト材４１のプラズマエッチング処理に際しては、Clイオン,Oイオン,およびCOイオンに起因してプラズマ中に生じる発光の発光強度とセルフバイアス電位とが測定される。その測定データと、ステップＳ５１で測定しておいたレジスト材４１の寸法値データ（計算値（□））とを、予め設定しておいたモデル式（式（１）等）に代入することで、プラズマ放電における諸条件を決定し（ステップＳ６２）、決定した諸条件に沿ってレジスト材４１のエッチング加工を行なう（ステップＳ５２）。 In the plasma etching process of the resist material 41 performed as described above, the emission intensity and self-bias potential of light emission generated in the plasma due to Cl ions, O ions, and CO ions are measured. By substituting the measurement data and the dimension value data (calculated value (□)) of the resist material 41 measured in step S51 into a preset model formula (formula (1), etc.). Then, various conditions in the plasma discharge are determined (step S62), and the resist material 41 is etched according to the determined conditions (step S52).
　以上の制御が行われるレジスト材４１のエッチング加工において、さらにClイオン,Oイオン,COイオンに起因して生じる発光における発光強度と、セルフバイアス電位とを測定する（ステップＳ６３）。 In the etching process of the resist material 41 in which the above control is performed, the emission intensity and the self-bias potential in light emission caused by Cl ions, O ions, and CO ions are further measured (step S63).
　処理時間と予め測定されているレジスト寸法値のデータとを、予め設定しておいたモデル式（式（１）等）に代入することによってエッチング処理後のレジスト材４１の寸法を予測する（ステップＳ６４）。 The dimension of the resist material 41 after the etching process is predicted by substituting the processing time and the data of the resist dimension value measured in advance into a preset model formula (formula (1), etc.) (step) S64).
　次に図３Ｂでは、エッチング処理後のレジスト材４１をマスクにして、酸化珪素または窒化珪素等からなる中間層４２のプラズマエッチングを行なう。ここでは例として、酸化珪素からなる中間層４２を例に挙げて説明する。この中間層４２をプラズマエッチングするためには、
・真空処理室１を0～10mTorr程度の低圧状態にする、
・上部電極６に0～500W程度の電力を印加する、
・下部電極３にも所定の電力を印加する、
・有機ハロゲン化物ガス（CF4またはCHF3等）とO2ガスとからなる混合ガスを真空処理室１内へ導入する、
ことで真空処理室１にプラズマ放電を生じさせ、イオンと中性ラジカルを用いたイオンアシスト反応を発生させて中間層４２をエッチングする。 Next, in FIG. 3B, plasma etching of the intermediate layer 42 made of silicon oxide, silicon nitride, or the like is performed using the resist material 41 after the etching process as a mask. Here, as an example, the intermediate layer 42 made of silicon oxide will be described as an example. In order to plasma etch this intermediate layer 42,
・ Set the vacuum processing chamber 1 to a low pressure of about 0 to 10 mTorr.
・ Apply electric power of about 0 to 500W to the upper electrode 6.
Apply predetermined power to the lower electrode 3;
-A mixed gas composed of an organic halide gas (such as CF 4 or CHF 3 ) and O 2 gas is introduced into the vacuum processing chamber 1.
As a result, plasma discharge is generated in the vacuum processing chamber 1 to generate an ion assist reaction using ions and neutral radicals, thereby etching the intermediate layer 42.
　このとき、レジスト材４１のエッチング処理後に算出したレジスト材４の寸法予測値（△）と、予め設定しておいた中間層４２の計算値（□）とを比較し、その寸法差（□－△）を算出する。算出した寸法差（□－△）が、予め設定しておいた値となるように、以下の修正を行う。 At this time, the predicted dimension value (Δ) of the resist material 4 calculated after the etching process of the resist material 41 is compared with the calculated value (□) of the intermediate layer 42 set in advance, and the dimension difference (□ − Δ) is calculated. The following corrections are made so that the calculated dimensional difference (□ -Δ) becomes a preset value.
　すなわち、半導体基板４７の今回処理の直前に行なった前回処理時の中間層処理時におけるセルフバイアス電位,Clイオン,Oイオン,およびCOイオンの発光強度の値と、今回処理時の中間層プラズマエッチング処理における処理時間と、レジスト材寸法予測値（△）とを、予め設定しておいたモデル式（式（１）等）に代入することで、
・真空処理室１に導入するガス流量、
・下部電極３,上部電極６に印加する高周波の電力、
を決定する（ステップＳ６５）。 That is, the self-bias potential, Cl ion, O ion, and CO ion emission intensity values during the intermediate layer processing of the previous processing performed immediately before the current processing of the semiconductor substrate 47 and the intermediate layer plasma etching during the current processing By substituting the processing time in processing and the resist material dimension predicted value (Δ) into a preset model formula (formula (1), etc.),
-Gas flow rate introduced into the vacuum processing chamber 1,
High frequency power applied to the lower electrode 3 and the upper electrode 6;
Is determined (step S65).
　具体的には中間層４２のエッチング加工後の寸法が所定の値になるように、そのエッチング時間と、混合ガス（有機ハロゲン化物ガス+O2ガス）における流量比（混合比）を変更することで、エッチング加工後の中間層４２のパターン形状変動を調整するとともにエッチング後の寸法を細らせる制御を行う。あるいは中間層４２のエッチング加工後において、下部電極３にバイアス電位を印加することなく、有機ハロゲン化物ガス（CHF3等）とO2ガスとの混合ガス、H2ガス、またはN2,He等の不活性ガスを真空処理室１に導入した状態で再度真空処理室１にプラズマ放電を発生させることで有機ポリマ材を発生させ、その有機ポリマ材からなる副生成物をレジスト材４１の側壁部と中間層４２の側壁部とに付着させ、これによってエッチング寸法を見かけ上、太くする制御を行う。その後、中間層４２の寸法が所定の値になるように、エッチング条件を変更させて、再度プラズマエッチング処理を行い、その際にエッチング時間の調整と、上記混合ガスにおける流量比（混合比）の調整とを実施して所定の寸法でかつ垂直形状となるようにエッチング処理を行う（ステップＳ５３）。 Specifically, the etching time and the flow rate ratio (mixing ratio) in the mixed gas (organic halide gas + O 2 gas) are changed so that the dimension after etching of the intermediate layer 42 becomes a predetermined value. Thus, control is performed to adjust the pattern shape variation of the intermediate layer 42 after etching and to reduce the dimension after etching. Alternatively, after etching the intermediate layer 42, a mixed gas of organic halide gas (CHF 3 or the like) and O 2 gas, H 2 gas, N 2 , He, or the like is applied without applying a bias potential to the lower electrode 3. In the state where the inert gas is introduced into the vacuum processing chamber 1, an organic polymer material is generated by generating a plasma discharge again in the vacuum processing chamber 1, and a by-product made of the organic polymer material is removed from the side wall portion of the resist material 41. To the side wall portion of the intermediate layer 42, thereby controlling the apparent increase in etching size. Thereafter, the etching conditions are changed so that the dimension of the intermediate layer 42 becomes a predetermined value, and the plasma etching process is performed again. At that time, the adjustment of the etching time and the flow ratio (mixing ratio) of the mixed gas are adjusted. The adjustment is performed and an etching process is performed so as to obtain a vertical shape with a predetermined dimension (step S53).
　以上の制御が行われる中間層４２のプラズマエッチング処理において、さらにFイオン,CFxイオン,Oイオン,COイオン等に起因して生じる発光における発光強度と、セルフバイアス電位とを測定する（ステップＳ６６）。 In the plasma etching process of the intermediate layer 42 in which the above control is performed, the emission intensity and the self-bias potential in light emission caused by F ions, CFx ions, O ions, CO ions, etc. are further measured (step S66). .
　前述した手法（ステップＳ６４）によって算出されたレジスト材４１の寸法予測値（△）と、今回処理時における中間層４２のプラズマエッチング処理における処理時間とを、予め設定しておいたモデル式（式（１）等）に代入することで、プラズマエッチング処理後の中間層４２の加工寸法を予測する（ステップＳ６７）。 A model equation (formula) in which the predicted dimension value (Δ) of the resist material 41 calculated by the above-described method (step S64) and the processing time in the plasma etching process of the intermediate layer 42 at the time of the current process are set in advance. By substituting into (1) etc.), the processing dimension of the intermediate layer 42 after the plasma etching process is predicted (step S67).
　次に図３Ｃでは、下層レジスト材４３のプラズマエッチング処理を行う。この処理では、
・真空処理室１を0～10mTorr程度の低圧状態にする、
・上部電極６に0～500W程度の電力を印加する、
・下部電極３にも所定の電力を印加する、
・レジスト材４１での処理と同様のガス種、あるいはCO2とAr等の不活性ガスとの混合ガスを真空処理室１内へ導入する、
ことで真空処理室１にプラズマ放電を生じさせ、イオンと中性ラジカルを用いたイオンアシスト反応を発生させて下層レジスト材４３をエッチングする（ステップＳ５４）。 Next, in FIG. 3C, plasma etching of the lower resist material 43 is performed. In this process,
・ Set the vacuum processing chamber 1 to a low pressure of about 0 to 10 mTorr.
・ Apply electric power of about 0 to 500W to the upper electrode 6.
Apply predetermined power to the lower electrode 3;
Introducing into the vacuum processing chamber 1 a gas type similar to the processing with the resist material 41 or a mixed gas of CO 2 and an inert gas such as Ar.
As a result, plasma discharge is generated in the vacuum processing chamber 1, and an ion assist reaction using ions and neutral radicals is generated to etch the lower resist material 43 (step S54).
　このとき、中間層４２のエッチング後に算出した中間層４２の寸法予測値（△）と、予め設定しておいた下層レジスト材４３のパターン計算値（□）とを比較し、その寸法差（□－△）を算出する。算出した寸法差（□－△）が、予め設定された寸法となるように、以下の修正を行う。 At this time, the predicted dimension value (Δ) of the intermediate layer 42 calculated after the etching of the intermediate layer 42 is compared with the preset pattern calculation value (□) of the lower layer resist material 43, and the dimensional difference (□ -△) is calculated. The following correction is performed so that the calculated dimension difference (□ -Δ) becomes a preset dimension.
　すなわち、前回処理時の下層レジスト材処理中におけるClイオン,Oイオン,COイオンの発光強度と、セルフバイアス電位と、今回処理時における下層レジスト材処理時における処理時間と、中間層寸法予測値（△）とを、予め設定しておいたモデル式（式（１）等）に代入することで、
・真空処理室１に導入するガス流量、
・下部電極３,上部電極６に印加する高周波の電力、
を決定する（ステップＳ６８）。 That is, the emission intensity of Cl ions, O ions, CO ions during the lower layer resist material processing during the previous processing, self-bias potential, processing time during the lower layer resist material processing during the current processing, and predicted intermediate layer dimensions ( By substituting △) into a preset model formula (formula (1) etc.),
-Gas flow rate introduced into the vacuum processing chamber 1,
High frequency power applied to the lower electrode 3 and the upper electrode 6;
Is determined (step S68).
　具体的には下層レジスト材４３のエッチング加工後の寸法が所定の値になるように、そのエッチング時間と、混合ガス（CO2ガス+O2ガスまたは有機ハロゲン化物ガス+O2ガス）の流量比（混合比）とを変更することで、エッチング加工後の下層レジスト材４３の寸法を細らせる制御を行う。あるいは、下層レジスト材４３のエッチング加工後において、下部電極３にバイアス電位を印加することなく、混合ガス（有機ハロゲン化物（CHF3等）,O2ガスが混合されている）と、H2ガスと,不活性ガス（N2,He等）とのうちのいずれかのガスを真空処理室１に導入した状態で再度真空処理室１にプラズマ放電を発生させることで有機ポリマ材を発生させ、その有機ポリマ材からなる副生成物を下層レジスト材４３の側壁部と中間層４２の側壁部とに付着させる。これにより下層レジスト材４３のエッチング寸法が見かけ上、太くなる制御を行う。その後、下層レジスト材４３の寸法が所定の寸法でかつ垂直形状となるようにエッチング条件を変更させて、エッチング処理を行う（ステップＳ５４）。 Specifically, the etching time and the flow rate of the mixed gas (CO 2 gas + O 2 gas or organic halide gas + O 2 gas) so that the dimension after etching of the lower resist material 43 becomes a predetermined value. By changing the ratio (mixing ratio), control is performed to reduce the size of the lower layer resist material 43 after the etching process. Alternatively, after etching the lower resist material 43, a mixed gas (organic halide (CHF 3 or the like), O 2 gas is mixed) and H 2 gas without applying a bias potential to the lower electrode 3 are used. And an inert gas (N 2 , He, etc.) with any gas introduced into the vacuum processing chamber 1 to generate a plasma discharge in the vacuum processing chamber 1 again to generate an organic polymer material, The by-product made of the organic polymer material is adhered to the side wall portion of the lower resist material 43 and the side wall portion of the intermediate layer 42. Thereby, the etching dimension of the lower resist material 43 is controlled to be apparently thick. Thereafter, the etching conditions are changed so that the lower resist material 43 has a predetermined dimension and a vertical shape, and an etching process is performed (step S54).
　以上の制御が行われる下層レジスト材４３のプラズマエッチング処理中において、さらにハロゲン(F等),有機ハロゲン化物(CF等),COイオン,Oイオン,Arイオン等に起因して生じる発光における発光強度とセルフバイアス電位とを測定する（ステップＳ６９）。 During the plasma etching process of the lower resist material 43 in which the above control is performed, emission intensity in light emission caused by halogen (F, etc.), organic halide (CF, etc.), CO ions, O ions, Ar ions, etc. And the self-bias potential are measured (step S69).
　前述の手法（ステップＳ６７）によって算出された中間層４２の寸法予測値（△）と、今回処理の下層レジスト材４３のプラズマエッチング処理における処理時間とを、予め設定しておいたモデル式（式（１）等）に代入することで、プラズマエッチング処理後の下層レジスト材４３の加工寸法を予測する（ステップＳ７０）。 A model equation (formula) in which the predicted dimension value (Δ) of the intermediate layer 42 calculated by the above-described method (step S67) and the processing time in the plasma etching process of the lower resist material 43 in this process are set in advance. By substituting into (1) etc.), the processing dimension of the lower layer resist material 43 after the plasma etching process is predicted (step S70).
　次に図３Ｄでは、ゲート電極材４４のプラズマエッチング処理を行う。この処理では、
・真空処理室１を0～10mTorr程度の低圧状態にする、
・上部電極６に0～500W程度の電力を印加する、
・下部電極３にも所定の電力を印加する、
・Cl2とHBrとの混合ガス,CF4ガス,O2ガス等を真空処理室１内へ導入する、
ことで、真空処理室１にプラズマ放電を生じさせ、イオンと中性ラジカルを用いたイオンアシスト反応を発生させてゲート電極材４４をエッチングする。ゲート電極材４４（ポリシリコン膜）はその膜厚の８０％程度までエッチングする。 Next, in FIG. 3D, plasma etching of the gate electrode material 44 is performed. In this process,
・ Set the vacuum processing chamber 1 to a low pressure of about 0 to 10 mTorr.
・ Apply electric power of about 0 to 500W to the upper electrode 6.
Apply predetermined power to the lower electrode 3;
・ Introducing a mixed gas of Cl 2 and HBr, CF 4 gas, O 2 gas, etc. into the vacuum processing chamber 1,
As a result, plasma discharge is generated in the vacuum processing chamber 1, and an ion assist reaction using ions and neutral radicals is generated to etch the gate electrode material 44. The gate electrode material 44 (polysilicon film) is etched to about 80% of its film thickness.
　このとき、下層レジスト材４３のエッチング後に算出した下層レジスト材４３の寸法予測値（△）と、予め設定しておいたゲート電極材４４の計算値（□）とを比較し、その寸法差（□－△）を算出する。算出した寸法差（□－△）が、予め設定しておいた寸法となるように、以下の修正を行う。すなわち、前回処理時のゲート電極材処理中における各イオン種（H,Br,有機ハロゲン化物（CF等),ハロゲン化物（F等）,O,CO等）に起因して生じる発光における発光強度と、セルフバイアス電位と,今回処理時のゲート電極材処理時における処理時間と、下層レジスト材寸法予測値（△）とを、予め設定しておいたモデル式（式（１）等）に代入することで、
・真空処理室１に導入する各ガス種（HBr,CF4,O2等）のガス流量、
・下部電極３,上部電極６に印加する高周波の電力、
を決定する（ステップＳ７１）。 At this time, the predicted size (Δ) of the lower resist material 43 calculated after the etching of the lower resist material 43 is compared with the preset calculated value (□) of the gate electrode material 44, and the dimensional difference ( □-△) is calculated. The following corrections are made so that the calculated dimensional difference (□ -Δ) becomes a preset dimension. That is, the emission intensity of light emission caused by each ion species (H, Br, organic halide (CF, etc.), halide (F, etc.), O, CO, etc.) during the gate electrode material treatment at the previous treatment The self-bias potential, the processing time at the time of the gate electrode material processing at this time, and the lower resist material dimension predicted value (Δ) are substituted into a preset model formula (formula (1), etc.). With that
・ Gas flow rate of each gas type (HBr, CF 4 , O 2 etc.) introduced into the vacuum processing chamber 1
High frequency power applied to the lower electrode 3 and the upper electrode 6;
Is determined (step S71).
　具体的にはゲート電極材４４のエッチング後の寸法が所定の値になるように、そのエッチング時間と、各ガス種（Cl2,HBｒ,CF4,O2等）の流量比（混合比）と下部電極３に印加するバイアス電力とを変更することで、エッチング加工後のゲート電極材４４の寸法を細らせる制御を行う。あるいは、ゲート電極材４４のエッチング加工後において、下部電極３にバイアス電位を印加することなく、有機ハロゲン化物（CHF3等）とO2ガスとの混合ガス、H2ガス、またはN2,He等の不活性ガスを真空処理室１に導入した状態で再度真空処理室１にプラズマ放電を発生させることで有機ポリマ材を発生させ、その有機ポリマ材からなる副生成物を下層レジスト材４３の側壁部と中間層４２の側壁部とに付着させる。これによりエッチング寸法が見かけ上、太くなる制御を行う。その後、ゲート電極材４４が所定の寸法でかつ垂直形状となるようにエッチング条件を変更させて、エッチング処理を行う（ステップＳ５５）。 Specifically, the etching time and the flow rate ratio (mixing ratio) of each gas type (Cl 2 , HBr, CF 4 , O 2, etc.) so that the dimension after etching of the gate electrode material 44 becomes a predetermined value. And the bias power applied to the lower electrode 3 are controlled to reduce the size of the gate electrode material 44 after the etching process. Alternatively, after the gate electrode material 44 is etched, a mixed gas of organic halide (CHF 3 or the like) and O 2 gas, H 2 gas, or N 2 , He is applied without applying a bias potential to the lower electrode 3. An organic polymer material is generated by generating a plasma discharge in the vacuum processing chamber 1 again in a state where an inert gas such as is introduced into the vacuum processing chamber 1, and a by-product made of the organic polymer material is formed in the lower resist material 43. It adheres to a side wall part and the side wall part of the intermediate | middle layer 42. FIG. Thereby, the etching dimension is controlled to become thicker. Thereafter, the etching conditions are changed so that the gate electrode material 44 has a predetermined size and a vertical shape, and an etching process is performed (step S55).
　このゲート電極材処理中において、有機ハロゲン化物（H,Br,CF等)、ハロゲン化物（F等),O,CO等の各イオン種に起因して生じる発光における発光強度とセルフバイアス電位とを測定する（ステップＳ７２）。 During the processing of the gate electrode material, the emission intensity and self-bias potential in the light emission caused by each ion species such as organic halide (H, Br, CF, etc.), halide (F, etc.), O, CO, etc. Measurement is performed (step S72).
　処理時間と、前述の手法（ステップＳ７０）にて算出した下層レジスト材４３の寸法予測値（△）とを、予め設定したモデル式（式（１）等）に代入することで、プラズマエッチング後のゲート電極材４４のエッチング後の加工寸法を予測する（ステップＳ７３）。 By substituting the processing time and the predicted dimension value (Δ) of the lower resist material 43 calculated by the above-described method (step S70) into a preset model formula (formula (1), etc.), after plasma etching The processing dimension after etching of the gate electrode material 44 is predicted (step S73).
　前述のゲート電極材４４のエッチング処理を経てもゲート電極材４４は、膜厚比で２０％程度が残存している。図３Ｅでは、ゲート電極材エッチング後に残っているゲート電極材４４のプラズマエッチング処理を行う。以下の説明では、エッチング処理後に残存しているゲート電極材４４を残余のゲート電極材４４’と称し、ゲート電極材４４と区別する。
この処理では、
・先に実施したゲート電極材４４のプラズマエッチング処理に比して、真空処理室１を低圧状態にする、
・下部電極３にも電力印加を行うものの、上部電極３,または下部電極６に印加する電力を、先に実施したゲート電極材４４のプラズマエッチング処理に比して低電力にする、
・Cl2とHBrとの混合ガス,CF4ガス,O2ガス等を真空処理室１内に導入する、
ことで、真空処理室１にプラズマ放電を生じさせ、イオンと中性ラジカルを用いたイオンアシスト反応を発生させて、残余のゲート電極材４４’をエッチングする。残余のゲート電極材４４’のエッチング処理では、ゲート電極材４４のエッチング処理に比して低圧,低バイアス電力条件にすることで、当該エッチング処理時において残余のゲート電極材４４’の下層に位置するTi窒化物等が、ポリマとなってポリシリコン側壁部に飛散して付着することが抑制される。これにより、残余のゲート電極材４４’をエッチングする際におけるゲート電極材４４のパターン寸法変動を抑えることができる。 Even after the etching process of the gate electrode material 44 described above, about 20% of the gate electrode material 44 remains in a film thickness ratio. In FIG. 3E, plasma etching is performed on the gate electrode material 44 remaining after the gate electrode material etching. In the following description, the gate electrode material 44 remaining after the etching process is referred to as the remaining gate electrode material 44 ′ and is distinguished from the gate electrode material 44.
In this process,
-Compared with the plasma etching process of the gate electrode material 44 implemented previously, the vacuum processing chamber 1 is made into a low-pressure state,
Although power is also applied to the lower electrode 3, the power applied to the upper electrode 3 or the lower electrode 6 is set to be lower than that of the plasma etching process of the gate electrode material 44 performed earlier.
・ Introducing a mixed gas of Cl 2 and HBr, CF 4 gas, O 2 gas, etc. into the vacuum processing chamber 1,
Thus, plasma discharge is generated in the vacuum processing chamber 1 to generate an ion assist reaction using ions and neutral radicals, and the remaining gate electrode material 44 ′ is etched. In the etching process of the remaining gate electrode material 44 ′, the low-voltage and low-bias power conditions are set as compared with the etching process of the gate electrode material 44, so that the remaining gate electrode material 44 ′ is positioned below the remaining gate electrode material 44 ′. Ti nitride or the like to be a polymer is prevented from scattering and adhering to the polysilicon side wall. Thereby, the pattern dimension fluctuation | variation of the gate electrode material 44 at the time of etching remaining gate electrode material 44 'can be suppressed.
　以上の処理を行う残余のゲート電極材４４’のエッチング処理時において、残余のゲート電極材４４’のエッチング後に算出したゲート電極材４４の寸法予測値（△）と、予め設定しておいたゲート電極材４４の計算値（□）とを比較し、その寸法差（□-△）を算出する。算出した寸法差（□-△）が、予め設定しておいた寸法となるように、以下の修正を行う。 At the time of etching the remaining gate electrode material 44 ′ for which the above processing is performed, the predicted size (Δ) of the gate electrode material 44 calculated after the etching of the remaining gate electrode material 44 ′ and a preset gate The calculated value (□) of the electrode material 44 is compared, and the dimensional difference (□ -Δ) is calculated. The following corrections are made so that the calculated dimensional difference (□ -Δ) becomes a preset dimension.
　すなわち、残余のゲート電極材４４’の処理中における各イオン種(有機ハロゲン化物（H,Br,CF等),ハロゲン化物（F等）,O,CO等）に起因して生じる発光における発光強度と、セルフバイアス電位と,今回処理時の残余のゲート電極材処理時における処理時間と、ゲート電極材寸法予測値（△）とを、予め設定しておいたモデル式（式（１）等）に代入することで、
・真空処理室１に導入する各ガス種（HBr,CF4,O2等）のガス流量比（混合比）、
・下部電極３,上部電極６に印加する高周波の電力、
を決定する（ステップＳ７４）。 That is, the emission intensity in light emission caused by each ion species (organic halide (H, Br, CF, etc.), halide (F, etc.), O, CO, etc.) during the treatment of the remaining gate electrode material 44 ' And a model formula (formula (1), etc.) set in advance for the self-bias potential, the processing time for the remaining gate electrode material processing at the time of the current processing, and the gate electrode material size predicted value (Δ) By substituting
・ Gas flow ratio (mixing ratio) of each gas type (HBr, CF 4 , O 2 etc.) introduced into the vacuum processing chamber 1,
High frequency power applied to the lower electrode 3 and the upper electrode 6;
Is determined (step S74).
　具体的にはゲート電極材４４のエッチング後のパターン寸法が所定の値になるように、そのエッチング時間と、Cl2と各ガス種（HBr,CF4,O2等）の流量比（混合比）と下部電極６に印加するバイアス電力とを変更することで、エッチング加工後のゲート電極材４４の寸法を細らせる制御を行う。あるいは、残余のゲート電極材４４’のエッチング加工後において、下部電極６にバイアス電位を印加することなく、有機ハロゲン化物（CHF3等）とO2ガスとの混合ガス,H2ガス,不活性ガス（N2,He等）を真空処理室１に導入した状態で、再度真空処理室１にプラズマ放電を発生させることで、有機ポリマ材を発生させ、その有機ポリマ材からなる副生成物を下層レジスト材４３の側壁部と中間層４２の側壁部とに付着させる。これによりエッチング寸法が見かけ上、太くなる制御を行う。その後、ゲート電極材４４が所定の寸法でかつ垂直形状となるようにエッチング条件を変更させて、エッチング処理を行う（ステップＳ５６）。 Specifically, the etching time and the flow rate ratio (mixing ratio) of Cl 2 and each gas type (HBr, CF 4 , O 2 etc.) so that the pattern dimension after etching of the gate electrode material 44 becomes a predetermined value. ) And the bias power applied to the lower electrode 6 are controlled to reduce the dimension of the gate electrode material 44 after the etching process. Alternatively, after etching the remaining gate electrode material 44 ', a mixed gas of organic halide (CHF 3 or the like) and O 2 gas, H 2 gas, or inert without applying a bias potential to the lower electrode 6 With the gas (N 2 , He, etc.) introduced into the vacuum processing chamber 1, plasma discharge is generated again in the vacuum processing chamber 1 to generate an organic polymer material, and a by-product made of the organic polymer material is generated. It is made to adhere to the side wall part of the lower layer resist material 43 and the side wall part of the intermediate layer 42. Thereby, the etching dimension is controlled to become thicker. Thereafter, the etching conditions are changed so that the gate electrode material 44 has a predetermined size and a vertical shape, and an etching process is performed (step S56).
　このゲート電極材４４処理中におけるH,Br,有機ハロゲン化物（CF等),ハロゲン化物（F等),O,CO等のイオン種に起因して生じる発光における発光強度とセルフバイアス電位とを測定する（ステップＳ７５）。 Measurement of emission intensity and self-bias potential in light emission caused by ion species such as H, Br, organic halides (CF, etc.), halides (F, etc.), O, CO, etc. during processing of the gate electrode material 44 (Step S75).
　前述した手法（ステップＳ７３）によって算出されたゲート電極材４４の寸法予測値（△）と今回処理時のゲート電極材プラズマエッチング処理における処理時間とを予め設定しておいたモデル式（式（１）等）に代入することで、残余のゲート電極材４４’をプラズマエッチング処理した後におけるゲート電極材４４の加工寸法を予測する（ステップＳ７６）。 A model formula (formula (1)) in which the predicted dimension value (Δ) of the gate electrode material 44 calculated by the above-described method (step S73) and the processing time in the gate electrode material plasma etching process at this time are set in advance. ) Etc.), the processing dimension of the gate electrode material 44 after the remaining gate electrode material 44 'is subjected to the plasma etching process is predicted (step S76).
　次に図３Ｆでは、メタル材膜４５のプラズマエッチング処理を行う。この処理では、
・真空処理室１を0～10mTorr程度の低圧状態にする、
・上部電極６に0～150W程度の電力を印加する、
・下部電極３にも所定の電力を印加する、
・ハロゲンガス（Cl2等）や有機ハロゲン化物ならなるガス種を真空処理室１内へ導入する、
ことで真空処理室１にプラズマ放電を生じさせ、イオンと中性ラジカルを用いたイオンアシスト反応を発生させてメタル材膜４５をエッチングする（ステップＳ５７）。 Next, in FIG. 3F, plasma etching of the metal material film 45 is performed. In this process,
・ Set the vacuum processing chamber 1 to a low pressure of about 0 to 10 mTorr.
・ Apply electric power of about 0 to 150W to the upper electrode 6.
Apply predetermined power to the lower electrode 3;
・ Introduce halogen gas (such as Cl 2 ) or organic halide into the vacuum processing chamber 1;
As a result, plasma discharge is generated in the vacuum processing chamber 1, and an ion assist reaction using ions and neutral radicals is generated to etch the metal material film 45 (step S57).
　このとき、ゲート電極材４４のエッチング後に算出したゲート電極材４４の寸法予測値（△）と、予め設定しておいたメタル材膜４５の計算値（□）とを比較し、その寸法差（□－△）を算出する。算出した寸法差（□－△）が、予め設定された寸法となるように、以下の修正を行う。 At this time, the estimated dimension value (Δ) of the gate electrode material 44 calculated after the etching of the gate electrode material 44 is compared with a preset calculated value (□) of the metal material film 45, and the dimension difference ( □-△) is calculated. The following correction is performed so that the calculated dimension difference (□ -Δ) becomes a preset dimension.
　すなわち、処理中におけるセルフバイアス電位と、Cl,O,CO等のイオン種に起因して生じる発光における発光強度とを測定し（ステップＳ７８）、これら測定値と、今回処理におけるメタル材膜プラズマエッチング処理の処理時間と、前述した手法（ステップＳ７６）で算出したゲート電極材４４の寸法予測値（△）とを、予め設定したモデル式（式（１）等）に代入することで、プラズマエッチング処理後のメタル材膜４５の加工寸法を予測する（ステップＳ７７）。 That is, the self-bias potential during processing and the emission intensity in light emission caused by ion species such as Cl, O, and CO are measured (step S78), and these measured values and metal material film plasma etching in this processing are measured. Plasma etching is performed by substituting the processing time of the processing and the predicted size (Δ) of the gate electrode material 44 calculated by the above-described method (step S76) into a preset model formula (formula (1), etc.). A processing dimension of the metal material film 45 after processing is predicted (step S77).
　具体的にはメタル材膜４５のエッチング後のパターン寸法が所定の値になるように、メタル材膜４５のエッチング後において、下部電極３にバイアス電位を印加することなく、有機ハロゲン化物（CHF3等）とO2ガスとの混合ガス,H2,不活性ガス（N2,He等）を真空処理室１に導入した状態で、再度真空処理室１にプラズマ放電を生じさせることで、有機ポリマ材を発生させ、その有機ポリマ材からなる副生成物をメタル材膜４５の側壁部に付着させる。これにより、メタル材膜４５のエッチング寸法が見かけ上、太くなる制御等を行うことで、メタル材膜４５を所定の寸法となるように制御する。 Specifically, the organic halide (CHF 3) is applied without applying a bias potential to the lower electrode 3 after the etching of the metal material film 45 so that the pattern dimension after the etching of the metal material film 45 becomes a predetermined value. Etc.) and a mixed gas of O 2 gas, H 2 , inert gas (N 2 , He, etc.) is introduced into the vacuum processing chamber 1, and plasma discharge is generated again in the vacuum processing chamber 1, thereby organic A polymer material is generated, and a by-product made of the organic polymer material is attached to the side wall portion of the metal material film 45. Accordingly, the metal material film 45 is controlled to have a predetermined size by performing control such that the etching size of the metal material film 45 is apparently thickened.
　このメタル材膜４５処理中においてCl,O,CO等のイオン種に起因して生じる発光における発光強度とセルフバイアス電位とを測定する（ステップＳ７８）。 During the processing of the metal material film 45, the emission intensity and the self-bias potential in the luminescence generated due to the ion species such as Cl, O, and CO are measured (step S78).
　前述した手法（ステップＳ７６）によって算出されたゲート電極材４４の寸法予測値（△）と今回処理におけるメタル材膜プラズマエッチング処理の処理時間とを、予め設定しておいたモデル式（式（１）等）に代入することで、プラズマエッチング処理後におけるメタル材膜４５の加工寸法を予測する（ステップＳ７９）。 A model equation (formula (1)) in which the predicted dimension value (Δ) of the gate electrode material 44 calculated by the above-described method (step S76) and the processing time of the metal material film plasma etching process in the current process are set. ) Etc.), the processing dimensions of the metal material film 45 after the plasma etching process are predicted (step S79).
　次に図３Ｇでは、Ｈｉｇｈ－ｋ材膜４６（このではHｆ酸化物）のプラズマエッチング処理を行う。この処理では、
・真空処理室１を0～100mTorr程度の低圧状態にする、
・上部電極６に0～1500W程度の電力を印加する、
・下部電極３にも所定の電力を印加する、
・ハロゲン化物（BCl3等）からなるガス種を真空処理室１内に導入する、
ことで真空処理室１にプラズマ放電を生じさせ、イオンと中性ラジカルを用いたイオンアシスト反応を発生させてＨｉｇｈ－ｋ材膜４６をエッチングする（ステップＳ５８）。 Next, in FIG. 3G, plasma etching of the high-k material film 46 (in this case, Hf oxide) is performed. In this process,
・ Vacuum processing chamber 1 is in a low pressure state of about 0-100mTorr.
・ Apply electric power of 0-1500W to the upper electrode 6.
Apply predetermined power to the lower electrode 3;
-Introduce a gas species consisting of halide (BCl 3 etc.) into the vacuum processing chamber 1;
As a result, plasma discharge is generated in the vacuum processing chamber 1, and an ion-assisted reaction using ions and neutral radicals is generated to etch the high-k material film 46 (step S58).
　このとき、Ｈｉｇｈ－ｋ材膜４６のエッチング処理中におけるセルフバイアス電位と、Bイオン,Clイオン,COイオン等に起因して生じる発光における発光強度とを測定し（ステップＳ８０）、これら測定値と、前述した手法（ステップＳ５７）にて算出したメタル材膜４５の寸法予測値とを、予め設定しておいたモデル式（式（１）等）に代入することで、プラズマエッチング処理後のＨｉｇｈ－ｋ材膜４６の加工寸法を予測する（ステップＳ８１）。 At this time, the self-bias potential during the etching process of the high-k material film 46 and the luminescence intensity in the luminescence caused by B ions, Cl ions, CO ions, etc. are measured (step S80). By substituting the predicted dimension value of the metal material film 45 calculated by the above-described method (step S57) into a preset model formula (formula (1), etc.), the high level after the plasma etching process is obtained. -The processing dimension of the k material film 46 is predicted (step S81).
　以上により、複数層の連続エッチング加工において、各エッチング処理後におけるパターンの形状や寸法を測定することなく以下のようにして予測することが可能となる。すなわち、真空処理室１内に生成されたプラズマ１３と真空処理室１の内壁または半導体基板４との間の生じる電荷量に応じて変動するバイアス電位を計測する一方、プラズマ１３中において各イオン種に基づいて生じる発光（それぞれ波長が異なる）の発光強度を測定する。そして、これら測定結果を予め設定しておいたモデル式に代入することで、各膜種のエッチング処理毎に、その膜種のエッチング後の加工寸法を予測する。これにより、次の膜のエッチング後寸法が所定の寸法値になるよう処理条件を変更したうえで連続して次の膜種のエッチング処理を行うことが可能となる。そのため、膜種毎にエッチング後寸法や形状を補正することができる。したがって、金属材料やＨｉｇｈ－ｋ材料を含む複数層の膜から構成されるゲート電極材料をドライエッチング加工する際、下地膜選択性が高くなってこれら材料を垂直な形状に加工することが可能となる。 As described above, in a continuous etching process of a plurality of layers, it is possible to predict as follows without measuring the shape and dimensions of the pattern after each etching process. That is, while measuring the bias potential varying according to the amount of charge generated between the plasma 13 generated in the vacuum processing chamber 1 and the inner wall of the vacuum processing chamber 1 or the semiconductor substrate 4, each ion species in the plasma 13 is measured. The emission intensity of light emission (wavelengths different from each other) generated based on the above is measured. Then, by substituting these measurement results into a preset model equation, the processing dimensions after etching of each film type are predicted for each etching process of each film type. This makes it possible to continuously perform the etching process for the next film type after changing the processing conditions so that the dimension after etching of the next film becomes a predetermined dimension value. Therefore, the dimension and shape after etching can be corrected for each film type. Therefore, when a gate electrode material composed of a plurality of layers including a metal material or a high-k material is dry-etched, the base film selectivity is increased, and these materials can be processed into a vertical shape. Become.
　さらには、Ｈｉｇｈ－ｋ材膜４６の加工においては、加工後の寸法予測値（△）と、予め設定されている計算値（□）と比較し、その寸法差（□－△）を算出したうえで、算出した寸法差（□－△）が予め設定しておいた値となるように、Ｈｉｇｈ－ｋ材膜４６の寸法予測データ（寸法差（□－△）等）を、レジストのプラズマ放電による寸法制御方法へフィードバックすることができる（図４の矢印Ａ参照）。そうすれば、Ｈｉｇｈ－ｋ材膜４６の加工寸法精度を、さらに向上させることができる。 Further, in the processing of the high-k material film 46, the dimension difference value (□ -Δ) was calculated by comparing the predicted dimension value (Δ) after processing with a preset calculation value (□). In addition, the predicted size data of the high-k material film 46 (eg, the size difference (□ -Δ)) is used as a resist plasma so that the calculated size difference (□ -Δ) becomes a preset value. It is possible to feed back to the dimension control method by discharging (see arrow A in FIG. 4). Then, the processing dimensional accuracy of the high-k material film 46 can be further improved.
　なお、上記実施形態では、ゲート電極材４４としてポリシリコンを挙げたが、これに限るものではなく、他の例として、TiSi,CoSi,PtSi,NiSi,WSi等を挙げることができる。また、メタル材膜４５としてTi窒化物を挙げたが、これに限るものではなく、他の例として、W,Ta,Pt,Ni,Co,Al等の金属またはこれらの合金を挙げることができる。 In the above embodiment, polysilicon is used as the gate electrode material 44. However, the present invention is not limited to this, and other examples include TiSi, CoSi, PtSi, NiSi, and WSi. Further, Ti nitride is exemplified as the metal material film 45, but the present invention is not limited to this, and other examples include metals such as W, Ta, Pt, Ni, Co, and Al or alloys thereof. .
　さらに演算部２５,上部電力制御部２８,下部電力制御部２９,ガス導入量制御装置３３等が実施する前述した手順の一部あるいは全部をコンピュータに実行させるためのプログラムを、インターネットなどの電気通信回線を用いたり、コンピュータ読み取り可能な記録媒体に格納したりすることで、関係者や第三者に提供することができる。例えばプログラムの指令を電気信号,光信号,磁気信号などで表現し、その信号を搬送波に載せて送信することで、同軸ケーブルや銅線,光ファイバのような伝送媒体でそのプログラムを提供することができる。またコンピュータ読み取り可能な記録媒体としては、ＣＤ－ＲＯＭ,ＤＶＤ－ＲＯＭなどの光学メディアや、フレキシブルディスクのような磁気メディアや、フラッシュメモリ,ＲＡＭのような半導体メモリを利用することができる。 Furthermore, a program for causing a computer to execute part or all of the above-described procedures performed by the arithmetic unit 25, the upper power control unit 28, the lower power control unit 29, the gas introduction amount control device 33, etc. By using a line or storing it in a computer-readable recording medium, it can be provided to related parties and third parties. For example, a program command is expressed by an electrical signal, an optical signal, a magnetic signal, etc., and the program is provided on a transmission medium such as a coaxial cable, copper wire, or optical fiber by transmitting the signal on a carrier wave. Can do. As a computer-readable recording medium, optical media such as CD-ROM and DVD-ROM, magnetic media such as a flexible disk, and semiconductor memory such as flash memory and RAM can be used.
　本発明は、金属材料やＨｉｇｈ－ｋ材料を含む複数層の膜から構成されるゲート電極材料をドライエッチング加工する際、下地膜選択性が高く垂直な形状への加工を安定に制御するプラズマ処理方法として有用である。 The present invention provides plasma processing that stably controls processing into a vertical shape with high base film selectivity when a gate electrode material composed of a plurality of layers including a metal material or a high-k material is dry-etched. Useful as a method.
　１　真空処理室
　２　真空排気器
　３　下部電極
　４　半導体基板（被処理物）
　５　ガス導入器
　６　上部電極（プラズマ励起電極）
　７、１１　高周波電源
　８、１５　インピーダンス整合器
　９、２６　測定回路
　１２　コイル
　１３　プラズマ
　１４　副生成物
　２５　演算部
　２８　上部電力制御部
　２９　下部電力制御部
　３０　発光分光強度測定器
　３１　情報処理装置
　３２　生産システム
　３３　ガス導入量制御装置
　４１　レジスト材
　４２　中間層
　４３　下層レジスト材
　４４　ゲート電極材(poly-Si等）
　４５　メタル材膜(TiN等)
　４６　Ｈｉｇｈ－ｋ材膜
　４７　半導体基板（Si基板） DESCRIPTION OF SYMBOLS 1 Vacuum processing chamber 2 Vacuum exhauster 3 Lower electrode 4 Semiconductor substrate (processed object)
5 Gas introduction device 6 Upper electrode (plasma excitation electrode)
7, 11 High- frequency power supply 8, 15 Impedance matching unit 9, 26 Measurement circuit 12 Coil 13 Plasma 14 By-product 25 Calculation unit 28 Upper power control unit 29 Lower power control unit 30 Emission spectral intensity measurement device 31 Information processing device 32 Production system 33 Gas introduction amount control device 41 Resist material 42 Intermediate layer 43 Lower layer resist material 44 Gate electrode material (poly-Si, etc.)
45 Metal material film (TiN, etc.)
46 High-k material film 47 Semiconductor substrate (Si substrate)

Claims (11)

  1. 　積層膜を表面に有する被処理物を真空処理室内の下部電極上に載置したうえで、前記被処理物にバイアス電位を形成するためのバイアス電力を前記真空処理室に供給しながら、当該真空処理室に複数のガスを含むエッチングガスを供給することで前記比処理物上にプラズマを発生させ、かつ前記エッチングガスの混合比と、前記バイアス電力とを適宜調整することで、前記積層膜を構成する膜それぞれに適した状態に前記プラズマを調整しつつ前記膜を膜毎にプラズマエッチング処理するプラズマ処理方法であって、
    　前記膜のプラズマエッチング処理毎に、前記プラズマの状態の時間変化を検知する第１の工程と、
    　前記膜のプラズマエッチング処理毎に、前記被処理物上に入射するイオンエネルギ分布と前記プラズマ中の各イオン種の密度とに基づいて前記膜の加工形状を予測したうえで、その予測結果が所望加工形状になるように前記バイアス電力と前記エッチングガスの混合比とを制御する第２の工程と、
    　を含む、
    　プラズマ処理方法。     The workpiece having the laminated film on the surface is placed on the lower electrode in the vacuum processing chamber, and the vacuum power is supplied to the vacuum processing chamber while supplying bias power for forming a bias potential to the workpiece. By supplying an etching gas containing a plurality of gases into the processing chamber, plasma is generated on the specific processing object, and the mixing ratio of the etching gas and the bias power are adjusted as appropriate, whereby the stacked film is formed. A plasma processing method for plasma-etching the film for each film while adjusting the plasma to a state suitable for each of the films to be configured;
    A first step of detecting a time change of the plasma state for each plasma etching treatment of the film;
    For each plasma etching process of the film, the processing shape of the film is predicted based on the distribution of ion energy incident on the object to be processed and the density of each ion species in the plasma. A second step of controlling the mixing ratio of the bias power and the etching gas so as to obtain a processed shape;
    including,
    Plasma processing method.
  2. 　前記積層膜は、金属材料を有する酸化膜とＨｉｇｈ－ｋ材膜とのうちのすくなくとも一つを含む、
    　請求項１のプラズマ処理方法。     The laminated film includes at least one of an oxide film having a metal material and a high-k material film.
    The plasma processing method according to claim 1.
  3. 　前記エッチングガスは有機ハロゲン化物とO2ガスとの混合ガスであり、
    　前記バイアス電力は前記下部電極に印加する電力を含み、
    　前記第２の工程は、
    　前記予測結果に応じて、前記下部電極に印加する電力を可及的にゼロにした状態で前記バイアス電力を供給することで前記被処理物上に前記プラズマを発生させ、当該プラズマによって生じる前記有機ハロゲン化物と前記O2ガスとの分解反応で生成される副成分物を前記膜の前記加工形状に堆積させて当該加工形状の形状調整を行う第１の調整工程を、
    　含む、
    　請求項１のプラズマ処理方法。     The etching gas is a mixed gas of organic halide and O 2 gas,
    The bias power includes power applied to the lower electrode,
    The second step includes
    According to the prediction result, the plasma is generated on the workpiece by supplying the bias power with the power applied to the lower electrode as zero as possible, and the organic generated by the plasma is generated. A first adjustment step of adjusting the shape of the processed shape by depositing by-products generated in the decomposition reaction between the halide and the O 2 gas on the processed shape of the film;
    Including,
    The plasma processing method according to claim 1.
  4. 　前記第２の工程は、第２の調整工程をさらに含み、
    　前記第２の調整工程では、
    　前記第１の調整工程を行ったのち、前記下部電極への電力印加を再開して前記膜のプラズマエッチング処理を行なうことで、前記第１の調整工程によって形状調整された前記膜の前記加工形状を削除調整する、
    　請求項３のプラズマ処理方法。     The second step further includes a second adjustment step,
    In the second adjustment step,
    After performing the first adjustment step, the power application to the lower electrode is resumed and the film is subjected to plasma etching, whereby the processed shape of the film whose shape has been adjusted by the first adjustment step Remove, adjust,
    The plasma processing method of Claim 3.
  5. 　前記第２の工程は、
    　前記真空処理室の内壁と前記プラズマとの間の電荷量に応じて変動する物理量と、前記エッチングガスに基づく各イオン種に起因して前記プラズマ内で生じる発光の発光強度とを測定する測定工程と、
    　前記測定工程の測定結果を、あらかじめ設定しておいたモデル式に代入することで、前記膜の前記加工形状を予測する予測工程と、
    　をさらに含む、
    　請求項１のプラズマ処理方法。     The second step includes
    A measurement step of measuring a physical quantity that varies according to an amount of electric charge between the inner wall of the vacuum processing chamber and the plasma, and an emission intensity of light emission generated in the plasma due to each ion species based on the etching gas. When,
    By substituting the measurement result of the measurement step into a model equation set in advance, a prediction step of predicting the processed shape of the film,
    Further including
    The plasma processing method according to claim 1.
  6. 　前記積層膜は、前記膜の下方に位置して当該膜の次に当該膜をエッチングマスクにしてプラズマエッチング処理される下側膜を有しており、
    　前記第２の工程では、
    　前記下側膜の加工形状を、前記膜の前記予測結果に基づいて予測したうえで、当該下側膜の予測結果が予め設定された規格値になるように、前記バイアス電力と、前記エッチングガスの混合比とを制御して前記下側膜のプラズマエッチング処理を行う、
    　請求項１のプラズマ処理方法。     The laminated film has a lower film positioned below the film and plasma-etched using the film as an etching mask next to the film,
    In the second step,
    After predicting the processing shape of the lower film based on the prediction result of the film, the bias power and the etching gas are set so that the prediction result of the lower film becomes a preset standard value. The lower layer film is plasma etched by controlling the mixing ratio of
    The plasma processing method according to claim 1.
  7. 　前記第２の工程では、前記積層膜において前記膜と前記下側膜とを設定して行う各膜のプラズマエッチング処理を繰り返し実施することで、各膜を、当該膜に設定された所望加工形状に成形する、
    　請求項６のプラズマ処理方法。     In the second step, each film is formed into a desired processing shape set in the film by repeatedly performing a plasma etching process of each film performed by setting the film and the lower film in the stacked film. To mold,
    The plasma processing method according to claim 6.
  8. 　前記第２の工程では、
    　各膜のプラズマエッチング処理毎に当該プラズマエッチング処理を実施する各種設備から設備パラメータを取得したうえで、
    　取得した前記設備パラメータに基づいて、前記被処理物上に入射するイオンエネルギ分布と前記プラズマ中の各イオン種の密度とを算出し、かつ前記予測結果と前記所望加工形状とを比較することで、前記加工形状の要否を判定する、
    　請求項１のプラズマ処理方法。     In the second step,
    After obtaining equipment parameters from various facilities that perform the plasma etching process for each plasma etching process of each film,
    By calculating the ion energy distribution incident on the workpiece and the density of each ion species in the plasma based on the acquired equipment parameters, and comparing the prediction result with the desired processing shape , Determining whether the processed shape is necessary,
    The plasma processing method according to claim 1.
  9. 　積層膜を表面に有する被処理物が収納される真空処理室と、
    　前記被処理物にバイアス電位を形成するためのバイアス電力を前記真空処理室に供給する高周波電源と、
    　前記真空処理室に設けられて前記被処理物が載置されるとともに、前記バイアス電力を前記真空処理室に印加する複数の電極のうちの一つである下部電極と、
    　複数のガスを含むエッチングガスを前記真空処理室に供給するガス導入器と、
    　前記下部電極のバイアス電位を測定する測定回路と、
    　前記プラズマの発光分光強度を測定する測定器と、
    　前記下部電極に印加される前記バイアス電力を制御する下部電力制御部と、
    　前記エッチングガスを構成するガス種の選定と選定した前記ガス種の混合比とを制御するガス導入量制御装置と、
    　前記ガス導入量制御装置が制御する前記ガス種の選定並びに前記エッチングガスの混合比と、前記下部電力制御部が制御する前記バイアス電力とを適宜調整することで、前記積層膜を構成する膜それぞれのエッチングに適した状態に前記プラズマを調整する演算部と、
    　を備え、
    　前記演算部は、前記測定回路の測定結果と前記測定器の測定結果とに基づいて前記膜の加工形状を予測したうえで、その予測結果が所望加工形状になるように、前記下部電力制御部および前記ガス導入量制御装置を制御する、
    　プラズマ処理装置。     A vacuum processing chamber in which an object to be processed having a laminated film is stored;
    A high-frequency power supply for supplying a bias power to the vacuum processing chamber for forming a bias potential in the workpiece;
    A lower electrode that is one of a plurality of electrodes that are provided in the vacuum processing chamber and on which the workpiece is placed and that applies the bias power to the vacuum processing chamber;
    A gas introducer for supplying an etching gas containing a plurality of gases to the vacuum processing chamber;
    A measurement circuit for measuring the bias potential of the lower electrode;
    A measuring instrument for measuring the emission spectral intensity of the plasma;
    A lower power controller that controls the bias power applied to the lower electrode;
    A gas introduction amount control device for controlling selection of a gas type constituting the etching gas and a mixing ratio of the selected gas type;
    Each of the films constituting the laminated film is appropriately adjusted by selecting the gas type controlled by the gas introduction amount control device and adjusting the mixing ratio of the etching gas and the bias power controlled by the lower power control unit. An arithmetic unit for adjusting the plasma to a state suitable for the etching of
    With
    The arithmetic unit predicts the processing shape of the film based on the measurement result of the measurement circuit and the measurement result of the measuring device, and then the lower power control unit so that the prediction result becomes a desired processing shape. And controlling the gas introduction amount control device,
    Plasma processing equipment.
  10. 　前記演算部は、前記測定回路の測定結果と前記測定器の測定結果とを、あらかじめ設定しておいたモデル式に代入することで、前記膜の前記加工形状を予測する、
    　請求項９のプラズマ処理装置。     The calculation unit predicts the processing shape of the film by substituting the measurement result of the measurement circuit and the measurement result of the measuring instrument into a model equation set in advance.
    The plasma processing apparatus according to claim 9.
  11. 　積層膜を表面に有する被処理物を真空処理室内の下部電極上に載置したうえで、前記被処理物にバイアス電位を形成するためのバイアス電力を前記真空処理室に供給しながら、当該真空処理室に複数のガスを含むエッチングガスを供給することで前記比処理物上にプラズマを発生させ、かつ前記エッチングガスの混合比と、前記バイアス電力とを適宜調整することで、前記積層膜を構成する膜それぞれに適した状態に前記プラズマを調整しつつ前記膜を膜毎にプラズマエッチング処理するプラズマ処理方法であって、
    　前記膜のプラズマエッチング処理毎に、前記プラズマの状態の時間変化を検知する第１の工程と、
    　前記膜のプラズマエッチング処理毎に、前記被処理物上に入射するイオンエネルギ分布と前記プラズマ中の各イオン種の密度とに基づいて前記膜の加工形状を予測したうえで、その予測結果が所望加工形状になるように前記バイアス電力と前記エッチングガスの混合比とを制御する第２の工程と、
    　を含む、
    　プラズマ処理方法をコンピュータで実行するプログラムが保存されたコンピュータ読み取り可能な記録媒体。     The workpiece having the laminated film on the surface is placed on the lower electrode in the vacuum processing chamber, and the vacuum power is supplied to the vacuum processing chamber while supplying bias power for forming a bias potential to the workpiece. By supplying an etching gas containing a plurality of gases into the processing chamber, plasma is generated on the specific processing object, and the mixing ratio of the etching gas and the bias power are adjusted as appropriate, whereby the stacked film is formed. A plasma processing method for plasma-etching the film for each film while adjusting the plasma to a state suitable for each of the films to be configured;
    A first step of detecting a time change of the plasma state for each plasma etching treatment of the film;
    For each plasma etching process of the film, the processing shape of the film is predicted based on the distribution of ion energy incident on the object to be processed and the density of each ion species in the plasma. A second step of controlling the mixing ratio of the bias power and the etching gas so as to obtain a processed shape;
    including,
    A computer-readable recording medium storing a program for executing a plasma processing method on a computer.
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