JP2005142582A - Semiconductor fabrication apparatus, and processing method therefor - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor fabrication apparatus and its processing method that can determine, by measurement or calculation, wafer voltage during processing and impedance from the wafer to the earth through plasma by use of a plasma etcher, a plasma CVD, and the like, thus doing processing based on the impedance. <P>SOLUTION: The semiconductor fabrication apparatus can be completed by having a wafer potential probe 24, a current/voltage probe 17 that measures at least either one of voltage and current applied to a wafer stage, a calculation part that determines impedance from the wafer to the earth through plasma on the basis of a wafer voltage value, a voltage value or a current value applied to the wafer stage, and a processing part that does processing based on the impedance. Use of the above permits wafer voltage and plasma impedance to be precisely found, and controlling etching parameters on the basis of this information allows reproducible etching to be achieved, thus preventing the yield from being lowered. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to a semiconductor manufacturing apparatus and processing method for processing a semiconductor wafer using plasma, and a wafer potential probe.

  As semiconductor devices have been highly integrated in recent years, circuit patterns have been increasingly miniaturized, and the required processing dimension accuracy has become increasingly severe. In addition to increasing the wafer size for the purpose of improving productivity, application of new materials and changes in the wiring structure are being studied in order to improve device performance. Along with this, development of new process technology has been promoted, and development of process technology has become very difficult and costly.

  Further, in a semiconductor manufacturing apparatus that processes a wafer using plasma, such as a plasma etcher or plasma CVD, it is very important to accurately grasp and control the energy of ions incident on the substrate. As a result, the process start-up period can be shortened. Conversely, if the ion energy cannot be accurately grasped, problems such as variations in product performance and a decrease in yield arise.

  An example of a method for monitoring and controlling the energy of ions incident on the substrate during such plasma processing is disclosed in, for example, Japanese Patent Laid-Open No. 7-135180. In this disclosed example, an electrode on which a substrate to be processed is loaded is grounded via a capacitor, and a potential measuring means for measuring the potential between the capacitor and the electrode is provided to measure the potential of the substrate being processed. Is disclosed.

  USP5808415 and USP6061006 disclose a method for manufacturing a probe for measuring the current and voltage applied to plasma, and how to determine the plasma impedance in the plasma chamber.

JP-A-7-135180 USP5808415 Publication USP6061006 Publication

  However, in the disclosed example of Japanese Patent Laid-Open No. 7-135180, as a method for measuring the surface potential of the substrate in order to control the energy of ions incident on the substrate, an electrode on which the substrate is loaded and a capacitor connected to the electrode are used. Since the voltage between them is measured with a voltmeter and the potential of the substrate is not directly measured, it may cause a problem. For example, when the substrate is attracted and fixed by an electrostatic chuck and etching is performed, an example in which deposits adhere to the surface of the electrostatic chuck as the number of wafers processed increases. This will be described with reference to FIG. In the disclosed example, in order to obtain the surface potential Vg of the substrate, a capacitor C1 having a known capacitance is connected to the electrode on which the substrate is mounted. A method is disclosed in which the capacitance Cg of the substrate is examined in advance, the potential Vs is measured by the means shown in the disclosed example, and Vg is calculated by Vs + (C1 / Cg) * Vs. If the electrode has an electrostatic chuck function and a dielectric film or the like is attached to the electrode surface, Cg may be corrected in consideration of the capacitance of the dielectric film. If the deposit adheres to the surface of the dielectric film as compared to immediately after the etching process is started, the capacitance Cg changes, and as a result, the substrate potential cannot be obtained accurately.

  In actual manufacturing equipment, the terminal connected to the electrode is not only electrically connected to the substrate via the electrode, but also supplies an electric circuit connected to the ground via a capacitor component and high-frequency power. There is an inductance component of the power supply line. Therefore, even if the potential across the capacitor connected to the electrode is simply measured, the actual potential of the substrate is not accurately measured.

  In addition, for example, in the etching process, when a reaction product or the like adheres to the inner wall of a vacuum chamber in which plasma is confined, even if the potential of the substrate can be measured by the method of the disclosed example, If the plasma state itself has changed, the processing result may change even if the substrate voltage is controlled.

  On the other hand, in the disclosed examples of USP5808415 and USP6061006, the plasma network impedance network is expressed by chamber resistance, electrode inductance, electrode-to-ground capacitance, and stray capacitance, and the true plasma impedance is obtained from the current and voltage waveforms present during discharge. A method is disclosed. However, in this disclosed example, since the surface potential of the wafer processed in plasma cannot be obtained, there is a problem that the ion energy incident on the wafer cannot be controlled.

  In order to solve these problems, both the substrate potential and the plasma impedance are measured or calculated, and in some cases, the impedance of the deposit attached to the inner wall of the vacuum chamber is measured or calculated, and these are calculated. It is necessary to appropriately control the etching parameters based on the above information.

  Accordingly, a first object of the present invention is to manufacture a semiconductor device that measures or calculates the potential of the substrate being processed and the impedance from the substrate to the ground via the plasma in a semiconductor manufacturing apparatus using plasma. It is to provide an apparatus and a processing method.

  The second object of the present invention is to measure or calculate the potential of the substrate being processed and the impedance from the substrate to the ground via the plasma in a semiconductor manufacturing apparatus using plasma, and based on these information. Another object of the present invention is to provide a semiconductor manufacturing apparatus and a processing method capable of controlling etching parameters.

  A third object of the present invention is to provide a semiconductor manufacturing apparatus and a process capable of easily determining an appropriate cleaning time by monitoring the thickness of a film adhering to a processing chamber wall in a semiconductor manufacturing apparatus using plasma. Is to provide a method.

  A fourth object of the present invention is a semiconductor manufacturing apparatus using plasma, in which a potential of a substrate being processed, a potential of a susceptor disposed so as to surround the substrate, and a ground via a plasma on the substrate being processed. Measure the impedance up to and the impedance to the ground through the plasma on the susceptor or obtain it by calculation, and based on this information, you can control the bias voltage applied to the substrate and susceptor independently It is to provide an apparatus and a processing method.

  A fifth object of the present invention is to provide a probe capable of measuring the potential of a substrate being processed and a susceptor arranged so as to surround the substrate.

  The first object is applied to a wafer stage from a wafer potential probe that measures the voltage of the semiconductor wafer from the back surface of the semiconductor wafer and a high-frequency power source, for example, in a semiconductor manufacturing apparatus that processes a semiconductor wafer using plasma. Having a current / voltage probe for measuring at least one of a voltage value and a current value, the semiconductor wafer voltage value measured by the wafer potential probe and the voltage or current value measured by the current / voltage probe from the semiconductor This can be accomplished by calculating the impedance to ground via plasma on the wafer.

  The second object can be achieved, for example, by controlling various processing parameters based on at least one of the obtained impedance and wafer potential.

  In addition, for example, the impedance is calculated from the voltage and current measured by the current / voltage probe, and this impedance and the equivalent from the high-frequency power source (precisely the current / voltage probe) obtained in advance to the ground via the plasma. This can be achieved by calculating the impedance from the wafer to the ground via the plasma and the potential of the wafer by calculating the synthetic impedance of the circuit model and controlling various processing parameters based on this impedance and the potential of the wafer.

  Further, for example, if a film thickness probe capable of measuring the film thickness of the film attached to the inner wall of the vacuum processing chamber is provided and the impedance of the film thickness measured by this probe is calculated, the surface of the film attached to the processing chamber wall from the wafer is calculated. Since the impedance up to (the plasma impedance) can be accurately calculated, the etching can be controlled more accurately by controlling various parameters based on this information.

  The third object is, for example, to provide a means for measuring the thickness of a film attached to the inner wall of a vacuum processing chamber in a semiconductor manufacturing apparatus for processing a semiconductor wafer using plasma, and monitor the film thickness during processing. This can be achieved.

  The fourth object is applied to a wafer stage from a wafer potential probe that measures the voltage of the semiconductor wafer from the back surface of the semiconductor wafer and a high-frequency power source, for example, in a semiconductor manufacturing apparatus that processes a semiconductor wafer using plasma. A current / voltage probe for measuring at least one of a voltage and a current value, and a susceptor potential probe for measuring a voltage of a susceptor arranged so as to surround the semiconductor wafer, the semiconductor wafer measured by the wafer potential probe The voltage value, the voltage or current value measured by the current / voltage probe, and the impedance from the susceptor voltage value measured by the susceptor potential probe to the ground via the plasma on the semiconductor wafer and the plasma on the susceptor. Calculate the impedance to the ground, and It can be achieved by controlling the RF voltage applied to the motor independently.

  Further, for example, if a film thickness probe capable of measuring the film thickness of the film attached to the inner wall of the vacuum processing chamber is provided and the impedance of the film thickness measured by this probe is calculated, the surface of the film attached to the processing chamber wall from the wafer is calculated. Since the impedance from the susceptor to the surface of the film attached to the processing chamber wall can be calculated, the etching can be controlled more accurately by controlling various parameters based on this information.

  The fifth object is to support, for example, an electrically conductive stylus that is brought into contact with the back surface of the semiconductor wafer whose voltage is to be measured by an elastic member having electrical conductivity, and this elastic member is fixed to the vacuum chamber. It can be achieved by exposing to the atmosphere side while being electrically insulated from the flange for measuring the voltage of this portion.

  In addition, for example, the position in the height direction of the stylus can be measured with good reproducibility by enabling adjustment from the atmosphere side. Further, if the material of the stylus is harder than the hardness of the silicon oxide existing on the back surface of the wafer, measurement can be performed with higher reproducibility.

  As described above, according to the present invention, since the potential of the wafer being processed with plasma and the current flowing in the plasma can be measured, the wafer potential and the plasma impedance can be accurately obtained. In addition, by controlling the etching parameters and controlling the ion energy, it is possible to achieve etching with good reproducibility and prevent the yield from decreasing. That is, a semiconductor manufacturing apparatus with low manufacturing cost can be provided.

  In addition, since the potential of the wafer being processed can be directly monitored, if a rapid change in the wafer potential is observed, it is possible to quickly determine that an etching abnormality has occurred and minimize wafer waste. It can be expected that the manufacturing cost can be reduced.

  Further, according to the present invention, the potential of the wafer being processed with plasma, the potential of the silicon susceptor disposed around the wafer, the current flowing from the wafer into the plasma, and the current flowing into the plasma from the silicon susceptor can be measured. And the plasma impedance on the silicon susceptor can be calculated. Therefore, by controlling the etching conditions based on the information on the wafer potential and plasma impedance, it is possible to provide a semiconductor manufacturing apparatus that can perform etching with good reproducibility.

  In addition, according to the present invention, since the high frequency voltage applied to the wafer and the high frequency voltage applied to the silicon plate can be distributed, the distribution of plasma incident on the wafer can be controlled. Therefore, a semiconductor manufacturing apparatus capable of controlling the etching distribution in the wafer surface can be provided.

  Furthermore, according to the present invention, it is possible to provide a probe capable of measuring the wafer potential during processing with plasma from the back surface of the wafer.

  Embodiments in which the present invention is applied to a plasma etching apparatus will be described below.

  First, a first embodiment of the present invention will be described with reference to FIGS. In the following description, components having the same functions as those of the first embodiment are denoted by the same reference numerals as those of the first embodiment, and description thereof is omitted.

FIG. 1 shows an example of a plasma etching apparatus according to the first embodiment of the present invention. The processing gas 1 introduced into the processing chamber is in a plasma 4 state by being inductively coupled and capacitively coupled by a magnetic field and an electric field created by a coil 3 connected to a high frequency power source 2 and applied with a high frequency voltage at both ends. The semiconductor wafer 5 is loaded on the wafer stage 6. The wafer stage 6 is provided with a ceramic dielectric film 7 on the surface, and has an electrostatic chuck function. The wafer stage 6 is fixed on the electrode 8 with a bolt, and is electrically insulated from the vacuum chamber 10 by an insulating plate 9. Further, the electrode 8 electrically connected to the wafer stage 6 is connected to a power feed rod 12 electrically insulated from the flange 11 so that power can be supplied from an external power source using the power feed rod 12. It has become. In this embodiment, a high frequency power supply 13 having a frequency of 800 kHz is connected to a wafer stage via a matching box 14 in order to apply a bias voltage to the wafer in order to effectively attract ions in the plasma to the wafer. Reference numerals 15 and 16 denote impedance matching coils and variable capacitance capacitors. The voltage and current value at the exit of the matching box 14 are monitored by a current / voltage probe 17 and input to an external computer 18. The computer 18 has a calculation unit for obtaining an impedance from the semiconductor wafer to the ground via the plasma based on the measured voltage value or current value, and a process (for example, display process, parameter control process) based on the obtained impedance. Etc.). Further, a DC power source 19 for causing the electrostatic chuck to function is also connected to the power supply rod 12. This DC power source is connected via a coil 20 for cutting high-frequency voltage, and when a DC voltage is applied to the wafer stage while the plasma 4 is ignited, the wafer 7 is in contact with the vacuum chamber. A DC voltage circuit is formed through the plasma at the ground potential, a potential difference is generated between the wafer 7 and the electrode 8, and the dielectric film 7 is charged and adsorbed by Coulomb force. Reference numeral 21 denotes a cover for protecting the outer periphery of the electrode 8 and the wafer stage 6 from plasma. Reference numerals 22 and 23 denote turbo molecular pumps and dry pumps for exhausting the processing gas and reaction products. Reference numeral 24 denotes a wafer potential probe for measuring the potential of the wafer during plasma processing. The display unit 80 is for displaying and monitoring the impedance obtained by the computer, and is a CRT, for example. The parameter control device 82 controls various parameters of the semiconductor manufacturing apparatus (plasma etching apparatus) in accordance with instructions from the computer 18.

  FIG. 2 shows a detailed configuration diagram of the wafer potential probe 24. In FIG. 2, the wafer potential probe 24 is composed of components other than the components indicated by reference numerals 5-10. The wafer potential probe used in the present invention comprises an electrically conductive stylus 36 that contacts the back surface of the semiconductor wafer to be measured, an electrically conductive elastic member 35 that supports the stylus, A current introduction terminal 27 having a flange structure while supporting an elastic member, the potential of the stylus can be measured on the atmosphere side, and the position of the stylus in the height direction can be adjusted from the atmosphere side. Configured as follows. Details of the configuration will be described below.

The vacuum chamber 10, the insulating plate 9, the electrode 8, and the wafer stage 6 are provided with coaxial through holes, and ceramic insulating pipes for electrically insulating the probe from the electrodes and the wafer stage are provided in the through holes. 68 is embedded. The wafer potential probe has a flange 25 structure so that it can be attached to a vacuum chamber, and is vacuum sealed with an O-ring 70. A through hole is provided in the center of the flange, and a female screw 26 is provided in a part of the through hole. A terminal 27 for measuring the voltage of the wafer is attached to the through hole. The terminal 27 has a structure in which a hollow insulating pipe 71 is embedded therein, and a conductive core wire 69 is embedded therein. A part of the outer periphery of the terminal 27 has a male screw 28 structure and is attached to a female screw 26 provided on the flange. Further, an O-ring 29 is provided on the upper portion of the terminal, and the inner surface 30 of the upper portion of the flange 25 can be sealed. A conductive connecting rod 32 is provided at the end of the terminal core wire on the vacuum side. The connecting rod 32 has a socket 33 structure so that one end thereof receives the core wire, and a coil spring 35 is attached to the other end using a spring stopper 34. A stylus 36 is provided on the upper portion of the coil spring 35 so as to be driven up and down along the connecting rod. The stylus is attached such that the tip protrudes from the wafer stage surface, and moves downward by weight when the wafer is placed. This protrusion amount is determined in consideration of the spring constant of the coil spring. Desirably, it is sufficient that the semiconductor wafer is fully submerged to the wafer stage by its own weight when the semiconductor wafer is loaded on the wafer stage. Further, the stylus is made of a conductive material, and the tip thereof has a radius of curvature and hardness enough to break through the oxide film and nitride film present on the back surface of the semiconductor wafer. In this embodiment, the material of the stylus is tungsten carbide, but other materials such as conductive diamond can also be used. The value of the radius of curvature should be determined by the spring constant of the coil spring and the amount of protrusion of the stylus, that is, the amount of deformation of the spring, and is appropriately determined depending on the state of the semiconductor wafer that is actually measured. As an example, the radius of curvature R required when the spring constant of the coil spring 35 is k, the protrusion amount is L, and an oxide film having a thickness t is attached to the back surface of the 8-inch wafer is shown. When the weight of an 8-inch wafer is set to W, the Young's modulus and Poisson's ratio of the stylus are set to E _n and ν _n , respectively, and the Young's modulus and Poisson's ratio of the oxide film are set to E _w and ν _W , respectively, The radius “a” of the contact circle between the front end and the oxide film on the back of the wafer can be expressed by equation (1).
a = {3WR ((1−ν _n ² ) / E _n + (1−ν _W ² ) / E _w ) / 4} ^1/3 (1) Formula (2) Calculated by
p = 3W / 2πa ² (2) Equation If the pressure p is larger than the hardness of the oxide film, the stylus penetrates the oxide film and makes electrical contact with conductive silicon, and the potential of the wafer can be measured. It becomes. That is, when the Vickers hardness of the oxide film is Hv, it can be understood that any curvature radius R satisfying the expression (3) is sufficient.
Hv <p (3) Formula The amount of protrusion of the stylus 36 when the wafer is not placed is adjusted by adjusting the position of the terminal 27 described above. If a scale is attached to the atmosphere side of the terminal so that the amount of the tip of the stylus protruding from the wafer stage 7 can be easily determined from the atmosphere side, the operation becomes easier. A nut 31 can be attached to the atmosphere side of the terminal 27 and fixed after the position of the stylus is determined, and the vertical position of the terminal can be arbitrarily set. Accordingly, since the potential substantially equal to the potential of the wafer being processed can be observed on the core wire of the terminal, the potential of the wafer can be measured by measuring the voltage of this core wire with a voltmeter. Reference numeral 62 denotes an insulating cylinder for electrically insulating the probe from the wafer stage, electrodes, and insulator.

Next, how to obtain the impedance (plasma impedance) from the wafer to the ground through plasma will be described. FIG. 3 shows an equivalent circuit model from the high frequency power source (more precisely, current / voltage probe) to the ground via the wafer stage in the first embodiment of the present invention. This equivalent circuit model may be examined in advance with an impedance measuring machine or the like. In the figure, reference numeral 37 denotes the electric potential of the vacuum chamber 10 and is ground. 38 is a plasma impedance on the wafer, 39 is a resistance component of the dielectric film 7, 40 is a capacitance component of the dielectric film 7, 41 is a blocking capacitor, and others are as described above. The measured values of the wafer potential 42Vw measured by the wafer potential probe 24, the voltage 43Ve of the electrode connected to the exit of the matching box, and the current 44Ie flowing into the electrode are taken into a computer. When the plasma impedance 38 is set to Zp, the voltage applied to Zp at a certain time is the output voltage of the wafer potential probe 24, that is, the wafer potential Vw,
Since the current flowing through Zp is the current 44Ie flowing into the electrode, Zp can be calculated by Vw / Ie. The value of Zp can be read after being processed one by one in the computer. In this embodiment, in order to obtain Zp, the voltage at the outlet of the matching box, that is, the electrode potential 43Ve is measured as the voltage value, but the potential 42Vw of the wafer actually being processed is measured. The reason is that in this embodiment, the dielectric film 7 is attached to the surface of the wafer stage for the purpose of providing an electrostatic chuck function. A voltage drop occurs at this portion, and the voltage at the exit of the matching box, that is, the electrode voltage Ve. This is because the voltage of the wafer does not become. That is, in order to obtain the value of plasma impedance, if the voltage value Ve measured at the exit of the matching box is used to calculate Ve / Ie, the actual plasma impedance is not obtained.

  As an example of a problem when the plasma impedance is calculated by Ve / Ie, it is conceivable that a deposition film adheres to the surface of the dielectric film on the wafer stage as the number of processed wafers increases. When the deposition film adheres and the capacitance of the dielectric film decreases, the impedance increases, so the voltage at the exit of the matching box increases. Therefore, even though the plasma state has not changed, it is judged as if the plasma impedance has increased. If the voltage Ve of the electrode is lowered in order to keep the etching rate constant based on this information, the etching rate will be lowered, resulting in an etching failure. Conversely, if the input power of the high-frequency power source for generating plasma is increased in order to reduce the plasma impedance, the etching rate increases too much, leading to over-etching. As a result, etching failure is caused.

  On the other hand, when the plasma impedance Zp is obtained with the configuration of the present embodiment, the result of directly measuring the wafer voltage is used to calculate the plasma impedance, so that more accurate impedance and wafer potential can be measured or Since it can be obtained by calculation, for example, the ion energy incident on the wafer being processed, that is, the bias voltage of the wafer can be appropriately adjusted, and etching defects can be prevented.

FIG. 11 is a flowchart showing the flow of processing until the wafer potential Vw and the plasma impedance Zp according to the first embodiment of the present invention are obtained and used. The following processing from FIG. 11 to FIG. 16 is executed by a program in the computer 18 shown in FIG. 1, FIG. 4, FIG. 6, and FIG. First, an equivalent circuit model from the high frequency power source (more precisely, current / voltage probe) to the ground via the wafer stage in the first embodiment is determined as shown in FIG. 3 (step 110). Next, the wafer potential Vw, the wafer stage current Ie, and the voltage Ve are measured using the wafer potential probe and the current / voltage probe (step 111). Next, the plasma impedance Zp is calculated by the computer 18 that has captured the measurement result (step 112). Eventually, it should be determined by the user's judgment, but when the wafer potential Vw and the plasma impedance Zp are monitored, they are displayed on the display unit 80 (step 113). Further, when controlling the process parameter based on the obtained impedance or the like, a signal, information, etc. are sent from the computer 18 to the process parameter control device 82, and the control signal is sent from the control device 82 to the target of parameter control, For example, the parameters are sent to the high frequency power source 13 and the like to control various parameters (step 114).

  If the condition of the inner wall of the processing chamber does not change due to the plasma processing or if a certain condition is maintained by cleaning (there is no deposit film on the inner wall of the processing chamber), the calculated impedance is calculated from the semiconductor wafer. By setting the impedance to the vacuum processing chamber wall through plasma and controlling various processing parameters based on the calculated impedance, it is possible to process a semiconductor wafer being processed with plasma.

  As described above, according to the present invention, it is possible to perform processing while accurately measuring the potential of the wafer while monitoring the plasma state based on the plasma impedance. Therefore, the potential of the wafer can be controlled based on these results. Thus, since ion energy incident on the wafer can be used accurately, etching with good reproducibility can be achieved, and a decrease in yield can be prevented.

  In this embodiment, the case where the bias voltage is controlled as a parameter controlled using the plasma impedance has been described. However, the present invention is not necessarily limited to this. Other control parameters include, for example, the frequency or power of a high-frequency power source for generating plasma, the frequency or voltage or power of a high-frequency power source applied to the wafer stage, the temperature and temperature distribution of the vacuum chamber wall, and the temperature and temperature of the wafer. Examples include distribution, processing pressure, gas type and flow rate and mixing ratio of processing gas, intensity and intensity distribution of magnetic field applied to plasma, etching time, and the like. It is also conceivable to control by combining a plurality of these parameters.

  In addition, the semiconductor product described by the processing method described in this embodiment has an important advantage over a product manufactured without applying the method of this embodiment. This is because the processing of the wafer is always performed within a certain range of conditions, so that processing with very good reproducibility is performed, so that there is no variation in performance between products, that is, the product is highly reliable. Therefore, since the yield at the time of manufacture is good, the cost is low and the product is inexpensive.

  In this embodiment, the plasma impedance is obtained by calculation based on the wafer potential and the voltage and current value at the matching box outlet, and the etching parameters are controlled based on this result. Not just controlling parameters. For example, the plasma impedance may be used to monitor the etching state. In some cases, the potential of the wafer or the voltage or current at the exit of the matching box is monitored, and this change information can be used to determine when to stop or maintain the device. It can also be decided. For example, if the number of etching processes is repeated while monitoring the wafer potential, and a sudden change in wafer potential is observed during a certain process, it can be easily predicted that some abnormality has occurred. In other words, it can also be used as a monitor for checking whether or not the etching process is proceeding normally. In this case, since it is possible to immediately determine that an abnormality has occurred in the apparatus, it is possible to minimize the waste of the wafer.

  In this embodiment, a rod body having a coil spring is used as the elastic member for supporting the stylus. However, it is not always necessary, and a leaf spring may be used. The important points are that the stylus has elasticity in the vertical direction and that the position of the entire stylus can be arbitrarily adjusted in the vertical direction from the main body side.

  Furthermore, in this embodiment, the probe for measuring the potential of the wafer is a probe of the type that is in direct contact with the back surface of the wafer. However, the present invention is not limited to this. For example, a method of measuring the potential of the wafer by embedding a capacitance type non-contact electrometer in the wafer stage is also conceivable. However, in this case as well, it is conceivable that the absolute value of the voltage of the wafer changes depending on the attachment position of the electrometer. Therefore, it is necessary to adjust the attachment position from the outside of the vacuum chamber as in this embodiment.

  In the present embodiment, the voltage of the wafer is measured in order to obtain the impedance (plasma impedance) from the wafer to the ground via plasma. However, it is also possible to calculate the impedance and the wafer voltage from the equivalent circuit model, the voltage 43Ve of the electrode connected to the outlet of the matching box, and the current 44Ie flowing into the electrode. This method is effective in a process in which the cleanliness due to wear powder (foreign matter) from the back surface of the wafer, which is generated when the stylus of the wafer potential probe 24 contacts and slides on the back surface of the wafer, is also a problem. . For example, this may be the case when foreign matter adhering to the back surface of the wafer is transferred to the front surface of the wafer in a process (for example, wet cleaning) performed after the plasma process. This will be described below.

First, the phase difference θ is obtained by a computer calculation process that is taken from the waveform Ve (t) accompanying the time change of the electrode voltage 43Ve and the waveform Ie (t) accompanying the time change of the current 44Ie. At this time, the impedance at the matching box outlet is displayed as an imaginary number and set to a + bj. here,
a = Z / (1+ (tan θ) ² ) ^0.5 ,
b = Z * tanθ / (1+ (tanθ) ² ) ^0.5
Z = Ve / Ie
It becomes. Similarly, the plasma impedance is expressed as an imaginary number and set as c + dj. The aforementioned plasma impedance Zp has a magnitude of c + dj expressed in an imaginary number. In this case, (c ² +
d ² ) ^0.5 At this time, the combined impedance Ztotal from the matching box outlet to the ground through the plasma can be expressed by the following equation using a resistance component 39 (denoted as R (Ω)) and a capacitive component 40 (denoted as Xc (Ω)).
Ztotal = (c + R * Xc ² / (R ² + Xc ² ))
+ (D−R ² * Xc / (R ² + Xc ² )) j
This combined impedance Ztotal is the impedance a + at the matching box exit
Since it is equal to bj, the real component and the imaginary component are compared, and the values of c and d can be obtained from the following equations.
Z / (1+ (tan θ) ² ) ^0.5 = c + R * Xc ² / (R ² + Xc ² )
Z * tanθ / (1+ (tanθ) ² ) ^0.5 = d−R ² * Xc / (R ² + Xc ² )
If the values of c and d are obtained, the plasma impedance Zp and the wafer potential Vw are calculated by the following equations.
Zp = (c ² + d ² ) ^0.5
Vw = Ie * Zp
By calculating in such a procedure, it is not necessary to measure the wafer voltage Vw with the probe 24. Therefore, when the stylus of the wafer potential probe 24 contacts and slides on the back surface of the wafer, wear powder (foreign matter) is not generated from the back surface of the wafer, and the cleanliness is not reduced. However, in this embodiment, when the deposition film is deposited on the wafer stage, there is a problem that the value of the equivalent circuit model itself changes, so that it is not accurate. However, it can be used as a clean plasma impedance monitoring method under conditions where conditions are kept constant, such as processing while cleaning the surface of the wafer stage with plasma.

  FIG. 12 is a flowchart showing the flow from obtaining the wafer potential Vw and the plasma impedance Zp by the above method to using them. First, an equivalent circuit model from the high frequency power source (more precisely, current / voltage probe) to the ground via the wafer stage in this embodiment is determined as shown in FIG. 3 (step 120). Next, the combined impedance from the current / voltage probe to the ground through the plasma is calculated (step 121). Next, using a current / voltage probe, the waveform Vw (t) of the wafer potential and the waveform Ie (t) of the wafer stage current are measured to obtain the phase difference (step 122). Next, based on these values, the impedance at the position of the current / voltage probe is calculated (step 123). Next, the plasma impedance Zp and the wafer potential Vw are calculated by comparing the previously calculated synthetic impedance and the impedance obtained in step 123 (step 124). Eventually, it should be determined by the user's judgment, but when the wafer potential Vw and the plasma impedance Zp are monitored, they are displayed on the display unit 80 (step 125) to control the process parameters. In this case, information is sent to the process parameter controller 82 to control the process parameters (step 126).

In the above method, the current Ie flowing into the electrode is always measured, but it is also possible to calculate the plasma impedance by obtaining Ie by calculation. In this case, the wafer voltage waveform Vw (t) and the electrode voltage waveform Ve (t) are obtained by the wafer potential probe, and the current waveform Ie (t) flowing through the circuit is calculated from the impedance Zm of the dielectric film portion. . At this time, the impedance Zd of the dielectric film portion and the current waveform Ie (t) can be calculated by the following equations.
Zd = RXc ² / (Xc ² + R ² ) −jXcR ² / (Xc ² + R ² )
Ie (t) = (Vw (t) −Ve (t)) / Zd
From this result, the plasma impedance Zp is calculated by the following equation.
Zp = Vw / Ie
Although three methods for calculating the plasma impedance have been described above, which method is to be used may be appropriately selected according to the process.

  FIG. 14 is a flowchart showing a flow from obtaining the wafer potential Vw and the plasma impedance Zp by the above method to using them. First, an equivalent circuit model is determined as shown in FIG. 3 (step 140). Next, the wafer voltage waveform Vw (t) and the wafer stage voltage waveform Ve (t) are measured by the wafer potential probe and the current / voltage probe (step 141). Next, the wafer stage current waveform Ie (t) is calculated from the equivalent circuit model and the voltage waveform obtained in step 141 (step 142). Next, the plasma impedance Zp is calculated (step 143). Eventually, it should be determined by the user's judgment, but when the wafer potential Vw and the plasma impedance Zp are monitored, they are displayed on the display unit 80 (step 145), and the process parameters are controlled. Sends information to the process parameter controller 82 to control the process parameters (step 146).

Conversely, if the wafer potential is calculated using the above-described equivalent circuit model while actually measuring the wafer potential using the wafer potential probe, the display unit 80 can display the state of the deposit on the dielectric film surface of the wafer stage. . The procedure will be described with reference to FIG. First, the wafer potential Vw is measured with a wafer potential probe (step 130). Next, the current waveform Ie (t) and the voltage waveform Ve (t) of the wafer stage are measured with a current / voltage probe to obtain the phase difference θ (step 131). Next, the wafer voltage Vw ′ is calculated from Ie, Ve, θ using the equivalent circuit model of FIG. 3 (step 132). Next, a difference Vw−Vw ′ between the wafer voltage Vw previously measured by the wafer potential probe and the wafer voltage Vw ′ obtained by calculation is obtained (step 133). If there is no problem that the deposition film adheres to the surface of the dielectric film or the surface of the dielectric film is not reduced by etching, the potential of the wafer measured by the wafer potential probe Since the wafer potentials calculated by the equivalent circuit are almost the same, Vw−Vw ′ is close to zero. Specifically, the range of the value of Vw−Vw ′ is determined in advance, and the wafer potential Vw and plasma impedance Zp are output if within a certain range. In this case, it can be seen that there is no problem with the dielectric film. If the deposition film is deposited on the dielectric film surface and the film thickness is increased or the film thickness is decreased by etching, the difference between Vw and Vw ′ is a value exceeding a certain range. In this case, the value C of the dielectric film capacitance 40 in the equivalent circuit model is changed by ΔC (step 134), and Vw ′ is again set based on the changed value C ′ (= C + ΔC) of the dielectric film capacitance 40. Calculate Vw-Vw '(step 132). If the recalculated value Vw ′ falls within the predetermined range as described above, ΔC, Vw and Zp are obtained and a determination is made (step 135). That is, when the value of ΔC in this case is positive, the surface of the dielectric film is etched and the film thickness is reduced. When the value of ΔC is negative, the deposition film is formed on the surface of the dielectric film. It can be determined that the film thickness has increased due to adhesion. As described above, it can also be used as a dielectric film monitor. This process can also be applied to the embodiment of FIG. In this embodiment, only the resistance component and the capacitance component of the dielectric film of the wafer stage are considered as the equivalent circuit model. However, the present invention is not limited to this, and the inductance component between the wafer stage and the high-frequency power source, the wafer stage and, for example, the vacuum Capacitance components between chamber walls may be included. In this case, more detailed calculation of plasma impedance can be performed, and as a result, an effect that leads to improvement in accuracy and reproducibility of monitoring of plasma processing can be expected.

  As described above, the first embodiment is established when the condition of the inner wall of the processing chamber is not changed by the plasma processing or when a certain condition is maintained by the cleaning, but a deposition film or the like is formed on the inner wall of the processing chamber. It can be a problem under certain conditions. However, even in such a case, the problem can be avoided by adopting a configuration obtained by developing the present embodiment. This will be described below.

FIG. 4 shows the configuration of the second embodiment of the present invention. FIG. 5 shows an equivalent circuit model from the high frequency power source (more precisely, current / voltage probe) to the ground via the wafer stage in the second embodiment. In this embodiment, the process is performed in a process in which the adhesion film 65 adheres to the inner wall of the vacuum chamber. Because of the adhesion film, the impedance from the wafer to the ground changes, so that the plasma impedance cannot be accurately obtained by the method of the first embodiment. Therefore, in this embodiment, in order to obtain the impedance of the deposited film, in addition to the apparatus configuration of the first embodiment, a film thickness probe 63 for measuring the plasma potential during processing, and a signal such as a potential measured by the film thickness probe 63. Is provided with an arithmetic circuit 64 for calculating the film thickness based on the above. The film thickness probe 63 and the arithmetic circuit 64 constitute a film thickness probe unit. Note that the arithmetic circuit 64 may be provided in the computer 18. Examples of the film thickness probe include a crystal oscillator type film thickness measuring instrument and an optical film thickness measuring instrument using an interference wave. If the film thickness probe is used, the thickness of the film attached to the inner wall of the vacuum chamber can be measured, and the capacitance 67 and the impedance of the attached film can be calculated from the thickness of the film. For example, when an adhesion film having a relative dielectric constant ε is attached to a region having a thickness T and an area S, if the vacuum dielectric constant is ε ₀ , the capacitance Cm is εε ₀ S / T. When the frequency of the high frequency power supply 13 is f, the impedance Zm of the film is 1 / 2πfCm. If the plasma impedance Zp at this time is c + dj, the combined impedance from the wafer to the ground can be c + (d−Zm) j. From the equivalent circuit model, the combined impedance Ztotal of the resistance component 39 (R (Ω)) and the capacitance component 40 (Xc (Ω)) can be expressed by the following equation.
Ztotal = (c + R * Xc ² / (R ² + Xc ² ))
+ (D−Zm−R ² * Xc / (R ² + Xc ² )) j
Since this is the same as the impedance measured by the current / voltage probe, the real and imaginary components can be compared to obtain the values of c and d from the following equations. The impedance at the exit of the matching box can be expressed as follows when expressed as a + bj as in the first embodiment.
a = Z / (1+ (tan θ) ² ) ^0.5 ,
b = Z * tanθ / (1+ (tanθ) ² ) ^0.5
Z = Ve / Ie
Therefore, c and d are obtained by comparing the real number component and the imaginary number component and solving the lowering equation.
Z / (1+ (tan θ) ² ) ^0.5 = c + R * Xc ² / (R ² + Xc ² )
Z * tanθ / (1+ (tanθ) ² ) ^0.5 = d−Zm−R ² * Xc / (R ² + Xc ² )
The magnitude of the plasma impedance at this time can be calculated by (c ² + d ² ) ^0.5 . Therefore, by adding the function of measuring the thickness of the deposited film in addition to the first embodiment, the plasma impedance can be accurately measured even when the deposits adhere to the processing chamber wall and the plasma state changes. Can be calculated and the state of the plasma can be monitored. In addition, the potential of the wafer can be directly measured by the wafer potential probe or can be obtained by calculation based on the measurement result of the current / voltage probe and the equivalent circuit model. Therefore, if the potential of the wafer is controlled based on this information, the wafer potential can be controlled. The energy of incident ions can be controlled.

FIG. 15 is a flowchart showing a flow from obtaining the wafer potential Vw and the plasma impedance Zp by the above method to using them. First, based on the output of the film thickness probe 63, the thickness of the deposition film adhering to the processing chamber inner wall is measured (step 150). Next, the impedance of the deposition film is calculated (step 151). Next, an equivalent circuit model is determined (step 152). Next, the combined impedance from the current / voltage probe to the ground through the plasma and deposition film is calculated (step 153). Next, a wafer potential waveform Vw (t) and a wafer stage current waveform Ie (t) are measured using a current / voltage probe to obtain a phase difference (step 154). Next, the impedance at the position of the current / voltage probe is calculated (step 155). Next, the plasma impedance Zp and the wafer potential Vw are calculated by comparing the previously calculated synthetic impedance and the impedance obtained in step 155 (step 156). Eventually, it should be determined by the user's judgment. When the wafer potential Vw and the plasma impedance Zp are monitored, they are displayed on the display unit 80 (step 157), and the process parameters are controlled. Sends information to the process parameter controller 82 to control the process parameters (step 158).

  Therefore, in this embodiment, various processing parameters can be controlled based on the plasma impedance as in the first embodiment, and a manufacturing apparatus with good reproducibility can be provided. In addition, the product manufactured by this processing method is characterized by low price and stable performance as in the first embodiment.

  Furthermore, effects different from those of the first embodiment that can be expected in the case of this embodiment will be described. In a process in which a film adheres to the inner wall of the processing chamber, the thickness of the film gradually increases as the processing is repeated. When this film reaches a certain thickness, it peels off due to the film stress, and when this film gets on the wafer, it may cause a product defect. On the other hand, if the thickness of the adhesion film is monitored by the method shown in this embodiment, the cleaning time can be easily determined, and there is an effect that the product defect is not caused by the foreign matter.

Next, FIG. 6 shows the configuration of the third embodiment of the present invention. In this embodiment, a susceptor 45 is arranged so as to surround the periphery of the wafer stage of the first embodiment. The susceptor 45 has a structure in which a donut-shaped silicon plate 46 is attached to the surface facing the plasma 4 on the surface of a ceramic cover. Further, the silicon plate 46 is connected to a power supply rod 48 that is electrically insulated 47 from other components, and is connected to a power supply portion at the outlet of the matching box 14 via a variable capacitance capacitor 49 provided outside the vacuum chamber. Has been. Further, a terminal 50 electrically connected is provided on the back surface side of the silicon plate, and this terminal 50 is connected to a susceptor potential probe 66 having a socket part 51 electrically insulated from other components, and is connected to a vacuum chamber. And is taken into the computer 18 as in the first embodiment. Therefore, if the potential of the core wire of the susceptor potential probe is measured with a voltmeter, the voltage of the silicon plate 46 being processed can be measured. Further, in order to measure the voltage of the silicon plate, in addition to such a configuration, the voltage of the power feeding rod 48 connected to the silicon plate may be measured. The reason why the silicon plate is disposed on the susceptor surface is to eliminate non-uniformity of the fluorine radical distribution generated in the wafer surface when a fluorine-based gas is used for etching the oxide film. In other words, the fluorine radicals in the plasma react with the silicon in the wafer and etching progresses, but it is consumed in areas where the wafer is actually present and areas where silicon is not present such as the susceptor. Since there is a difference in the amount of fluorine radicals to be produced, the amount of fluorine radicals differs between the vicinity of the center and the periphery of the wafer, resulting in a difference in etching rate. Therefore, by disposing silicon on the susceptor, fluorine radicals are consumed to the same extent as in the region where the wafer is present to obtain a uniform distribution. Reference numeral 52 denotes a ground member for preventing abnormal discharge from being generated by applying a high frequency voltage to the power feeding rod.

  In this embodiment, in order to positively control the distribution of fluorine radicals in the wafer central region and the outer periphery, the bias power supplied from the matching box by changing the capacitance of the capacitor 49 is applied to the wafer stage and the silicon plate on the susceptor. Appropriate distribution. The method for obtaining the plasma impedance on the wafer and the bias power distribution method in this embodiment will be described below.

FIG. 7 shows an equivalent circuit model diagram of the third embodiment of the present invention. In this equivalent circuit model, since the ground member 52 and the silicon plate 46 are added, the equivalent circuit model is slightly more complicated than the equivalent circuit model of the first embodiment. For example, 53 is a capacitance component of the space existing between the electrode and the ground member, 54 is a capacitance component of the variable capacitance capacitor 49 connected to the silicon plate, and 55 is a capacitance component between the wafer and the silicon plate 46. It is. The values of these electrostatic capacitance components 40, 53, and 55 can be obtained by experiments using a capacitance sensor when a high frequency voltage having the same frequency as the bias voltage applied to the wafer stage is applied in an actual apparatus configuration. In this example, when the capacitance was actually measured, 40 was 3 nF, 53 was 0.3 nF, and 55 was 0.1 nF at 800 kHz. When such an equivalent circuit is known in advance, the plasma impedance 56Zw on the wafer and the plasma impedance 57Zs on the silicon plate can be calculated by the following procedure. First, the waveform Ve (t) of the electrode voltage (in this case, equal to the potential of the wafer stage) 43 and the current flowing out of the matching box by the current / voltage probe 17 provided between the outlet of the matching box and the electrode. 44 waveforms Ie (t) are measured. Next, the wafer voltage waveform Vw (t) being processed is measured using the same wafer potential probe 24 as the probe of the first embodiment. Further, the waveform Vs (t) of the potential 58 of the silicon plate being processed is obtained by measuring the voltage at the terminal 50 with a voltmeter. Of the current 44Ie (t), the current 59Is (t) flowing into the silicon plate side is obtained by the following equation, where the impedance of the capacitor 54 is Zc.
Is (t) = (Vs (t) −Ve (t)) / Zc
Here, the impedance Zc can be easily calculated from the frequency of the bias voltage and the capacitance of the capacitor 54. Further, the current flowing to the ground through the capacitor 53 can be calculated by Ve (t) / Z, where Z is the impedance of the capacitor 53.

Accordingly, the current value 60Iw (t) flowing on the wafer side in the current 44Ie (t) is obtained by the following equation.
Iw (t) = Ie (t) −Is (t) −Ve (t) / Z
Further, the current 61Iws (t) flowing between the wafer and the silicon plate can be obtained by the following equation when the impedance between the wafer and the silicon plate is Zws.
Iws (t) = (Vw (t) −Vs (t)) / Zws
From the above, the current values 62Izw (t) and 63Izs (t) flowing into the plasma impedance 56Zw on the wafer and the plasma impedance 57Zs on the silicon plate can be obtained as follows.
Izw (t) = Iw (t) −Iws (t)
Izs (t) = Is (t) + Iws (t)
Further, since the voltages Vw (t) and Vs (t) are measured, Zw and Zs can be obtained by the following equations, respectively.
Zw = Vw (t) / Izw (t)
Zs = Vs (t) / Izs (t)
In the present configuration, the bias power applied to the wafer and the silicon plate can be arbitrarily changed by changing the capacitance of the variable capacitance capacitor 54. Therefore, the etching of the oxide film can control the consumption of fluorine radicals, so that the distribution in the wafer surface of the etching can be controlled. In addition, since the potential of the wafer being processed and the silicon plate and the impedance to the ground via the plasma can be measured simultaneously, the etching conditions can be controlled based on this signal.

FIG. 16 is a flowchart showing the flow from obtaining the plasma impedances Zw and Zs, the wafer potential Vw and the susceptor potential Vs by the above method until they are used. First, an equivalent circuit model in this embodiment shown in FIG. 7 is determined (step 160). Next, a wafer voltage waveform Vw (t), a susceptor voltage waveform Vs (t), a wafer stage current waveform Ie (t), and a voltage waveform Ve () by a wafer potential probe, a susceptor potential probe, and a current / voltage probe. t) is measured (step 161). Next, a current waveform Izw (t) flowing from the wafer into the plasma and a current waveform Izs (t) flowing from the susceptor into the plasma are calculated (step 162). Next, plasma impedances Zw and Zs are calculated (step 163). Eventually, it should be determined by the user's judgment, but when the wafer potential Vw, the susceptor potential Vs, and the plasma impedances Zw and Zs are monitored, they are displayed on the display unit 80 (step 165). When the process parameters are controlled, information is sent to the process parameter control device 82 to control the process parameters (step 166).

  An example of actual application when an oxide film is etched using a fluorine-based gas will be described. The wafer potential during processing, the silicon plate potential, the plasma impedance on the wafer, and the plasma impedance on the silicon plate were monitored at the same time, and the etching process was performed continuously. Ascending phenomenon was observed. From past experience, it has been known that there is a high possibility that deposits are attached to the silicon plate even if the number of treatments starts to increase, but in this case the capacitance of the variable capacitor is increased. Then, a large amount of electric power was applied to the silicon plate of the high frequency bias applied to the electrode to clean the deposit. As a result, it was possible to quickly return to normal processing conditions. In this example, in the conventional method, the cause was investigated for the first time after the occurrence of etching failure, and the procedure to take countermeasures was taken, so it took time and the cost of wasted wafers affected the manufacturing cost. However, in this embodiment, there is an advantage that the progress of etching can be grasped while performing the etching, and it can be dealt with quickly. Therefore, the apparatus operating rate is high and the manufacturing cost can be kept low.

  Furthermore, if the plasma impedance during etching or the voltage of the wafer or silicon susceptor is monitored and abrupt changes are observed, there is a high possibility that some problem has occurred. Since measures such as stopping the apparatus can be performed, it is possible to minimize the waste of the wafer. That is, it is possible to expect an effect of improving the apparatus operating rate and reducing the manufacturing cost.

  In this embodiment, a variable-capacitance type capacitor is used to control the amount of bias power distributed from the matching box outlet to the wafer stage and the silicon plate, but this need not necessarily be the case. For example, it is possible to apply the bias voltage using a power source different from the power source that applies the bias voltage to the wafer stage. However, if it is necessary to align the phases of the bias voltage applied to the wafer stage and the bias voltage applied to the silicon plate from the viewpoint of process control, it is possible to provide a phase controller and match the phases.

  In the description of the above embodiments, either the wafer potential or the impedance from the wafer to the earth, or the susceptor voltage and the impedance from the susceptor to the earth is monitored, and any of the silicon plate on the wafer stage and the susceptor is detected. Alternatively, the high-frequency power applied to both is controlled, but the present invention is not necessarily limited to this. For example, the correlation between the wafer potential and plasma impedance, such as the etching rate, the etching rate distribution in the wafer surface, the thickness of the deposited film deposited in the vacuum chamber, the state of adsorption of the wafer by the electrostatic chuck, the occurrence of device damage, etc. As a result, it is possible to positively change the etching parameters and determine the cleaning time by comparing with the wafer potential and plasma impedance during the wafer processing. Therefore, it can be expected to improve the yield and reduce the manufacturing cost.

In this embodiment, as shown in the first and second embodiments, Zs and Zw cannot be calculated from the equivalent circuit model without measuring the voltages 42 and 58 from the back surface. The reason is that there are a total of four real components and two imaginary components of Zw and Zs, whereas only one real component and one imaginary component of the points at which Ve43 and Ie44 are measured can be obtained. However, practically, it can be simply calculated by assuming that, for example, Zw and Zs are distributed by the ratio of the area facing the plasma. In this case, as described in the first and second embodiments, the total combined impedance can be calculated and compared with the impedances at the measurement points Ve and Ie. In this way, since it is not necessary to directly measure the voltage of the wafer or the voltage of the silicon plate, a cleaner monitoring method can be provided.

FIG. 8 shows the configuration of the fourth embodiment of the present invention. FIG. 9 shows an equivalent circuit model from the high frequency power source (more precisely, current / voltage probe) to the ground via the wafer stage in the fourth embodiment. In this embodiment, a process is performed in which the adhesion film 65 adheres to the inner wall of the vacuum chamber as in the second embodiment. Therefore, for the same reason as in the second embodiment, in this embodiment, in order to determine the impedance of the deposited film, in addition to the apparatus configuration of the third embodiment, the thickness of the film deposited on the inner wall of the vacuum chamber is measured. A probe 63 and an arithmetic circuit 64 are provided. If a film thickness probe is used, the film thickness can be measured, and the capacitance Cm and impedance Zm can be calculated by the same procedure as described in the second embodiment. Therefore, the plasma impedance on the wafer and the plasma impedance on the susceptor can be calculated by adding the capacitance Cm to the equivalent circuit model of the third embodiment.

  Therefore, if the function of measuring the thickness of the deposited film is added, the plasma impedance can be accurately calculated even when the deposits adhere to the processing chamber wall and the plasma state changes. The state of the plasma can be monitored. In addition, the wafer potential and the susceptor potential can be measured directly with a potential probe, or can be obtained by calculation using the measurement results of an electric current / voltage probe and an equivalent circuit model, so that the energy of ions incident on the wafer can be controlled. Can do.

  Although the present invention has been described with reference to an example in which the present invention is applied to a dry etcher, a great effect can be expected when applied to a plasma CVD apparatus. For example, since a plasma CVD apparatus forms a film on a wafer using plasma, a large amount of deposits adhere to the inner wall of the vacuum chamber. If this deposit exceeds a certain thickness, there is a problem that it peels off the inner wall of the chamber and causes contamination of the wafer. However, since the thickness of the film adhering to the processing chamber wall can be predicted by the method of this embodiment, the cleaning time can be determined before the product defect is produced. In this case, since the wafer is not wasted, the manufacturing cost can be kept low. In addition, since the wafer potential and plasma impedance can be accurately monitored, the ion energy incident on the wafer can be controlled by controlling the high-frequency voltage applied based on this, so that etching with good reproducibility can be realized. As a result, an improvement in yield can be expected, and the resulting cost can be reduced.

The figure which shows the structural example of the plasma etching apparatus by 1st Example of this invention. Sectional drawing which shows the structural example of the wafer potential probe used in this invention. The equivalent circuit schematic of the principal part of 1st Example of this invention. The figure which shows the structural example of the plasma etching apparatus by the 2nd Example of this invention. The equivalent circuit schematic of the principal part of the 2nd Example of this invention. The figure which shows the structural example of the plasma etching apparatus by the 3rd Example of this invention. The equivalent circuit schematic of the principal part of the 3rd Example of this invention. The figure which shows the structural example of the plasma etching apparatus by 4th Example of this invention. The equivalent circuit schematic of the principal part of 4th Example of this invention. The equivalent circuit diagram of the principal part of the plasma etching apparatus by a prior art. The flowchart explaining the calculation process of the impedance in a 1st Example. The flowchart explaining another calculation process of the impedance in a 1st Example. The flowchart explaining the monitor process of the deposit state of the dielectric film surface of the wafer stage in a 1st Example. The flowchart explaining the utilization process of the calculated | required plasma impedance in a 1st Example. The flowchart explaining the calculation process of the impedance in a 2nd Example. The flowchart explaining another calculation process of the impedance in a 3rd Example.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 ... Processing gas, 2 ... High frequency power supply, 3 ... Coil, 4 ... Plasma, 5 ... Semiconductor wafer, 6 ... Wafer stage, 7 ... Dielectric film, 8 ... Electrode, 9 ... Insulating plate, 10 ... Vacuum chamber, 11 ... Flange , 12, 48 ... feed rod, 13 ... high frequency power supply, 14 ... matching box, 15,20 ... coil, 16 ... capacitance variable capacitor, 17 ... current / voltage probe, 18 ... computer, 19 ... DC power supply, 21 ... cover, 22 ... turbo molecular pump, 23 ... dry pump, 24 ... wafer potential probe, 25 ... flange, 26 ... female screw, 27 ... terminal, 28 ... male screw, 29, 70 ... O-ring, 30 ... flange upper inner surface, 31 ... nut, 32 ... Connecting rod, 33 ... Socket, 34 ... Spring stopper, 35 ... Coil spring, 36 ... Stylus, 37 ... Earth, 38 ... Plasma impedance, 39 ... Resistance component of electric film, 40: Capacitance component of dielectric film, 41: Blocking capacitor, 42: Potential of wafer, 43: Voltage of electrode, 44, 59, 60, 61, 72, 73 ... Current, 45 ... Susceptor, 46 ... Silicon plate, 47 ... Insulation, 49 ... Capacitance variable capacitor, 50 ... Terminal, 51 ... Socket, 52 ... Earth member, 53 ... Capacitance between electrode and earth member, 54 ... Capacitance variable capacitor, 55 ... Wafer and silicon Capacitance between plates, 56 ... plasma impedance on wafer, 57 ... plasma impedance on silicon plate, 58 ... silicon plate potential, 62 ... insulating cylinder, 63 ... film thickness probe, 64 ... arithmetic circuit, 65 ... adhesion film , 66 ... Susceptor potential probe, 67 ... Capacitance of attached film, 68 ... Insulating pipe, 69 ... Core wire, 71 ... Insulating pipe, 8 ... display unit, 82 ... parameters of the control device.

Claims (5)

In a semiconductor manufacturing apparatus for processing a semiconductor wafer,
A unit for generating plasma in the vacuum processing chamber;
A wafer stage for holding a semiconductor wafer to be introduced into the vacuum processing chamber;
A high-frequency power source for applying a high-frequency voltage to the wafer stage;
A current / voltage probe for measuring the voltage and current applied to the wafer stage from the high-frequency power source;
The impedance at the position of the current / voltage probe is determined by measuring the waveform of the potential of the semiconductor wafer and the current waveform of the wafer stage using the current / voltage probe to obtain a phase difference, and the obtained impedance Calculation to calculate the impedance from the semiconductor wafer to the ground via the plasma by processing the synthesized impedance of the equivalent circuit model from the current / voltage probe to the ground via the wafer stage prepared in advance And
A semiconductor manufacturing apparatus comprising: a processing unit that performs processing based on the calculated impedance.   The semiconductor manufacturing apparatus according to claim 1, wherein the processing unit displays the calculated impedance on a display unit.   The semiconductor manufacturing apparatus according to claim 1, wherein the processing unit controls various processing parameters based on the calculated impedance.   4. The semiconductor manufacturing apparatus according to claim 3, wherein the various processing parameters include a frequency or power of a high-frequency voltage for generating the plasma, a frequency or power of a high-frequency voltage applied to the wafer stage, or the vacuum processing chamber. At least one of the temperature or temperature distribution of the walls forming the semiconductor wafer, the temperature or temperature distribution of the semiconductor wafer, the pressure of the vacuum processing chamber, the type or flow rate of the processing gas flowing into the vacuum processing chamber, or the mixing ratio of the processing gases Or at least one type of magnetic field or etching time applied in the vacuum processing chamber. In a semiconductor manufacturing apparatus comprising a unit for generating plasma in a vacuum processing chamber, a wafer stage for holding a semiconductor wafer introduced into the vacuum processing chamber, and a high-frequency power source for applying a high-frequency voltage to the wafer stage, A method for processing a semiconductor wafer includes:
The current / voltage probe is used to measure the potential waveform of the semiconductor wafer and the current waveform of the wafer stage, and the phase difference is obtained to obtain the impedance at the position of the current / voltage probe. Calculating the impedance from the semiconductor wafer to the ground via the plasma by performing arithmetic processing on the synthesized impedance of the equivalent circuit model from the prepared current / voltage probe to the ground via the wafer stage; and ,
And a step of performing processing based on the calculated impedance.

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