JP2012209420A - Semiconductor integrated circuit device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a circuit for detecting temporarily fluctuating variation which in an integrated circuit.SOLUTION: A detection circuit 100, an arithmetic circuit 101, and a variation/voltage conversion circuit 113 are provided in an integrated circuit. In the detection circuit 100, characteristic variation of the integrated circuit is detected as an oscillation frequency of an output signal of the detection circuit 100. In the arithmetic circuit 101, variation information detected for every time interval regulated by a timer 106 is stored in a register 111, statistical processing is performed by a statistic arithmetic circuit 112, and the temporarily fluctuating characteristic variation of the integrated circuit is detected. The variation/voltage conversion circuit 113 further converts the characteristic variation into voltage information corresponding to the detected characteristic variation.

Description

  The present invention relates to characteristic variation management of a semiconductor integrated circuit.

  With the progress of miniaturization, the variation in transistor characteristics increases, and the influence of the variation on the semiconductor integrated circuit continues to increase as the power supply voltage decreases. In order to compensate for the variation in characteristics of the semiconductor integrated circuit, there is a technique for detecting the variation in the integrated circuit and controlling the power supply voltage, the transistor substrate voltage, the operating frequency, and the like based on the detection result. As a conventional technique of this type, for example, in Patent Document 1, a monitor circuit arranged in an integrated circuit detects the delay characteristics of the integrated circuit to calculate the variation of the integrated circuit. Based on the detected variation, the optimum power supply voltage and operating frequency are determined, and the variation of the integrated circuit is compensated.

JP 2008-011323 A

  However, in the background art method of detecting variation based on monitor information at a certain time, even if the amount of variation (spatial) in a semiconductor integrated circuit can be detected, Cannot detect and compensate. This is because there is no mechanism for detecting and calculating variation information over time. And it can be said that the problem caused by the miniaturization of the semiconductor cannot be solved unless the influence of the variation phenomenon after the chip manufacturing is reduced.

  Next, as an example of the variation of the variation amount with time, there is a phenomenon called RTN (Random Telegraph Noise) shown in FIG. RTN is a phenomenon in which the transistor threshold voltage varies with time due to a slight structural defect at the atomic level. Further, the time variation has random characteristics. In the prior art, since variation that varies with time cannot be detected, the amount of variation cannot be accurately grasped. Therefore, in designing an integrated circuit, a variation amount that varies with time is predicted and designed as a margin, but this design method allows for an excessive margin. Therefore, there arises a problem that the power consumption of the integrated circuit is increased and the cost is deteriorated.

  The present invention has been made to solve such a problem, and one of its purposes is to provide a circuit for detecting variation in characteristics of a semiconductor integrated circuit that varies with time. The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

  The outline of the invention disclosed in the present application will be described as follows. That is, the present invention relates to a detection circuit having a plurality of oscillation circuits using delay elements, a counter circuit connected to the detection circuit and counting the number of oscillations of the oscillation circuit for a certain period, and connected to the counter circuit. A control circuit that outputs a control signal for controlling the counter circuit; a timer circuit that is connected to the control circuit and that outputs a timer signal serving as a reference for the control signal to the control circuit; and is connected to the counter circuit And an arithmetic circuit that calculates a count result of the counter circuit, the detection circuit includes a first oscillation circuit, and the timer circuit includes the counter circuit that determines the number of oscillations of the first oscillation circuit. The timer signal is output after a predetermined period of time, and the counter circuit determines the number of oscillations of the first oscillation circuit based on the timer signal. A period counting, the arithmetic circuit is characterized in that statistical calculation a plurality of counting results in the first oscillation circuit.

  According to the present application, it is possible to manage the variation of the integrated circuit that varies with time.

FIG. 3 is a circuit diagram showing a configuration example of the variation detection circuit according to the first embodiment of the present invention. It is a schematic diagram of general RTN variation. It is the figure which showed distribution of the LSI operation speed by the characteristic variation of the transistor of LSI. It is the figure which showed the structural example of power supply voltage control. It is a figure showing a processing flow from LSI variation detection to statistical calculation. FIG. 2 is a circuit diagram illustrating a detailed configuration example of a detection circuit in FIG. 1. FIG. 7 is a circuit diagram illustrating a detailed configuration example of the inverter circuit of FIG. 6. FIG. 7 is a circuit diagram showing another detailed configuration example of the inverter circuit of FIG. 6. FIG. 6 is a circuit diagram showing a configuration example of a variation detection circuit according to a second embodiment of the present invention.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. In all the drawings for explaining the embodiments, the same members are denoted by the same reference symbols in principle, and the repeated explanation thereof is omitted. Further, in the following embodiments, when it is necessary for the sake of convenience, the description will be divided into a plurality of sections or embodiments. However, unless otherwise specified, they are not irrelevant to each other. Is related to some or all of the other modifications, details, supplementary explanations, and the like.

  Further, in each embodiment, when referring to the number of elements (including the number, numerical value, quantity, range, etc.), unless explicitly stated or limited to a specific number in principle, etc. The number is not limited to the specific number, and may be a specific number or more. Further, in the following embodiments, the constituent elements (including element steps and the like) are not necessarily indispensable unless otherwise specified and apparently essential in principle. Needless to say. Similarly, in each embodiment, when referring to the shape, positional relationship, etc. of the component, etc., the shape, etc. substantially, unless otherwise specified, or otherwise apparently not in principle. It shall include those that are approximate or similar to. The same applies to the above numerical values and ranges.

  First, prior to the description of each embodiment, a configuration relating to a variation detection circuit of the present invention will be briefly described.

  The variation detection circuit according to the present embodiment includes a detection circuit that detects spatial or temporal variation information of the LSI, and an operation that calculates the variation of the entire LSI by performing statistical calculation processing on the variation information detected by the detection circuit. And a circuit. With the above configuration, it is possible to grasp the variation of the integrated circuit that varies spatially or temporally.

  Further, it may be configured to include a variation / voltage conversion circuit that converts variation information into a control voltage value of an LSI power supply. This makes it possible to compensate for variations in characteristics such as LSI operation speed and power consumption due to transistor characteristic variations to the standard state at the time of design.

  Here, more specifically, the detection circuit for detecting spatial or temporal variation information of the LSI includes an oscillation circuit using a delay element. For example, a ring oscillator circuit configured by connecting delay elements such as an inverter circuit in multiple stages. One or a plurality of ring oscillator circuits are arranged in the LSI and output an oscillation signal. The input terminal of the inverter circuit that constitutes the ring oscillator circuit includes a transistor that controls connection and disconnection of the input signal, and the input terminal is set to a voltage higher than the voltage of the input signal in the previous stage, for example, a power supply voltage or higher. A transistor to be fixed is connected to a transistor whose input terminal is fixed to a voltage lower than the voltage of the previous input signal, for example, a ground potential. In this way, the oscillation operation and the input signal can be switched between power supply and ground potential.

  Note that a transistor in which the input terminal is fixed at a voltage higher than the voltage of the input signal in the previous stage has an effect of increasing temporal variation in the detection target and facilitating detection of temporal variation (acceleration test). Further, the transistor that fixes the input terminal to a voltage lower than the voltage of the input signal in the previous stage has an effect of reducing temporal variation in the detection target and relatively easily detecting the local variation.

  More specifically, the arithmetic circuit for calculating the variation of the entire LSI converts, for example, a first selection circuit that selects a detection result of the detection circuit and a detection result of the first selection circuit into a digital signal. A counter circuit, a register for storing the digital signal, a second selection circuit for selecting the register, a statistical operation circuit for statistically processing the digital signal stored in the register, and an operation time interval between the detection circuit and the operation circuit And a control circuit for controlling the detection circuit, the first and second selection circuits, the counter circuit, and the statistical operation circuit.

  In the above configuration, one or a plurality of spatial or temporal variation detection results can be converted into a count number measured by a counter circuit and stored in a register.

  More specifically, the statistical calculation circuit in the calculation circuit is configured to calculate the difference between the oscillation frequencies of the ring oscillator circuit or the oscillation frequencies of the plurality of ring oscillators and calculate the sum of squares thereof. This makes it possible to detect LSI variations.

  More specifically, the variation / voltage conversion circuit has a configuration in which, for example, the relationship between the variation amount and the power supply voltage value of the controlled LSI is stored as a table. By supplying a power supply voltage corresponding to the amount of variation obtained by the variation / voltage conversion circuit to the LSI, characteristics such as the operating speed and power consumption of the LSI that have fluctuated due to transistor variations can be compensated to the standard state at the time of design. . As an example of the table described above, there is a table in which a voltage change due to variation, an optimum power supply voltage for compensating the voltage change, and a control signal value for the power supply IC 403 are associated with each other.

  Next, a more specific configuration of the variation detection circuit including these configurations will be described below.

  FIG. 1 is a block diagram showing a configuration example of the variation detection circuit according to the first embodiment of the present invention. Before explaining FIG. 1, FIG. 4 shows an example of an LSI to which the variation detection circuit shown in FIG. 1 is applied and its system configuration.

  In the system configuration shown in FIG. 4, LSI characteristic variations due to transistor spatial and temporal characteristic variations are compensated by controlling the power supply voltage of the LSI. The LSI 401 includes a power supply IC 403 that is disposed outside the LSI 401 and generates a power supply voltage.

  In the LSI 401, a controller 402 that controls the power supply IC 403 from the detection results of one or a plurality of detection circuits 400 and the ring oscillator circuit 104 is disposed.

  The controller 402 performs arithmetic processing on the variation information detected by the detection circuit 400, and determines the LSI operating voltage based on the calculated variation information. Further, the controller 402 outputs a control signal for the power supply IC 403 and controls the operation voltage determined by the controller 402 to be output to the power supply IC 403. Note that the function realized by the controller 402 does not necessarily exist in the same LSI, and can be replaced by input / output from an external chip.

  FIG. 3 is a drawing examined by the inventor prior to the present invention. That is, it is a diagram showing a distribution of LSI operation speeds due to characteristic variations of a certain LSI transistor. A waveform 300 is a velocity distribution due to LSI spatial variation. A waveform 301 is a velocity distribution considering transistor characteristics (for example, variation due to RTN) that varies with time in addition to the spatial variation of the LSI.

  Since the distribution of the waveform 301 includes a variation that changes with time, the variation is larger than the distribution of the waveform 300. Therefore, by controlling the power supply voltage of the LSI, it is possible to compensate for variations in the characteristics of the LSI so that the distribution changes as shown in the waveform 302, for example, so as to satisfy a desired operation speed. The control of the waveform 302 is a result of supplying a high voltage to the power supply for an LSI with a low operating speed and supplying a low voltage for an LSI with a high operating speed.

  As described above, the voltage control has been described with respect to the compensation of the characteristic variation of the transistor by taking the compensation of the operation speed of the LSI as an example. Further, the power supply voltage is not limited only to compensation for operating speed and power consumption.

  The variation detection circuit shown in FIG. 1 includes a detection circuit 100, an arithmetic circuit 101, and a variation / voltage conversion circuit 113. The detection circuit 100 includes one or a plurality of ring oscillator circuits 104. The ring oscillator circuit 104 is controlled to operate and stop by an enable signal ROEN. The ring oscillator circuit 104 self-oscillates during operation, and the transmission signal is sent to the arithmetic circuit 101.

  The detection circuit 100 detects a spatial or temporal variation of the LSI. In the case of detecting temporal variation, the same ring oscillator circuit 104 is operated a plurality of times with time, and the operation result is used. When detecting spatial variations, the operation results of a plurality of ring oscillator circuits 104 arranged in the LSI are used. Here, the time interval for performing the operation a plurality of times in order to detect temporal variations may be determined from the viewpoint of compensating the LSI operation speed to an appropriate value. This is because the temporal variation in transistor characteristics is large in individual time intervals.

  The arithmetic circuit 101 measures the period of the output signal of the first selection circuit 108 that selects the oscillation signal of the ring oscillator circuit 104 and the first selection circuit that is one of the oscillation signals of the ring oscillator circuit 104, and converts it into a digital signal. A counter 109 for conversion, one or more registers 111 for storing the digitized period information, a second selection circuit 110 for selecting which register 111 stores the period information, and statistical processing of the period information Controlling the statistical operation circuit 112, the timer circuit 106 that measures the operation time interval of the detection circuit 100 and the arithmetic circuit 101, the detection circuit 100, the first selection circuit 108, the second selection circuit 110, and the statistical calculation circuit 112. And a control circuit 107.

  The control circuit 107 is controlled to operate and stop by an enable signal COUNTEN input to the control circuit 107. The control circuit 107 starts operation in response to the enable signal CONTEN and outputs the enable signal TEN of the timer circuit 106. The timer circuit 106 can set an arbitrary time.

  The timer circuit 106 measures the set time and outputs a trigger signal TRG that defines the operation start timing of the control circuit 107 after the set time.

  The control circuit 107 receives the trigger signal TRG from the timer circuit 106 and starts its operation. The enable signal ROEN of the ring oscillator circuit 104, the selection signals SSEL1 and SSEL2 of the first and second selection circuits 108 and 110, and the counter circuit 109 The enable signal CEN and the enable signal STATCALCEN of the statistical calculation circuit 112 are output. The ring oscillator circuit 104 starts an oscillation operation in response to the enable signal ROEN and transmits the oscillation signal to the first selection circuit 108.

  The first selection circuit 108 selects one oscillation signal by the selection signal SSEL1. The counter circuit 109 starts a count operation in response to the enable signal CEN. The selected oscillation signal is converted in the counter circuit 109 into a count number whose oscillation frequency is a digital signal.

  In the second selection circuit 110, the register 111 to be written is selected by the selection signal SSEL2, and the count number is stored in the register 111. When detecting a variation that varies with time, one ring oscillator circuit 104 is continuously operated at a constant time interval, and the time variation of the oscillation frequency of the ring oscillator circuit 104 is stored in the register 111.

  Here, among the plurality of ring oscillators, if the count values of the frequencies detected from the same ring oscillator are compared while changing the time, it is possible to determine the fluctuation due to the time. That is, it can be determined whether or not random variation occurs in the target ring oscillator. Further, if the time interval to be detected is changed by the timer circuit, it is possible to determine how much time interval is generated from the presence or absence of the occurrence of random variations.

  Further, by calculating the time distribution in the frequency count value detected from the same ring oscillator, it is possible to determine how much the voltage fluctuation width of the random variation in the target ring oscillator is. Therefore, when storing in a register, it is good to store so that the place where the ring oscillator is arrange | positioned, and the measured time may be known.

  After completion of this series of processing from detection of variation to writing to the register, the control circuit 107 transmits the enable signal TEN of the timer circuit 106 to the timer circuit 106, and starts the time count of the timer circuit again. The process of storing the result of the ring oscillator circuit 104 in the register 111 is repeated once or a plurality of prescribed times according to an algorithm described in detail later.

  When detecting spatial variations in the LSI, the detection results of the plurality of ring oscillator circuits 104 are stored in the register 111 in order. When detecting both temporal and spatial variations, both processing flows are combined. Note that not only spatial variations but also temporal variations vary in nature depending on the design rules and the operating environment. That is, which variation is dominant and varies at the time of design and operation, so that it is possible to perform flexible compensation for a given operating environment by providing a configuration for detecting both.

  After all the results detected by the detection circuit 100 are stored in the register 111, the operation is started in the statistical calculation circuit 112 by the enable signal STATCALCEN. Then, a statistical calculation is performed on the count number stored in the register 111. Thereby, the characteristic variation of LSI can be detected.

  The statistical calculation circuit 112 performs statistical processing on one or more count numbers (indicating detection results in each ring oscillator circuit 104) stored in the register 111 to detect LSI variations. The statistical calculation circuit 112 calculates a statistical value indicating the spread of the distribution such as the standard deviation or variance of the count number, and sends the result to the variation / voltage conversion circuit 113.

  The variation / voltage conversion circuit 113 converts LSI variation information calculated by the statistical calculation circuit 112 into LSI power supply voltage information. This power supply voltage information is determined to be an optimum voltage for compensating for variations in LSI, that is, a voltage that stabilizes the operation speed of the circuit. The variation / voltage conversion circuit 113 generates a control signal for the power supply IC 403 outside the LSI to output the determined power supply voltage.

  A specific method for converting the variation information of the LSI into the control signal of the power supply IC 403 may be realized by, for example, a table in which the variation amount and the control signal value are associated with each other, but is not limited thereto. As a result, it is possible to compensate for characteristics such as LSI operation speed and power consumption, which fluctuate due to transistor variations, in the standard state at the time of design.

  FIG. 5 shows a processing flow from the detection of variation varying with time in the ring oscillator circuit 104 to the statistical analysis in the statistical calculation circuit 112. The oscillation frequency of a certain ring oscillator circuit 104 is measured a prescribed number of times at time intervals prescribed in advance by the timer circuit 106. In order to obtain the result of statistical processing, the number of times may be determined as the number of times that variation appears as a tendency. Specifically, there are many cases where the number of times is approximately several tens to several hundreds, but this is not a limitation.

  Next, the result of converting the oscillation frequency of the ring oscillator circuit 104 (here, the first ring oscillator circuit is selected as an example and measurement with that circuit) into a count number is stored in the register 111. Then, it is determined whether or not the above-mentioned prescribed number of times has been reached. If not, it waits after the time measured by the timer circuit 106, that is, at a prescribed interval, and returns to the variation detection processing in the first ring oscillator circuit 104. On the other hand, when the specified number of times is reached, the processing shifts to statistical processing and analysis in the statistical operation circuit 112, and the variation of the LSI is detected.

  FIG. 6 is an example of a circuit diagram of the ring oscillator circuit 104. The ring oscillator circuit 104 includes a NAND circuit 500 and a plurality of stages of inverter circuits 501. The NAND circuit 500 is inserted in order to switch the operation and stop of the ring oscillator circuit 104 by the enable signal ROEN.

  The oscillation signal output of the ring oscillator circuit 104 is output as a signal ROUT. When ROEN is set to High, the circuit operates and stops at Low. A control signal ACC is connected to the inverter circuit 501. The control signal ACC is a signal for selecting whether the input of the inverter circuit 501 is connected to the output of the previous stage or the input is connected to a fixed potential. That is, if it is connected to the output of the previous stage, the detection operation can be performed, and if the input is set to an arbitrary fixed potential, the frequency of occurrence of variation can be varied.

  FIG. 7 is an example of a detailed circuit of the inverter circuit 501 shown in FIG. The inverter circuit 501 includes an inverter circuit 603, a transistor 601 that controls connection and interruption of the input signal IN, and a transistor 602 that fixes the input terminal to a power supply voltage or a third voltage higher than that. The third voltage may be directly connected to the power supply, and the third voltage may be the power supply voltage. An inverted signal is generated by the signal ACC for controlling the transistor 601 and the inverter circuit 604. Note that the transistor 601 can reduce the influence on temporal variation by increasing the element size.

  When the control signal ACC is set to High, the input signal IN is connected to the inverter circuit 603. When the control signal ACC is set to Low, the input signal IN is disconnected from the inverter circuit 603. At that time, the input signal of the inverter circuit 603 is fixed to the power supply voltage or higher by the transistor 602. The reason is that it is known that the frequency of occurrence of time-varying variation depends on the voltage applied to the transistor. Therefore, when the input signal of the inverter circuit 603 is fixed to a power supply voltage or higher, it is possible to increase the frequency of occurrence of a variation phenomenon that varies with time.

  6 and 7, ROEN and ACC are separated, but they may be connected. In that case, when the ring oscillator circuit 104 is stopped, the input of the inverter circuit 501 is always fixed to the third voltage, and the state in which the variation phenomenon that varies with time is high is maintained. There is an effect to.

  FIG. 8 shows an example of another configuration of the inverter circuit 501 shown in FIG. The inverter circuit 501 includes an inverter circuit 803, a transistor 800 that controls connection and disconnection of the input signal IN, a transistor 801 that fixes the input terminal to a third voltage higher than the power supply voltage, and the input terminal to the ground potential. A fixed transistor 802 and a control signal generation unit 804 that controls the transistors 800, 801, and 802 are configured. The third voltage may be directly connected to the power supply, and the third voltage may be the power supply voltage. 7 differs from the circuit shown in FIG. 7 in that the input signal of the inverter circuit 803 can be fixed to the ground potential.

  When the control signal ACC is set to High, the input signal IN is connected to the inverter circuit 803. When the control signal ACC is set to Low, the input signal IN is disconnected from the inverter circuit 803 by the transistor 800 that controls connection / disconnection. At that time, the input signal of the inverter circuit 803 is fixed to either the third voltage or the ground potential by the transistors 801 and 802 and the signal HL which is an input signal to them. That is, the input potential of the inverter 803 becomes the third potential when the signal HL is High and the transistor 802 becomes conductive and becomes the ground potential, and when the signal HL is Low, the transistor 602 becomes conductive and becomes the third potential.

  The reason why the input signal of the inverter circuit 803 is fixed to the power supply voltage or higher is to increase the frequency of occurrence of a variation phenomenon that varies with time. The reason for fixing to the ground potential is to minimize the occurrence frequency of time-varying variations. When detecting spatial variations, it is necessary to suppress the frequency of temporal variations as much as possible. Therefore, before operating the ring oscillator circuit 104, the input of the inverter circuit 803 is fixed to the ground potential.

  As described above, the detection circuit 100 detects the LSI characteristic variation and the arithmetic circuit 101 obtains the LSI spatial or temporal variation, whereby the LSI variation can be accurately grasped. Further, based on the detected LSI variation information, the variation / voltage conversion circuit 113 determines the control power supply voltage value and controls the external power supply IC 403 to compensate for the LSI variation.

  As described above, by providing a mechanism for converting the variation information detected in the subsequent stage of the arithmetic circuit into the control voltage value of the LSI power supply, it is possible to compensate for the variation of the LSI.

  Therefore, by controlling the power supply voltage of the integrated circuit based on the grasped variation information, it becomes possible to correct the characteristics such as the operation speed and the power consumption of the integrated circuit which are fluctuated due to the variation to the standard state at the time of design. .

  Furthermore, a detection circuit according to another embodiment of the present invention has the configuration as described above, and two or more ring oscillator circuits are arranged in the vicinity of each other. By using these characteristic differences between the ring oscillator circuits, it is possible to detect random variations in the LSI that are not systematic.

  FIG. 9 is a block diagram showing a configuration example of the variation detection circuit according to the second embodiment of the present invention. The variation detection circuit shown in FIG. 9 is capable of detecting not only systematic variations having a certain variation tendency but also random variations having no correlation with the variation tendency. The fluctuation detection circuit includes a first detection circuit 1000, a second detection circuit 1001, a first selector circuit 1002, a second selector circuit 1003, an arithmetic circuit 1006, a variation / voltage conversion circuit 1007, and the like. Consists of

  The first detection circuit 1000 and the second detection circuit 1001 include one or a plurality of ring oscillator circuits 1008 and 1009. The ring oscillator circuits 1008 and 1009 have the same configuration as the ring oscillator circuit of the first embodiment shown in FIG.

  The ring oscillator circuits 1008 and 1009 are arranged in pairs near each other while having the above-described configuration. One or a plurality of sets of ring oscillator circuits 1008 and 1009 arranged in pairs are arranged in the LSI. With this configuration, it is possible to reduce the influence of the fluctuation of the voltage due to the distance from the power source and the interaction of the layout pattern.

  The first selector circuit 1002 selects the output signal of the first detection circuit 1000, and the second selector circuit 1003 selects the output signal of the second detection circuit 1001. The first and second selector circuits 1002 and 1003 select the oscillation signal output of the ring oscillator circuits 1008 and 1009 arranged in pairs.

  The arithmetic circuit 1006 includes a frequency difference detection circuit 1004 and a square sum arithmetic circuit 1005. The oscillation signals selected by the first and second selector circuits 1002 and 1003 are input to the frequency difference detection circuit 1004. The frequency difference detection circuit converts the oscillation frequency of the oscillation signal into a count number and calculates the difference between the two count numbers. The difference signal of the obtained count number is output to the square sum operation circuit 1005. The sum-of-squares calculation circuit 1005 calculates the sum of squares of the difference signal, and calculates a statistical value indicating the spread of the distribution such as standard deviation and variance.

  By detecting the difference in oscillation frequency characteristics of a pair of ring oscillator circuits 1008 and 1009 arranged in the vicinity and performing statistical processing, it detects not random systematic variations with a certain tendency, but random variations within the LSI. It becomes possible. Further, by statistically processing the difference signal instead of the oscillation frequency itself of the ring oscillator circuit, the number of bits of the count number can be reduced, and compensation with a greatly reduced calculation amount can be performed.

  The frequency difference detection circuit 1004 statistically processes the oscillation frequency count number of one of the ring oscillator circuits 1008 or 1009, not the difference between the oscillation frequency count numbers of the oscillation signals of the two ring oscillator circuits 1008 and 1009. Thus, it is possible to detect spatial variations in the entire LSI including the random variations.

  The variation / voltage conversion circuit 1007 converts the LSI variation information calculated by the statistical calculation circuit 112 into LSI power supply voltage information. This power supply voltage information is determined to be an optimum voltage for compensating for variations in LSI. The variation / voltage conversion circuit 1007 generates a control signal for the power supply IC 403 outside the LSI to output the determined power supply voltage.

  A specific method for converting the variation information of the LSI into the control signal of the power supply IC 403 may be realized by a table in which the variation amount and the control signal value are associated with each other as in the first embodiment, but is not limited thereto. It is not a thing.

  As a result, it is possible to compensate for characteristics such as LSI operation speed and power consumption, which fluctuate due to transistor variations, in the standard state at the time of design.

  As described above, the detection circuit 1000 and the detection circuit 1001 detect LSI characteristic variation, and the arithmetic circuit 1006 obtains spatial variation including random variation of the LSI, thereby accurately grasping the variation of the LSI. It is possible. Further, the variation of the LSI can be compensated by determining the control power supply voltage value by the variation / voltage conversion circuit 1007 based on the detected variation information of the LSI and controlling the external power supply IC 403.

  Note that the functions realized by the frequency difference detection circuit 1004, the sum of squares operation circuit 1005, the operation circuit 1006, and the variation / voltage conversion circuit 1007 do not necessarily exist in the same LSI, and are replaced by input / output from an external chip. Needless to say, it can also be done.

  As described above, the variation detection circuit and the compensation method thereof according to each embodiment are particularly useful techniques when applied to a semiconductor integrated circuit mainly composed of a logic circuit such as a microcomputer or a processor. The present invention is not limited to this, and can be widely applied to semiconductor integrated circuits that need to compensate for characteristic variations.

100, 400, 1000, 1001 Detection circuit 101, 1006 Arithmetic circuit 104, 1008, 1009 Ring oscillator circuit 106 Timer circuit 107 Control circuit 108 First selection circuit 109 Counter circuit 110 Second selection circuit 111 Register circuit 112 Statistical processing circuit 113, 1007 Variation / voltage conversion circuit 200 RTN variation waveform 300, 301, 302 LSI speed distribution waveform 401 Semiconductor integrated circuit (LSI)
402 Controller 403 Power supply IC
404 Power supply voltage of integrated circuit 405 Power supply IC control signal 500 NAND circuit 501, 603, 803 Inverter circuit 601, 800 Switch circuit 804 Control signal generator 1002, 1003 Selector circuit 1004 Frequency difference detection circuit 1005 Square sum operation circuit 1006 Operation circuit 1007 Variation / voltage conversion circuit

Claims (11)

A detection circuit having a plurality of oscillation circuits using delay elements;
A counter circuit connected to the detection circuit and counting the number of oscillations of the oscillation circuit for a certain period;
A control circuit connected to the counter circuit and outputting a control signal for controlling the counter circuit;
A timer circuit connected to the control circuit and outputting a timer signal serving as a reference of the control signal to the control circuit;
An arithmetic circuit connected to the counter circuit and calculating a count result of the counter circuit,
The detection circuit includes a first oscillation circuit;
The timer circuit outputs the timer signal after a predetermined period after the counter circuit counts the number of oscillations of the first oscillation circuit for the certain period,
The counter circuit counts the number of oscillations of the first oscillation circuit based on the timer signal for the certain period,
The semiconductor integrated circuit device, wherein the arithmetic circuit statistically calculates a plurality of count results in the first oscillation circuit. In claim 1,
The plurality of oscillation circuits further include a second oscillation circuit,
The semiconductor integrated circuit device, wherein the arithmetic circuit statistically calculates a count result of the counter circuit in the first oscillation circuit and the second oscillation circuit. In claim 2,
A register circuit that is connected to the counter circuit and is output from the counter circuit operated a plurality of times, and holds a plurality of count results.
A semiconductor integrated circuit device. In claim 3,
The semiconductor integrated circuit device, wherein the arithmetic circuit is an arithmetic circuit that is connected to the register circuit and statistically calculates the plurality of count results. In claim 4,
The arithmetic circuit holds information in which a variation voltage statistically calculated based on the count result, a power supply voltage that compensates for the variation voltage, and a control signal value for the external power supply are associated with each other. A semiconductor integrated circuit device. In claim 5,
The arithmetic circuit outputs a signal for varying the voltage to an external power source,
The semiconductor integrated circuit device is supplied with the variable voltage from the external power supply. In claim 4,
The arithmetic unit is a difference detection circuit for obtaining a difference between a plurality of count results,
And a sum of squares calculation circuit for obtaining a standard deviation or variance based on the difference. In claim 2,
The semiconductor integrated circuit device, wherein the second oscillation circuit is disposed in the vicinity of the first oscillation circuit. In claim 1,
The semiconductor integrated circuit device, wherein the plurality of oscillation circuits are ring oscillators having inverter circuits. In claim 9,
The semiconductor integrated circuit device according to claim 1, wherein a voltage input to the first oscillation circuit is higher than an input voltage of an input signal of an inverter circuit at a preceding stage in the ring oscillator. In claim 9,
The semiconductor integrated circuit device according to claim 1, wherein a voltage input to the first oscillation circuit is lower than an input voltage of an input signal of an inverter circuit at a preceding stage in the ring oscillator.

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