JP2008124406A - Semiconductor integrated circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor integrated circuit for aiming at a miniaturization and reduction of power consumption. <P>SOLUTION: A semiconductor integrated circuit 1 includes: two or more analog circuits (circuits to be corrected) 2, 2 which constitute various functions of the semiconductor integrated circuit 1; and a control unit 3 for feeding monitoring data which offer information on current element characteristics about manufacturing variation and temperature variation of each element (transistor, resistor, and capacitor in this implementation) included in each analog circuit 2 are provided. The control unit 3 does it all the monitoring of the manufacturing variation and the temperature of the element of the semiconductor integrated circuit. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a semiconductor integrated circuit, and more particularly to a semiconductor integrated circuit for maintaining circuit characteristics.

  In recent years, LSI (Large Scale Integration circuit) tends to be equipped with a large number of various analog circuits such as A / D converters, D / A converters, and amplifiers due to the demand for SOC (System On Chip).

FIG. 26 is a diagram illustrating an example of a conventional LSI.
The LSI 90 shown in FIG. 26 is a DDR2 SDRAM (Double Data Rate 2 Synchronous DRAM).

  The LSI 90 includes analog circuits 92 to 96 provided in the logic unit 91. Each analog circuit 92 has a BGR (band gap reference). The analog circuit 93 has a bias generation unit. The analog circuit 94 has a margin adjustment circuit. The analog circuit 95 has a constant current source. The analog circuit 96 includes an ODT (On Die Termination) having a termination resistor for reducing signal reflection, and an OCD (Off Chip Driver calibration) having a pull-up resistor and a pull-down resistor for adjusting the impedance value of the output driver in the LSI 90. And have.

  Since such analog circuits 92 to 96 have a great influence on element characteristic fluctuations due to manufacturing variations and temperature changes, for example, sensors for measuring temperature and correction functions for canceling the influence of characteristic fluctuations are provided. Have it individually. However, there is a problem that the area occupied by the correction function and the ratio of power consumption are larger than the total area and power consumption of the circuit.

FIG. 27 is a diagram showing a conventional D / A converter.
The D / A converter (analog circuit) 97 includes a bias generator 971 that generates a bias voltage, a digital data input receiving unit 972 for conversion, and an analog data output unit 973 that converts the digital data and outputs analog data. And have.

  Here, the bias generation unit 971 has a large circuit scale and a large proportion of the entire circuit, and the analog data output unit 973 has to narrow down the bias to compensate for variations. In any case, there is a problem that the circuit becomes huge.

FIG. 28 is a diagram illustrating a conventional active filter.
The active filter 98 that outputs the voltage VOUT with respect to the voltage VIN includes an anti-aliasing unit 981 for removing sampling noise, a filter circuit 982, and a smoothing circuit 983 for smoothing switching of the operational amplifier OP90 in the filter circuit 982. have.

The time constant Teff of the active filter 98 is expressed by the following expression (1), where Ts is the sampling period of the switches (transfer gates) Sw91 to Sw94.
Teff = Ts × (Ci / Cs) (1)
Here, the capacitors Ci and Cs are the same type of elements, and Ci / Cs cancels element variations and temperature characteristics of the capacitors.

Here, a method is known in which variations in elements constituting an analog circuit are detected by a single circuit (see, for example, Patent Document 1).
JP-A-7-86900

  However, since the target characteristics are different between different analog circuits, such as the analog circuits 92 to 96, and the mechanism for canceling the influence of manufacturing variation and temperature is also different, the sensors and correction functions of the analog circuits 92 to 96 are different. Measurement results cannot be shared.

  Further, even if the analog circuits 92 are of the same type, even if the bias voltage generated from the BGR circuit is supplied to other analog circuits, a bias voltage transfer line is generated on the chip. Under the influence of noise, the characteristics may deteriorate rapidly. For this reason, a bias voltage having a larger error is supplied to an analog circuit that is located farther away from the bias circuit, and the measurement result cannot be shared.

  For example, in the active filter 98 shown in FIG. 28, the anti-folding unit 981 has a large circuit scale and directly takes in the voltage VIN, so even the same type of filter cannot be shared. Further, since the smoothing circuit 983 has a huge circuit scale and is directly connected to the voltage VOUT, even the same kind of filter cannot be shared.

As described above, an LSI having a large number of these analog circuits, regardless of whether they are of the same type or different types, has a problem that a chip occupation area and power consumption increase.
The present invention has been made in view of these points, and an object of the present invention is to provide a semiconductor integrated circuit that can be reduced in size and power consumption.

  In order to solve the above-described problems, the present invention provides a digital monitor that corrects the characteristics of a plurality of elements in a semiconductor integrated circuit that corrects the analog circuits according to changes in the element characteristics of a plurality of analog circuits to be controlled. Based on the received monitor data, a control unit that outputs data, a plurality of analog circuits, a receiving unit that receives only the monitor data related to elements used in the analog circuit from among the monitor data, There is provided a semiconductor integrated circuit including a characteristic correction unit that corrects the characteristic of the element of the analog circuit, wherein the control unit and the plurality of analog circuits are provided separately.

  According to such a semiconductor integrated circuit, monitor data for correcting the characteristics of a plurality of elements is output by the control unit. Only the monitor data used in the analog circuit is received from the monitor data by the receiving unit of the analog circuit provided separately from the control unit. The characteristic correction unit corrects the characteristics of the elements of the analog circuit that outputs the analog data based on the received monitor data.

  According to the present invention, since data is digitized and transmitted / received, it is not easily affected by noise, and the circuit characteristics of the analog circuit can be corrected more accurately by correcting the element characteristics.

  In addition, since a control unit is provided separately and data to be transmitted to each analog circuit is shared, each analog circuit can be reduced in size and power consumption can be reduced. Therefore, the entire semiconductor integrated circuit can be reduced in size and power consumption can be reduced.

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.
FIG. 1 is a plan view showing a semiconductor integrated circuit according to the embodiment.
A semiconductor integrated circuit 1 shown in FIG. 1 includes a plurality of analog circuits (correction target circuits) 2, 2,... That constitute various functions of the semiconductor integrated circuit 1, and elements included in each analog circuit 2 (the present embodiment). In this case, the control unit 3 has a single control unit 3 that supplies monitor data for providing information on current element characteristics due to manufacturing variations of transistors, resistors, capacitors), temperature changes, and the like.

The adjacent control units 3 and the analog circuits 2 and the adjacent analog circuits 2 are connected to each other by communication lines 4.
Each analog circuit 2 includes a monitor data receiving unit 21, a switching determination unit 22, and an element switching unit 23.

The monitor data receiving unit 21 receives monitor data transmitted from the control unit 3.
The switching determination unit 22 determines the current manufacturing variation and temperature from the received monitor data, determines the combination of the element switching unit 23 for maintaining the circuit characteristics, and gives an instruction to the element switching unit 23.

  The element switching unit 23 includes a switch for switching the effective / invalidity of the element that determines the output value (analog data) of the analog circuit 2, and performs switch switching as instructed by the switching determination unit 22. Thereby, the output value of the analog data that changes in accordance with the change in the characteristics of the element is corrected.

  The control unit 3 takes charge of manufacturing variations of elements of the semiconductor integrated circuit 1 and temperature monitoring. The control unit 3 includes a monitor data generation unit 31 that generates monitor data for converting the monitor result into digital data, and a monitor data transmission unit 32 that transmits the monitor data to the analog circuit 2 that requires element correction. Yes. In the present embodiment, as an example, it is assumed that all analog circuits 2 require correction.

FIG. 2 is a diagram illustrating a configuration of the control unit.
The monitor data generation unit 31 includes a temperature sensor unit 33 and an element process sensor unit 34, and the monitor data transmission unit 32 includes a monitor data transmission synchronization unit 35.

The temperature sensor unit 33 measures the temperature of the semiconductor integrated circuit 1 and outputs temperature information of the measurement result.
FIG. 3 is a diagram illustrating an example of the configuration of the temperature sensor unit.

The temperature sensor unit 33 includes a BGR (band gap reference) unit 33a that generates a Bias voltage and a reference potential VBG, and a temperature determination unit 33b.
The temperature determination unit 33b includes a transistor Tr10 and a resistor R1, and a grounded-emitter amplifier circuit for outputting a measured potential M corresponding to a Bias voltage. The reference potential VBG is input to a non-inverting input terminal to configure a voltage follower. An operational amplifier OP1, a voltage dividing resistor R2, R3, R4, R5 connected in series in this order to the output terminal of the operational amplifier OP1, and comparators CMP1, CMP2, CMP3.

The other end of the voltage dividing resistor R5 is connected to GND.
A measured potential M is input to each non-inverting input terminal of the comparators CMP1, CMP2, and CMP3.

  The reference potential A between the voltage dividing resistors R2 and R3 is input to the inverting input terminal of the comparator CMP1. The reference potential B between the voltage dividing resistors R3 and R4 is input to the inverting input terminal of the comparator CMP2. The reference potential C between the voltage dividing resistors R4 and R5 is input to the inverting input terminal of the comparator CMP3. With such a configuration, since the reference potential A> the reference potential B> the reference potential C, the high reference potential is input in the order of the comparators CMP1, CMP2, and CMP3. Then, combinations of output values a, b, and c (0 or 1) of the comparators CMP1, CMP2, and CMP3 are output as the temperature signal pre_Temp.

FIG. 4 is a diagram illustrating the operation of the temperature sensor unit.
As shown in FIG. 4, a region where the measured potential M is less than the reference potential C is defined as a low temperature region. A region where the measured potential M is greater than or equal to the reference potential C and less than the reference potential B is defined as a normal temperature region. A region where the measured potential M is not less than the reference potential B and not more than the reference potential A is defined as a high temperature region. A region where the measured potential M is equal to or higher than the reference potential A is defined as an ultra-high temperature region. This temperature range setting can be arbitrarily set by changing each resistance value of the voltage dividing resistors R2, R3, R4, and R5.

FIG. 5 is a diagram illustrating the output value of the temperature signal. For example, in the low temperature range, “000” is output as the temperature signal pre_Temp.
Returning again to FIG.

  The element process sensor unit 34 includes a measurement control unit 34a, a transistor / sensor unit 34b that detects element characteristics of a transistor, a resistance sensor unit 34c that detects element characteristics of a resistor, and a capacitance sensor unit that detects element characteristics of a capacitor. 34d.

  The measurement control unit 34a obtains a temperature signal pre_Temp from the temperature sensor unit 33, a monitor measurement sampling time from a CPU (Central Processing Unit) (not shown) of the semiconductor integrated circuit 1, and a reference for synchronizing monitor data transmission / reception. And a measurement signal M_Tr that defines a monitor data measurement period (described later) of the transistor / sensor unit 34b and a monitor data measurement of the resistance sensor unit 34c. A measurement signal M_Res that defines a period, a measurement signal M_Cap that defines a monitor data measurement period of the capacitance sensor unit 34d, and a data transmission signal send that controls data transmission / reception timing are generated and output.

  The transistor / sensor unit 34b, the resistance sensor unit 34c, and the capacitance sensor unit 34d detect characteristics according to manufacturing variations of the respective elements, respectively, and detect temperature changes based on temperature information, respectively. Sensor signals pre_Tr, pre_Res, and pre_Cap that maintain the characteristic information of the element are generated and output to the monitor data transmission synchronization unit 35.

Next, the circuit configuration of the transistor / sensor unit 34b, the resistance sensor unit 34c, and the capacitance sensor unit 34d will be described.
FIG. 6 is a diagram illustrating each configuration of the transistor / sensor unit, the resistance sensor unit, and the capacitance sensor unit.

  The transistor / sensor unit 34b includes a NAND gate 51, a plurality (four in FIG. 6) of inverters 52, 53, 54, and 55 and a 3-bit (n-bit) counter 56 from the input side to the output side. It has in this order.

The measurement signal M_Tr and the output value of the inverter 55 are input to the two input terminals of the NAND gate 51, respectively.
The output value of the inverter 55 is input to the input of the counter 56, and the measurement signal M_Tr is input to the reset and hold terminal.

  In the transistor / sensor unit 34b, when M_Tr = H, the inverters 52, 53, 54, and 55 operate as oscillators, and the counter 56 counts the number of oscillations. When M_Tr = L, the transmission operation is stopped and the counter value of the counter 56 is reset. The 3-bit counter value is output as the sensor signal pre_Tr and held in the counter 56.

Here, the greater the driving force of the inverter composed of transistors, the faster the counter counts up, and thus the counter value of the counter 56 increases.
In addition to the configuration of the transistor / sensor unit 34b, the resistance sensor unit 34c includes resistors R61, R62, R63, and R64 between the NAND gate 61 and the inverter 62 and between the inverters 62, 63, 64, and 65, respectively. . The resistors R61, R62, R63, and R64 have the same element characteristics.

  Since the operation of the resistance sensor unit 34c is the same as that of the transistor / sensor unit 34b, description thereof is omitted. The counter value of the counter 66 of the resistance sensor unit 34c is output as the sensor signal pre_Res.

  In addition to the configuration of the transistor / sensor unit 34b, the capacitance sensor unit 34d includes capacitors C71, C72, C72, C72, which are connected to the ground between the NAND gate 71 and the inverter 72 and between the inverters 72, 73, 74, and 75, respectively. C73 and C74 are included. Capacitors C71, C72, C73, and C74 have the same element characteristics.

  Since the operation of the capacitance sensor unit 34d is the same as that of the transistor / sensor unit 34b, description thereof is omitted. The counter value of the counter 76 of the capacitance sensor unit 34d is output as the sensor signal pre_Cap.

Next, the configuration of the monitor data transmission synchronization unit 35 will be described.
FIG. 7 is a diagram illustrating a configuration of the monitor data transmission synchronization unit.
The monitor data transmission synchronization unit 35 includes a flip-flop FF1 that inputs the temperature signal pre_Temp, a flip-flop FF2 that inputs the sensor signal pre_Tr, a flip-flop FF3 that inputs the sensor signal pre_Res, and a flip-flop that inputs the sensor signal pre_Cap. It has an FF4 and a gated clock buffer 351 composed of an AND circuit.

  The clock signal CLK and the data transmission signal send are input to the two input terminals of the gated clock buffer 351, respectively. The gated clock buffer 351 outputs (supplies) the clock signal send_clk to the flip-flops FF1, FF2, FF3, and FF4 when the clock signal CLK is input in a state where the data transmission signal send is input.

  The flip-flop FF1 holds the signal when the temperature signal pre_Temp is input, and outputs the held signal as the temperature signal Temp when the clock signal send_clk is input. Similarly, the flip-flop FF2 holds the signal when the sensor signal pre_Tr is input, and outputs the held signal as the sensor signal Tr when the clock signal send_clk is input. The flip-flop FF3 holds the signal when the sensor signal pre_Res is input, and outputs the held signal as the sensor signal Res when the clock signal send_clk is input. The flip-flop FF4 holds the signal when the sensor signal pre_Cap is input, and outputs the held signal as the sensor signal Cap when the clock signal send_clk is input.

In this way, the monitor data transmission synchronization unit 35 outputs the temperature signal Temp and the sensor signals Tr, Res, Cap to the analog circuits 2 as monitor data.
Next, the monitor data transmission operation of the control unit 3 will be described.

  Factors of manufacturing variation of each element include those that change with time (for example, due to changes in potential and temperature over time) and those that do not change. Therefore, the element process sensor unit 34 performs an operation corresponding to these.

FIG. 8 is a diagram illustrating an operation waveform of the control unit when detecting a manufacturing variation of an element due to a factor that does not change with time.
In this case, for example, the variation is detected once when the semiconductor integrated circuit 1 is started. Specifically, as shown in FIG. 8, the Test signal changes from Lo to Hi by the power-on reset signal output from the CPU when the semiconductor integrated circuit 1 is started (time T1). As a result, measurement of the measurement signals M_Tr, M_Res, and M_Cap is started by the measurement control unit 34a in accordance with the rising timing (time T2) of the next clock. When the Test signal changes from Hi to Lo, measurement of the measurement signals M_Tr, M_Res, and M_Cap is finished according to the next clock rising timing (time T3). In addition, the data transmission signal send changes to Hi with the end of measurement (enabled output).

  Thereafter, the element process sensor unit 34 outputs the sensor signals pre_Tr, pre_Res, and pre_Cap to the monitor data transmission synchronization unit 35, and holds them in the monitor data transmission synchronization unit 35 (from time T4). Thereafter, the temperature signal Temp and the sensor signals Tr, Res, and Cap are used as monitor data by the monitor data transmission synchronization unit 35 in accordance with the rising timing (time T5) of the first clock after the data transmission signal send becomes Hi. Output (transmit) all at once.

Thus, when measuring the manufacturing variation of the element which does not change with time, the monitor data is output by operating the Test signal periodically.
Next, temperature will be described as an example of a factor of manufacturing variation of elements that changes with time.

FIG. 9 is a diagram illustrating operation waveforms of the control unit in the case of detecting element manufacturing variations due to factors that change with time. In FIG. 9, a part of FIG. 8 is omitted.
When measuring the manufacturing variation of the element that changes with temperature, the measurement control unit 34a determines whether or not there is a change (state change) in the value of the temperature signal pre_Temp from the temperature sensor unit 33 at every rising timing of the clock. . Then, when a change in the value of the temperature signal is detected (time T6), measurement of the measurement signals M_Tr and M_Res is started. At this time, since the capacitor is an element whose characteristic change is small with temperature, the capacitance sensor unit 34d excludes the measurement signal M_Cap in advance from the measurement target. Then, measurement of the measurement signal is finished in accordance with the next clock rising timing (time T7). Since temperature is a parameter that changes over time, it is always measured.

Next, the communication line 4 will be described in detail.
FIG. 10 is a diagram showing details of the communication line.
The communication line 4 includes twelve monitor data transmission / reception lines 41 provided according to the number of bits of monitor data, a clock supply line 42 that supplies a clock CLK, and a data transmission signal supply line 43 that supplies a data transmission signal send. I have.

  Each analog circuit 2 is connected in parallel to the control unit 3 via a monitor data transmission / reception wiring 41. Each analog circuit 2 is connected so as to receive only necessary sensor signals according to the type, application, and function of the circuit.

Next, the configuration of the analog circuit 2 will be described in detail.
FIG. 11 is a diagram illustrating a configuration of the monitor data receiving unit.
The monitor data receiving unit 21 receives the flip-flop FF11 to which the temperature signal Temp is input, the flip-flop FF12 to which the sensor signal Tr is input, the flip-flop FF13 to which the sensor signal Res is input, and the sensor signal Cap. The flip-flop FF 14 includes a gated clock buffer 211 formed of an AND circuit, and a flip-flop FF 15 provided on the input side of the gated clock buffer 211.

  The output side of the flip-flop FF15 is connected to one input terminal of the gated clock buffer 211. When the clock signal CLK is input in a state where the data transmission signal send is input, the data reception signal receive is output.

  The gated clock buffer 211 outputs the clock signal receive_clk to each of the flip-flops FF11, FF12, FF13, and FF14 when the clock signal CLK is input in a state where the data reception signal receive is input.

  The flip-flop FF11 holds the signal when the temperature signal Temp is input, and outputs the held signal to the switching determination unit 22 when the clock signal receive_clk is input. Similarly, the flip-flop FF12 holds the signal when the sensor signal Tr is input, and outputs the held signal to the switching determination unit 22 when the clock signal receive_clk is input. The flip-flop FF13 holds the signal when the sensor signal Res is input, and outputs the held signal to the switching determination unit 22 when the clock signal receive_clk is input. The flip-flop FF14 holds the signal when the sensor signal Cap is input, and outputs the held signal to the switching determination unit 22 when the clock signal send_clk is input.

Next, monitor data transmission / reception timing will be described.
FIG. 12 is a timing chart showing monitor data transmission / reception operations. In FIG. 12, “pre_ *” indicates the temperature signal pre_Temp, the sensor signal pre_Tr, the sensor signal pre_Res, and the sensor signal pre_Cap. “Monitor” indicates monitor data.

  As described above, when the data transmission signal send is input to the gated clock buffer 351, the clock signal send_clk is output (time Ta1). At the same time, the temperature signal pre_Temp, the sensor signal pre_Tr, the sensor signal pre_Res, and the sensor signal pre_Cap are transmitted as monitor data to each analog circuit 2 (time Ta1).

  On the other hand, on the analog circuit 2 side, the flip-flop FF15 outputs the data reception signal receive with a predetermined time delay from the time Ta1 (time Ta2). Then, the clock signal receive_clk is output at the next rising edge of the clock (time Ta3).

  As described above, when the data transmission signal send is enabled and output, the monitor data transmission synchronization unit 35 and the monitor data reception unit 21 operate at the same time to transmit and receive updated monitor data. More specifically, since the monitor data transmission synchronization unit 35 uses the gated clock buffer 351 to generate the monitor data at the AND timing of the data transmission signal send and the clock CLK, unnecessary monitoring is not performed. . Therefore, power consumption can be reduced. Further, the data transmission signal send and the clock CLK are also supplied to the monitor data receiving unit 21, and the monitor data receiving unit 21 outputs the data reception signal receive delayed for a predetermined time to the gated clock buffer 211 using the flip-flop FF 15. Since the gated clock buffer 211 outputs the clock signal receive_clk delayed by a predetermined time with respect to the clock signal send_clk, monitor data can be transmitted and received efficiently.

  Further, since the data transmission signal send is enabled and output only when the monitor result is updated, the monitor data transmission synchronization unit 35 and the monitor data reception unit 21 are not allowed to operate unnecessarily in the monitor result maintenance phase. Thereby, useless clock charging / discharging can be suppressed.

Next, the analog circuit 2 will be described by taking a D / A converter and an active filter as an example.
FIG. 13 is a circuit diagram showing a D / A converter.

  The D / A converter 2a includes a Tr data receiving unit 21a, a temperature data receiving unit 21b, and a resistance data receiving unit 21c that configure the monitor data receiving unit 21, and a Tr element switching determining unit 22a and a resistor that configure the switching determining unit 22. It has an element switching determination unit 22b and an analog data output unit 23a that creates analog data from the input digital data to be D / A converted. 6-bit digital data is input to the D / A converter 2a.

  Each of the Tr data receiving unit 21a, the temperature data receiving unit 21b, and the resistance data receiving unit 21c takes in a necessary signal among the monitor data (for example, the Tr data receiving unit 21a takes in the sensor signal Tr), and a switching determination unit. The signal is sent to 22 corresponding parts (for example, the Tr data receiving unit 21a is the Tr element switching determination unit 22a).

  The Tr element switching determination unit 22a is a transistor switching pattern provided in the analog data output unit 23a based on the received signal value and D / A conversion target digital data (for example, by ANDing each digital value). Determine (bit of digital value). Thus, the Tr element switching determination unit 22a also serves as a digital monitor data receiving unit. Thereby, size reduction of D / A converter 2a can be achieved.

The resistance element switching determination unit 22b determines a resistance switching pattern provided in the analog data output unit 23a based on the value of the received signal.
The analog data output unit 23a includes a plurality of transistors, and includes element switching units 231 to 236 that switch on / off of these transistors according to a switching pattern determined by the Tr element switching determination unit 22a, and a plurality of resistors. And an element switching unit 237 including a switch for switching these resistances according to a switching pattern from the resistance element switching determination unit 22b.

  The element switching units 231 to 236 are provided to convert the digital value of each bit of the digital data into an analog value, and the element switching unit 231 corresponds to the most significant bit (sixth bit) of the digital data. These correspond to the lower bits in the following order. The element switching unit 236 corresponds to the least significant bit (first bit) of the digital data.

FIG. 14 is a diagram illustrating a relationship between the switching determination unit and each element to be switched by the element switching unit.
The element switching unit 231 has a transistor Tr1 that is turned on by default when a desired data value enters the most significant bit of the digital data, and an On / Off according to the switching pattern of the Tr element switching determination unit 22a. In addition, three transistors Tr2, Tr3 and Tr4 for adjusting the analog output value are provided. Here, the transistor Tr4 has a driving power four times that of the transistor Tr2 (twice that of the transistor Tr3).

The element switching units 232 to 236 have the same configuration as the element switching unit 231 and will not be described.
The element switching unit 237 has one end connected to GND, a default resistor R11 not to be switched by the resistance element switching determination unit 22b, and three load resistors R12, R13, and R14 connected in series to the default resistor R11 in this order. The switches Sw1, Sw2, and Sw3 are provided corresponding to the load resistors R12, R13, and R14, respectively, and are turned on / off according to the switching pattern of the resistance element switching determination unit 22b. The element characteristics of the default resistor R11 and the load resistors R12, R13, and R14 have the same element characteristics as the resistors R61 to R64 of the resistance sensor unit 34c, respectively. The other end of R14 is connected to each emitter of transistors Tr1 to Tr4. When the switches Sw1 to Sw3 are turned on / off, the resistance value of the element switching unit 237 changes.

Next, determination operations of the Tr element switching determination unit 22a and the resistance element switching determination unit 22b will be described.
The Tr element switching determination unit 22a and the resistance element switching determination unit 22b perform determination based on a conversion table prepared in advance according to the temperature signal Temp. This conversion table is provided for each of the element switching units 231 to 237.

Hereinafter, the element switching unit 231 will be described as an example.
FIG. 15 is a diagram showing a conversion table.
The conversion table 238 is a table used in the normal temperature range.

  The conversion table 238 includes columns for received data, D5, default, x4, x2, and x1. Information arranged in the horizontal direction of each column is associated with each other.

In the column of received data, columns of Temp and Tr are further provided.
In the Temp column, a 3-bit value of the temperature signal Temp is set. “XXX” indicates a case where received data is ignored in the element switching determination unit 22a.

A 3-bit value of the sensor signal Tr is set in the Tr column.
In the column D5, the value of the sixth bit of the digital data is set. In FIG. 15, when the value of the sixth bit is “0”, the transistors Tr1, Tr2, Tr3, and Tr4 are all set to Off regardless of the information of the temperature signal Temp and the sensor signal Tr, and switching is not performed. Is set.

In the default column, “Off” is set when digital data is not received, and “On” is set when digital data is received.
In the columns x4, x2, and x1, the transistor switching pattern is set so as to change the driving force of the element switching unit 231 corresponding to the third bit, the second bit, and the first bit of the received sensor signal Tr. The

  Here, the conversion table 238 indicates that the larger the 3-bit value of the sensor signal Tr, the greater the driving force of the transistor element. Is set. Thereby, the driving force of the entire transistor as the element switching unit 231 is made constant. Conversely, the smaller the 3-bit value of the sensor signal Tr is, the smaller the driving power of the transistor element is, so the switching pattern is set so as to increase the driving power of the transistor to be turned on. .

  The Tr element switching determination unit 22a instructs switching of the transistors Tr1 to Tr4 based on the conversion table 238. Specifically, the transistor Tr4 is turned on / off according to the setting of the x4 column of the conversion table 238, the transistor Tr3 is turned on / off according to the setting of the x2 column, and the transistor is turned on according to the setting of the x1 column. Turn Tr2 On / Off.

  By doing so, it becomes possible to obtain variation information from the outside, so that no bias is necessary. Therefore, the transistor size can be made very small compared to the conventional case, and as a result, the analog data output unit 23a can be made very small.

Next, another temperature range conversion table will be described.
FIG. 16 is a diagram showing a conversion table in another temperature range, FIG. 16 (a) is a diagram showing a conversion table in a low temperature range, and FIG. 16 (b) is a conversion table in a high temperature range. FIG. 16C is a diagram showing a conversion table in the ultra-high temperature region.

  In the low temperature range, the 3-bit value of the sensor signal Tr is larger than the actual driving power information of the transistor element compared to the normal temperature range. A conversion table in which the transistors Tr2 to Tr4 are turned on regardless of the value of the least significant bit when the 2-bit value is “0”, and the transistor Tr2 is turned on even when the value of the sensor signal Tr is “111” at the maximum. 238a is set.

  In the high temperature range, the 3-bit value of the sensor signal Tr is smaller than the actual driving power information of the transistor element as compared to the normal temperature range. When the 2-bit value is “1”, the conversion table is set so that the transistors Tr2 to Tr4 are turned off regardless of the value of the least significant bit, and the transistor Tr2 is turned off even when the value of the sensor signal Tr is “000”. 238b is set.

  In the ultra-high temperature range, there is a risk of element destruction, and in order to ensure the reliability of the device, a conversion table that turns off all the transistors Tr1 to Tr4 regardless of the values of the received digital data D5 and sensor signal Tr 238c is set.

By properly using these tables in accordance with the temperature, it is possible to accurately correct the temperature change.
Next, the active filter will be described. In addition, the same code | symbol is attached | subjected about the part provided with the function similar to D / A converter 2a.

FIG. 17 is a diagram illustrating a circuit configuration of the active filter.
The monitor data receiving unit 21 of the active filter 2b includes a temperature data receiving unit 21d that receives the temperature signal Temp, a resistance data receiving unit 21e that receives the sensor signal Res, and a capacitance data receiving unit 21f that receives the sensor signal Cap. ing.

  The switching determination unit 22 of the active filter 2b includes a capacitive element switching determination unit 22c that switches a capacitive element (described later) of the analog data output unit 23b and a resistive element switching determination unit 22d that switches a resistive element.

  The analog data output unit 23b includes an operational amplifier OP2, an element switching unit 239, and an element switching unit 240 that constitute an integrator. The analog data output unit 23b applies a low-pass filter to the voltage VIN and outputs a voltage VOUT.

FIG. 18 is a diagram illustrating details of the element switching unit of the active filter.
The element switching unit 239 is provided corresponding to the capacitor Ci1 that is not to be switched by the capacitive element switching determination unit 22c, the three capacitors Ci2, Ci3, Ci4 connected in parallel to the capacitor Ci1, and the capacitors Ci2, Ci3, Ci4, respectively. In addition, three switches Sw11, Sw12, and Sw13 that turn on / off according to the switching pattern of the capacitive element switching determination unit 22c and adjust the capacitance value of the element switching unit 239 are provided. The capacitors Ci1 to Ci4 have the same element characteristics as the capacitors C71 to C74 of the capacitance sensor unit 34d, respectively.

  The capacitive element switching determination unit 22c is provided with a conversion table having the same configuration as the conversion table 238. The capacitive element switching determination unit 22c is based on this conversion table in the same manner as the Tr element switching determination unit 22a. The switching pattern of the switches Sw11 to Sw13 is instructed.

  The element switching unit 240 is connected at one end to the inverting input terminal of the operational amplifier OP2, and is not switched by the resistive element switching determination unit 22d, and three load resistors R22 connected in series to the default resistor R21 in this order. , R23, and R24, and switches Sw21, Sw22, and Sw23 that are provided corresponding to the load resistors R22, R23, and R24, and are turned on / off according to the switching pattern of the resistance element switching determination unit 22d. The voltage VIN is applied to the other end side of the load resistor R24. When the switches Sw21 to Sw23 are turned on / off, the resistance value of the element switching unit 240 changes.

Here, the time constant Teff of the filter is obtained by the following equation (2), where Ci is the output value of the element switching unit 239 and Ri is the output value of the element switching unit 240.
Teff = Ri × Ci (2)
Here, since the element variation between Ri and Ci and the temperature characteristic are not related, the deterioration of the characteristic is usually amplified, but the characteristic can be maintained by switching the switch based on the monitor data.

  In addition, since monitor data is obtained from the outside, different elements (load resistors R21 to R24 and capacitors Ci1 to Ci4) can be used. As a result, in this example, the necessity of sampling can be eliminated, and the unnecessary noise removal mechanism can be omitted.

  As described above, according to the semiconductor integrated circuit 1, since the control unit 3 converts a large amount of monitor data into digital data and transfers it, data errors are less likely to occur due to the influence of noise than in the prior art. Accurate measurement results can be supplied to the plurality of analog circuits 2. Therefore, it is possible to perform corrections for variations in the element characteristics of each analog circuit 2 at once.

  As a result, it is not necessary to individually insert a mechanism for correcting manufacturing variations and temperature changes into each analog circuit 2, and it is only necessary to install an element switching unit having a simple configuration with a small circuit area. Miniaturization and reduction of power consumption can be achieved.

  Some types of analog circuits occupy an area of 90% or more with only the correction unit. There is also a case where the power consumed by the correction mechanism exceeds 50% of the entire circuit. The effect of applying the present invention is great for LSIs having a large number of analog circuits and those having a large proportion of correction units in the analog circuits.

  Further, since the control unit 3 and each analog circuit 2 are connected in parallel, and the monitor data transmission synchronization unit 35 outputs the monitor data in parallel, the monitor data is transferred. Sometimes monitor data can be transmitted simultaneously and at high speed.

  In this embodiment, an example in which a transistor, a resistor, and a capacitor are used as elements to be corrected has been described. However, elements that can be applied to the present invention are not limited to this, and for example, a diode, a bipolar, an inductor The present invention can also be applied.

  In this embodiment, a D / A converter and an active filter are exemplified as the analog circuit 2, but other analog circuits applicable to the present invention include, for example, S / H (sample and hold) of an A / D converter circuit. ) Circuits, current sources, etc.

Next, a semiconductor integrated circuit according to a second embodiment will be described.
Hereinafter, the semiconductor integrated circuit according to the second embodiment will be described focusing on the differences from the first embodiment described above, and description of similar matters will be omitted.

The semiconductor integrated circuit of the second embodiment is different from the first embodiment in the communication method between each analog circuit and the control unit.
FIG. 19 is a diagram illustrating a connection between each analog circuit and the control unit of the semiconductor integrated circuit according to the second embodiment.

In the semiconductor integrated circuit 1 a of the second embodiment, each analog circuit 20 and the control unit 30 are connected in a loop by a communication line 40.
The communication line 40 of the second embodiment has a data bus 44 for transferring monitor data and a notification signal line 45 for transferring a notification signal (described later).

The data bus 44 is a serial bus and constitutes a serial transfer path for monitor data.
The notification signal line 45 is a notification signal bus for causing the monitor data receiving unit of each analog circuit 20 to recognize monitor data using a prescribed communication protocol. By defining the communication protocol, it is possible to prevent erroneous recognition of data in the monitor data receiving unit of each analog circuit 20.

  Further, the semiconductor integrated circuit 1a differs from the first embodiment in the configuration of the monitor data receiving unit of each analog circuit 20 and the configuration of the monitor data transmission synchronization unit of the control unit 30 in accordance with the change of the communication method.

FIG. 20 is a diagram illustrating a circuit configuration of a monitor data transmission synchronization unit according to the second embodiment.
The monitor data transmission synchronization unit 350 includes a communication control unit 352, a monitor data storage register 353, a data bus register 354, and a notification signal register 355.

The communication control unit 352 controls the monitor data storage register 353, the data bus register 354, and the notification signal register 355.
The monitor data storage register 353 includes a Tr storage register 353a that stores the sensor signal Tr input to the monitor data transmission synchronization unit 35, a Res storage register 353b that stores the sensor signal Res, and a Cap that stores the sensor signal Cap. A storage register 353c and a Temp storage register 353d for storing the temperature signal Temp are provided.

Data in the monitor data storage register 353 is stored in the data bus register 354 when monitor data is transmitted through the data bus 44.
The notification signal register 355 stores the notification signal.

FIG. 21 is a diagram illustrating a circuit configuration of the monitor data receiving unit according to the second embodiment.
The monitor data receiving unit 210 includes a communication control unit 212, a data bus register 213, a notification signal register 214, and a monitor data storage register 215.

The communication control unit 212 controls the data bus register 213, the notification signal register 214, and the monitor data storage register 215.
The data bus register 213 is provided corresponding to the data bus register 354 and stores the monitor data transmitted from the data bus register 354 via the data bus 44.

The notification signal register 214 is provided corresponding to the notification signal register 355 and stores the notification signal transmitted from the notification signal register 355.
The monitor data storage register 215 holds monitor data written from the data bus register 213 in accordance with the value of the notification signal stored in the notification signal register 214.

Next, a method for transmitting and receiving monitor data from the control unit 30 to each analog circuit 20 will be described.
22 and 23 are diagrams showing a monitor data transmission operation of the process / temperature sensor unit.

  In the present embodiment, the leftmost register in FIG. 22 of the data bus register 354 and the notification signal register 355 is called MSB (Most Significant Bit), and the rightmost register is called LSB (Least Significant Bit).

First, the communication control unit 352 initializes the values of all the notification signal registers 355 to “0”.
Next, as shown in FIG. 22A, the communication control unit 352 transfers the monitor data stored in the monitor data storage register 353 to the data bus register 354 at the same time as the monitor data update, and sends a notification signal. “1” is written to the LSB of the register 355 (initial state).

  Next, as shown in FIG. 22B, when the scan clock SCLK is input to the communication control unit 352, the monitor data stored in the data bus register 354 and the notification signal register 214 are stored. The notification signal is shifted to the upper bit by one bit. As a result, one bit of monitor data stored in the MSB of the data bus register 354 and one bit of the notification signal stored in the MSB of the notification signal register 355 are transferred to one end of the control unit 30. The data is transmitted to the monitor data receiving unit 210 of the connected analog circuit 20 (hereinafter referred to as the one-end-side analog circuit 20). At this time, unknown data “X” is written to the data bus register 354 via the data bus 44 from the analog circuit 20 connected to the other end side of the control unit 30 (hereinafter, the other end side analog circuit 20). In addition, a one-bit notification signal “0” is written from the other end side analog circuit 20 to the notification signal register 355 via the notification signal line 45.

The monitor data storage register 353 continues to hold the monitor data even during data transmission.
Thus, every time the scan clock SCLK is input, one bit of monitor data stored in the MSB of the data bus register 354 and one bit of the notification signal stored in the MSB of the notification signal register 355 are stored. Is transmitted to the one-end-side analog circuit 20, 1-bit data of the monitor data is written from the other-end-side analog circuit 20 to the LSB of the data bus register 354, and the notification signal 1 is transmitted to the LSB of the notification signal register 355. Bits are written.

  After that, as shown in FIGS. 23A and 23B, when “1” is stored in the MSB of the notification signal register 355, when the scan clock SCLK is input to the communication control unit 352, One bit of monitor data stored in the MSB of the data bus register 354 and one bit of the notification signal “1” stored in the MSB of the notification signal register 355 are sent to the one-end analog circuit 20. While being transmitted, the 1-bit notification signal “1” input from the analog circuit 20 on the other end side is written to the LSB of the notification signal register 355. As a result, the communication control unit 352 determines that communication of the updated monitor data has ended, and the transfer of the monitor data ends.

24 and 25 are diagrams illustrating the operation of the monitor data receiving unit.
As shown in FIG. 24A, the monitor data storage register 215 of the monitor data receiving unit 210 stores the monitor data “Q” before update.

The communication control unit 212 receives 1 bit of monitor data and 1 bit of a notification signal bit by bit each time the scan clock SCLK is input.
As shown in FIGS. 24B and 25A, every time the scan clock SCLK is input, one bit of monitor data stored in the MSB of the data bus register 213 and the notification signal register One bit of the notification signal stored in 214 is transmitted bit by bit to the adjacent communication control unit (communication control unit 212 or communication control unit 352).

  Then, as shown in FIG. 24B, when a 1-bit notification signal “1” is written to the LSB of the notification signal register 214, the data is simultaneously transferred from the data bus register 213 to the monitor data storage register 215. And monitor data is updated. As long as 1 is not written in the LSB of the notification signal register 214, the contents of the monitor data storage register 215 are not rewritten.

According to the semiconductor integrated circuit 1a of the second embodiment, the same effect as the semiconductor integrated circuit 1 of the first embodiment can be obtained.
According to the semiconductor integrated circuit 1a of the second embodiment, the monitor data transmission / reception protocol of each element is further standardized, and the monitor data receiving unit 210 is provided in each analog circuit 20 to provide a data bus (serial bus). Since data transfer is performed, data transmission / reception can be performed without increasing the number of buses even if the amount of monitor data increases. Therefore, for example, an empty channel of the signal wiring channel can be used for other purposes.

  As described above, the semiconductor integrated circuit of the present invention has been described based on the illustrated embodiment, but the present invention is not limited to this, and the configuration of each part is an arbitrary configuration having the same function. Can be replaced. Moreover, other arbitrary structures and processes may be added to the present invention.

Further, the present invention may be a combination of any two or more configurations (features) of the above-described embodiments.
(Additional remark 1) In the semiconductor integrated circuit which correct | amends the said analog circuit according to the change of the element characteristic of the several analog circuit used as control object,
A control unit that outputs digital monitor data for correcting the characteristics of a plurality of elements;
Multiple analog circuits,
A receiving unit that receives only the monitor data related to elements used in the analog circuit from the monitor data;
A characteristic correction unit that corrects the characteristic of the element of the analog circuit based on the received monitor data;
The control unit and the plurality of analog circuits are provided separately,
A semiconductor integrated circuit.

  (Supplementary Note 2) The control unit includes a temperature sensor unit that detects a temperature of the semiconductor integrated circuit, an element process sensor unit that measures manufacturing variations of the plurality of elements, data indicating manufacturing variations of the elements, The semiconductor integrated circuit according to appendix 1, further comprising a transmitter that transmits data indicating temperature as the monitor data.

  (Supplementary Note 3) The element process sensor unit includes a measurement control unit that outputs a measurement signal, and a plurality of element sensor units that measure manufacturing variation of the element based on the measurement signal. The semiconductor integrated circuit according to appendix 2.

  (Additional remark 4) The said element sensor part converts the signal transmission speed of the said element in a predetermined period into a count value, and outputs the said count value as data which shows the manufacture dispersion | variation in the said element. Semiconductor integrated circuit.

(Additional remark 5) The said measurement control part outputs the said signal for a measurement according to the temperature change detected by the said temperature sensor part, The semiconductor integrated circuit of Additional remark 3 characterized by the above-mentioned.
(Supplementary Note 6) The analog circuit includes a plurality of elements that switch the output value of the analog circuit in stages,
The characteristic correction unit is configured to determine a switching element among the plurality of elements based on a digital value included in the monitor data, and to determine a substantial part of the plurality of elements based on the determination of the switching determination unit. 2. The semiconductor integrated circuit according to appendix 1, further comprising an element switching unit that switches between various conductive states.

(Supplementary Note 7) The switching determination unit includes a plurality of tables in which a relationship between a digital value included in the monitor data and a switching element is changed according to a value of data indicating a temperature included in the monitor data.
The switching determination unit selects the table to be used according to the value of the data indicating the temperature included in the monitor data, and performs the determination based on the selected table and the digital value included in the monitor data. The semiconductor integrated circuit according to appendix 6, wherein:

  (Supplementary Note 8) Each of the plurality of analog circuits is connected in a loop with a notification signal line for a data completion notification signal and one data bus, and the control unit transmits the monitor data together with the data completion notification signal via the data bus. Serial data is transmitted to the adjacent analog circuit buffer bit by bit, and each analog circuit collectively receives the monitor data stored in the buffer when receiving the data completion notification signal. The semiconductor integrated circuit according to appendix 1.

It is a top view which shows the semiconductor integrated circuit of embodiment. It is a figure which shows the structure of a control part. It is a figure which shows an example of a structure of a temperature sensor part. It is a figure which shows operation | movement of a temperature sensor part. It is a figure which shows the output value of a temperature signal. It is a figure which shows each structure of a transistor sensor part, a resistance sensor part, and a capacity | capacitance sensor part. It is a figure which shows the structure of a monitor data transmission synchronization part. It is a figure which shows the operation waveform of the control part in the case of detecting the manufacture dispersion | variation in the element in the factor which does not change with time. It is a figure which shows the operation | movement waveform of the control part in the case of detecting the manufacture dispersion | variation in the element in the factor which changes with time. It is a figure which shows the detail of a communication line. It is a figure which shows the structure of a monitor data receiving part. It is a timing chart which shows the transmission / reception operation | movement of monitor data. It is a circuit diagram which shows a D / A converter. It is a figure which shows the relationship between each element used as the switching object of a switching determination part and an element switching part. It is a figure which shows a conversion table. It is a figure which shows the conversion table in another temperature range. It is a figure which shows the circuit structure of an active filter. It is a figure which shows the detail of the element switching part of an active filter. It is a figure which shows the connection of each analog circuit and control part of the semiconductor integrated circuit of 2nd Embodiment. It is a figure which shows the circuit structure of the monitor data transmission synchronization part of 2nd Embodiment. It is a figure which shows the circuit structure of the monitor data receiving part of 2nd Embodiment. It is a figure which shows the monitor data transmission operation | movement of a process and temperature sensor part. It is a figure which shows the monitor data transmission operation | movement of a process and temperature sensor part. It is a figure which shows operation | movement of a monitor data receiving part. It is a figure which shows operation | movement of a monitor data receiving part. It is a figure which shows an example of the conventional LSI. It is a figure which shows the conventional D / A converter. It is a figure which shows the conventional active filter.

Explanation of symbols

1, 1a Semiconductor integrated circuit 2, 20 Analog circuit 2a D / A converter 2b Active filter 3, 30 Control unit 4, 40 Communication line 21, 210 Monitor data receiving unit 21a Tr data receiving unit 21b, 21d Temperature data receiving unit 21c , 21e Resistance data reception unit 21f Capacitance data reception unit 22 Switching determination unit 22a Tr element switching determination unit 22b, 22d Resistance element switching determination unit 22c Capacitance element switching determination unit 23 Element switching unit 23a, 23b Analog data output unit 31 Monitor data generation Unit 32 Monitor data transmission unit 33 Temperature sensor unit 33a BGR unit 33b Temperature determination unit 34 Element process sensor unit 34a Measurement control unit 34b Transistor / sensor unit 34c Resistance sensor unit 34d Capacitance sensor unit 35, 350 Monitor data transmission synchronization unit 41 Monitor data Transmission / reception wiring 42 Clock supply line 43 Data transmission signal supply line 44 Data bus 45 Notification signal line 51, 61, 71 NAND gate 52-55, 62-65, 72-75 Inverter 56, 66, 76 Counter 211, 351 Gated clock buffer 212, 352 Communication control unit 213, 354 Data bus register 214, 355 Notification signal register 215, 353 Monitor data storage register 215a, 353a Tr storage register 215b, 353b Res storage register 215c, 353c Cap storage register 215d 353d Temp storage register 231-237, 239, 240 Element switching unit 238, 238a, 238b, 238c Conversion table C71-C74, Ci1-Ci4 capacitor CMP1- MP3 comparators FF1 to FF4, FF11 to FF15 flip-flops OP1, OP2 operational amplifiers R1, R61 to R64 resistors R2 to R5 voltage dividing resistors R11, R21 default resistors R12 to R14 load resistors Sw1 to Sw13, Sw11 to Sw13, Sw21 to Sw23 switches Tr1 ~ Tr4 transistor

Claims (5)

In a semiconductor integrated circuit that corrects the analog circuit according to changes in element characteristics of a plurality of analog circuits to be controlled,
A control unit that outputs digital monitor data for correcting the characteristics of a plurality of elements;
Multiple analog circuits,
A receiving unit that receives only the monitor data related to elements used in the analog circuit from the monitor data;
A characteristic correction unit that corrects the characteristic of the element of the analog circuit based on the received monitor data;
The control unit and the plurality of analog circuits are provided separately,
A semiconductor integrated circuit.   The control unit includes a temperature sensor unit that detects a temperature of the semiconductor integrated circuit, an element process sensor unit that measures manufacturing variations of the plurality of elements, data that indicates manufacturing variations of the elements, and data that indicates the temperature. 2. The semiconductor integrated circuit according to claim 1, further comprising: a transmitter that transmits the data as the monitor data.   The element process sensor unit includes a measurement control unit that outputs a measurement signal, and a plurality of element sensor units that measure manufacturing variations of the element based on the measurement signal. 3. The semiconductor integrated circuit according to 2. The analog circuit has a plurality of elements that switch the output value of the analog circuit in stages,
The characteristic correction unit is configured to determine a switching element among the plurality of elements based on a digital value included in the monitor data, and to determine a substantial part of the plurality of elements based on the determination of the switching determination unit. The semiconductor integrated circuit according to claim 1, further comprising an element switching unit that switches between various conductive states.   The plurality of analog circuits are respectively connected in a loop by a notification signal line for a data completion notification signal and one data bus, and the control unit sends the monitor data together with the data completion notification signal bit by bit through the data bus. 2. The serial data is transmitted to a buffer of the adjacent analog circuit, and each analog circuit collectively receives the monitor data stored in the buffer when receiving the data completion notification signal. The semiconductor integrated circuit as described.

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