CN111103522B - Chip and efficiency monitoring method - Google Patents

Chip and efficiency monitoring method Download PDF

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Publication number
CN111103522B
CN111103522B CN201811246223.0A CN201811246223A CN111103522B CN 111103522 B CN111103522 B CN 111103522B CN 201811246223 A CN201811246223 A CN 201811246223A CN 111103522 B CN111103522 B CN 111103522B
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chip
oscillator
oscillator circuit
oscillation signals
oscillation
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CN111103522A (en
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汪鼎豪
林倍如
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
Global Unichip Corp
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
Global Unichip Corp
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    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/2851—Testing of integrated circuits [IC]

Abstract

A chip and a performance monitoring method. The chip includes at least an oscillator circuitry and a controller circuitry. At least one oscillator circuit system is arranged at different positions in the chip and respectively generates a plurality of oscillation signals. The controller circuit system transmits the oscillation signals to an external system so as to determine the performance of the chip according to the oscillation signals. Each of the at least one oscillator circuitry includes a first oscillator circuit and a second oscillator circuit. The first oscillator circuit senses variations of the semiconductor device within the chip to generate a first one of the oscillation signals. The second oscillator circuit senses a variation of a parasitic element in the chip to generate a second oscillation signal of the oscillation signals. The chip of the scheme can determine the efficiency according to the frequency of a plurality of oscillation signals generated in the chip, wherein the oscillation signals are set to reflect a plurality of variation factors (devices, resistance values, voltages and the like) so as to estimate the efficiency of the chip more accurately.

Description

Chip and efficiency monitoring method
Technical Field
The present disclosure relates to a chip (chip) and a performance monitoring method, and more particularly, to a chip and a performance monitoring method suitable for use in a chip with a built-in test circuit.
Background
Integrated circuits are widely used in electronic devices, wherein the performance of the integrated circuits often determines the overall performance of the electronic device. In some related techniques, the performance of an integrated circuit may be determined by estimating a critical path. However, due to variations introduced by actual operating conditions or processes, the actual critical path cannot be accurately determined.
Disclosure of Invention
In order to solve the above problems, some aspects of the present disclosure provide a chip including at least an oscillator circuit system and a controller circuit system. At least one oscillator circuit system is arranged at different positions in the chip and is used for respectively generating a plurality of oscillation signals. The controller circuitry is coupled to the at least one oscillator circuitry and configured to receive the plurality of oscillator signals and transmit the plurality of oscillator signals to an external system to determine a performance of the chip based on the plurality of oscillator signals. Wherein each of the at least one oscillator circuitry comprises a first oscillator circuit and a second oscillator circuit. The first oscillator circuit is used for sensing a semiconductor device variation in the chip to generate a first oscillation signal in the oscillation signals. The second oscillator circuit is used for sensing a parasitic element variation in the chip to generate a second oscillation signal in the oscillation signals.
In other aspects, a performance monitoring method is provided, which includes the following operations: generating a plurality of oscillation signals through at least one oscillator circuit system in the chip respectively, wherein the at least one oscillator circuit system is arranged at different positions in the chip; and transmitting the plurality of oscillation signals to an external system to determine a performance of the chip according to the plurality of oscillation signals, wherein the at least one oscillator circuitry each comprises a first oscillator circuit and a second oscillator circuit, and generating the plurality of oscillation signals comprises: sensing, by the first oscillator circuit, a semiconductor device variation within the chip to generate a first oscillation signal of the plurality of oscillation signals; and sensing a parasitic element variation in the chip by the second oscillator circuit to generate a second oscillation signal of the oscillation signals.
In some embodiments, the at least one oscillator circuitry includes a first oscillator circuitry disposed at a predetermined location in the chip.
In some embodiments, the chip includes an input/output terminal for receiving a supply voltage, and the predetermined position is a position in the chip adjacent to the input/output terminal.
In some embodiments, each of the at least one oscillator circuitry further comprises a third oscillator circuit. The third oscillator circuit is configured to sense a voltage variation within the chip to generate a third oscillation signal of the at least one oscillation signal, wherein the third oscillation signal output from the first oscillator circuit system is a reference signal for evaluating the voltage variation.
In some embodiments, the plurality of interconnects of the second oscillator circuit are implemented with different metal layers.
In some embodiments, the frequency of the first oscillating signal, the frequency of the second oscillating signal and the frequency of the third oscillating signal show different variation trends.
In summary, the chip and the monitoring method provided by the present disclosure can determine the performance according to the frequencies of the plurality of oscillation signals generated in the chip, wherein the plurality of oscillation signals are configured to reflect various variation factors (devices, resistances, voltages, etc.) so as to more accurately estimate the performance of the chip.
Drawings
In order to make the aforementioned and other objects, features, advantages and embodiments of the present invention comprehensible, the following description is given:
fig. 1 is a schematic diagram of a chip according to some embodiments of the disclosure;
fig. 2 is a schematic diagram of the oscillator circuitry of fig. 1 according to some embodiments of the disclosure;
fig. 3 is a flow chart of a performance monitoring method according to some embodiments of the disclosure; and
fig. 4 is a schematic diagram illustrating the frequencies of a plurality of oscillating signals as shown in fig. 2 versus a supply voltage according to some embodiments of the disclosure.
Detailed Description
All terms used herein have their ordinary meaning. The definitions of the above-mentioned words in commonly used dictionaries, any use of the words discussed herein in the context of this specification is by way of example only and should not be construed as limiting the scope or meaning of the present disclosure. Likewise, the present disclosure is not limited to the various embodiments shown in this specification.
It will be understood that the terms first, second, third, etc. may be used herein to describe various elements, components, regions, layers and/or sections. These elements, components, regions, layers and/or regions should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present disclosure. As used herein, "and/or" includes any and all combinations of one or more of the associated items.
As used herein, the term "couple" or "connect" refers to two or more elements being in direct physical or electrical contact with each other, or in indirect physical or electrical contact with each other, or to the mutual operation or action of two or more elements.
As used herein, the term "circuit system" generally refers to a single system comprising one or more circuits (circuits). The term "circuit" broadly refers to an object connected in some manner by one or more transistors and/or one or more active and passive components to process a signal.
Referring to fig. 1, fig. 1 is a schematic diagram illustrating a chip 100 according to some embodiments of the disclosure. In some embodiments, there may be one or more integrated circuits within chip 100.
Chip 100 includes a plurality of oscillator circuitry 120 and controller circuitry 140. A plurality of oscillator circuitry 120 is disposed at different locations on chip 100. Each oscillator circuit system 120 generates a plurality of oscillation signals SO with different frequencies based on process, voltage, and temperature variations corresponding to different locations in the chip 100. The controller circuitry 140 is coupled to the oscillator circuitry 120 to receive the oscillation signals SO.
The number of oscillator circuitry 120 is provided for purposes of example and is not intended to be limiting. In various embodiments, chip 100 may include any number (e.g., one or more) of oscillator circuitry 120.
In some embodiments, each of the oscillation signals SO shown in fig. 1 may be a combination (or set) of a plurality of oscillation signals (e.g., the signals SO1, SO2, and SO3 of fig. 2, which are described later).
In some embodiments, the controller circuitry 140 may determine the performance of the chip 100 according to a plurality of oscillation signals SO. Alternatively, in some embodiments, the controller circuitry 140 may transmit the oscillation signals SO to the external system 100A according to a command sent by the external system 100A (e.g., a tester, a computer, etc.). Thus, the external system 100A may perform calculations based on the oscillation signals SO to determine a performance of the chip 100.
In some embodiments, the controller circuitry 140 may be implemented by a processing circuit and/or a signal transmission interface circuit to determine the performance of the chip 100 and/or to transmit the oscillation signals SO to the external system 100A.
In some embodiments, the oscillator circuitry 120R is disposed adjacent to an input/output (I/O) terminal 101 of the chip 100, and is configured to receive a supply voltage VDD, wherein the supply voltage VDD is used for driving the chip 100. In some embodiments, since the oscillator circuit 120R is disposed at a known predetermined position (e.g., the vicinity of the input/output terminal 101), the oscillating signal SOR generated by the oscillator circuit 120R can be used as the reference signal. The known predetermined positions are exemplified by adjacent positions of the input/output terminal 101, but the disclosure is not limited thereto.
In addition, for ease of understanding, in fig. 1, the supply voltage VDD is only shown as being transmitted to the oscillator circuitry 120R. However, in some embodiments, the supply voltage VDD is delivered to all of the oscillator circuitry 120 and/or other circuits (not shown) in the chip 100 to drive these circuit elements.
Referring to fig. 2, fig. 2 is a schematic diagram of the oscillator circuitry 120 of fig. 1 according to some embodiments of the disclosure. In some embodiments, the oscillator circuitry 120 includes a plurality of oscillator circuits 120A and 120B.
In some embodiments, the oscillator circuit 120A is configured to sense at least one semiconductor device variation within the chip 100. For example, oscillator circuit 120A includes ring oscillators A1-A3, ring oscillators B1-B3, and ring oscillators C1-C3. In some embodiments, each of the ring oscillators A1-A3, B1-B3, and C1-C3 may be formed by a plurality of inverters INV connected in series, wherein the inverters INV may be implemented by a P-type transistor MP and an N-type transistor MN connected in series. In this example, the threshold voltages of the P-type transistors MP in the ring oscillators A1-A3 are different from each other. For example, the P-type transistor MP in the ring oscillator a1 is set to have a low threshold voltage, the P-type transistor MP in the ring oscillator a2 is set to have a standard threshold voltage, and the P-type transistor MP in the ring oscillator a2 is set to have a high threshold voltage.
Similarly, in this example, the threshold voltages of the N-type transistors MN in the ring oscillators B1-B3 are different from each other. For example, the N-type transistor MN in the ring oscillator B1 is set to have a low threshold voltage, the N-type transistor MN in the ring oscillator B2 is set to have a standard threshold voltage, and the N-type transistor MN in the ring oscillator B3 is set to have a high threshold voltage.
Further, in this example, the threshold voltages of the P-type transistor MP and the N-type transistor MN in the ring oscillators C1-C3 are different from each other. For example, the P-type transistor MP and the N-type transistor MN in the ring oscillator C1 are both configured to have a low threshold voltage, the P-type transistor MP and the N-type transistor MN in the ring oscillator C2 are both configured to have a standard threshold voltage, and the P-type transistor MP and the N-type transistor MN in the ring oscillator C3 are both configured to have a high threshold voltage.
With this arrangement, the oscillator circuit 120A may be more sensitive to device variations. The oscillator circuit 120A may generate a plurality of oscillation signals SO1 based on transistors having different threshold voltages. Thus, the frequency of the oscillation signals SO1 can be used to reflect the effect of device variations on the chip 100.
The above arrangement of the oscillator circuit 120A is for example, and the present disclosure is not limited thereto. Various configurations for detecting device variations are within the scope of the present disclosure.
In some embodiments, the oscillator circuit 120B is configured to detect at least one parasitic element variation within the chip 100. In some embodiments, the at least one parasitic element may include a parasitic capacitance and/or a parasitic resistance caused by an actual conductive line. For example, the oscillator circuit 120B includes ring oscillators D1-D6. The interconnect WR of the oscillators D1-D6 (e.g., the interconnect between the serially connected inverters INV) is implemented by different metal layers. For example, the interconnect WR of the ring oscillator D1 is implemented by the first metal layer M1. The interconnect WR of the ring oscillator D2 is implemented by the second metal layer M2. By analogy, the oscillator circuit 120B may be sensitive to variations of parasitic elements (e.g., parasitic resistance or parasitic capacitance variations caused by metal traces). The oscillator circuit 120B may generate a plurality of oscillation signals SO2 based on different metal layers. Thus, the frequencies of the oscillation signals SO2 can be used to reflect the influence of parasitic element variations on the chip 100.
The above arrangement of the oscillator circuit 120B is for example, and the present disclosure is not limited thereto. Various configurations for detecting parasitic element variations are contemplated.
In some embodiments, oscillator circuitry 120 may only provide oscillator circuits 120A and 120B. In some further embodiments, in order to more accurately determine the performance of the chip 100, the oscillator circuitry 120 may further comprise an oscillator circuit 120C. The oscillator circuit 120C is configured to detect at least one voltage variation within the chip 100. For example, oscillator circuit 120C includes a ring oscillator E1. In some embodiments, the output terminals of the cascaded inverters (not shown) in the oscillator E1 are respectively coupled to a voltage-controlled device 200. In other words, the voltage control device 200 can be regarded as a load of the inverter. In this example, the supply voltage VDD can be used to drive inverters in the ring oscillator E1 and to set voltage controlled elements. For example, the voltage-controlled element 200 can be a voltage-controlled capacitor, and the capacitance thereof can be determined according to the received supply voltage VDD. With this arrangement, the oscillator circuit 120C can generate the oscillation signal SO3 with different frequencies based on the variation of the received supply voltage VDD. Thus, the frequency of the oscillating signal SO3 can be used to reflect the effect of voltage variation on the chip 100.
The above arrangement of the oscillator circuit 120C is for example, and the present disclosure is not limited thereto. In addition, the above oscillator circuits are only illustrated as ring oscillators, and other arrangements for detecting voltage variations are all within the scope of the present disclosure.
In addition, as mentioned above, the oscillating signal SOR outputted from the oscillator circuit system 120R can be used as a reference signal. For example, since the oscillator circuit system 120R is adjacent to the input/output terminal 101, the received supply voltage VDD has relatively low variation. Under this condition, the oscillation signal SO3 output by the oscillator circuit 120C in the oscillator circuitry 120R can be regarded as a reference signal. In some embodiments, the reference signal may be compared with the oscillation signal SO3 output by other oscillator circuitry 120 to evaluate the effect of voltage variations on the chip 100.
Referring to fig. 3, fig. 3 is a flow chart illustrating a performance monitoring method 300 according to some embodiments of the disclosure. In some embodiments, the performance monitoring method 300 may be used to determine the performance of the chip 100 of fig. 1. For ease of explanation, reference is also made to fig. 1-2.
In operation S310, a plurality of oscillator circuits 120 are disposed in the chip 100 to generate a plurality of oscillation signals SO.
For example, as shown in fig. 1, a plurality of oscillator circuitry 120 is disposed within chip 100. When the chip 100 is powered on (e.g., receives the supply voltage VDD), the oscillator circuits 120 are activated and generate different oscillating signals SO according to the operating conditions (i.e., process, voltage, and/or temperature conditions) associated with their respective locations. As shown in fig. 2, the oscillator circuits 120A, 120B, and 120C in each oscillator circuit system 120 respectively generate a plurality of oscillation signals SO1, SO2, and SO3 according to different settings. In other words, each of the oscillation signals SO represents a plurality of oscillation signals SO1, SO2 and SO3 corresponding to different settings.
In operation S320, the controller circuitry 140 collects a plurality of oscillation signals SO and transmits them to the external system 100A.
In operation S330, the external system 100A performs an operation according to the oscillation signals SO to determine the performance of the chip 100.
For example, as shown in FIG. 1, the external system 100A receives a plurality of oscillation signals SO 1-SO 3 via the controller circuitry 140. During the measurement process, the supply voltage VDD is decreased from an initial value. In response to the drop of the supply voltage VDD, the frequencies of the plurality of oscillation signals SO1, SO2, and SO3 generated by the respective oscillator circuitry 120 start to decrease. When the supply voltage VDD is low enough to disable the operation of the chip 100 (or its performance is lower than a target value), the external system 100A records the frequencies of the received oscillation signals SO1, SO2 and SO 3.
Then, the external system 100A determines the performance of the chip 100 according to a performance function and the frequencies of the collected oscillation signals SO1, SO2, and SO 3. In some embodiments, the performance function may be expressed as follows:
T＝funcT(func1(K1×f1),func2(K2×f2),func3(K3×f3))
where T is the efficiency of chip 100 and K1、K2、K3Is a weight coefficient, f1、f2、f3The frequencies, func, of the oscillation signals SO1, SO2 and SO3, respectively1For processing frequency f1Subfunction of (1), func2For processing frequency f2A subfunction of (1), and func3For processing frequency f3A subfunction of (1), and funcTIs a performance function for processing the results of the sub-functions.
In some embodiments, the subfunction func1、func2And func3May be a weight summing (weighting) function. In some embodiments, the performance function funcTMay be a weight summing function. In some embodiments, if the oscillating signal SO3 generated by the oscillator circuitry 120R disposed at a known location is used as the reference signal, the sub-function func3The operation of the deviation function may be further added. Under this condition, the reference signal can be regarded as a standard value (or can be regarded as an average value) in the deviation function, so as to further cover the deviation of each position in the chip 100 caused by the voltage variation to estimate the performance T of the chip 100. In some embodiments, the deviation function may be an average difference function, a standard deviation function, or the like.
In some embodiments, during the initial test, the external system 100A may calculate the weight coefficient K when collecting a certain amount of frequencies of the oscillation signals SO1, SO2, and SO31、K2And K3The value of (c). For example, after collecting the frequencies of the oscillation signals SO1, SO2, and SO3 corresponding to the plurality of chips 100, the external system 100 may perform interpolation or polynomial regression according to the performance T of the plurality of chips 100 to estimate the plurality of weight coefficients K1、K2And K3The value of (c). In further embodiments, the external system 100A may perform the above operations through machine learning or the like. After solving a plurality of weight coefficients K1、K2And K3The external system 100A may then determine the performance of the chip 100 directly according to the performance function and the frequencies of the collected oscillation signals SO1, SO2, and SO 3.
For easy understanding, the oscillation signals SO1, SO2 and SO3 are used for illustration, but the disclosure is not limited thereto. As previously described, in some embodiments, oscillator circuitry 120 may only provide oscillator circuits 120B and 120C. In some embodiments, the oscillator circuitry 120 may further include an oscillator circuit 120C to more accurately estimate the performance of the chip 100 based on voltage variations across a location in the chip 100.
The above arrangement of the functions is used for example, but the present disclosure is not limited thereto. Various functions or operations that may be used to determine the chip 100 are within the scope of the present disclosure.
Referring to fig. 4, fig. 4 is a schematic diagram illustrating a relationship between frequencies of the oscillation signals SO1, SO2 and SO3 of fig. 2 and the supply voltage VDD according to some embodiments of the disclosure.
As shown in fig. 4, the plurality of curves 401 corresponds to the simulation result of the oscillating signal SO1, the curve 402 corresponds to the simulation result of the oscillating signal SO2, and the curve 403 corresponds to the simulation result of the oscillating signal SO 3. As mentioned above, the frequency of the oscillating signal SO1 may reflect device variations, the frequency of the oscillating signal SO2 may reflect parasitic element variations, and the frequency of the oscillating signal SO3 may reflect voltage variations. As can be seen from fig. 4, the curves 402 and 403 both show different trend (e.g., different slope change in the frequency versus voltage relationship) compared to the curve 401. Therefore, in some embodiments additionally using the oscillator circuit 120C, the external system 100A may further correct the performance of the chip 100 according to the voltage variation to estimate a more accurate real performance.
In some related art, a plurality of ring oscillators or counters are placed only within a chip, wherein the ring oscillators or counters are used to reflect device variations. In these techniques, as shown in fig. 4, when the performance of the chip is calculated, the variation factors with different variation trends are not considered, so the determined performance of the chip is not accurate. In contrast to these techniques, the embodiments of the present disclosure may determine the actual performance of the chip 100 more accurately by comprehensively considering various factors such as device variation, parasitic element variation, voltage variation, and the like.
In summary, the chip and the monitoring method provided by the present disclosure can determine the performance according to the frequencies of the plurality of oscillation signals generated in the chip, wherein the plurality of oscillation signals are configured to reflect various variation factors (devices, resistances, voltages, etc.) so as to more accurately estimate the performance of the chip.
Although the present disclosure has been described with reference to particular embodiments, it will be understood by those skilled in the art that various changes and modifications may be made without departing from the spirit and scope of the disclosure, and therefore, the scope of the disclosure is to be determined by the appended claims.

Claims (8)

1. A chip, comprising:
at least one oscillator circuit system arranged at different positions in the chip and used for respectively generating a plurality of oscillation signals; and
a controller circuitry coupled to the at least one oscillator circuitry and configured to receive the plurality of oscillator signals and transmit the plurality of oscillator signals to an external system for determining a performance of the chip based on the plurality of oscillator signals,
wherein each of the at least one oscillator circuitry comprises:
a first oscillator circuit for sensing a semiconductor device variation in the chip to generate a first oscillation signal of the oscillation signals;
a second oscillator circuit for sensing a parasitic element variation in the chip to generate a second oscillation signal of the plurality of oscillation signals; and
a third oscillator circuit for sensing a supply voltage variation within the chip to generate a third oscillation signal of the plurality of oscillation signals;
the at least one oscillator circuit system comprises a first oscillator circuit system which is arranged at a preset position in the chip;
wherein the third oscillating signal output from the first oscillator circuitry is a reference signal used to evaluate the supply voltage variation.
2. The chip of claim 1, wherein the chip comprises an input/output for receiving a supply voltage, and the predetermined position is a position in the chip adjacent to the input/output.
3. The chip of claim 1, wherein the frequencies of the first oscillating signal, the second oscillating signal and the third oscillating signal show different variation trends.
4. The chip of claim 1, wherein the plurality of interconnects of the second oscillator circuit are implemented with different metal layers.
5. A method for performance monitoring, comprising:
generating a plurality of oscillation signals through at least one oscillator circuit system in a chip respectively, wherein the at least one oscillator circuit system is arranged at different positions in the chip; and
transmitting the oscillation signals to an external system to determine a performance of the chip according to the oscillation signals,
wherein each of the at least one oscillator circuitry comprises a first oscillator circuit, a second oscillator circuit, and a third oscillator circuit, and generating the plurality of oscillation signals comprises:
sensing, by the first oscillator circuit, a semiconductor device variation within the chip to generate a first oscillation signal of the plurality of oscillation signals;
sensing a parasitic element variation in the chip by the second oscillator circuit to generate a second oscillation signal of the plurality of oscillation signals; and
sensing a supply voltage variation in the chip by the third oscillator circuit to generate a third oscillation signal of the plurality of oscillation signals;
the at least one oscillator circuit system comprises a first oscillator circuit system which is arranged at a preset position in the chip;
wherein the third oscillating signal output from the first oscillator circuitry is a reference signal used to evaluate the supply voltage variation.
6. The performance monitoring method of claim 5, wherein the chip includes an input/output for receiving a voltage, and the predetermined location is a location of the chip adjacent to the input/output.
7. The performance monitoring method of claim 5, wherein the frequencies of the first oscillating signal, the second oscillating signal and the third oscillating signal show different variation trends.
8. The performance monitoring method of claim 5, wherein the plurality of interconnects of the second oscillator circuit are implemented with different metal layers.
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