JP2008011323A - Operating speed detection apparatus - Google Patents

Operating speed detection apparatus Download PDF

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Publication number
JP2008011323A
JP2008011323A JP2006181091A JP2006181091A JP2008011323A JP 2008011323 A JP2008011323 A JP 2008011323A JP 2006181091 A JP2006181091 A JP 2006181091A JP 2006181091 A JP2006181091 A JP 2006181091A JP 2008011323 A JP2008011323 A JP 2008011323A
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Japan
Prior art keywords
delay
unit
speed detection
operation speed
detection device
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JP2006181091A
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Japanese (ja)
Inventor
Kimiaki Ando
公晃 安藤
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Matsushita Electric Ind Co Ltd
松下電器産業株式会社
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Priority to JP2006181091A priority Critical patent/JP2008011323A/en
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Abstract

<P>PROBLEM TO BE SOLVED: To provide an operating speed detection apparatus for setting an optimum parameter for an integrated circuit high in the latitude of design and high in integration degree. <P>SOLUTION: The operating speed detection apparatus detects the operating speed of the integrated circuit from the delay characteristic of the integrated circuit composed of digital logic circuits. The operating speed detection apparatus includes a plurality of delay parts constituted of digital logic circuits to delay an input clock and an operation part for executing statistical operation processing by using data obtained from respective delay parts. The plurality of delay parts are dispersedly arranged in the integrated circuit. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to an operation speed detection apparatus for setting optimum parameters for an integrated circuit having a high degree of design freedom and a high degree of integration.

  Devices that require low power consumption, such as mobile phones, control power supply voltage and operating frequency in order to achieve efficient, high-speed, and low-power processing of large-scale integrated circuits (LSIs). To do. Parameters for controlling the power supply voltage and the operating frequency are the operation limit speed, processing amount, leakage current, and the like of the LSI. For this reason, a conventional device includes a monitor circuit that detects an operation limit speed and a leakage current inside the LSI, and controls a power supply voltage, a threshold voltage, and an operation frequency according to the detection result. A large number of transistors are integrated in an LSI, and there are variations in characteristics within the device. For this reason, the device determines a power supply voltage and an operating frequency at which all transistors can perform a prescribed operation.

  There are two types of monitor circuits described above: analog detection circuits and digital detection circuits. The monitor circuit that detects in analog detects the drain-source current, the gate-drain current, and the substrate current of the reference transistor having characteristics close to those of the transistors that constitute the LSI. Also, the monitor circuit that detects digitally detects the propagation delay amount of the reference critical path.

  FIG. 9 is a block diagram showing an apparatus for controlling a threshold voltage and a power supply voltage using an analog detection monitor circuit. The monitor circuit 11 detects the saturation current value of the reference transistor 13. The threshold control circuit 15 controls the threshold voltage of the transistors in the LSI according to the detection result of the monitor circuit 11. The power supply voltage control circuit 17 controls the power supply voltage according to the detection result of the monitor circuit 11.

JP 2004-20325 A

  When the monitor circuit 11 described with reference to FIG. 9 is composed of analog elements, it is necessary to provide a specific area for arranging the monitor circuit 11 inside the LSI. Providing such a specific area in the LSI is a factor that reduces the degree of freedom in design and integration of the LSI. The detection result output from the monitor circuit 11 is an analog signal, and the LSI needs to process the analog signal. This complicates the LSI configuration.

  Further, although the characteristics of the transistors in the LSI vary, it is unclear which transistor the reference transistor 13 is close to. For this reason, it is necessary to determine the power supply voltage, the threshold voltage, and the operating frequency from the detection result of the monitor circuit 11 and the variation prediction range with a margin in which all the transistors can operate. For this reason, the power supply voltage, threshold voltage, and operating frequency of optimum values may not be set. Even when a digitally detected monitor circuit is used, there is a problem similar to the above because only representative characteristics in the LSI are detected.

  SUMMARY OF THE INVENTION An object of the present invention is to provide an operating speed detection device capable of increasing the degree of design freedom and integration of an integrated circuit and setting optimum parameters.

  The present invention relates to an operation speed detection device for detecting an operation speed of an integrated circuit from delay characteristics of the integrated circuit configured by the digital logic circuit, and includes a plurality of delay circuits configured by the digital logic circuit to delay an input clock. A delay unit; and a calculation unit that performs statistical calculation processing using data obtained from each of the plurality of delay units, wherein the plurality of delay units are distributed in the integrated circuit. An operating speed detecting device is provided.

  In the operation speed detection device, the calculation unit includes a counting unit that counts the number of occurrences of setup errors based on data obtained from the plurality of delay units, and the number of occurrences of setup errors counted by the counting unit. A comparison unit that compares the threshold value.

  In the operation speed detection device, the threshold value is variable.

  In the operation speed detection device, each of the plurality of delay units includes a shift register.

  In the operation speed detection device, each of the plurality of delay units outputs multi-value data indicating how many stages of the shift register are shifted based on a signal obtained from each tap of the shift register. And a data processing unit.

  In the operation speed detection device, the calculation unit, based on data obtained from the plurality of delay units, a standard deviation calculation unit that calculates a standard deviation for calculating a standard deviation of a delay amount in each delay unit; Based on data obtained from the plurality of delay units, a center value calculation unit that calculates a median value indicating an average value, median value, or mode value of the delay amount in each delay unit, and the standard deviation calculation unit A comparator that compares the calculated standard deviation and the central value calculated by the central value calculator with a threshold value.

  In the operation speed detection device, each of the plurality of delay units includes a scan test circuit that detects speed of a critical path.

  According to the operation speed detection device of the present invention, since the delay unit arranged in the integrated circuit is configured by a digital logic circuit, the degree of freedom in design and integration of the integrated circuit can be increased. In addition, since the plurality of delay units are provided in a distributed manner in the integrated circuit, it is possible to determine an optimum parameter according to the manufacturing variation of the integrated circuit.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. An operation speed detection device described below detects an operation speed from the delay characteristics of the LSI in order to set an optimal operation frequency and power supply voltage of a large scale integrated circuit (LSI) constituted by digital logic circuits.

(First embodiment)
FIG. 1 is a block diagram illustrating a configuration of an operation speed detection device according to the first embodiment. As illustrated in FIG. 1, the operation speed detection apparatus 100 according to the first embodiment includes a control unit 101, a measurement clock generation unit 103, a plurality of delay units 105, and a calculation unit 107. The plurality of delay units 105 are distributed and arranged in an LSI (not shown). By arranging a plurality of delay units, it is possible to compensate for variations in the delay units themselves, and to perform control according to LSI variations regarding delay characteristics. In addition, since a plurality of delay units are arranged, it is possible to detect LSI variations regarding delay characteristics with multiple values.

  The control unit 101 controls the delay unit 105 and the calculation unit 107. The measurement clock generator 103 supplies the measurement clock to each of the delay units 105 according to the reference clock.

  The delay unit 105 is constituted by a digital logic circuit, and is a shift register in which a buffer for generating a delay is arranged between registers as shown in FIG. The delay unit 105 receives the measurement clock supplied from the measurement clock generation unit 103. The number of stages in which a setup error occurs is input to a buffer arranged between the registers when a clock having a predetermined frequency is input under a certain voltage / temperature condition. The voltage / temperature conditions and the predetermined frequency are set on the basis of switching conditions of the operating frequency of the LSI, a clock that is always supplied when the power is turned on, and the like.

  The first stage logic of the shift register is shifted by the clock supplied from the measurement clock generator 103. Depending on whether an H level signal is output from the output when the predetermined number of clocks is reached, it is determined whether the predetermined maximum operating frequency and minimum operating voltage criteria are satisfied. By configuring the shift registers in a plurality of stages, the arithmetic unit 107 can perform delay detection by integrating the dispersion of delay values between the shift registers.

  The arithmetic unit 107 performs statistical arithmetic processing using the data input from each of the plurality of delay units 105, and outputs a comparison result based on the number of occurrences of LSI setup errors. The maximum operating frequency and minimum operating voltage of the LSI are determined based on information output from the arithmetic unit 107. FIG. 3 is a block diagram illustrating an internal configuration of the calculation unit 107 of the present embodiment. As illustrated in FIG. 3, the calculation unit 107 includes a counting unit 151, a threshold storage unit 153, and a comparison unit 155. The counting unit 151 counts the number of setup errors generated based on the signal input from the delay unit 105. The setup error is a parameter serving as a reference similar to the saturation current value of the transistor. The threshold storage unit 153 stores a threshold regarding the number of setup errors. The comparison unit 155 compares the threshold value stored in the threshold value storage unit 153 with the number of occurrences of setup errors counted by the counting unit 151. The comparison unit 155 outputs information indicating the magnitude relationship between the number of setup errors generated from a plurality of data and the threshold value.

  Information output from the arithmetic unit 107 is input to the operating frequency determining unit 171 and the operating voltage determining unit 173 shown in FIG. The operating frequency determination unit 171 controls the clock generation unit 175 according to the input information. The clock generated from the clock generator 175 is supplied to the LSI. The operating voltage determination unit 173 controls the power supply unit 177 according to the input information. The operating voltage determination unit 173 may control the substrate voltage for the purpose of suppressing leakage current and controlling the operating frequency by controlling the threshold voltage in addition to the power supply voltage. The power supply unit 177 may be provided inside or outside of the LSI chip.

  Since the threshold value stored in the threshold value storage unit 153 is a value determined by LSI design and evaluation, it is desirable that the threshold value can be switched after the LSI is manufactured. In addition, in order to perform multi-stage control, a plurality of threshold values may exist.

  The distribution of delay between the shift registers of the delay unit in the present embodiment will be described with reference to FIG. In the present embodiment, in order to increase the number change of the number of setup errors and improve the accuracy of speed determination, it is desirable to set the setup allowable value of the delay unit as close to the center of the distribution as possible. The delay unit is manufactured by cell-based design, which is a standard LSI design method. For this reason, as shown in FIG. 4, the design value varies within a certain range. On the other hand, in a normally used circuit other than the delay unit, the voltage, temperature, and frequency conditions, which are the determination conditions of the delay unit, are different from the normal operation conditions, so a certain delay margin value (which may be negative) have. The setup limit value 275 is a constant ratio with the setup limit value 273 of the delay unit. A setup error number 272 is defined for a standard individual, and the LSI performance can be determined based on whether the number of setups in the delay unit is larger or smaller.

Next, a specific calculation process will be described. When a clock having a predetermined frequency is input to a circuit randomly laid out in a standard cell-based design, the delay performance between the shift registers of the delay unit shows a distribution as indicated by the frequency 270. In addition, the frequency 271 in FIG. 4 is a cumulative frequency. “Performance” in this case refers to the design performance. If the delay value of the critical path of some shift registers exceeds the setup limit Tdw274 for the voltage / temperature / frequency with a delay part as a design value for a specified input frequency in the frequency distribution, a setup error occurs. This number of errors is set to Eds272. On the other hand, there is a setup limit Tnw 275 in the voltage, temperature, and frequency used for detection by the delay unit of the normally used circuit. It is equal to the delay value of the critical path at the maximum operating frequency of a normal circuit. Tnw and Tdw do not match because the delay unit and other normally used circuits may operate under different clock and voltage conditions. Eps273 is the number (allowable value) at which a setup error may occur in the delay unit for delaying the normally used circuit within Tnw. There is a correlation between Eds and Eps depending on voltage and temperature. When Eds fluctuates due to actual manufacturing variations, it is indirectly determined by measuring the value of Eds whether voltage / temperature conditions, etc. are satisfied with respect to Tnw, and how much room is available. Can do. Since the correlation between Eds and Eps can be expressed by a certain function, when the maximum processing capacity is to be operated at the lowest operating voltage, control should be performed so that the value of Eds is constant, and the maximum processing capacity is not required. The allowable Eps s for the calculated Tnw can be calculated. When there is a proportional relationship between Tdw and Tnw, an equation regarding Eps s is shown below. Tnw max is an allowable delay value at the maximum operating frequency, and Tnw min is an allowable delay value when the maximum processing capacity is not required.

By obtaining the measured value of the error number Eds for each setup limit Tdw, the correlation between the period and the allowable error number can be found. Therefore, it is possible to calculate a good number Eps s also happening up errors based on the value.

  As described above, according to the operation speed detection device 100 of the present embodiment, the delay circuit arranged in the LSI is configured by a digital logic circuit, and therefore, it is necessary to design a special analog circuit for the LSI. There is no. For this reason, the design freedom and integration degree of LSI can be increased. In addition, since a plurality of delay units are provided in a distributed manner in the LSI, it is possible to determine optimal parameters (maximum operating frequency, minimum power supply voltage, etc.) according to manufacturing variations of the LSI.

(Second Embodiment)
The operating speed detection device of the second embodiment is different from the operating speed detection device of the first embodiment in the internal configuration of the delay unit and the internal configuration of the calculation unit. Except for this point, the second embodiment is the same as the first embodiment. FIG. 5 is a block diagram showing the internal configuration of the delay unit of the present embodiment. FIG. 6 is a block diagram illustrating an internal configuration of the calculation unit of the present embodiment. FIG. 7 is a diagram illustrating a delay distribution between the shift registers of the delay unit in the present embodiment.

  As illustrated in FIG. 5, the delay unit 205 of the present embodiment includes a shift register in which a buffer and the like are arranged between registers, and a binary data conversion unit 231. This shift register is the same as the shift register constituting the delay unit 105 of the first embodiment. The binary data conversion unit 231 obtains a signal from each tap of the shift register, and outputs multi-value binary data indicating how many stages of the shift register are shifted.

  The calculation unit 207 of this embodiment performs statistical calculation processing using data input from each of the plurality of delay units 205, and outputs a comparison result based on the maximum delay value of the LSI. Information output from the calculation unit 207 indicates the highest operating frequency and the lowest operating voltage of the LSI. As shown in FIG. 6, the calculation unit 207 compares the standard deviation calculation unit 251, the average value calculation unit 253, the multiplication unit 255, the guarantee count storage unit 257, the addition unit 259, and the threshold storage unit 261. Part 263.

  The standard deviation calculation unit 251 calculates the standard deviation σ of the delay amount by each delay unit using the data input from the delay unit 205. The standard deviation σ indicating the variation in the delay amount is calculated by the following equation.

  The average value calculation unit 253 calculates an average value of delay amounts using data input from each of the plurality of delay units 205. If the distribution of delay amount is a normal distribution, the average value, median value, and mode value match, but the distribution may be skewed. Use them according to your needs. For this reason, the average value calculation unit 253 may calculate a median value or a mode value instead of the average value.

  The multiplication unit 255 multiplies the standard deviation σ calculated by the standard deviation calculation unit 251 by the guarantee count stored in the guarantee count storage unit 257. The adding unit 259 adds the average value calculated by the average value calculating unit 253 to the standard deviation (eg, 3σ) multiplied by the guarantee count, and outputs the maximum delay value. The comparison unit 263 compares the threshold value stored in the threshold value storage unit 261 with the maximum delay value. The comparison unit 263 outputs information indicating the magnitude relationship between the maximum delay value and the threshold value. Note that calculating the standard deviation by hardware brings about circuit complexity, so it may be calculated by software using a CPU or the like.

  Since the number of delay units included in the operation speed detection device of the present embodiment described above is limited, it is not always possible to completely detect LSI variations. However, since the range of the deviation σ that can be detected based on the number of delay units is self-evident, the calculation unit 207 estimates the delay characteristics based on the deviation and the coefficient. For this reason, since the delay characteristics of an LSI that are close to actuality are predicted, the optimum power supply voltage and operating frequency can be determined.

(Third embodiment)
The difference between the operation speed detection device of the third embodiment and the operation speed detection device of the first embodiment is the internal configuration of the delay unit. Except for this point, the second embodiment is the same as the first embodiment. FIG. 8 is a block diagram showing the internal configuration of the delay unit of the present embodiment.

  As shown in FIG. 8, the delay unit 305 of this embodiment includes a shift register and a scan test circuit that is used as a standard in LSI. By setting the shift switching signal 331 to normal and inputting a clock to the normal path 333, data is transmitted to the input side register 335 via the critical path. The operating speed can be determined by determining whether the data is correctly transmitted. As described above, since the scan test circuit is used, a wide range of characteristics of the LSI chip can be measured, and since the normal path is used, the evaluation can be performed with a more practical circuit configuration.

  Based on the detection result obtained by the operation speed detection device of the embodiment described above, at the time of LSI shipping inspection, a fuse is cut in a trimming (correction) circuit inside the LSI, or correction information is stored in a nonvolatile memory or the like. By writing, an LSI in which the variation is corrected can be shipped. Further, by marking the LSI based on the detection result obtained by the operation speed detection device, the LSI can be shipped after sorting according to the operable speed of the LSI.

  The operation speed detection device according to the present invention is useful as an inspection device or the like for setting optimum parameters for an integrated circuit having a high degree of design freedom and integration.

The block diagram which shows the structure of the operating speed detection apparatus of 1st Embodiment. The block diagram which shows the internal structure of the delay part of 1st Embodiment. The block diagram which shows the internal structure of the calculating part of 1st Embodiment. The figure which shows distribution of the delay between the shift registers of the delay part in 1st Embodiment. The block diagram which shows the internal structure of the delay part of 2nd Embodiment. The block diagram which shows the internal structure of the calculating part of 2nd Embodiment. The figure which shows distribution of the delay between the shift registers of the delay part in 2nd Embodiment. The block diagram which shows the internal structure of the delay part of 3rd Embodiment. A block diagram showing an apparatus for controlling a threshold voltage and a power supply voltage using a monitor circuit that detects analogly

Explanation of symbols

101 Control Unit 103 Measurement Clock Generation Unit 105, 205 Delay Unit 107, 207 Operation Unit 171 Operation Frequency Determination Unit 173 Operation Voltage Determination Unit 151 Count Unit 153 Threshold Storage Unit 155 Comparison Unit 231 Binary Data Conversion Unit 251 Standard Deviation Calculation Unit 253 Average value calculation unit 255 Multiplication unit 257 Guaranteed count storage unit 259 Addition unit 261 Threshold storage unit 263 Comparison unit

Claims (7)

  1. An operation speed detection device for detecting an operation speed of an integrated circuit from delay characteristics of the integrated circuit constituted by a digital logic circuit,
    A plurality of delay units configured by a digital logic circuit and delaying an input clock; and
    An arithmetic unit that performs statistical arithmetic processing using data obtained from each of the plurality of delay units,
    The operating speed detecting device, wherein the plurality of delay units are distributed in the integrated circuit.
  2. The operation speed detection device according to claim 1,
    The computing unit is
    A counting unit for counting the number of occurrences of setup errors based on data obtained from the plurality of delay units;
    A comparison unit for comparing the number of occurrences of setup errors counted by the counting unit with a threshold;
    An operation speed detection device comprising:
  3. The operation speed detection device according to claim 2,
    The operating speed detecting device, wherein the threshold value is variable.
  4. The operation speed detection device according to claim 1,
    Each of the plurality of delay units includes a shift register.
  5. The operation speed detection device according to claim 4,
    Each of the plurality of delay units further includes a data processing unit that outputs multi-level data indicating how many stages of the shift register are shifted based on a signal obtained from each tap of the shift register. An operation speed detection device characterized by the above.
  6. The operation speed detection device according to claim 1,
    The computing unit is
    Based on data obtained from the plurality of delay units, a standard deviation calculation unit that calculates a standard deviation for calculating a standard deviation of a delay amount in each delay unit;
    Based on the data obtained from the plurality of delay units, a center value calculation unit that calculates a center value indicating an average value, median value, or mode value of the delay amount in each delay unit;
    A comparison unit that compares the standard deviation calculated by the standard deviation calculation unit and the central value calculated by the central value calculation unit with a threshold value;
    An operation speed detection device comprising:
  7. The operation speed detection device according to claim 1,
    Each of the plurality of delay units includes a scan test circuit for detecting a speed of a critical path.
JP2006181091A 2006-06-30 2006-06-30 Operating speed detection apparatus Pending JP2008011323A (en)

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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP2082679A2 (en) 2008-01-22 2009-07-29 Fujifilm Corporation Flexible endoscope
JP2012209420A (en) * 2011-03-30 2012-10-25 Hitachi Ltd Semiconductor integrated circuit device
JP2016531424A (en) * 2013-07-17 2016-10-06 エイアールエム リミテッド Integrated circuit manufacturing using direct lithography

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JPH1140749A (en) * 1997-07-18 1999-02-12 Nec Corp Reference voltage generation circuit
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JP2002073181A (en) * 2000-08-30 2002-03-12 Nec Commun Syst Ltd Operation guarantee voltage control system
JP2002217369A (en) * 2001-01-16 2002-08-02 Fuji Electric Co Ltd Reference voltage semiconductor device
JP2003022946A (en) * 2001-07-06 2003-01-24 Hitachi Ltd Method for producing semiconductor device
JP2003224771A (en) * 2002-01-29 2003-08-08 Fuji Photo Film Co Ltd Image processing method, image processing apparatus and electronic camera
JP2004177375A (en) * 2002-11-29 2004-06-24 Ishida Co Ltd Combinational measuring device
JP2005166698A (en) * 2003-11-28 2005-06-23 Matsushita Electric Ind Co Ltd Semiconductor integrated circuit

Patent Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH1140749A (en) * 1997-07-18 1999-02-12 Nec Corp Reference voltage generation circuit
JP2001156261A (en) * 1999-09-13 2001-06-08 Hitachi Ltd Semiconductor integrated-circuit device
JP2002073181A (en) * 2000-08-30 2002-03-12 Nec Commun Syst Ltd Operation guarantee voltage control system
JP2002217369A (en) * 2001-01-16 2002-08-02 Fuji Electric Co Ltd Reference voltage semiconductor device
JP2003022946A (en) * 2001-07-06 2003-01-24 Hitachi Ltd Method for producing semiconductor device
JP2003224771A (en) * 2002-01-29 2003-08-08 Fuji Photo Film Co Ltd Image processing method, image processing apparatus and electronic camera
JP2004177375A (en) * 2002-11-29 2004-06-24 Ishida Co Ltd Combinational measuring device
JP2005166698A (en) * 2003-11-28 2005-06-23 Matsushita Electric Ind Co Ltd Semiconductor integrated circuit

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP2082679A2 (en) 2008-01-22 2009-07-29 Fujifilm Corporation Flexible endoscope
JP2012209420A (en) * 2011-03-30 2012-10-25 Hitachi Ltd Semiconductor integrated circuit device
JP2016531424A (en) * 2013-07-17 2016-10-06 エイアールエム リミテッド Integrated circuit manufacturing using direct lithography
US10303840B2 (en) 2013-07-17 2019-05-28 Arm Limited Integrated circuit manufacture using direct write lithography

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