JP2012199787A - Device and method for determining image format - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent incorrect determination of an image format even when input timing of a horizontal synchronous signal and a vertical synchronous signal fluctuates.SOLUTION: An image format determination device includes: a field determination period measurement unit for measuring a predetermined period including a first vertical blanking period in a data enable signal, to generate first period information indicative of the measured period, and for measuring a predetermined period, including a second vertical blanking period in the data enable signal, after a predetermined number of vertical blanking periods from the first vertical blanking period, to generate second period information indicative of the measured period; and a format determination unit for comparing the period indicated by the first period information with the period indicated by the second period information, and according to the relationship of magnitude in the compared periods, for determining the image format displayed subsequent to the first vertical blanking period or the second vertical blanking period.

Description

  The present invention relates to an image format determination device and an image format determination method.

  In an image display device, a scaler that upscales an input image according to the resolution of the display is required as the resolution of the display increases. Here, the image display device is, for example, a PC (Personal Computer) monitor or a digital television. In addition, it is necessary to perform image processing for obtaining a high-quality image with respect to the image after upscaling. Image processing for obtaining a high-quality image is, for example, image processing for improving blurring and deterioration of an image that occurs during upscaling.

  The image format includes a progressive mode in which one frame display is performed by one scan and an interlace method in which one frame display is performed by two scans of odd lines and even lines. Interlace can suppress flickering when displaying moving images, but flickering and blurring occur when displaying still images and characters. Therefore, interlace is often used for televisions that often display moving images, and progressive is often used for PC monitors that often display still images and characters. In the interlace, one frame is divided into two fields Field1 and Field2. Therefore, when interlace and progressive are combined, there are a total of three formats. As described above, in the interlace, one frame image is displayed by the two fields Field1 and Field2. On the other hand, in progressive, the number of fields matches the number of frames.

  The three formats of progressive, interlaced field 1 and interlaced field 2 are characterized by the phase difference between the horizontal synchronizing signal and the vertical synchronizing signal and the length of the V blank period, respectively. Although the V blank period will be described in detail later, in the present embodiment, the “V blank period” is a period excluding a period of the horizontal blanking period in the vertical blanking period.

  In the progressive mode, the horizontal sync signal and the vertical sync signal are in phase for each frame, and the V blank period is also constant. This is because in the progressive mode, the horizontal blanking period and the vertical blanking period are constant.

  In interlace, a field (hereinafter referred to as “Field 1”) in which the phase of the horizontal synchronizing signal and the vertical synchronizing signal are aligned for each field, and the phase of the horizontal synchronizing signal and the vertical synchronizing signal are shifted by 1/2 line for each field. 2 fields (hereinafter referred to as “Field2”) alternate, and in the V blank period, two fields having different lengths by one line alternate. In Field1, the horizontal synchronizing signal and the vertical synchronizing signal are in phase, and the V blank period is shorter than Field2 by one line. In Field 2, the phase of the horizontal synchronizing signal and that of the vertical synchronizing signal are shifted by ½ line, and the V blank period is longer by one line than Field 1. This is because, in interlace, the horizontal blanking period is constant, but the vertical blanking periods are alternately different in length by one line.

  Since the scaler upscales the input image, the horizontal synchronization frequency, the vertical synchronization frequency, and the pixel frequency are changed in accordance with the resolution of the output image. However, as the demand for lower prices has increased in recent years, upscaling has been realized with limited buffer capacity and simple processing, so the horizontal and vertical synchronization frequencies that match the resolution of a part of the output image It can be seen that it does not meet. The fact that the horizontal synchronization frequency and the vertical synchronization frequency suitable for the image resolution are not satisfied means that the horizontal synchronization signal and the vertical synchronization signal are shifted from the desired timing. The timing difference between the horizontal synchronization signal and the vertical synchronization signal occurs depending on the scaler upscaling method and the image enlargement ratio. Therefore, the timing of the horizontal synchronization signal and the vertical synchronization signal of the image output from the scaler varies.

  Since it is necessary to change the image processing contents according to the image format, when processing the image upscaled by the scaler, the image format can be accurately adjusted even if the timing of the horizontal and vertical sync signals varies. It is essential to judge.

  Patent Document 1 discloses a technique for providing a field discriminating circuit that can perform stable field discriminating even when the input timing of a synchronization signal varies and suppresses an increase in circuit size. ing.

  The field discrimination circuit disclosed in Patent Document 1 will be described with reference to FIGS. 7 and 8 are block diagrams showing the configuration of the field discrimination circuit. FIG. 9 is a waveform diagram showing the operation of the field discrimination circuit.

  The field determination circuit 100 receives a vertical synchronization signal VD from an input terminal 101 and a horizontal synchronization signal HD from an input terminal 102. The vertical synchronization signal VD is inverted by the inverter 103, delayed by the delay unit 104, and input to the VD signal differential pulse creation unit 105 and the field determination signal polarity defining unit 106 as the delayed signal VDDEL.

  The VD signal differential pulse creation unit 105 creates a VD signal differential pulse VBIBUN corresponding to one edge of the delayed signal VDDEL. The field discrimination signal polarity defining unit 106 receives the horizontal synchronization signal HD from the input terminal 102 together with the delay signal VDDEL, and creates a differential pulse FBIBUN corresponding to one edge of the delay signal VDDEL. The differential pulse FBIBUN is generated by sampling the H level or L level of the horizontal synchronization signal HD at the timing of the delay signal VDDEL.

  The VD signal differential pulse VBIBUN output from the VD signal differential pulse creation unit 105 and the differential pulse FBIBUN output from the field discrimination signal polarity defining unit 106 are input to the field discrimination stabilization unit 107. The field discrimination stabilization unit 107 creates a field discrimination signal FIELD based on the VD signal differential pulse VBIBUN and outputs it from the output terminal 108. The field discrimination stabilization unit 107 defines the polarity of the field discrimination signal based on the differential pulse FBIBUN.

  FIG. 8 shows a more specific configuration of the field discrimination circuit. The VD signal differential pulse generator 105 includes a first D flip-flop 110 and a second D flip-flop 111. The field discrimination signal polarity defining unit 106 includes an inverter 115, a third D flip-flop 112, and a fourth D flip-flop 113. The field discrimination stabilization unit 107 includes a T flip-flop 114.

  In the first D flip-flop 110, the data input is fixed to the power supply potential, and the delay signal VDDEL is input from the delay unit 104 to the clock. The Q output of the first D flip-flop 110 is input to the data of the second D flip-flop 111. A signal obtained by inverting the horizontal synchronization signal HD by the inverter 115 is input to the clock of the second D flip-flop 111. The VD signal differential pulse VBIBUN, which is the NQ output of the second D flip-flop 111, is input to the reset terminal of the first D flip-flop 110, the clock terminal of the T flip-flop 114, and the reset terminal of the fourth D flip-flop 113.

  The 3D flip-flop 112 receives the delay signal VDDEL from the delay unit 104 as a clock. An inverted signal of the horizontal synchronizing signal HD is input from the inverter 15 to the data. From the Q output of the third D flip-flop 112, the signal FIELDP in the previous stage of the field discrimination signal FIELD is output. The data input of the fourth D flip-flop 113 is fixed to the power supply potential, and the signal FIELDP is input to the clock. The differential pulse FBIBUN output from the NQ output of the fourth D flip-flop 113 is input to the reset of the T flip-flop 114. The T flip-flop 114 is connected to the output terminal 108 at the Q output, and outputs a field discrimination signal FIELD.

  Detailed operation of the field discriminating circuit configured as described above will be described with reference to FIGS.

  First, a signal obtained by inverting the vertical synchronization signal VD by the inverter 103 is input to the delay unit 104, delayed by t1, and output as the delay signal VDDEL. This delay signal VDDEL is input to the third D flip-flop 112 as a clock. A signal obtained by inverting the horizontal synchronization signal HD by the inverter 15 is input to the third D flip-flop 112 as data.

  At the rising edge of the delay signal VDDEL that arrives once in one field, the L portion of the horizontal synchronizing signal HD is sampled in the first field, and the H portion of the horizontal synchronizing signal HD is sampled in the second field. As a result, a signal FIELDP in the previous stage of the field discrimination signal FIELD which is inverted once every field is output. Here, in order to capture the H portion and L portion of the horizontal synchronization signal HD at the rising edge of the delay signal VDDEL, the delay portion 104 delays the vertical synchronization signal VD by t1, and the clock of the third D flip-flop 112 ( Data setup time for the delay signal VDDEL) is gained.

  On the other hand, the delay signal VDDEL is input to the clock of the first D flip-flop 110. As a result, the power supply potential H is captured at the rising edge of the delay signal VDDEL. The fetched H data of the power supply potential becomes the data input of the next second D flip-flop 111. The second D flip-flop 111 receives the rising edge of the inverted signal of the horizontal synchronizing signal HD at the clock input after the Q output of the first D flip-flop 110 input to the data shifts to H, and captures H. Output as a VD signal differential pulse VBIBUN. Thereby, the first D flip-flop 110 is reset. That is, the signal that is the Q output of the first D flip-flop 110 shifts to the moment L when the second D flip-flop 111 takes in the data. Therefore, the second D flip-flop 111 holds the data H until the next rising edge of the delay signal VDDEL arrives at the clock input of the first D flip-flop 110. Here, since the VD signal differential pulse VBIBUN is an NQ output, a differential pulse of the vertical synchronizing signal VD is obtained as a negative pulse once per field.

  This VD signal differential pulse VBIBUN is input to the T flip-flop 114 as a clock. A signal obtained by dividing the rising edge of the VD signal differential pulse VBIBUN by ½ is output from the output terminal 108 as the field discrimination signal FIELD.

  In the fourth D flip-flop 113, the signal FIELDP is input from the third D flip-flop 112 to the clock, and the VD signal differential pulse VBIBUN is input from the second D flip-flop 111 to the reset terminal. The fourth D flip-flop 113 samples the power supply potential H at the rising edge of the signal FIELDP that arrives once in two fields, and is then reset when the VD signal differential pulse VBIBUN shifts to L. Accordingly, the fourth D flip-flop 113 outputs a differential pulse FBIBUN in which L arrives once in two fields. This differential pulse FBIBUN is input to the reset terminal of the T flip-flop 114. As a result, the field determination signal FIELD is reset by the L period of the differential pulse FBIBUN before the field determination signal FIELD is generated by the rise of the VD signal differential pulse VBIBUN. Therefore, the polarity of the first field is defined as H.

  However, in the technique disclosed in Patent Document 1, the delay amount of the delay unit 104 for sampling the H portion and the L portion of the horizontal synchronization signal HD at the rising edge of the delay signal VDDEL of the vertical synchronization signal VD is not appropriate. In addition, when the input timing of the horizontal synchronizing signal and the vertical synchronizing signal of the video signal varies, there is a problem that the polarity of the first field cannot be defined to H level and the field discrimination result may be erroneously determined.

  However, the variation or degree of variation in the input timing of the horizontal synchronization signal and the vertical synchronization signal differs from field to field depending on the scaler upscaling method and the change in magnification. In the first place, since the devices connected to the vertical synchronization signal VD of the input terminal 101 and the horizontal synchronization signal HD of the input terminal 102 are not yet determined, there are cases where the variation method or the variation degree is unknown. Furthermore, if the adjustment amount of the sampling timing is different for each field, it is not always possible to adjust the sampling timing with a unique delay amount for all fields. Therefore, the delay amount of the delay unit 104 for sampling the H portion and the L portion of the horizontal synchronization signal HD cannot be determined to an appropriate value at the rising edge of the delay signal VDDEL of the vertical synchronization signal VD. There is also.

  If the delay amount of the delay unit 104 is not appropriate, the H portion of the horizontal synchronization signal HD is sampled at the rising edge of the delay signal VDDEL regardless of the first field. When the H portion of the horizontal synchronization signal HD is sampled in the first field, the signal FEILDP remains at the L level, so that the differential pulse FBIBUN remains at the H level. If the differential pulse FBIBUN remains at the H level, the field determination signal FIELD is not reset, and the polarity of the first field cannot be defined as H. Therefore, the field determination result is erroneously determined.

  Similarly, if the input timing of the horizontal synchronization signal and the vertical synchronization signal varies in the second field, the L portion of the horizontal synchronization signal HD is sampled at the rising edge of the delay signal VDDEL regardless of the second field. End up. When the L portion of the horizontal synchronizing signal HD is sampled in the second field, the signal FEILDP becomes H level, so that the differential pulse FBIBUN becomes L level. Since the differential pulse FBIBUN becomes the L level, the field determination signal FIELD is reset, and the polarity is defined to be H regardless of the second field. Therefore, the field determination result is erroneously determined.

  Patent Document 2 discloses a field determination method for the purpose of preventing erroneous determination due to a delay of a video signal source, a phase difference detection circuit, noise, or the like. The field determination method disclosed in Patent Document 2 includes an extraction circuit, a phase difference detection circuit, a previous detection result holding circuit, and field determination means. The extraction circuit extracts a horizontal synchronization signal and a vertical synchronization signal from the video signal. The phase difference detection circuit detects a phase difference between the vertical synchronization signal and the horizontal synchronization signal extracted by the extraction circuit. The previous detection result holding circuit holds the previous phase difference detection result by the phase difference detection circuit. The field determination means logically makes a determination based on the current phase difference detection result by the phase difference detection circuit, the previous phase difference detection result held in the detection result holding circuit, and the previous determination result. Judgment of odd or even of the field.

  In Patent Document 3, complicated processing such as resetting of the frequency division ratio is performed even when a composite type horizontal synchronizing signal including a pulse having a period different from that of a normal horizontal synchronizing signal such as an equalized pulse is input. There has been disclosed a video display device intended to perform stable interlace discrimination and field discrimination without any problems. The video display device disclosed in Patent Document 3 includes a frequency measurement unit, a gate horizontal synchronization signal generation unit, and an interlace discrimination and field discrimination unit. The frequency measuring means measures the period of the horizontal synchronizing signal during a period in which there is no different period pulse train after a preset delay time from the rising time of the vertical synchronizing signal, and outputs a horizontal synchronizing signal period as a measured value. The gate horizontal synchronizing signal generating means generates a gate horizontal synchronizing signal obtained by filtering the horizontal synchronizing signal and removing the signal of the different period pulse train based on the horizontal synchronizing signal period. The interlace discrimination and field discrimination means generates an interlace discrimination signal and a field discrimination signal based on the gate horizontal synchronization signal.

  Patent Document 4 discloses a field type discrimination device for the purpose of performing field type discrimination regardless of the period of the horizontal synchronizing signal of the input video signal. The field type determination device disclosed in Patent Document 4 includes a delay circuit, a frequency measurement circuit, a microcomputer, and a field type determination circuit. The delay circuit delays the vertical synchronization signal of the input video signal. The frequency measurement circuit delays the horizontal synchronization signal of the input video signal. The microcomputer controls the delay time of the delay circuit based on the frequency of the horizontal synchronizing signal measured by the frequency measuring circuit. The field type determination circuit determines the field type based on the phase relationship between the vertical synchronizing signal output from the delay circuit and the signal synchronized with the horizontal synchronizing signal of the input video signal.

  Patent Document 5 discloses a field determination circuit that has a relatively simple circuit configuration and a small circuit scale, and aims to stably determine odd and even fields from a decoded video signal. The field determination circuit disclosed in Patent Document 5 includes a synchronization separation circuit, a delay circuit, a monostable multivibrator circuit, a shift register circuit, and a determination circuit. The sync separator circuit separates the composite sync signal from the input composite video signal. The delay circuit generates a shift clock signal having a rising edge delayed by a certain time from the falling edge of the composite synchronizing signal separated by the synchronizing separation circuit. The shift register takes in the decoded synchronization signal at every rising edge of the shift clock signal from the delay circuit, and shifts to obtain a shift register output. The determination circuit holds the shift register output obtained by the shift register by the holding clock signal from the multivibrator circuit. The determination circuit detects different bit patterns from the output of the shift register, and determines an odd field and an even field of the decoded video signal based on the detection result.

  Patent Document 6 discloses a field determination device for the purpose of reliably performing field determination without being affected by noise mixed in a vertical blanking period of a video signal. The field determination device disclosed in Patent Document 6 includes synchronization separation means, a horizontal synchronization duty ratio changing unit, a vertical synchronization delay circuit, and a field determination unit. The synchronization separation means separates the horizontal synchronization signal and the vertical synchronization signal from the video signal. The horizontal synchronization duty ratio changing unit changes the duty ratio of the horizontal synchronization signal obtained by the synchronization separation unit. The vertical synchronization delay circuit delays the vertical synchronization signal obtained by the synchronization separation means by a predetermined time. The field determination unit determines whether the video signal is an odd field or an even field according to the level of the horizontal synchronization signal after the duty ratio is changed at the rising edge of the vertical synchronization signal delayed by the delay circuit.

  However, Patent Documents 2 to 6 determine the image format based on the enable signal as in the present invention, so that even if the input timing of the horizontal synchronization signal and the vertical synchronization signal varies, It does not disclose a technique that can prevent erroneous determination.

JP 2007-082134 A JP 05-037809 A JP 2002-354288 A JP 2002-051233 A JP 2001-245176 A JP 2000-324359 A

  As described above, the technique disclosed in Patent Document 1 has a problem that the image format is erroneously determined when the input timing of the horizontal synchronization signal and the vertical synchronization signal varies.

  An image format determination apparatus according to a first aspect of the present invention is an image format determination apparatus that determines the format of an image displayed by a video signal, and an effective display period in which the image is displayed in the video signal. In the data enable signal indicating a blanking period that is one of a horizontal blanking period and a vertical blanking period in which the image is not displayed, a predetermined period including the first vertical blanking period is measured, and the measured period And a predetermined period including a second vertical blanking period after a predetermined number of vertical blanking periods from the first vertical blanking period in the data enable signal. A field determination period measuring unit that measures and generates second period information indicating the measured period; The period indicated by the first period information and the period indicated by the second period information are compared, and the first vertical blanking period or the second vertical blanking period is determined according to the magnitude relationship of the compared periods. A format determination unit that determines the format of an image displayed following the ranking period.

  An image format determination method according to a second aspect of the present invention is an image format determination method for determining a format of an image displayed by a video signal, and an effective display period in which the image is displayed in the video signal. In the data enable signal indicating a blanking period that is one of a horizontal blanking period and a vertical blanking period in which the image is not displayed, a predetermined period including the first vertical blanking period is measured, and the measured period And a predetermined period including a second vertical blanking period after a predetermined number of vertical blanking periods from the first vertical blanking period in the data enable signal. The second period information indicating the measured period is generated, and the period indicated by the first period information And the period indicated by the second period information, and an image displayed subsequent to the first vertical blanking period or the second vertical blanking period according to the magnitude relationship of the compared periods. The format is determined.

  According to each aspect of the present invention described above, the image format can be determined without using both the horizontal synchronization signal and the vertical synchronization signal. That is, the image format can be determined without depending on the input timing of the horizontal synchronization signal and the vertical synchronization signal.

  According to each aspect of the present invention described above, an image format determination apparatus and an image format determination method that can prevent erroneous determination of an image format even when the input timings of the horizontal synchronization signal and the vertical synchronization signal vary. Can be provided.

It is a block diagram of the image format determination circuit concerning Embodiment 1 of this invention. It is a timing chart of the data enable signal concerning Embodiment 1 of this invention. It is a flowchart of the image format determination process concerning Embodiment 1 of this invention. It is a block diagram of the image format determination circuit concerning Embodiment 2 of this invention. It is a timing chart of the data enable signal and VSYNC signal concerning Embodiment 2 of this invention. It is a flowchart of the image format determination process concerning Embodiment 2 of this invention. 10 is a block diagram of a field determination circuit according to Patent Document 1. FIG. 10 is a block diagram of a field determination circuit according to Patent Document 1. FIG. 10 is a waveform diagram showing an operation of a field determination circuit according to Patent Document 1. FIG.

Embodiment 1 of the present invention.
With reference to FIG. 1, the structure of the image format determination circuit 1 according to the first exemplary embodiment of the present invention will be described. FIG. 1 is a configuration diagram of an image format determination circuit 1 according to the first embodiment of the present invention.

  The image format determination circuit 1 includes a DE assertion interval measurement unit 10, a V blank period determination unit 11, a DE inactive period measurement unit 12, a previous DE inactive period holding unit 13, and a format determination unit 14.

  The image format determination circuit 1 is provided, for example, in an image display device that displays video based on a video signal. The image display device is, for example, a PC monitor or a digital television. Video signals are video signals, data enable signals (hereinafter also referred to as “DE signals”), vertical synchronization signals (hereinafter also referred to as “VSYNC signals”), horizontal synchronization signals and the like (hereinafter also referred to as “HSYNC signals”). )including.

  The video signal indicates an image displayed by the image display device. The DE signal indicates an effective display period in which an image is displayed and a blanking period in which no image is displayed in the video signal. The DE signal becomes active during the effective display period and becomes inactive during the blanking period. The blanking period indicated by the DE signal is either a horizontal blanking period or a vertical blanking period. The horizontal blanking period is a period from the end of image display on one line to the start of image display on the next line. The vertical blanking period is a period from the end of image display on the last line in a certain field to the start of image display on the first line in the next field.

  The image format determination circuit 1 determines the format of the image displayed by the video signal for each field based on the DE signal input from the image display device. The image display device displays an image by a display method suitable for the image format of each field based on the format determination result output for each field from the image format determination circuit 1.

  The DE assertion interval measurement unit 10 receives the DE signal of the video signal. The DE assertion interval measurement unit 10 measures the assertion interval of the DE signal. The assertion interval of the DE signal is a period from the start of assertion of the DE signal in a certain line to the start of assertion of the DE signal in the next line. The DE assertion interval measurement unit 10 includes a DE assertion interval measurement counter (not shown). The DE assertion interval measurement unit 10 measures the assertion interval of the DE signal by counting a DE assertion interval measurement counter. For example, the DE assertion interval measurement unit 10 counts the assertion interval of the DE signal by a clock signal. The DE assertion interval measurement unit 10 outputs the DE assertion interval measurement counter value to the V blank period determination unit 11.

  The V blank period determination unit 11 receives the DE assertion interval measurement counter value output from the DE assertion interval measurement unit 10. The V blank period determination unit 11 holds the DE assertion interval measurement counter value output from the DE assertion interval measurement unit 10 as a DE assertion interval measurement result at the end of measurement of the DE signal assertion interval. The V blank period determination unit 11 includes a storage device (not shown) that holds a DE assertion interval measurement counter value. The storage device is, for example, a register or a memory.

  The V blank period determination unit 11 compares the DE assertion interval measurement counter value held last time with the DE assertion interval measurement counter value output from the DE assertion interval measurement unit 10 this time, thereby determining the format in the field. It is determined whether or not the position corresponding to the DE signal input to the circuit 1 is in the V blank period. That is, the V blank period determination unit 11 determines whether or not the V blank period is included in the assertion interval of the DE signal currently being measured.

  Here, in the present embodiment, the “V blank period” is a period after a period of a length corresponding to the horizontal blanking period has elapsed since the DE signal became inactive in the vertical blanking period. It is a period. In other words, the “V blank period” is a period excluding a period of a length corresponding to the horizontal blanking period in the vertical blanking period. The V blank period determination unit 11 outputs the V blank period determination result to the DE inactive period measurement unit 12. The V blank period determination result is information indicating whether or not it is a V blank period.

  The DE inactive period measurement unit 12 receives the DE signal of the video signal and the V blank period determination result output from the V blank period determination unit 11. The DE inactive period measuring unit 12 measures the inactive period of the DE signal during the V blank period. Here, since the DE signal is inactive during the V blank period, the DE inactive period measuring unit 12 measures the V blank period. The DE inactive period measurement unit 12 measures a period from when the V blank period determination result indicating that it is a V blank period is output from the V blank period determination unit 11 to when the DE signal becomes active.

  The DE inactive period measuring unit 12 includes a DE inactive period measuring counter (not shown). The DE inactive period measuring unit 12 measures the inactive period of the DE signal during the V blank period by counting the DE inactive period measuring counter. For example, the DE inactive period measuring unit 12 counts the inactive period of the DE signal by a clock signal. The DE inactive period measuring unit 12 outputs the DE inactive period measuring counter value to the previous DE inactive period holding unit 13 and the format determining unit 14 as a DE inactive period measuring result.

  The previous DE inactive period holding unit 13 receives the DE inactive period measurement result output from the DE inactive period measuring unit 12. The previous DE inactive period holding unit 13 holds the DE inactive period measurement result for use in determining the image format in the next field when the measurement of the DE inactive period is completed. Specifically, the previous DE inactive period holding unit 13 holds the DE inactive period measurement result output from the DE inactive period measuring unit 12. The previous DE inactive period holding unit 13 includes a storage device that holds a DE inactive period measurement result. The previous DE inactive period holding unit 13 outputs the DE inactive period measurement result held last time to the format determining unit 14.

  The format determination unit 14 compares the current DE inactive period measurement result output from the DE inactive period measurement unit 12 with the previous DE inactive period measurement result output from the previous DE inactive period holding unit 13. By doing so, the image format is determined. The format determination unit 14 outputs an image format determination result.

  Next, the operation of the image format determination circuit 1 according to the first exemplary embodiment of the present invention will be described with reference to FIGS. FIG. 2 is a timing chart of the data enable signal according to the first exemplary embodiment of the present invention.

  The image format determination circuit 1 determines the image format by using the fact that the length of the V blank period of the image format has different characteristics in each image format. Here, all the DE signal assert intervals T2 included in the active period T1 are substantially constant. The DE signal assert interval including the V blank periods T0A and T0B is sufficiently longer than the DE signal assert interval T2 included in the active period T1. This is because the vertical blanking period is longer than the horizontal blanking period. Of the DE signal assertion interval T2 included in the active period T1, a period during which the DE signal is inactive is a horizontal blanking period. As described above, in this embodiment, a period longer than the horizontal blanking period in the vertical blanking period is defined as the V blank period. Using these things, the V blank period determination unit 11 determines whether or not the V blank periods T0A and T0B are included in the inactive period of the DE signal.

  Specifically, the V blank period determination unit 11 determines that the DE assertion interval measurement counter value currently measured and output from the DE assertion interval measurement unit 10 is larger than the previous DE assertion interval measurement counter value. , It is determined that the position of the DE signal is in the V blank period T0A and T0B. On the other hand, when the DE assertion interval measurement counter value output from the DE assertion interval measurement unit 10 is equal to or less than the previous DE assertion interval measurement counter value, the V blank period determination unit 11 starts asserting the next DE signal. The position of the DE signal is determined to be in the active period T1, and the current DE assertion interval measurement counter value output from the DE assertion interval measurement unit 10 is held as a DE assertion interval measurement result. The V blank period determination unit 11 uses the stored DE assertion interval measurement result for the next V blank period determination.

  The DE inactive period measurement unit 12 measures a period until the next DE assertion is started after the V blank period, and outputs the measured DE inactive period measurement counter value. That is, the DE inactive period measuring unit 12 measures the V blank period T0A or T0B. The previous DE inactive period holding unit 13 holds the DE inactive period measurement counter value indicating the V blank period as the DE inactive period measurement result, and outputs the previous DE inactive period measurement result.

  The format determination unit 14 is based on the current DE inactive period measurement result output from the DE inactive period measurement unit 12 and the previous DE inactive period measurement result output from the previous DE inactive period holding unit 13. To determine the image format. The image format determination according to the first embodiment uses the fact that the V blank period is constant for each frame in the case of progressive, and that different lengths alternate for each field in the case of interlace. To determine the image format. Hereinafter, a case where the V blank period indicated by the current DE inactive period measurement counter value is T0B and the V blank period indicated by the previous DE inactive period measurement counter value is T0A will be described.

  The format determination unit 14 includes the current DE inactive period measurement counter value output from the DE inactive period measurement unit 12 and the previous DE inactive period measurement counter value output from the previous DE inactive period holding unit 13. Compare If the difference between the two is equal within the allowable range (T0A≈T0B), the format determination unit 14 determines that the image format is progressive. If the difference between the two is not equal within the allowable range, the format determination unit 14 determines that the image format is not progressive but interlaced. The allowable range described above may be arbitrarily determined in advance.

  Further, if the difference between the two is not within an allowable range, if the current DE inactive period measurement counter value is larger (if T0A <T0B), the format determination unit 14 determines that the image format is Interlaced Field2. It is determined that If the previous DE inactive period measurement counter value is larger (if T0A> T0B), the format determination unit 14 determines that the image format is interlaced Field1.

  Next, the operation of the image format determination circuit 1 according to the first exemplary embodiment of the present invention will be described with reference to FIGS. FIG. 3 is a flowchart of the image format determination process according to the first embodiment of the present invention.

  The DE assertion interval measurement unit 10 measures the assertion interval of the DE signal (S100). That is, the DE assertion interval measurement unit 10 measures a period from the start of assertion of the DE signal of a certain line to the start of assertion of the DE signal of the next line. The DE assertion interval measurement unit 10 outputs the DE assertion interval measurement counter value counting the DE signal assertion interval to the V blank period determination unit 11 as needed.

  Next, the DE assertion interval measurement unit 10 determines whether or not the measurement of the DE signal assertion interval has been completed (S101). The DE assertion interval measurement unit 10 determines whether or not the measurement of the DE signal assertion interval has been completed based on whether or not the assertion on the next line of the DE signal has started.

  When the measurement of the DE signal assertion interval ends (S101: Yes), the DE assertion interval measurement unit 10 resets the DE assertion interval measurement counter. The V blank period determination unit 11 holds the DE assertion interval measurement counter value output from the DE assertion interval measurement unit 10 before the reset as the previous DE assertion interval measurement counter value (S102). For example, when a reset DE assertion interval measurement counter value is output from the DE assertion interval measurement unit 10, the V blank period determination unit 11 detects that the measurement of the DE signal assertion interval has ended. The DE assertion interval measurement unit 10 starts measuring the assertion interval of the next DE signal after resetting the DE assertion interval measurement counter (S100).

  When the measurement of the DE signal assert interval has not been completed (S101: No), the V blank period determination unit 11 determines the previous DE assert interval measurement counter value output from the DE assert interval measurement unit 10 based on the previous value. It is determined whether or not the DE assertion interval measurement counter value has decreased (S103). Here, even if the previous DE assertion interval measurement counter value is smaller than the current DE assertion interval measurement counter value, the V blank period determination unit 11 determines that the current DE assertion interval measurement counter value is equal within a predetermined range. It may not be determined that the previous DE assertion interval measurement counter value has become smaller than the assertion interval measurement counter value.

If the previous DE assertion interval measurement counter value is not smaller than the current DE assertion interval measurement counter value (S103: No), the DE assertion interval measurement unit 10 continues to measure the DE signal assertion interval. (S100).
When the previous DE assertion interval measurement counter value is smaller than the current DE assertion interval measurement counter value (S103: Yes), the V blank period determination unit 11 determines that the position of the DE signal is in the V blank period. judge. The V blank period determination unit 11 outputs a V blank period determination result indicating the V blank period to the DE inactive period measurement unit 12.

  The DE inactive period measurement unit 12 starts measuring the inactive period of the DE signal in response to the output of the V blank period determination result indicating the V blank period from the V blank period determination unit 11 (S104). . The DE inactive period measuring unit 12 ends the measurement when the DE signal becomes active. Thereby, the V blank period T0A or T0B can be measured. The DE inactive period measuring unit 12 outputs the DE inactive period measuring counter value of the V blank period to the previous DE inactive period holding unit 13 and the format determining unit 14.

  The previous DE inactive period holding unit 13 holds the DE inactive period measurement counter value output from the DE inactive period measuring unit 12 (S105). The previous DE inactive period holding unit 13 outputs the previous DE inactive period measurement counter value held last time to the format determining unit 14. Here, the previous DE inactive period measurement counter value holds the previous DE inactive period measurement counter value and the current DE inactive period measurement counter value so as to hold the previous DE inactive period measurement counter value. May be output. The previous DE inactive period holding unit 13 holds only the previous DE inactive period measuring counter value, and the DE inactive period measuring counter value output from the DE inactive period measuring unit 12 is a new one. When the value is changed, the DE inactive period measurement counter value before the change may be held.

  The format determination unit 14 includes the current DE inactive period measurement counter value output from the DE inactive period measurement unit 12 and the previous DE inactive period measurement counter value output from the previous DE inactive period holding unit 13. Are compared to determine whether or not the difference between them is equal within an allowable range (T0A≈T0B) (S106). Hereinafter, a case where the V blank period indicated by the current DE inactive period measurement counter value is T0B and the V blank period indicated by the previous DE inactive period measurement counter value is T0A will be described.

When the difference between the two is equal within the allowable range (S106: Yes), the format determination unit 14 determines that the image format is progressive (S107).
When the difference between the two is not equal within the allowable range (S106: No), the format determination unit 14 determines that the current DE inactive period measurement counter value is larger than the previous DE inactive period measurement counter value (T0A <T0B). It is determined whether or not (S108).

When it is determined that the current DE inactive period measurement counter value is greater than the previous DE inactive period measurement counter value (T0A <T0B) (S108: Yes), it is determined that the image format is interlaced Field2 (S109). )
When it is determined that the current DE inactive period measurement counter value is not larger than the previous DE inactive period measurement counter value (T0A> T0B) (S108: No), it is determined that the image format is interlaced Field1. (S110).

  According to the image format determination circuit 1 according to the first embodiment described above, erroneous determination of image format determination can be prevented even when the input timing of the horizontal synchronization signal and the vertical synchronization signal of the video signal varies. it can. The reason will be described below. In the field discrimination circuit according to Patent Document 1, the field discrimination is performed by adjusting the sampling timing of the horizontal synchronization signal by the delay amount of the vertical synchronization signal and defining the polarity of the first field to H level. Therefore, there is a problem that the image format is erroneously determined when the input timings of the horizontal synchronization signal and the vertical synchronization signal vary. On the other hand, according to the first embodiment, the DE inactive period of the V blank period is measured by using the fact that the length of the V blank period is different for each image format. And the previous DE inactive period are compared to determine the image format. That is, the image format can be determined without using both the horizontal synchronization signal and the vertical synchronization signal. Therefore, the image format determination is not affected by the input timing of the horizontal synchronization signal and the vertical synchronization signal.

Embodiment 2 of the present invention. ?
Next, the configuration of the image format determination circuit 2 according to the second exemplary embodiment of the present invention will be described with reference to FIG. FIG. 4 is a configuration diagram of the image format determination circuit 2 according to the second embodiment of the present invention.

  The image format determination circuit 2 includes a DE assertion interval measurement unit 20, a V blank period determination unit 21, a DE assertion interval holding unit 22, a previous DE assertion interval holding unit 23, and a format determination unit 24. For example, the image format determination circuit 2 is provided in the image display device, similarly to the image format determination circuit 1 according to the first embodiment.

  The DE assertion interval measurement unit 20 receives the DE signal of the video signal. The DE assertion interval measurement unit 20 measures the assertion interval of the DE signal, similarly to the DE assertion interval measurement unit 10 according to the first embodiment. The DE assertion interval measurement unit 20 outputs the DE assertion interval measurement counter value to the DE assertion interval holding unit 22 as a DE assertion interval measurement result at the end of measurement of the DE signal assertion interval.

  The V blank period determination unit 21 receives the VSYNC signal of the video signal. The V blank period determination unit 21 detects whether the position corresponding to the DE signal in the field is in the vertical blanking period by detecting assertion of the VSYNC signal. Here, the vertical blanking period includes a V blank period. That is, the V blank period determination unit 21 determines whether or not the V blank period is included in the assertion interval of the DE signal currently being measured. The V blank period determination unit 21 outputs the V blank period determination result to the DE assertion interval holding unit 22.

  The DE assertion interval holding unit 22 receives the DE assertion interval measurement result output from the DE assertion interval measurement unit 20 and the V blank period determination result output from the V blank period determination unit 21. The DE assertion interval holding unit 22 holds a DE assertion interval measurement result obtained by measuring the assertion interval of the DE signal including the V blank period. That is, the DE assertion interval holding unit 22 outputs the DE assertion interval output from the DE assertion interval measurement unit 20 when the V blank period determination result indicating the V blank period is output from the V blank period determination unit 21. Holds measurement results. As a result, only the DE assertion interval measurement result indicating the assertion interval of the DE signal including the V blank period is held in the DE assertion interval holding unit 22.

  Further, the DE assertion interval holding unit 22 outputs the previous DE assertion interval measurement result held before the new DE assertion interval measurement result to the previous DE assertion interval holding unit 23. That is, the DE assertion interval holding unit 22 includes a storage device that holds the DE assertion interval measurement result. The DE assertion interval holding unit 22 outputs the DE assertion interval measurement result held this time to the format determination unit 24.

  The previous DE assertion interval holding unit 23 receives the previous DE assertion interval measurement result output from the DE assertion interval holding unit 22. The previous DE assertion interval holding unit 23 holds the previous DE assertion interval measurement result output from the DE assertion interval holding unit 22. That is, the previous DE assertion interval holding unit 23 includes a storage device that holds the DE assertion interval measurement result. The previous DE assertion interval holding unit 23 outputs the held previous DE assertion interval measurement result to the format determination unit 24.

  The format determination unit 24 compares the current DE assertion interval measurement result output from the DE assertion interval holding unit 22 with the previous DE assertion interval measurement result output from the previous DE assertion interval holding unit 23. Determine the image format. In the determination of the image format according to the second embodiment, the assertion interval of the DE signal including the V blank period is constant for each frame in the case of progressive, and a different length for each field in the case of interlace. The image format is determined using the alternating of. The format determination unit 24 outputs the image format determination result.

  Subsequently, the operation of the image format determination circuit 2 according to the second exemplary embodiment of the present invention will be described with reference to FIGS. FIG. 5 is a timing chart of the data enable signal and the VSYNC signal according to the second embodiment of the present invention. FIG. 6 is a flowchart of image format determination processing according to the second embodiment of the present invention.

The DE assertion interval measurement unit 20 measures the assertion interval of the DE signal (S200). That is, the DE assertion interval measuring unit 20 measures a period from the start of assertion of the DE signal in a certain line to the start of assertion of the DE signal in the next line.
The DE assertion interval measurement unit 20 determines whether or not the measurement of the DE signal assertion interval has ended (S201). The DE assertion interval measurement unit 20 determines whether or not the measurement of the DE signal assertion interval has been completed based on whether or not the assertion of the DE signal of the next line has started.

  When the measurement of the DE signal assertion interval is completed (S201: Yes), the DE assertion interval measurement unit 20 outputs the DE assertion interval measurement counter value to the DE assertion interval holding unit 22 and resets the DE assertion interval measurement counter. . The DE assertion interval measurement unit 20 starts measuring the assertion interval of the next DE signal after resetting the DE assertion interval measurement counter (S200).

When the measurement of the DE signal assert interval has not ended (S201: No), the V blank period determination unit 11 determines whether or not the VSYNC signal is asserted (S203).
When the VSYNC signal is not asserted (S203: No), the DE assertion interval measurement unit 20 continues to measure the DE signal assertion interval (S200).
When the VSYNC signal is asserted (S203: Yes), the V blank period determination unit 11 determines that the position of the DE signal is in the vertical blanking period. That is, the V blank period is included in the assertion interval period of the DE signal currently being measured. The V blank period determination unit 21 outputs a V blank period determination result indicating the V blank period to the DE assertion interval holding unit 22. The measurement of the DE signal assertion interval by the DE assertion interval measurement unit 20 is continued (S204).

If the measurement of the DE signal assert interval has not been completed (S205: No), the measurement of the DE signal assert interval by the DE assert interval measurement unit 20 is continued (S204).
When the measurement of the DE signal assert interval is completed (S205: Yes), the DE assert interval measurement unit 20 outputs the DE assert interval measurement counter value to the DE assert interval holding unit 22 as a DE assert interval measurement result.

  The DE assertion interval holding unit 22 stores the previous DE assertion interval measurement result held in the previous DE assertion interval holding unit 23 before holding the DE assertion interval measurement counter value output from the DE assertion interval measurement unit 20. Output. The previous DE assertion interval holding unit 23 holds the previous DE assertion interval measurement counter value output from the DE assertion interval holding unit 22 (S206). Then, the assertion interval holding unit 22 holds the DE assertion interval measurement counter value output from the DE assertion interval measurement unit 20 (S207).

  The DE assertion interval holding unit 22 measures the DE assertion interval output from the DE assertion interval measurement unit 20 after the V blank period determination unit 21 outputs the V blank period determination result indicating the V blank period. Holds the counter value. That is, the processes of steps S206 and S207 are executed. Thus, only the DE assertion interval measurement counter value indicating the assertion interval of the DE signal including the V blank period is held in the DE assertion interval holding unit 22. The DE assertion interval holding unit 22 outputs the DE assertion interval measurement counter value held this time to the format determination unit 24.

  The format determination unit 24 compares the current DE assertion interval measurement counter value output from the DE assertion interval holding unit 22 with the previous DE assertion interval measurement counter value output from the previous DE assertion interval holding unit 23. Then, it is determined whether or not the difference between them is equal within an allowable range (T0C≈T0D) (S208). A case will be described below in which the DE signal assertion interval indicated by the current DE assertion interval measurement counter value is T0D and the DE signal assertion interval indicated by the previous DE assertion interval measurement counter value is T0C.

When the difference between the two is equal within the allowable range (S208: Yes), the format determination unit 24 determines that the image format is progressive (S209).
If the difference between the two is not equal within the allowable range (S208: No), the format determination unit 24 determines whether or not the current DE assertion interval measurement counter value is larger than the previous DE assertion interval measurement counter value (T0C <T0D). Is determined (S210).

If it is determined that the current DE assertion interval measurement counter value is greater than the previous DE assertion interval measurement counter value (T0C <T0D) (S210: Yes), it is determined that the image format is interlaced Field2 (S211). .
If it is determined that the current DE assertion interval measurement counter value is not larger than the previous DE assertion interval measurement counter value (T0C> T0D) (S210: No), it is determined that the image format is interlaced Field1 (S212). ).

  According to the image format determination circuit 2 according to the second embodiment described above, it is possible to prevent erroneous determination of image format determination even when the input timing of the horizontal synchronization signal and the vertical synchronization signal of the video signal varies. it can. According to the second embodiment, the length of the DE signal assertion interval including the V blank period is different in each image format, and the DE including the V blank period is based on the VSYNC signal. The signal assertion interval is measured, and the image format is determined by comparing the present and previous assertion intervals of the DE signal. That is, the image format can be determined without using both the horizontal synchronization signal and the vertical synchronization signal. Therefore, the image format determination is not affected by the input timing of the horizontal synchronization signal and the vertical synchronization signal.

  In the second embodiment, whether or not the V blank period is included in the DE signal assert interval is determined depending on whether or not the VSYNC signal is asserted during the DE signal assert interval having a certain range. ing. Therefore, even when the input timing of the VSYNC signal varies, it is possible to prevent erroneous determination of the image format.

  As described above, in the present embodiment, in the video signal, an effective display period in which an image is displayed, and a blanking period that is one of a horizontal blanking period and a vertical blanking period in which no image is displayed, In the data enable signal shown, a predetermined period including the first vertical blanking period is measured, and first period information indicating the measured period is generated. Further, in the data enable signal, a predetermined period including a second vertical blanking period after a predetermined number of vertical blanking periods from the first vertical blanking period is measured, and second period information indicating the measured period Is generated. Then, the period indicated by the first period information is compared with the period indicated by the second period information, and the first vertical blanking period or the second vertical blanking period is determined depending on the magnitude relationship of the compared periods. Subsequently, the format of the image to be displayed is determined.

  Further, in the present embodiment, the vertical blanking period is detected by using the fact that the vertical blanking period is constant in the case of progressive, and alternating in different lengths in the case of interlace. The format of the image is determined by measuring and comparing a predetermined period including the detected vertical blanking period. Here, in the first embodiment, the V blank period is detected by the enable signal. Since the V blank period is included in the vertical blanking period, it can be said that the vertical blanking period is detected by the enable signal in the first embodiment. In the second embodiment, the vertical blanking period is detected by the VSYNC signal.

  In the first embodiment, the case where the predetermined period is a V blank period excluding the period of the horizontal blanking period in the vertical blanking period is illustrated. That is, in the first embodiment, the V blank period including a part of the vertical blanking period is measured. In the second embodiment, the case where the predetermined period is one period of the data enable signal including the vertical blanking period is illustrated. In the present embodiment, the second vertical blanking period after a predetermined number of vertical blanking periods after the first vertical blanking period is used as the second vertical blanking period after the first vertical blanking period. The case of the period is illustrated.

  According to this, in the first embodiment, the image format can be determined without using the horizontal synchronization signal and the vertical synchronization signal. In the second embodiment, the image format can be determined without using the horizontal synchronization signal. Therefore, the image format can be determined without using both the horizontal synchronization signal and the vertical synchronization signal. That is, the image format can be determined without depending on the input timing of the horizontal synchronization signal and the vertical synchronization signal. Therefore, according to the present embodiment, it is possible to prevent erroneous determination of the image format even when the input timing of the horizontal synchronization signal and the vertical synchronization signal varies.

  Note that the present invention is not limited to the above-described embodiment, and can be changed as appropriate without departing from the spirit of the present invention.

  In the first embodiment, the DE inactive period measuring unit 12 measures the V blank period including a part of the vertical blanking period, but is not limited thereto. The predetermined period measured by the DE inactive period measuring unit 12 may be a period of a predetermined cycle including a vertical blanking period in the DE signal. For example, a vertical blanking period that is a half cycle of the DE signal may be measured. Further, in the DE signal, a period for one cycle including the vertical blanking period may be measured. Further, a plurality of periods of the DE signal including the vertical blanking period may be measured. That is, the assert interval for a predetermined period of the DE signal including the vertical blanking period may be measured.

  In these cases, for example, the DE inactive period measuring unit 12 outputs a V blank period determination result indicating that it is a V blank period from the V blank period determining unit 11 while measuring a period of a predetermined period. In this case, the measured period is set as a DE inactive period measurement result. Even in this case, since the horizontal blanking period and the DE signal assertion interval T2 are the same in any format, the period indicated by the DE inactive period measurement result is displayed following the vertical blanking period. The length depends on the image format. That is, the image format can be determined according to the magnitude relationship between the DE inactive period measurement results.

  Similarly, in the second embodiment, the DE assertion interval measurement unit 20 measures the assertion interval for one cycle of the DE signal including the vertical blanking period, but the DE signal including the vertical blanking period. The assert interval for a plurality of periods may be measured.

  In the first embodiment, the DE assertion interval measurement unit 10 measures the assertion interval for one period of the DE signal, but is not limited thereto. The assert interval for a plurality of periods of the DE signal may be measured. Even in this case, as described above, since the horizontal blanking period and the DE signal assertion interval T2 are the same in any format, the DE signal assertion interval includes the vertical blanking period. , Get bigger. That is, even in this way, the V blank period determination unit 11 can determine whether or not the V blank period is included in the DE assertion interval by comparing the DE assertion interval measurement results.

  In the first embodiment, in the format determination, a V blank period in a certain vertical blanking period and a V blank period in the next vertical blanking period are measured and compared. However, it is not limited to this. A V blank period in a certain vertical blanking period may be measured and compared with a V blank period in a vertical blanking period after a predetermined number of vertical blanking periods from the vertical blanking period. For example, a V blank period of a certain vertical blanking period may be measured and compared with a V blank period of an arbitrary odd number of vertical blanking periods after a certain vertical blanking period. Even in this case, in interlace, an image displayed following a certain vertical blanking period is different from an image displayed following an arbitrary odd vertical blanking period from a certain vertical blanking period. This is because the field determination can be performed because of the format.

  Similarly, in the second embodiment, in the format determination, the DE signal assert interval including a certain vertical blanking period and the DE signal assert interval including the vertical blanking period next to the vertical blanking period are determined. Although it measures and compares, it is not restricted to this. The DE signal assert interval including a certain vertical blanking period is measured and compared with the DE signal assert interval including a vertical blanking period after a predetermined number of vertical blanking periods from the vertical blanking period. Also good.

  Similarly, in the first embodiment, in the determination of the V blank period, the assert interval for one DE signal period including a certain blanking period and one DE signal period including the blanking period next to the blanking period are included. However, the present invention is not limited to this. The assertion interval of the DE signal including a certain blanking period may be measured and compared with the assertion interval of the DE signal including a blanking period after a predetermined number of blanking periods from the blanking period. For example, the assertion interval of the DE signal including a certain blanking period may be measured and compared with the assertion interval of the DE signal including any blanking period after the blanking period. This is because there is only one vertical blanking period per field, but a plurality of horizontal blanking periods are continued per field. That is, if the predetermined number of blanking periods is not the number of blanking periods included in one field, the assert interval including the vertical blanking period is compared with the assert interval including the horizontal blanking period. Because.

  In the first embodiment, when the format determination unit 14 measures and compares the V blank period of a certain vertical blanking period and the V blank period of the vertical blanking period subsequent to the vertical blanking period, Although the format of an image displayed following the next vertical blanking period is determined, the present invention is not limited to this. The format determination unit 14 may determine the format of an image displayed following a certain vertical blanking period. In this case, for example, when it is determined in step S108 that the current DE inactive period measurement counter value is larger than the previous DE inactive period measurement counter value (T0A <T0B), it is determined that the image format is Field1. When it is determined that the counter value is not larger than the previous DE inactive period measurement counter value (T0A> T0B), it is determined that the image format is Field2.

  Similarly, also in the second embodiment, the format determination unit 24 uses the DE signal assert interval including a certain vertical blanking period and the DE signal assert interval including the vertical blanking period next to the vertical blanking period. Is measured and compared, the format of the image displayed following the next vertical blanking period is determined, but the format of the image displayed following a certain vertical blanking period is determined. You may make it do.

1, 2 Image format determination circuit 10 DE assertion interval measurement unit 11, 21 V blank period determination unit 12 DE inactive period measurement unit 13 Previous DE inactive period holding unit 14, 24 Format determination unit 20 DE assertion interval measurement unit 22 DE Assertion interval holding unit 23 Previous DE assertion interval holding unit 100 Field discriminating circuit 101, 102 Input terminal 103 Inverter 104 Delay unit 105 VD signal differential pulse creating unit 106 Field discrimination signal polarity defining unit 107 Field discrimination stabilizing unit 108 Output terminal 110 1D flip-flop 111 Second D flip-flop 112 Third D flip-flop 113 Fourth D flip-flop 114 T flip-flop

Claims (10)

An image format determination device for determining a format of an image displayed by a video signal,
In the video signal, in a data enable signal indicating an effective display period in which the image is displayed and a blanking period that is one of a horizontal blanking period and a vertical blanking period in which the image is not displayed, a first vertical A predetermined period including a blanking period is measured, first period information indicating the measured period is generated, and after a predetermined number of vertical blanking periods from the first vertical blanking period in the data enable signal A format determination period measuring unit that measures the predetermined period including the second vertical blanking period and generates second period information indicating the measured period;
The period indicated by the first period information and the period indicated by the second period information are compared, and the first vertical blanking period or the second vertical blanking period is determined according to the magnitude relationship of the compared periods. A format determination unit that determines the format of an image displayed following the ranking period;
An image format determination device. The image format determination device further includes a detection unit that detects the vertical blanking period from a plurality of blanking periods indicated by the data enable signal based on the data enable signal or the vertical synchronization signal,
The image format determination apparatus according to claim 1, wherein the format determination period measurement unit measures the predetermined period including a vertical blanking period detected by the detection unit. The detector is
In the data enable signal, a period of a predetermined cycle including a first blanking period is measured, first period determination period information indicating the measured period is generated, and in the data enable signal, Blanking period determination period measurement for measuring a period of the predetermined period including a second blanking period after a predetermined number of blanking periods from the blanking period and generating second period determination information indicating the measured period. And
Blanking for comparing a period indicated by the first period determination information with a period indicated by the second period determination information and detecting a blanking period included in a larger period as the vertical blanking period A period determination unit;
The image format determination device according to claim 2, comprising:   The detection unit, when the vertical synchronization signal is asserted within a predetermined period including the blanking period, detects a blanking period included in the predetermined period as the vertical blanking period. Item 3. The image format determination device according to Item 2.   5. The image format determination device according to claim 1, wherein the predetermined period is a period excluding a period corresponding to the horizontal blanking period in the vertical blanking period. 6.   The image format determination device according to claim 1, wherein the predetermined period is a field determination period having a predetermined period of the data enable signal.   The image format determination device according to claim 1, wherein the second vertical blanking period is a vertical blanking period next to the first vertical blanking period.   In the format determination unit, the period indicated by the second period information is greater than the period indicated by the first period information, or the period indicated by the first period information is greater than the period indicated by the second period information. The method according to claim 1, wherein whether the format of the image is a first field in an interlace or a second field having a format different from the first field in the interlace is determined based on whether the image is large. The image format determination apparatus described in 1.   The format determination unit determines that the format of the image is progressive when the period indicated by the first period information and the period indicated by the second period information are equal within a predetermined range. 9. The method according to claim 1, wherein when the period indicated by the first period information and the period indicated by the second period information are not equal within a predetermined range, the format of the image is determined to be interlaced. The image format determination device according to any one of the preceding claims. An image format determination method for determining a format of an image displayed by a video signal,
In the video signal, in a data enable signal indicating an effective display period in which the image is displayed and a blanking period that is one of a horizontal blanking period and a vertical blanking period in which the image is not displayed, a first vertical A predetermined period including a blanking period is measured, first period information indicating the measured period is generated, and after a predetermined number of vertical blanking periods from the first vertical blanking period in the data enable signal Measuring the predetermined period including the second vertical blanking period, and generating second period information indicating the measured period,
The period indicated by the first period information and the period indicated by the second period information are compared, and the first vertical blanking period or the second vertical blanking period is determined according to the magnitude relationship of the compared periods. Determine the format of the image displayed following the ranking period,
Image format determination method.

Images