JP2012195330A - Semiconductor device manufacturing method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To inhibit warpage of a board (assembly) on which an encapsulating body is formed.SOLUTION: Because through holes 10e, 10f are formed in a multi piece-divided board 10, and an undersurface gate side cavity and an undersurface air vent side cavity are formed in a lower die of a molding die, not only a body encapsulation part 17a on a top face 10a side of the multi piece-divided board 10 and a gate side circumference encapsulation part 17b, but also on an undersurface 10b side, a gate side undersurface encapsulation part 18a and an air vent side undersurface encapsulation part 18b are formed. Accordingly, stress due to thermal expansion or thermal contraction can be generated on the undersurface 10b side of the board to balance stresses generated on both surfaces of the board thereby to inhibit warpage of the multi piece-divided board 10.

Description

  The present invention relates to a manufacturing technique of a semiconductor device, and more particularly to a technique effectively applied to a collective mold in which a plurality of device regions provided on a wiring board are collectively sealed with a resin.

  In assembling a semiconductor device in which a semiconductor chip is mounted on a base material (wiring board) and assembled, a plurality of device regions on the surface of the base material are collectively sealed with resin, and then separated into individual pieces after sealing. Assembling a semiconductor device, a so-called batch molding (collective sealing) method is known.

  As for assembling a semiconductor device to which such a collective molding method is applied, for example, Japanese Patent Application Laid-Open No. 2004-179345 (Patent Document 1) and Japanese Patent Application Laid-Open No. 2000-124163 (Patent Document 2) show a manufacturing method thereof. Yes.

JP 2004-179345 A JP 2000-124163 A

  Among resin-encapsulated semiconductor devices, a semiconductor device in which a sealing body is formed only on one side (upper surface, chip mounting surface) of a base material (wiring substrate) is likely to warp. The cause of this warp is that the linear expansion coefficient of the material (member) constituting the sealing body is different from the material (member) constituting the substrate.

  The problem of warpage of the base material is particularly noticeable when a batch molding method in which a plurality of device regions provided on the wiring board are collectively sealed with a resin is applied.

  Moreover, when the base material (assembly body) in which the sealing body is formed is warped, when the base material is transported from the process of forming the sealing body (molding process) to the next process, for example, a guide rail is used. It becomes difficult to use and convey.

  The guide rail method is a method of transporting while guiding the wiring board with the ends on both sides of the wiring board supported by the rail. However, if the wiring board is warped, the wiring board does not move or moves. A conveyance failure such as difficulty occurs.

  This invention is made | formed in view of the said subject, The objective is to provide the technique which can suppress the curvature of the board | substrate (assembly body) in which the sealing body was formed.

  The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

  Of the inventions disclosed in this application, the outline of typical ones will be briefly described as follows.

  A method of manufacturing a semiconductor device according to a representative embodiment includes a first through hole and a second through hole formed from one of an upper surface and a lower surface toward the other, a first through hole, and a second through hole. A wiring board including a plurality of upper surface side device regions provided between and a plurality of lower surface side device regions provided between the first through hole and the second through hole is prepared. Furthermore, the upper surface side sealing portion that collectively seals the plurality of semiconductor chips, the plurality of upper surface side device regions, the first through hole, and the second through hole, and the upper surface side sealing portion and the first through hole A first lower surface side sealing portion that is integrally formed and formed outside the plurality of lower surface side device regions and that seals the first through hole, and is integrated with the upper surface side sealing portion and the second through hole. And a second lower surface side sealing portion that is formed outside the plurality of lower surface side device regions and seals the second through hole. Furthermore, the wiring board on which the upper surface side sealing portion, the first lower surface side sealing portion, and the second lower surface side sealing portion are formed is transported to another processing portion using a guide rail.

  Of the inventions disclosed in the present application, effects obtained by typical ones will be briefly described as follows.

  Warpage of the substrate (assembly body) on which the sealing body is formed can be suppressed.

It is a top view which shows an example of the structure of the semiconductor device of Embodiment 1 of this invention. FIG. 2 is a back view illustrating an example of a structure on a back surface side of the semiconductor device illustrated in FIG. 1. FIG. 2 is a plan view showing an example of the internal structure of the semiconductor device shown in FIG. 1 through a sealing body. It is sectional drawing which shows an example of the structure cut | disconnected along the AA line of FIG. It is a top view which shows an example of the structure of the wiring board used by the assembly of the semiconductor device shown in FIG. FIG. 6 is a back view showing an example of the structure on the back side of the wiring board shown in FIG. 5. FIG. 2 is a perspective view showing an example of a structure during die bonding and wire bonding in the assembly of the semiconductor device of FIG. 1. FIG. 2 is a perspective view illustrating an example of a structure at the time of molding, mold baking, and marking in the assembly of the semiconductor device of FIG. 1. FIG. 2 is a perspective view illustrating an example of a structure when a ball is mounted, when a piece is cut, and when packing and shipping are performed in the assembly of the semiconductor device of FIG. 1. It is a top view which shows an example of the structure after the die bonding in the assembly of the semiconductor device of FIG. It is a fragmentary sectional view which shows an example of the structure of the shaping die used at the molding process of the assembly of the semiconductor device of FIG. It is a top view which shows an example of the structure of the assembly body after the resin mold in the assembly of the semiconductor device of FIG. It is sectional drawing which shows an example of the structure cut | disconnected along the AA line of FIG. It is sectional drawing which shows an example of the structure cut | disconnected along the BB line of FIG. FIG. 2 is a partial cross-sectional view illustrating an example of a rack storage state of an assembly in a mold baking process for assembling the semiconductor device of FIG. 1. It is a fragmentary sectional view which shows an example of the structure cut | disconnected along the AA line of FIG. FIG. 2 is a cross-sectional view showing an example of a laser irradiation state in a mark process for assembling the semiconductor device of FIG. 1. It is a top view which shows an example of the structure of the assembly body after the resin molding in the assembly of the semiconductor device of Embodiment 2 of this invention. It is sectional drawing which shows an example of the structure cut | disconnected along the AA of FIG. It is a fragmentary sectional view which shows an example of the structure of the shaping die used at the molding process of the assembly of the semiconductor device of Embodiment 2 of this invention. It is a top view which shows the structure of the assembly body after the resin molding of the 1st modification in the assembly of the semiconductor device of Embodiment 2 of this invention. It is sectional drawing which shows the structure of the assembly body after the resin molding of the 2nd modification in the assembly of the semiconductor device of Embodiment 2 of this invention. It is sectional drawing which shows the structure of the 3rd modification of Embodiment 2 of this invention. It is a fragmentary sectional view which shows the rack accommodation state of the assembly in the assembly of the semiconductor device of a comparative example. It is a fragmentary sectional view which shows the structure cut | disconnected along the AA of FIG. It is a fragmentary sectional view which shows the structure cut | disconnected along the BB line of FIG.

  In the following embodiments, the description of the same or similar parts will not be repeated in principle unless particularly necessary.

  Further, in the following embodiment, when it is necessary for the sake of convenience, the description will be divided into a plurality of sections or embodiments, but they are not irrelevant to each other unless otherwise specified. The other part or all of the modifications, details, supplementary explanations, and the like are related.

  Also, in the following embodiments, when referring to the number of elements (including the number, numerical value, quantity, range, etc.), particularly when clearly indicated and when clearly limited to a specific number in principle, etc. Except, it is not limited to the specific number, and it may be more or less than the specific number.

  Further, in the following embodiments, the constituent elements (including element steps) are not necessarily indispensable unless otherwise specified and clearly considered essential in principle. Needless to say.

  Further, in the following embodiments, regarding constituent elements and the like, when “consisting of A”, “consisting of A”, “having A”, and “including A” are specifically indicated that only those elements are included. It goes without saying that other elements are not excluded except in the case of such cases. Similarly, in the following embodiments, when referring to the shapes, positional relationships, etc. of the components, etc., the shapes are substantially the same unless otherwise specified, or otherwise apparent in principle. And the like are included. The same applies to the above numerical values and ranges.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. Note that components having the same function are denoted by the same reference symbols throughout the drawings for describing the embodiments, and the repetitive description thereof will be omitted.

(Embodiment 1)
1 is a plan view showing an example of the structure of the semiconductor device according to the first embodiment of the present invention, FIG. 2 is a back view showing an example of the structure on the back side of the semiconductor device shown in FIG. 1, and FIG. 3 is shown in FIG. FIG. 4 is a cross-sectional view showing an example of the structure cut along the line AA in FIG. 3.

  First, the semiconductor device of the first embodiment will be described.

  In the semiconductor device according to the first embodiment shown in FIGS. 1 to 4, the semiconductor chip 1 mounted on the upper surface 2a of the wiring substrate 2 as a base material is resin-sealed by the sealing body 4, and the semiconductor chip 1 is The semiconductor package is electrically connected to the bonding lead 2c of the wiring board 2 via the wire 7. In the first embodiment, a plurality of external connections are made to the lower surface 2b of the wiring board 2 as an example of the semiconductor device. A description will be given by taking up a BGA (Ball Grid Array) 9 in which the solder balls 5 serving as the terminals are provided on the outer periphery as shown in FIG. However, the solder balls 5 may be arranged in a grid shape (lattice shape), for example.

  The BGA 9 of the first embodiment is a semiconductor package that is resin-sealed by a batch molding method using a multi-piece substrate 10 as shown in FIG. 5 and is separated and assembled after resin sealing. is there.

  The detailed configuration of the BGA 9 will be described. The upper surface (front surface, chip mounting surface) 2a, the bonding leads 2c as a plurality of connection terminals formed on the upper surface 2a, and the lower surface (back surface, mounting surface) 2b opposite to the upper surface 2a. And a wiring substrate (also referred to as a BGA substrate or a package substrate) 2 having a plurality of lands 2d formed on the lower surface 2b, and a bonding pad 1c which is a plurality of electrode pads formed on the surface 1a and the surface 1a. And the semiconductor chip 1 mounted on the upper surface 2a of the wiring board 2, the plurality of wires 7 for electrically connecting the plurality of bonding leads 2c of the wiring board 2 and the plurality of bonding pads 1c of the semiconductor chip 1, respectively. A plurality of lands 2d of the wiring board 2 have a plurality of solder balls 5 as external connection terminals.

  That is, as shown in FIGS. 3 and 4, the BGA 9 has the semiconductor chip 1 mounted on the wiring board 2 and connected to the wiring board 2, and the semiconductor chip 1 and the plurality of wires 7 are made of resin. It is a substrate type semiconductor package sealed by a sealing body 4.

  As shown in FIG. 4, the semiconductor chip 1 has a front surface 1a and a back surface 1b opposite to the front surface 1a, and the back surface 1b is disposed so as to face the upper surface 2a of the wiring board 2. Further, it is fixed to the upper surface 2a of the wiring board 2 by a die bond material 6 such as a resin paste material.

  Here, the semiconductor chip 1 is made of, for example, silicon, and the wire 7 is, for example, a gold wire. The sealing resin 3 that forms the sealing body 4 is, for example, a thermosetting epoxy resin. The external connection terminal is a solder ball 5 using a solder material such as Sn-Pb solder or Pb-free solder.

  The wiring substrate 2 is a resin substrate in which a plurality of wiring layers and insulating layers are formed on a core material such as glass epoxy resin, for example, and a plurality of bonding leads 2c exposed on the upper surface 2a and a lower surface 2b. The regions other than the plurality of lands 2d exposed to the surface are covered with a solder resist film which is an insulating film. The wiring layer including the plurality of bonding leads 2c and the plurality of lands 2d is made of, for example, a copper alloy.

  In this way, the bonding pads 1c of the semiconductor chip 1 to the solder balls 5 as the external connection terminals of the BGA 9 are electrically connected through the wires 7, bonding leads 2c, vias (not shown), lands 2d, and the like. ing.

  Next, a method for manufacturing the BGA (semiconductor device) 9 according to the first embodiment will be described.

  5 is a plan view showing an example of the structure of the wiring board used in assembling the semiconductor device shown in FIG. 1, and FIG. 6 is a back view showing an example of the structure on the back side of the wiring board shown in FIG. 7 is a perspective view showing an example of a structure at the time of die bonding and wire bonding in the assembly of the semiconductor device of FIG. 1, and FIG. 8 is a view at the time of molding, mold baking and marking in the assembly of the semiconductor device of FIG. FIG. 9 is a perspective view showing an example of the structure at the time of ball mounting, individual piece cutting, packing and shipping in the assembly of the semiconductor device of FIG. Further, FIG. 10 is a plan view showing an example of a structure after die bonding in the assembly of the semiconductor device of FIG.

  First, an upper surface (surface, chip mounting surface) 10a having a rectangular shape as shown in FIG. 5 and a lower surface (back surface) having the same planar shape as shown in FIG. 6 and opposite to the upper surface 10a as shown in FIG. , Mounting surface) 10b, and a multi-piece substrate (wiring board) 10 is prepared.

  The multi-chip substrate 10 has an elongated slit (through hole) 10e (formed between the upper surface 10a and the lower surface 10b) formed from one of the upper surface 10a and the lower surface 10b to the other, An elongated slit (through hole) 10f formed from one of the upper surface 10a and the lower surface 10b to the other (formed between the upper surface 10a and the lower surface 10b) is formed.

  In the first embodiment, as shown in FIGS. 5 and 6, two through holes 10 e and two through holes 10 f are formed along the opposing long sides of the rectangular multi-cavity substrate 10. Yes. However, the through-holes 10e and 10f are through-holes that are formed along the opposing long sides of the multi-piece substrate 10 and through which the resin 3 can pass, and have a shape that does not significantly reduce the strength of the substrate. If it is, it will not be limited to slit shape, For example, a some long hole, a some circular hole, etc. may be sufficient.

  Further, on the upper surface 10a side of the multi-chip substrate 10, as shown in FIG. 5, a device which is a plurality of upper surface side device regions provided in a matrix arrangement between the through holes 10e and the through holes 10f in a plan view. A region 10c and a plurality of bonding leads (electrode pads) 2c shown in FIG. 3 formed in each of the plurality of device regions 10c are formed. Furthermore, a plurality of gate patterns 10g are formed along only the long sides of the multi-cavity substrate 10 corresponding to the gate side of the molding die 14 for resin sealing shown in FIG.

  In other words, each of the through hole 10e and the through hole 10f is disposed on an extension line from which the gate pattern 10g provided along the long side of the multi-chip substrate 10 extends. The gate pattern 10g is made of, for example, plating, and improves the peelability of the gate resin 19 (see FIG. 13) after resin sealing.

  Thus, each of the through-hole 10e and the through-hole 10f is arranged on an extension line extending the gate pattern 10g provided along the long side of the multi-cavity substrate 10, so that the resin at the time of resin injection 3 easily enters the through-hole 10e and the through-hole 10f along the flow, so that the resin 3 can be easily turned around to the lower surface 10b side of the substrate 10.

  On the other hand, on the lower surface 10b side of the multi-chip substrate 10, as shown in FIG. 6, there are devices that are a plurality of lower surface side device regions provided in a matrix arrangement between the through holes 10e and the through holes 10f in a plan view. A region 10d and a plurality of lands (electrode pads) 2d formed in each of the plurality of device regions 10d are formed. In the first embodiment, a case where a plurality of lands 2d are arranged in a lattice shape (grid shape) in each device region 10d will be described as an example. However, the number and arrangement of the plurality of lands 2d are particularly limited. (For convenience, FIG. 6 shows a case in which a plurality of lands 2d are arranged in a grid pattern. However, the arrangement of the lands 2d is not particularly limited. Depending on the case, it may be a peripheral arrangement as shown in FIG.

  One of the plurality of device regions 10c, 10d of the multi-piece substrate 10 corresponds to the wiring board 2 of the BGA 9 after assembly. Therefore, the multi-piece substrate 10 is also a core such as a glass epoxy resin, for example. A resin substrate in which a plurality of wiring layers and insulating layers are formed on a material.

  Further, as shown in FIGS. 5 and 6, a plurality of positioning or guide holes 10 h are formed in the peripheral portions of the long sides facing the multi-piece substrate 10.

  After preparing the multi-piece substrate 10 as described above, die bonding shown in step S1 of FIG. 7 is performed. Here, as shown in FIG. 10, a plurality of device regions (upper surface side device regions) 10 c on the upper surface 10 a of the multi-chip substrate 10 have a plurality of back surfaces 1 b facing the upper surface 10 a of the multi-chip substrate 10. Each semiconductor chip 1 is mounted. Here, as shown in FIGS. 3 and 4, the semiconductor chip 1 has a surface 1a, a plurality of bonding pads 1c formed on the surface 1a, and a back surface 1b opposite to the surface 1a.

  In the die bonding process, as shown in step S1 of FIG. 7, first, the multi-chip substrate 10 is placed on the heat stage 8, and then the semiconductor chip 1 is held by the collet 11 (for example, vacuum suction holding). Etc.) and is carried on each device region 10c shown in FIG. When the semiconductor chip 1 is transferred onto the substrate by the collet 11, a die bond material 6 (for example, a resin paste material) shown in FIG. 4 is applied to each device region 10c of the multi-chip substrate 10 in advance. deep.

  After completion of die bonding, wire bonding shown in step S2 of FIG. 7 is performed. Here, the bonding pads 1c of the semiconductor chip 1 mounted on the multi-chip substrate 10 shown in FIG. 3 and the bonding leads 2c of the multi-chip substrate 10 (wiring substrate 2) are electrically connected via the wires 7. . In the wire bonding step, as shown in FIG. 7, first, a multi-piece substrate 10 is placed on the heat stage 12, and the semiconductor chip 1 and the multi-piece substrate 10 are connected to each other using a bonding tool 13 such as a capillary. 7 is electrically connected.

  After the wire bonding is completed, the molding shown in step S3 in FIG. 8 is performed.

  11 is a partial cross-sectional view showing an example of the structure of a molding die used in the molding process of assembling the semiconductor device of FIG. 1, and FIG. 12 is an example of the structure of the assembly after resin molding in the assembly of the semiconductor device of FIG. FIG. 13 is a sectional view showing an example of the structure cut along the line AA in FIG. 12, and FIG. 14 is a sectional view showing an example of the structure cut along the line BB in FIG. It is. 15 is a partial cross-sectional view showing an example of the rack storage state of the assembly in the mold baking process for assembling the semiconductor device of FIG. 1, and FIG. 16 shows an example of the structure cut along the line AA in FIG. FIG. 17 is a cross-sectional view showing an example of a laser irradiation state in the mark process for assembling the semiconductor device of FIG.

  In the molding step, first, a molding die 14 for resin sealing as shown in FIG. 11 is prepared. The molding die 14 according to the first embodiment includes an upper die (die) 15 and a lower die (die) 16 that form a pair and are opposed to each other. A main cavity (recess for upper surface) 15a for forming the sealing body 4 shown in FIG. 4, a gate 15d as a resin injection port for supplying the resin 3 to the main cavity 15a, next to the gate side of the main cavity 15a. The upper surface gate side cavity (upper surface recess) 15b, the upper surface gate side protrusion (protrusion) 15c provided between the main cavity 15a and the upper surface gate side cavity 15b, and the main cavity 15a are connected to the main cavity 15a. An air vent 15e that sends out air in the cavity 15a is formed.

  Further, the upper mold 15 is formed with a runner 15f and a cull 15g that serve as a flow path for the sealing resin 3 and are connected to the gate 15d. The gate 15d is connected to the upper surface gate side cavity 15b, and the resin 3 injected from the gate 15d is filled into the main cavity 15a through the upper surface gate side cavity 15b.

  On the other hand, the lower mold 16 disposed opposite to the upper mold 15 is opposed to the substrate placement surface 16a and the upper gate side cavity 15b disposed opposite to the main cavity 15a, and the gate of the substrate placement surface 16a. A lower surface gate side cavity (lower surface recess) 16b formed adjacent to the substrate side and a lower surface air vent side cavity (lower surface recess) 16c formed adjacent to the air vent side of the substrate mounting surface 16a.

  Further, the lower mold 16 is provided with a pot 16d and a plunger 16e for accommodating the cured resin (tablet) 3 and for extruding the molten resin 3 toward the runner 15f. A suction passage 16f for adsorbing and supporting the take-up substrate 10 is formed. The suction passage 16f is open to the substrate mounting surface 16a and has a structure capable of vacuum-sucking the multi-piece substrate 10 during molding.

  The upper surface gate side cavity 15b, the upper surface gate side protrusion 15c, the lower surface gate side cavity 16b, and the lower surface air vent side cavity 16c are arranged along the longitudinal direction of the multi-chip substrate 10 placed on the substrate placement surface 16a. It is elongated.

  That is, the lower gate side cavity 16b is formed in an elongated shape so as to correspond to the two through holes 10e arranged in a row of the multi-piece substrate 10 placed on the substrate placement surface 16a. Has been. Similarly, the lower air vent side cavity 16c is also formed in an elongated shape so as to correspond to the two through holes 10f arranged in a row on the multi-cavity substrate 10. Furthermore, the upper surface gate side cavity 15b is formed in a shape extending in the same manner at a position facing the lower surface gate side cavity 16b.

  The upper gate-side protruding portion 15c is formed to protrude so as to divide the upper mold cavity into a main cavity 15a and an upper gate-side cavity 15b. However, as shown in FIG. 11, the protrusion is formed so as not to come into contact with the multi-cavity substrate 10 at the time of mold clamping. That is, when the mold is clamped, the upper surface gate side protrusion 15c is formed with a protrusion amount so that a desired gap is formed between the tip of the upper surface gate side protrusion 15c and the multi-piece substrate 10. The main cavity 15a and the upper surface gate side cavity 15b communicate with each other through a gap.

  The upper gate-side protruding portion 15c may be formed with a protruding amount so as to come into contact with the multi-cavity substrate 10 at the time of mold clamping. In this case, the main cavity 15a and the upper gate-side cavity 15b May be communicated with any one of the peripheral regions outside the device region 10c (device region 10d) of the multi-chip substrate 10.

  The molding die 14 having the above structure is prepared, and then the multi-piece substrate 10 is placed on the substrate placement surface 16 a of the lower die 16.

  Specifically, the plurality of device regions 10c of the multi-cavity substrate 10 are located inside the main cavity 15a in plan view, and the upper gate-side protruding portion 15c is located outside the plurality of device regions 10c (a plurality of devices in plan view). Between the region 10c and the through hole 10e), the through hole 10e is located inside the lower surface gate side cavity 16b in a plan view, and the through hole 10f is located inside the lower surface air vent side cavity 16c in a plan view. In addition, the multi-cavity substrate 10 is disposed between the upper die 15 and the lower die 16 so that the lower surface 10 b of the multi-cavity substrate 10 faces the lower die 16. Thereafter, the multi-piece substrate 10 is vacuum-held by the substrate placement surface 16a through the suction passage 16f.

  After the substrate is placed, the upper mold 15 and the lower mold 16 are clamped (clamped). When the clamping is performed, a plurality of gates 15d are arranged along the long side 10i shown in FIG. 5 of the multi-cavity substrate 10, and the slit-like through hole 10e and the through hole 10f are formed of the long side 10i and the long side 10i, respectively. It arrange | positions along the long side 10j facing the long side 10i.

  Further, the plurality of device regions 10c on the upper surface 10a of the multi-cavity substrate 10 are covered with the main cavity 15a of the upper die 15 by the clamping of the molding die 14 as shown in FIG.

  Thereafter, in a state where the multi-cavity substrate 10 is heated to, for example, about 170 ° C. by the lower mold 16, the resin 3 melted in the pot 16d is pushed out by the plunger 16e, and the inside of the cavity is passed through the runner 15f and the gate 15d. Resin 3 is supplied by supplying resin.

  At this time, when the resin 3 is injected from the gate 15d, the resin 3 first enters the upper surface gate side cavity 15b and then enters the main cavity 15a. Further, it enters the lower surface gate side cavity 16b through the through hole 10e of the multi-cavity substrate 10. Further, the resin 3 that has moved to the main cavity 15a then enters the lower air vent side cavity 16c. Thus, the resin 3 injected from the gate 15d sequentially fills the upper surface gate side cavity 15b, the lower surface gate side cavity 16b, the main cavity 15a, and the lower surface air vent side cavity 16c, and is extruded from the main cavity 15a by the flow of the resin 3. The generated bubbles (air) are sent out to the air vent 15e.

  Thereby, the upper surface side sealing portion 17 that collectively seals the plurality of semiconductor chips 1 as shown in FIGS. 12 to 14, the plurality of device regions 10c, the through holes 10e, and the through holes 10f in FIG. The gate side lower surface sealing portion (which is formed integrally with the side sealing portion 17 and the through hole 10e, and is formed outside the plurality of device regions 10d on the lower surface 10b in FIG. 6 and seals the through hole 10e ( The lower surface side sealing portion, the reinforcing sealing portion, the lower surface side peripheral sealing portion) 18a, the upper surface side sealing portion 17 and the through hole 10f are integrally formed, and the lower surface 10b is outside the plurality of device regions 10d. And an air vent side lower surface sealing portion (lower surface side sealing portion, reinforcing sealing portion, lower surface side peripheral sealing portion) 18b which is formed in the same and seals the through hole 10f.

  The upper surface side sealing portion 17 is formed integrally with the main body sealing portion 17a and the main body sealing portion 17a that collectively seal the plurality of semiconductor chips 1, the plurality of device regions 10c, and the through holes 10f. In addition, it has a gate side peripheral sealing portion 17b which is a first peripheral sealing portion (upper surface side peripheral sealing portion) for sealing the through holes 10e provided outside the plurality of device regions 10c. The main body sealing portion 17a is formed by the main cavity 15a of FIG. 11, and the gate side peripheral sealing portion 17b is formed by the upper surface gate side cavity 15b.

  As shown in FIGS. 12 and 13, a recess 17d is formed between the main body sealing portion 17a and the gate side peripheral sealing portion 17b. The concave portion 17d is formed by the upper surface gate side protruding portion 15c. A recess sealing portion 17e is formed under the recess 17d. Therefore, the recessed portion sealing portion 17e is located between the main body sealing portion 17a and the gate side peripheral sealing portion 17b, and the thickness thereof is larger than that of the main body sealing portion 17a and the gate side peripheral sealing portion 17b. Is much thinner.

  Further, a gate side lower surface sealing portion 18a and an air vent side lower surface sealing portion 18b are formed on the lower surface 10b side. A large number of gate side lower surface sealing portions 18a and air vent side lower surface sealing portions 18b are formed. It is formed along only the long sides 10i and 10j of the substrate 10, and is not formed along the short side. That is, the gate side lower surface sealing portion 18 a and the air vent side lower surface sealing portion 18 b formed on the lower surface 10 b side of the multi-piece substrate 10 are formed only in the longitudinal direction of the multi-piece substrate 10.

  Here, the characteristics of the mold according to the first embodiment will be described.

  In the resin filling in the molding process of the first embodiment, the resin 3 injected from the gate 15d into the cavity is passed through the slit-like through hole 10e of the substrate 10 to form a flow cavity (resin pool) on the lower surface 10b side. A gate side lower surface sealing portion 18a is formed by flowing into the lower surface gate side cavity 16b. Similarly, on the air vent side, a large number of the resins 3 are taken and passed through the slit-like through holes 10f of the substrate 10 to flow into the lower air vent side cavity 16c, which is a flow cavity, to form the air vent side lower surface sealing portion 18b.

  Therefore, the through-holes 10e and 10f formed in the multi-cavity substrate 10 may be slit-like or a plurality of small holes as long as the resin 3 is large enough to pass. The through holes 10e and 10f are preferably provided on the extended line of the gate 15d.

  When the through holes 10e and 10f are slit-shaped, the air remaining in the cavity is easy to escape (becomes difficult to remain in the cavity) and is effective as a countermeasure against voids. Moreover, when the through-holes 10e and 10f are a plurality of small holes, the strength of the multi-chip substrate 10 can be increased as compared with the case of the slit shape.

  As described above, through holes 10e and 10f are formed in the multi-piece substrate 10, and the lower gate 16 cavity 16b and the lower air vent side cavity 16c are formed in the lower mold 16 of the molding die 14. Not only the main body sealing portion 17a and the gate side peripheral sealing portion 17b on the upper surface (front surface, chip mounting surface) 10a side of the substrate (wiring substrate 2) 10 but also the lower surface on the gate side on the lower surface (back surface, mounting surface) 10b side. Since the sealing portion 18a and the air vent side lower surface sealing portion 18b are formed, stress due to thermal expansion or thermal contraction can be generated also on the lower surface 10b side of the multi-chip substrate 10.

  Thereby, the stress which generate | occur | produces in both surfaces of the multi-cavity board | substrate 10 can be balanced, and the curvature of the multi-cavity board | substrate (assembly body) 10 in which sealing parts, such as the main body sealing part 17a, were formed is suppressed ( Reduction).

  Further, in the cavity formed by clamping the upper mold 15 and the lower mold 16 of the molding die 14, the filling pressure of the resin 3 flowing on the gate 15d side is compared with the filling pressure of the resin 3 flowing on the air vent 15e side. High (big). Therefore, in the cavity (concave portion) formed in the upper mold 15, the upper gate-side protruding portion 15 c is provided at a position overlapping between the region including the plurality of device regions 10 c and the outside (peripheral portion) of the region in plan view. By forming the resin 3 when the resin 3 is supplied to a portion (the main cavity 15a (upper surface concave portion, main body sealing portion concave portion)) of the plurality of device regions 10c in the cavity, the resin 3 The flow rate of the can be reduced.

  Thereby, the filling pressure of the resin 3 applied to the wire 7 formed in the device region 10c located on the gate 15d side can be reduced, and the problem that the wire 7 flows can be suppressed.

  That is, the flow rate of the resin 3 injected into the cavity from the gate 15d is once dropped by the upper gate-side protruding portion 15c to reduce the stress applied to the wire 7 in the vicinity of the gate 15d (to make the resin injection pressure uniform). ). Thereby, while the problem which the wire 7 deform | transforms can be suppressed, the problem which the wire 7 flows can also be suppressed. In recent years, since the wire diameter of the wire 7 tends to be thin, wire deformation and wire flow are likely to occur, which is very effective as a countermeasure against problems of wire deformation and wire flow.

  Further, since the through hole 10e and the lower gate side cavity 16b are provided, the resin 3 injected from the gate 15d can be immediately poured into the lower gate side cavity 16b, and the resin injection pressure from the gate 15d is dispersed. Can be suppressed.

  Thereby, generation | occurrence | production of a wire deformation | transformation and a wire flow can be suppressed.

  On the other hand, at a position far from the gate 15d (on the air vent 15e side), the flow rate of the injected resin 3 is further reduced. Therefore, if the area to be sealed (device area 10c) is large, the air vent 15e side (in plan view) The filling pressure of the resin 3 in the region including the device region 10c and the outside (periphery portion) of this region is reduced, and the air (void) remaining in the cavity of the upper mold 15 is removed. It becomes difficult.

  Therefore, unlike the first embodiment, the air vent 15e side is not formed with a protrusion such as the above-described upper gate-side protruding portion 15c, thereby suppressing a further decrease in the flow rate of the resin 3 on the air vent 15e side. The resin 3 can be reliably supplied to the lower surface air vent side cavity 16c, which is a recess formed in the lower mold 16.

  That is, since the above-mentioned protrusion is not provided on the air vent 15e side, and the through hole 10f and the lower surface air vent side cavity 16c are provided, the resin 3 can be poured into the lower surface air vent side cavity 16c vigorously. The air (void) can be discharged.

  Thereby, reduction of a void can be achieved.

  Further, the gate side lower surface sealing portion 18a and the air vent side lower surface sealing portion 18b are formed along only the long sides 10i and 10j of the multi-piece substrate 10, and are not formed along the short sides. This is because the multi-cavity substrate 10 is more warped in the long side direction than in the short side direction.

  Therefore, on the lower surface 10b side of the multi-piece substrate 10, the gate side lower surface sealing portion 18a and the air vent side lower surface sealing portion 18b are not connected in a ring shape or the like, and both are separated on the lower surface 10b. That is, the lower surface gate side cavity 16b for forming the gate side lower surface sealing portion 18a is not directly connected to the lower surface air vent side cavity 16c for forming the air vent side lower surface sealing portion 18b. Therefore, the resin is not supplied first into the lower surface air vent side cavity 16c located on the air vent side before the resin is completely filled in the main cavity (upper concave portion) 15a. Does not flow backward from the air vent side to the gate side. This makes it difficult for voids (air) to remain in the formed sealing portion.

  Thereby, it is possible to prevent the resin 3 previously flowing into the lower surface gate side cavity 16b from flowing back from the lower surface 10b side to the upper surface 10a side, and it is possible to prevent the back flow of voids.

  When the molding is completed as described above, as shown in step S3 of FIG. 8, the gate resin 19, the calresin 20, the runner resin 21 and the like are formed integrally with the upper surface side sealing portion 17 on the multi-cavity substrate 10. .

  After the completion of molding, mold baking shown in step S4 in FIG. 8 is performed. That is, the multi-piece substrate in which the main body sealing portion 17a and the gate side peripheral sealing portion 17b which are the upper surface side sealing portion 17 and the gate side lower surface sealing portion 18a and the air vent side lower surface sealing portion 18b are formed by the mold. (Assembly) 10 is placed on the support portion 22a of the rack 22 having a plurality of support portions 22a and stored in the rack 22, and the baking process is performed in this state.

  The rack 22 is box-shaped, and support portions 22a are provided at substantially equal intervals on the left and right inner walls so that a plurality of multi-chip substrates 10 can be accommodated in the vertical direction at approximately equal intervals. As shown in FIG. 16, both ends of the multi-sided substrate 10 on the long sides 10i and 10j side (width direction) shown in FIG. 5 are supported by the support portions 22a.

  That is, the rack 22 of the first embodiment employs a guide rail type so that the multi-piece substrate 10 can be easily taken out and stored by simply sliding the multi-piece substrate 10. Thereby, for example, even if the processing steps before and after storing the multi-piece substrate 10 in the rack 22 are in the guide rail type transfer mode, the transfer of the multi-piece substrate 10 to the guide rail 25 causes the substrate to slide. Therefore, the multiple substrate 10 can be easily stored and taken out from the rack 22.

  After the mold baking, the mark shown in step S5 in FIG. 8 is performed.

  In the first embodiment, after mold baking, the multi-piece substrate (assembly) 10 is conveyed to the mark processing section (another processing section or other processing section) 24 of the marking process using the guide rail 25, Marking is performed on the upper surface side sealing portion 17 on the multi-piece substrate 10 by the mark processing portion 24.

  More specifically, the guide rail 25 is connected to the opening of the rack 22, the height of the support portion 22 a of the rack 22 and the height of the guide rail 25 are matched, the multi-piece substrate 10 is slid out of the rack 22, and is carried out as it is. Then, the multi-piece substrate 10 is conveyed to the mark processing unit (another processing unit) 24 in the mark process by the guide rail 25 and guided to the upper surface side sealing portion on the multi-piece substrate 10. Marking is performed on the 17 main body sealing portions 17a. At that time, each time the multi-piece substrate 10 is carried out, the rack 22 is moved up and down to realign the height positions of the support portion 22a and the guide rail 25, and the multi-piece substrate 10 is sequentially taken from the rack 22 one by one. Is carried out on the guide rail 25.

  Here, the reason why the guide rail system is adopted when the multi-piece substrate (assembly) 10 is transported in the first embodiment will be described.

  First, the effect of the conveyance method using a guide rail system is demonstrated. In the guide rail system, as described above, it is easy to take out the multi-piece substrate (wiring substrate) 10 from the rack 22. That is, by using a rack 22 (a rack with a guide) having a support portion 22a that can be connected to the guide rail 25, the rack 22 is connected to the guide rail 25, and the multi-piece substrate 10 is simply taken out and slid out. Therefore, it is easy to transfer the multi-piece substrate 10 to the guide rail 25.

  In addition, the alignment of the multi-piece substrate 10 is easy as compared with the suction conveyance method. That is, in the case of the guide rail system, since the both end portions of the multi-piece substrate 10 are supported, the multi-piece board 10 can be easily positioned as compared with the suction conveyance system. For example, as an example of a guide rail type substrate positioning method, there is a method of positioning by inserting positioning pins into the positioning holes at both ends of the multi-piece substrate 10. By providing, the positioning pin is inserted into the positioning hole by sliding on the guide rail 25, and the multi-piece substrate 10 can be easily positioned.

  However, in the case of the suction conveyance method, the multi-piece substrate 10 must be lowered from above with respect to the positioning pins to insert the positioning pins into the positioning holes of the substrate, and the positioning pins are inserted into the positioning holes of the substrate. It is difficult to do itself.

  Further, the guide rail system is a support system in which only the both end portions of the multi-piece substrate 10 are supported by the guide rail 25, and the vicinity of the center portion of the substrate is opened and exposed without being blocked by the guide rail 25. Therefore, in the mark process or the like, the laser mark can be performed as it is supported by the guide rail 25. That is, after the multi-piece substrate 10 is taken out from the rack 22, the multi-piece substrate 10 is transported to the mark processing unit 24 of the marking process by the guide rail 25 and immediately supported in the state supported by the guide rail 25 as it is. Marking can be performed, and marking can be performed efficiently.

  In the case of the guide rail system, even a relatively heavy multi-chip substrate 10 with a sealing portion formed can be transported and has high load resistance. However, in the suction conveyance system, when the substrate becomes heavy, it may fall and cause conveyance failure.

  Here, conveyance methods other than the guide rail method in substrate conveyance will be described.

  As a means for transporting the substrate such as the multi-piece substrate 10 to the next (separate) process, for example, a method of transporting the substrate with the suction nozzle being sucked (suction transport method), and holding the peripheral portion of the substrate by the arm There are also a method of conveying in the state (arm conveying method), a method of conveying the substrate by a belt conveyor (belt conveyor method), and the like.

  However, in any method, since it is necessary to take out the substrate from the rack 22 once, it is difficult to simplify the manufacturing process. As for the suction conveyance method, when the substrate is warped, the suction nozzle is brought into contact with the warped substrate (here, the surface of the sealing portion), and the substrate is held by vacuum suction. The suction nozzle must be pressed against the substrate so that no gap is formed between the suction nozzle and the substrate (here, the surface of the sealing body). However, if this load is too strong, cracks are generated in the substrate, so that it is more difficult to transport the warped substrate by the suction conveyance method.

  Therefore, the guide rail method employed in the first embodiment allows easy removal and transfer of the multi-piece substrate 10 from the rack 22, and further considers ease of alignment and high load resistance. Then, it can be said that a great number of effects are obtained in the substrate transportation including the high reliability in the substrate transportation (crack resistance of the substrate), and the necessity is high.

  In the marking step, as shown in FIG. 17, marking is performed on the upper surface side sealing portion 17 on the multi-chip substrate 10 in a state where both ends in the width direction of the multi-chip substrate 10 are supported by the guide rail 25. That is, after the multi-piece substrate (assembled body) 10 is conveyed to the mark processing unit 24 in the mark process using the guide rail 25, the marking is performed in a state where the multi-piece substrate 10 is supported by the guide rail 25.

  The marking is performed, for example, by irradiating the laser 23a from the laser marker 23 installed above the guide rail 25 toward the main body sealing portion 17a of the upper surface side sealing portion 17 formed on the multi-piece substrate 10.

  In the first embodiment, since the guide rail system is used for transporting the multi-piece substrate 10, the multi-piece substrate 10 taken out from the rack 22 is quickly conveyed to the mark processing unit 24 in the mark process by the guide rail 25. Furthermore, since the marking can be performed while being supported by the guide rail 25 as it is, the marking process can be performed efficiently.

  That is, in assembling the BGA 9, there is a mark process after mold baking, and alignment is also required in this mark process. In the first embodiment, a multi-piece substrate (assembly body) from the mold bake process to the mark process is used. ) By adopting the guide rail system for transporting 10, the multi-piece substrate 10 taken out from the rack 22 as described above can be quickly transported to the marking process by the guide rail 25 and supported by the guide rail 25 as it is. Marking can be performed in the state. Therefore, the countermeasure against warping of the multi-chip substrate 10 (sealing portions are provided on both the front and back sides of the multi-chip substrate 10) so that the conveyance failure of the multi-chip substrate 10 during the transport by the guide rail 25 can be reduced. It becomes important to.

  After completion of the mark process in the mark process, ball mounting in step S6 shown in FIG. 9 is performed. That is, in the ball attaching step, the solder balls 5 are provided on each of the plurality of lands 2d on the lower surface 10b of the multi-piece substrate 10. For example, the solder balls 5 are provided by a ball adsorption method in which a plurality of solder balls 5 are adsorbed using a flat plate or the like and mounted as they are. Also in this ball attaching step, warpage of the multi-cavity substrate 10 is reduced by providing sealing portions on both front and back surfaces of the multi-cavity substrate (assembly) 10. The positional deviation can be reduced, and the solder balls 5 can be evenly arranged on all the lands 2d of the multi-chip substrate 10.

  After mounting the ball, individual pieces are cut in step S7 shown in FIG. In other words, the multi-piece substrate 10 is placed on the dicing stage 26 in the dicing process, the blade 27 is run, and the upper surface side sealing portion 17 and the multi-piece substrate 10 are cut together to form individual BGAs 9. Divide into pieces. However, the cutting is performed in a state where the multi-piece substrate 10 is attached to the tape, and the tape is not cut. Therefore, the individual BGAs 9 are not separated and each BGA 9 is attached to the tape. .

  In the individual piece cutting step, since the warpage of the multi-piece substrate 10 is reduced by providing sealing portions on both the front and back surfaces of the multi-piece substrate (assembly) 10, the blade 27 is used. It is possible to reduce misalignment when mounting in pieces.

  After completion of the piece cutting, packing and shipment shown in step S8 of FIG. 9 are performed. Here, the cut multi-chip substrate 10 (each cut BGA 9 attached to the tape) is stored in the packing bag 28 and shipped.

  In the substrate conveyance by the guide rail system of the first embodiment, if the multi-cavity substrate 10 is warped, there is a high possibility of causing conveyance failure. This will be described in detail with reference to FIGS. Here, FIG. 24 is a partial cross-sectional view showing the rack storage state of the assembly in the assembly of the semiconductor device of the comparative example comparatively examined by the inventors of the present application, and FIG. 25 shows the structure cut along the line AA in FIG. FIG. 26 is a partial cross-sectional view showing the structure cut along the line BB in FIG. As shown in FIGS. 24 to 26, when the multi-piece substrate (assembly) 50 formed with the upper surface side sealing portion 17 is stored in the rack 22, the multi-piece substrate 50 is warped. In addition, when the multi-piece substrate 50 comes into contact with or is rubbed against the support portion 22a (guide rail) of the rack 22, a conveyance failure occurs when the multi-piece substrate 50 is stored and taken out. In particular, in the multi-cavity substrate 50 having a rectangular planar shape, as shown in FIG. 24, warping occurs remarkably in the longitudinal direction (long side). As a result, the multi-cavity substrate is obtained at the location shown in FIG. Although both ends in the width direction of the substrate 50 are supported by the support portions 22a of the rack 22, the multi-chip substrate 50 is in a state of being lifted from the support portion 22a at the location shown in FIG. Therefore, a method of reducing this conveyance failure by widening the gap between the upper and lower rails of the guide rail 25 is conceivable. However, when the warp of the multi-chip substrate 10 is large, the multi-chip substrate 10 is detached from the rail itself and falls. Since there is a fear, it is not preferable to widen the space between the upper and lower rails of the guide rail 25.

  On the other hand, in the present embodiment, as described above, not only the upper surface (front surface, chip mounting surface) 10a side of the multi-piece substrate (wiring substrate 2) 10 but also the lower surface (back surface, mounting surface) 10b side is sealed. Since the stop portions (the gate side lower surface sealing portion 18a and the air vent side lower surface sealing portion 18b) are formed, it is possible to balance the stress generated on both surfaces of the multi-cavity substrate 10, and the multi-cavity substrate ( Warpage of the assembly 10) can be suppressed (reduced). Thereby, the conveyance method using the guide rail 25 is applicable.

(Embodiment 2)
18 is a plan view showing an example of the structure of the assembly after resin molding in the assembly of the semiconductor device according to the second embodiment of the present invention, and FIG. 19 is an example of the structure cut along the line AA in FIG. FIG. 20 is a partial cross-sectional view showing an example of the structure of a molding die used in the molding process for assembling the semiconductor device according to the second embodiment of the present invention. Further, FIG. 21 is a plan view showing the structure of the assembly after resin molding of the first modified example in the assembly of the semiconductor device according to the second embodiment of the present invention, and FIG. 22 shows the structure of the semiconductor device according to the second embodiment of the present invention. Sectional drawing which shows the structure of the assembly body after the resin molding of the 2nd modification in an assembly, FIG. 23 is sectional drawing which shows the structure of the 3rd modification of Embodiment 2 of this invention.

  In the second embodiment, as shown in FIGS. 18 and 19, in the upper surface side sealing portion 17 of the multi-piece substrate 10, the concave portion (formed in the sealing portion) is formed on the air vent side as well as the concave portion 17 d on the gate side. Therefore, the air vent side peripheral sealing portion 17c, which is the second peripheral sealing portion, is formed outside the main body sealing portion 17a.

  This is because if the concave portion (groove or diaphragm) 17d is formed only on one side (gate side) on the surface of the sealing portion, the balance of stress generated in the sealing portion may become unstable. Therefore, when attention is paid to further improving the flatness of the multi-piece substrate (assembly) 10 on which the sealing portion is formed, the concave portion is also formed on the air vent side in the width direction of the sealing portion of the multi-piece substrate 10. It is preferable to form a (groove or aperture) 17f against warping of the substrate.

  Therefore, the upper surface side sealing portion 17 is formed integrally with the main body sealing portion 17a that collectively seals the plurality of semiconductor chips 1 and the plurality of device regions 10c, and the main body sealing portion 17a. A gate side peripheral sealing portion (first peripheral sealing portion) 17b for sealing the through-hole 10e provided outside the device region 10c and a main body sealing portion 17a are formed integrally with the plurality of device regions. And an air vent side peripheral sealing portion (second peripheral sealing portion) 17c that seals the through-hole 10f provided outside 10c.

  Further, a concave portion 17f is formed between the main body sealing portion 17a and the air vent side peripheral sealing portion 17c, and a concave portion sealing portion 17g is formed below the concave portion 17f similarly to the gate side. Yes. The thickness of the recess sealing portion 17g is thinner than the main body sealing portion 17a and the air vent side peripheral sealing portion 17c.

  Further, as shown in FIGS. 18 and 19, the gate side peripheral sealing portion 17b and the air vent side peripheral sealing portion 17c are separated from each other and are not connected on the upper surface side. That is, the upper surface gate side cavity 15b for forming the gate side peripheral sealing portion 17b is not directly connected to the upper surface air vent side cavity 15h for forming the air vent side peripheral sealing portion 17c. It is connected via a main cavity 15a for forming. Thus, the upper surface gate side cavity 15b and the upper surface air vent side cavity 15h are separated, so that the upper surface located on the air vent side before the resin is completely filled in the main cavity (upper surface recess) 15a. Since the resin is not supplied first into the air vent side cavity 15h, the supplied resin does not flow backward from the air vent side toward the gate side. This makes it difficult for voids (air) to remain in the formed sealing portion. For the same reason, the lower surface gate side cavity 16b for forming the gate side lower surface sealing portion 18a is not directly connected to the lower surface air vent side cavity 16c for forming the air vent side lower surface sealing portion 18b. It is.

  Further, a recess 17f formed between the main body sealing portion 17a and the air vent side peripheral sealing portion 17c is formed on the air vent side of the cavity of the upper die 15 on the gate side as shown in the molding die 14 of FIG. An upper surface air vent side protrusion (second protrusion) 15i similar to the upper surface gate side protrusion (first protrusion) 15c is provided, and is formed by the upper surface air vent side protrusion 15i.

  Therefore, in the upper mold 15 of the molding die 14 used in the molding process of the second embodiment, the upper air vent side protrusion 15i is formed between the main cavity 15a and the upper air vent side cavity (upper surface recess) 15h. ing.

  That is, the cavity of the upper die 15 includes a main cavity (upper surface recess) 15a, an upper surface gate side cavity (upper surface recess) 15b disposed adjacent to the gate side of the main cavity 15a, and the main cavity 15a and the upper surface gate side. An upper surface gate side protrusion (protrusion) 15c provided between the cavities 15b, an upper surface air vent side cavity (recess for upper surface) 15h arranged next to the air vent side of the main cavity 15a, the main cavity 15a and the upper surface air vent And an upper air vent side protrusion (protrusion) 15i provided between the side cavities 15h.

  On the other hand, the lower die 16 is the same as the lower die 16 of the first embodiment, and is disposed next to the substrate placement surface 16a and the gate side of the substrate placement surface 16a and faces the upper surface gate side cavity 15b. It has a lower surface gate side cavity 16b and a lower surface air vent side cavity 16c that is disposed adjacent to the air vent side of the substrate placement surface 16a and faces the upper surface air vent side cavity 15h.

  Thus, when the upper mold 15 and the lower mold 16 are clamped, the upper gate-side protruding portion 15c is positioned outside the plurality of device regions 10c (between the plurality of device regions 10c and the through holes 10e) in plan view. Furthermore, the upper surface air vent side protrusion 15i is positioned outside the plurality of device regions 10c (between the plurality of device regions 10c and the through holes 10f) in plan view.

  In the second embodiment, batch molding is performed using the molding die 14 as described above, and the batch molding procedure is the same as that of the first embodiment.

  According to the mold of the second embodiment, the balance of stress generated in the sealing portion formed on the multi-piece substrate 10 can be stabilized, and the multi-piece substrate (on which the sealing portion is formed ( The flatness of the assembly 10) can be improved (warping of the substrate can be reduced).

  The other effects obtained by the second embodiment are the same as the effects of the first embodiment, and thus redundant description thereof is omitted.

  As mentioned above, the invention made by the present inventor has been specifically described based on the embodiments of the invention. However, the present invention is not limited to the embodiments of the invention, and various modifications can be made without departing from the scope of the invention. It goes without saying that it is possible.

  For example, the main body sealing portion 17a formed on the upper surface 10a of the multi-chip substrate 10 described in the first and second embodiments may be further divided. That is, as shown in the first modified example of FIG. 21, the planar shape is divided into two at approximately the center in the long side direction of the main body sealing portion 17 a having a quadrangle (here, a rectangle). The stress generated in the portion can be dispersed (reduced), and the warpage of the multi-chip substrate 10 can be further alleviated.

  22 is an example in which the gate resin 19 is formed on the lower surface 10b side of the multi-piece substrate 10. In the second modification shown in FIG. That is, a large number of gates 15d of the molding die 14 shown in FIG. 20 are arranged on the lower surface (back surface, mounting surface) 10b side of the substrate (wiring substrate) 10, and resin is directed from the lower surface 10b side to the upper surface 10a side of the substrate. 3 is supplied (injected) to form the gate side lower surface sealing portion 18a, the upper surface side sealing portion 17 and the air vent side lower surface sealing portion 18b.

  As a result, when the resin is filled, since the resin 3 passes through the through hole (via) formed between the upper surface 10a and the lower surface 10b of the multi-chip substrate 10, the flow rate of the supplied resin 3 can be suppressed. It is possible to reduce the occurrence of a problem of flowing (tilting) of wires (in particular, wires in a device region arranged at a position close to the gate 15d among the plurality of device regions).

  In the first and second embodiments, the BGA 9 has been described as an example of the semiconductor device. However, as shown in the third modification of FIG. 23, the semiconductor device is a land (electrode pad) of the wiring board 2. If the package 2d is not covered with resin, an LGA (Land Grid Array) 29 or the like on which the solder balls 5 are not mounted may be used.

  The present invention can be used for assembling an electronic device to which the batch molding method is applied.

DESCRIPTION OF SYMBOLS 1 Semiconductor chip 1a Front surface 1b Back surface 1c Bonding pad 2 Wiring board 2a Upper surface (surface, chip mounting surface)
2b Bottom surface (rear surface, mounting surface)
2c Bonding lead (electrode pad)
2d land (electrode pad)
3 Resin 4 Sealing Body 5 Solder Ball 6 Die Bond Material 7 Wire 8 Heat Stage 9 BGA (Semiconductor Device)
10 Multi-piece substrate (wiring board)
10a Upper surface 10b Lower surface 10c Device region (device region on the upper surface side)
10d Device area (lower side device area)
10e Slit (through hole)
10f Slit (through hole)
10 g Gate pattern 10 h Hole 10 i Long side 10 j Long side 11 Collet 12 Heat stage 13 Bonding tool 14 Molding die 15 Upper die (die)
15a Main cavity (recess for upper surface)
15b Upper surface gate side cavity (recess for upper surface)
15c Top gate side protrusion (protrusion)
15d Gate 15e Air vent 15f Runner 15g Cull 15h Upper air vent side cavity (recess for upper surface)
15i Top air vent side protrusion (protrusion)
16 Lower mold (mold)
16a Substrate mounting surface 16b Lower surface gate side cavity (lower surface recess)
16c Lower air vent side cavity (recess for lower surface)
16d Pot 16e Plunger 16f Suction passage 17 Upper surface side sealing portion 17a Main body sealing portion 17b Gate side peripheral sealing portion (peripheral sealing portion)
17c Air vent side peripheral sealing part (peripheral sealing part)
17d Concave part 17e Concave part sealing part 17f Concave part 17g Concave part sealing part 18a Gate side lower surface sealing part (lower surface side sealing part, reinforcing sealing part, lower surface side peripheral sealing part)
18b Air vent side lower surface sealing part (lower surface side sealing part, reinforcing sealing part, lower surface side peripheral sealing part)
19 Gate Resin 20 Cal Resin 21 Runner Resin 22 Rack 22a Support Unit 23 Laser Marker 23a Laser 24 Mark Processing Unit (Another Processing Unit)
25 Guide Rail 26 Dicing Stage 27 Blade 28 Packing Bag 29 LGA (Semiconductor Device)
50 Multi-chip substrate

Claims (14)

A method for manufacturing a semiconductor device comprising the following steps:
(A) an upper surface, a lower surface opposite to the upper surface, a first through hole formed from one of the upper surface and the lower surface toward the other, and the one of the upper surface and the lower surface A second through hole formed toward the other side, and a plurality of upper surface side device regions formed in the upper surface and provided between the first through hole and the second through hole in a plan view. A plurality of bonding leads formed on each of the plurality of upper surface side device regions, and a plurality of bonding leads formed on the lower surface and provided between the first through hole and the second through hole in plan view. Preparing a wiring board comprising: a lower-surface-side device region; and a plurality of lands formed in each of the plurality of lower-surface-side device regions;
(B) mounting a plurality of semiconductor chips on the plurality of upper surface side device regions;
(C) an upper surface side sealing portion that collectively seals the plurality of semiconductor chips, the plurality of upper surface side device regions, the first through hole, and the second through hole; and the upper surface side sealing portion; A first lower surface side sealing portion that is formed integrally with the first through hole and is formed outside the plurality of lower surface side device regions on the lower surface, and that seals the first through hole; The upper surface side sealing portion and the second through hole are integrally formed, and the lower surface is formed outside the plurality of lower surface side device regions, and the second through hole is sealed. Forming a second lower surface side sealing portion;
(D) After the step (c), using the guide rail, the wiring board on which the upper surface side sealing portion, the first lower surface side sealing portion, and the second lower surface side sealing portion are formed is used. The process of conveying to another processing part. In claim 1,
The upper surface side sealing portion is formed integrally with the main body sealing portion and the main body sealing portion that collectively seals the plurality of semiconductor chips, the plurality of upper surface side device regions, and the second through hole. And a first peripheral sealing portion that seals the first through-hole provided outside the plurality of upper surface side device regions. In claim 1,
The upper surface side sealing portion is formed integrally with the main body sealing portion that collectively seals the plurality of semiconductor chips and the plurality of upper surface side device regions, and the plurality of the main surface sealing portions. A first peripheral sealing portion that seals the first through hole provided outside the upper surface side device region, and is formed integrally with the main body sealing portion, and outside the plurality of upper surface side device regions. A method of manufacturing a semiconductor device, comprising: a second peripheral sealing portion that seals the second through hole provided. In claim 2,
A method of manufacturing a semiconductor device, wherein a recess is formed between the main body sealing portion and the first peripheral sealing portion. In claim 3,
A recess is formed between the main body sealing portion and the first peripheral sealing portion, and between the main body sealing portion and the second peripheral sealing portion, respectively. Manufacturing method. In claim 5,
The method of manufacturing a semiconductor device, wherein the first peripheral sealing portion and the second peripheral sealing portion are separated from each other. In claim 1,
The wiring board has a rectangular planar shape, and the first lower surface side sealing portion and the second lower surface side sealing portion are formed along only the long side of the wiring substrate. Device manufacturing method. In claim 1,
The wiring board has a rectangular planar shape, and when clamped in the molding die in the step (c), a plurality of gates are arranged along the first long side of the wiring board, and the first through holes and The method of manufacturing a semiconductor device, wherein the second through hole is disposed along the first long side and the second long side opposite to the first long side. In claim 1,
A plurality of the first through holes and the second through holes are provided, and the first through holes and the second through holes are arranged on an extension line extending along a side of the wiring board. A method for manufacturing a semiconductor device. In claim 1,
The method of manufacturing a semiconductor device, wherein the step (d) is a mark step of marking the upper surface side sealing portion. In claim 1,
After the step (d), there is further provided a ball attaching step for providing solder balls on the plurality of lands of the wiring board, and a dicing step for dividing the individual semiconductor devices into individual pieces. Production method. In claim 1,
In the step (c), a resin is injected from a gate of a molding die disposed on the lower surface side of the wiring board to seal the first lower surface side sealing portion, the upper surface side sealing portion, and the second lower surface side sealing. A method of manufacturing a semiconductor device, comprising forming a stop. In claim 1,
After the step (c), the wiring board on which the upper surface side sealing portion, the first lower surface side sealing portion, and the second lower surface side sealing portion are formed, the support portion of the rack having a support portion. It is placed on the rack and accommodated in the rack, and then the support part of the rack and the guide rail are connected, and the wiring board is conveyed to the other processing part by the guide rail. A method for manufacturing a semiconductor device. In claim 10,
In the marking step, a marking is performed on the upper surface side sealing portion on the wiring board in a state where both ends of the wiring board are supported by the guide rail.

Images