JP2012190900A - Semiconductor device and method of manufacturing the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device capable of embedding a contact layer formed of a plated layer in a contact hole favorably so as to perform electrical connection between an upper layer and a lower layer.SOLUTION: There is provided a semiconductor device comprising: wiring layers 12, 16; a contact hole 14 having a triangular planar shape at least in a bottom part; and a contact layer 15 formed of a plated layer, formed by being embedded in the inside of the contact hole 14, and connected to the wiring layers 12, 16.

Description

  The present technology relates to a semiconductor device and a manufacturing method thereof.

  Conventionally, in order to electrically connect a lower conductor layer and an upper conductor layer, a via hole penetrating a semiconductor layer or an insulating layer between these conductor layers is formed, and then a conductor is placed in the via hole. A contact layer is buried to connect the upper and lower conductor layers.

For the contact layer embedded in the via hole, for example, electrolytic copper plating is used.
This electrolytic copper plating has the effect of the additive that the accelerator of the plating additive is adsorbed to the bent portion (concave portion) of the bottom of the via hole, and the accelerator is concentrated as the plating grows. This effect is characterized in that the growth of plating from the bottom of the via hole is accelerated.
Further, the leveler of the plating additive has a feature of gathering at the convex portions where electrons are easily accumulated during plating and suppressing plating (for example, see Non-Patent Document 1).
Generally, when forming a via hole, the lower metal wiring layer is connected to the contact layer, so that the process of forming the via hole on the lower metal wiring layer is stopped using a dry etching method or the like. Yes. For this reason, when wirings are stacked from the lower layer, the bottom of the contact hole is generally a flat surface.

A planar shape of a via hole for wiring of a semiconductor device is generally a square (see, for example, Patent Document 1). In addition to the square, there are also planar shapes such as a rectangle (see Patent Document 2) and a regular octagon (see Patent Document 3).
In general, when the via hole has a size just below the exposure limit, a square shape such as a square is rounded during exposure or dry etching.

By the way, for example, when a via hole is formed in a semiconductor layer by a so-called via first process, the via hole may be formed halfway through the semiconductor layer using a dry etching method. In this case, since the etching selection ratio cannot be taken sufficiently, the bottom of the via hole becomes U-shaped.
Further, in the case of forming a via hole by laser processing in a so-called via last process, since the laser ablation method is used, there is no concept of processing selectivity, and the bottom of the via hole is similarly U-shaped.

Japanese Patent No. 4333931 Japanese Patent Laid-Open No. 03-42838 Japanese Patent No. 2789743

A.C. West, S. Mayer and J. Reid, Electrochem. Solid-State Lett., 4, C50 (2001)

  When the upper and lower layers are electrically connected by embedding a contact layer made of a plating layer in a contact hole such as a via hole, the space inside the contact hole cannot be completely filled due to poor embedding. May cause embedded voids.

  An object of the present technology is to provide a semiconductor device having a structure in which the burying property of a contact layer is improved when a contact layer made of a plating layer is embedded in a contact hole to electrically connect upper and lower layers, and a method of manufacturing the same. Is.

  The semiconductor device of the present technology includes a wiring layer and two or more shapes which are composed of two or more surfaces at least at the bottom, and have an outwardly convex acute angle or the acute angle tip portion replaced with a curve. A contact hole having a planar shape. The contact layer includes a contact layer that is formed of a plating layer, is formed by filling the inside of the contact hole, and is connected to the wiring layer.

  The method for manufacturing a semiconductor device according to the present technology includes a step of forming a wiring layer and an insulating layer including the wiring layer therein. The insulating layer has a planar shape including two or more shapes in which the side surface is composed of two or more surfaces at least at the bottom, and the outwardly convex acute angle or the sharp tip portion is replaced with a curve. Forming a contact hole reaching the layer. Furthermore, a step of forming a contact layer so as to fill the inside of the contact hole and connect to the wiring layer by electrolytic plating is included.

  Another method for manufacturing a semiconductor device of the present technology includes a step of forming a wiring layer and an insulating layer including the wiring layer on a semiconductor substrate. And, the wiring layer and the semiconductor substrate and the insulating layer between them, at least at the bottom, the side surface is composed of two or more surfaces, and the outwardly convex acute angle or acute tip portion is replaced with a curve, A step of forming a contact hole having a planar shape including two or more. Furthermore, a step of forming a contact layer so as to fill the inside of the contact hole and connect to the wiring layer and the semiconductor substrate by electrolytic plating is included.

According to the above-described configuration of the semiconductor device of the present technology, at least at the bottom portion, two sides are formed by two or more sides, and the acute angle that protrudes outward or the tip portion of the acute angle is replaced with two curves. A planar contact hole including the above is formed. A contact layer made of a plating layer is formed so as to fill the inside of the contact hole.
Since the bottom of the contact hole has a planar shape that includes two or more shapes that have an acute convex or sharp tip replaced with a curve, plating is performed at a location where the sharp or sharp tip is replaced with a curve. The growth rate of plating when forming the layer can be increased.
As a result, the plating rate from the bottom of the contact hole is increased, and the bottom is quickly filled with the plating layer. Since the bottom portion is quickly filled with the plating layer, it is possible to prevent the upper portion from being buried before the bottom portion is sufficiently filled, thereby generating a buried void.
Therefore, it is possible to improve the embedding property when the plating layer is embedded in the contact hole by the electrolytic plating method.

According to the above-described method for manufacturing a semiconductor device of the present technology, the insulating layer is formed of two or more sides at least at the bottom, and the outwardly convex acute angle or acute angle tip is replaced with a curve. A contact hole having a planar shape including two or more is formed. Then, a contact layer is formed by electrolytic plating so as to fill the inside of the contact hole and connect to the wiring layer.
Since the bottom of the contact hole has a planar shape that includes two or more shapes that have an acute convex or sharp tip replaced with a curve, plating is performed at a location where the sharp or sharp tip is replaced with a curve. The growth rate of plating when forming the layer can be increased.
As a result, the plating rate from the bottom of the contact hole is increased, and the bottom is quickly filled with the plating layer. Since the bottom portion is quickly filled with the plating layer, it is possible to prevent the upper portion from being buried before the bottom portion is sufficiently filled, thereby generating a buried void.
Therefore, it is possible to improve the burying property of the plating layer in the step of forming the contact layer by filling the inside of the contact hole by electrolytic plating.

According to another method for manufacturing a semiconductor device of the present technology described above, the insulating layer has an acute angle or an acute angle tip portion that is composed of two or more side surfaces at least at the bottom and is convex outward. A contact hole having a planar shape including two or more shapes is formed. Then, the contact layer is formed by electrolytic plating so as to fill the inside of the contact hole and connect to the wiring layer and the semiconductor substrate.
As a result, as in the method of manufacturing a semiconductor device according to the present technology, the bottom portion is quickly filled with the plating layer, so that it is possible to prevent the upper portion from being buried before the bottom portion is sufficiently filled and the formation of a buried void.
Therefore, it is possible to improve the burying property of the plating layer in the step of forming the contact layer by filling the inside of the contact hole by electrolytic plating.

According to the above-described present technology, since it is possible to improve the embedding property when the plating layer is embedded in the contact hole by the electrolytic plating method, the contact made of the plating layer that electrically connects the lower layer and the upper layer. It becomes possible to improve the connection reliability of the layers.
Therefore, a highly reliable semiconductor device can be realized by the present technology.

1 is a schematic configuration diagram (cross-sectional view) of a semiconductor device according to a first embodiment; FIG. 2 is a plan view of the semiconductor device of FIG. 1. 2A to 2D are manufacturing process diagrams illustrating a manufacturing method of the semiconductor device of FIG. EG is a manufacturing process diagram showing the manufacturing method of the semiconductor device of FIG. It is a top view of the state of Drawing 3B. It is sectional drawing of the semiconductor device of the modification with respect to 1st Embodiment. It is a figure explaining the modification of the planar shape of AC contact hole. It is a figure explaining the curvature radius of the corner | angular part of A and B contact holes. It is the perspective view of the structure which changed the shape of the contact hole by the upper part and the lower part. It is a schematic block diagram (sectional drawing) of the semiconductor device of 2nd Embodiment. It is a top view of the semiconductor device of FIG. 11 is a manufacturing process diagram illustrating a manufacturing method of the semiconductor device of FIG. It is sectional drawing of the semiconductor device of the modification with respect to 2nd Embodiment. It is sectional drawing of the semiconductor device of the modification with respect to 2nd Embodiment. It is a schematic block diagram (sectional drawing) of the semiconductor device of 3rd Embodiment. FIG. 16 is a plan view of the semiconductor device of FIG. 15. FIG. 16 is a manufacturing process diagram illustrating the manufacturing method of the semiconductor device of FIG. 15; It is sectional drawing of the semiconductor device of the modification with respect to 3rd Embodiment. It is a schematic block diagram (sectional drawing) of the semiconductor device of 4th Embodiment. FIG. 20 is a plan view of the semiconductor device of FIG. 19. A and B are manufacturing process diagrams showing a manufacturing method of the semiconductor device of FIG. AC is a cross-sectional view of a semiconductor device according to a modification of the fourth embodiment. It is a cross-sectional photograph before completing the filling of the plating layer when the planar shape of the contact hole is a triangle and the bottom is a flat surface. It is a cross-sectional photograph before completing the filling of the plating layer when there is a convex portion at the bottom of the contact hole.

The best mode for carrying out the present technology (hereinafter referred to as an embodiment) will be described below.
The description will be given in the following order.
1. 1. Overview of this technology First Embodiment 3. FIG. Second embodiment 4. Third embodiment 5. Fourth embodiment

<1. Overview of this technology>
First, prior to description of specific embodiments, an outline of the present technology will be described.

When a large via hole having a size of several μm, such as TSV (through silicon via), is embedded with a plating layer, if the shape of the bottom of the via hole is U-shaped as described above, the embedded void Sometimes formed.
This is because the concentration of the plating accelerator (accelerator) on the U-shaped bottom of the via hole is slower than the case of having a flat bottom like the via hole formed on the embedded wiring, and the growth of electrolytic copper plating This is because the conformal depot becomes stronger. As a result, as the plating grows, the aspect ratio of the space to be filled becomes high, and the upper portion is buried before the bottom portion is sufficiently filled, so that a buried void may be formed.
The accelerator, which is a plating additive, has a function of being concentrated in the recess. If the bottom of the via hole is U-shaped, the center of the bottom becomes deep, and therefore the concentration of the accelerator is delayed compared to the case where the bottom of the via hole is a flat surface.

Further, if there is a convex portion on the bottom surface of the via hole, a plating additive leveler selectively adheres to the convex portion where electrons are likely to gather during plating, thereby suppressing plating.
Therefore, since the plating growth is suppressed at the convex portion on the bottom surface of the via hole, the upper portion is buried before the bottom portion is sufficiently filled, and a buried void is easily formed.

The planar shape of a contact hole formed by a via hole or the like is generally a shape that does not have a uniform corner consisting of a single curve, such as a circle, or a square, a rectangle, an octagon, The inner angle of the corner is 90 degrees or more (right angle or obtuse angle).
In the case of these planar shapes, a sufficient growth rate from the side surface of the contact hole cannot be secured, so that a buried void is easily formed.

  In response to the above-described problems, the function of the plating additive, that is, the function of concentrating the accelerator (accelerator) in the concave part and the function of concentrating the leveler in the convex part, is used to fill the contact hole. It is possible to improve.

Therefore, in this technology, the planar shape of at least the bottom part of the contact hole is not a circle or a quadrangle, but a triangle, a polygon having an acute angle at the inner angle (a sharp angle protruding outward), or the like, or the tip of the acute angle is replaced with a curve. Shape.
By forming a substantially V-shaped groove having an angle of less than 90 ° on the side wall of the contact hole so that there is a portion where the angle between the side surface and the side surface of the contact hole is less than 90 ° as this planar shape, Improve plating layer deposition from side grooves.

In addition, when there is a convex portion on the side wall of the via hole, the level of the plating additive is present on the convex portion where electrons are likely to gather, as in the case where the convex portion is present on the bottom surface of the via hole. Selectively adheres and suppresses plating.
When such a convex portion exists on the side wall of the via hole, the effect of improving the deposition rate due to the substantially V-shaped groove on the side wall of the hole is canceled.
Therefore, when the contact hole has a planar shape that is more than 180 degrees and includes a polygon that includes an inner angle that is convex inward, such as a star shape, the line on both sides that forms the angle (that is, the convex inward) It is preferable to replace the two sides between the corners with arcs in contact with those lines. Thereby, it can prevent that an electric current concentrates on a convex part at the time of metal plating.

When a contact hole reaching the wiring layer is formed on the wiring layer, the bottom surface of the contact hole becomes a flat surface.
In the contact hole having the planar shape described above, the bottom surface of the contact hole is further flattened to accelerate the growth of plating from the recesses formed by the three surfaces (the bottom surface and the two side surfaces) in the contact hole. Can do. As a result, the bottom-up effect in the entire contact hole can be enhanced and embedded voids can be suppressed.

Further, when the bottom surface of the contact hole is U-shaped, as described above, the burying property of the plating layer is inferior compared with the case where the bottom surface of the contact hole is a flat surface.
However, even if the bottom surface of the contact hole is U-shaped, if the present technology is applied and the planar shape of the bottom portion of the contact hole has a configuration in which an acute angle or a sharp tip portion is replaced with a curve, plating is performed. The embedding property of the layer can be improved. This makes it possible to improve the embedding property of the plating layer and suppress the generation of embedding voids as compared with the case where the planar shape is circular or square and the bottom surface is U-shaped.

  Here, the planar shape of the contact hole and the growth of the plating layer when the plating layer is formed by filling the contact hole will be described in more detail.

First, consider a case where a contact hole in which the planar shape of the entire contact hole is a triangle is formed by applying the present technology to a contact hole connecting a lower wiring layer and an upper wiring layer.
When such a contact hole is formed by connecting to a lower wiring layer (same as a pad layer made of the same conductor layer as the wiring layer), the bottom surface of the contact hole is flat and the side surface of the contact hole is The shape is such that three planes corresponding to the triangle are provided.
When a contact hole having such a shape is plated using an electrolytic copper plating solution used for copper wiring of a semiconductor device, the accelerator is adsorbed in the concave portion at the bottom of the hole, and the accelerator is concentrated as the plating grows. Happens. Accordingly, as shown in FIG. 23, which is a cross-sectional photograph before the filling of the plating layer is completed, the growth of the plating at the corner portion of the bottom surface of the hole becomes faster than the central portion of the bottom surface and the side surface of the upper portion of the contact hole.
Therefore, when a contact hole having a triangular bottom shape is formed, the plating speed from the corner of the bottom surface of the hole is higher than that of a conventional contact hole having a round shape or a square shape. Increases nature.

Thus, the planar shape in which the portion where the contact angle between the side surface and the side surface of the contact hole is less than 90 ° exists is not limited to a triangle.
For example, a star shape or the shape shown in FIG. 7A can be considered.
However, such a polygon has an inner angle larger than 180 ° on the side surface of the contact hole.

For example, in the case where the bottom surface of the contact hole has an upward convex portion, as described above, the plating speed of the convex portion becomes slow due to the effect of the accelerator and the leveler in the plating solution. For this reason, as shown in FIG. 24, a cross-sectional photograph before the embedding is completed, the plating speed of the convex portion surrounded by a dotted line is slowed, thereby weakening the bottom-up effect from the bottom corner indicated by the arrow in the figure. End up.
When the contact hole has an internal angle of 180 ° or more in the planar shape of the contact hole, the inner side has a convex part facing inward on the side wall of the contact hole. The embeddability of the layer is reduced.
Therefore, when the contact hole includes an internal angle of 180 ° or more in the plan shape of the contact hole, the line forming the angle (that is, the two sides sandwiching the inwardly convex corner) is replaced with an arc whose tangent is the line. Structure (see FIGS. 7B and 7C).
As a result, it is possible to reduce the influence of the convex portion during plating and to form a large number of locations in the contact hole where the angle between adjacent surfaces is less than 90 ° (acute angle). It can be made faster than the conventional shape.

Note that the corners (such as the apex of a triangle) of the planar shape of the contact hole have a curvature strictly because they have a resolution or processing limit during lithography and dry etching processing.
In addition, the present technology can be applied even when the corner portion has a curvature and the sharp tip portion of the planar shape is replaced with a curved line. By applying this technique, even when the sharp tip portion of the planar shape is replaced with a curve, the deposition rate of the plating layer from the tip portion can be increased, and the embedding property can be improved.
More preferably, the radius of curvature of the sharp tip portion (corner portion) of the planar shape of the contact hole is shorter than half the length of the shortest side of the planar polygon (see FIGS. 8A and 8B). ). By satisfying this condition, it is possible to sufficiently accelerate the deposition of the plating layer even when the corners are rounded.

<2. First Embodiment>
FIG. 1 shows a schematic configuration diagram (cross-sectional view) of the semiconductor device according to the first embodiment.
In this semiconductor device, a lower first wiring layer 12 and an upper second wiring layer 16 are electrically connected by a contact layer 15 embedded in a contact hole 14.

The first wiring layer 12 is formed by embedding a metal layer in a recess (groove) formed on the upper surface of the insulating layer 11.
The second wiring layer 16 and the contact layer 15 are formed of plating layers formed simultaneously.
The contact hole 14 is formed so as to penetrate the insulating layer 13 in the vertical direction.
The second wiring layer 16 is formed by embedding a plating layer in a recess (groove) formed on the upper surface of the insulating layer 13.

As the material of the metal layer of the first wiring layer 12, various metals and alloys used for wiring and electrodes can be used.
As a material of the plating layer of the second wiring layer 16 and the contact layer 15, a metal material that can be formed by copper or other plating can be used.
For example, a silicon oxide layer is used as the insulating layer 13, but two or more different insulating layers such as a silicon nitride layer and a silicon oxide layer may be stacked.

  Note that circuit elements such as transistors and capacitors are formed in portions not shown, and the circuit elements and the first wiring layer 12 or the second wiring layer 16 are electrically connected.

The present embodiment is particularly characterized by the planar shape of the contact hole 14.
The planar shape of the contact hole 14 is not a circle or a rectangle that has been conventionally used, but is, for example, a triangle as shown in the plan view of the semiconductor device in FIG.
In FIG. 2, only the first wiring layer 12, the contact hole 14, the contact layer 15, and the second wiring layer 16 are shown, and the surrounding insulating layers 11 and 13 are omitted.
As described above, since the planar shape of the contact hole 14 is a triangle, the side wall portion of the contact hole 14 that corresponds to the corner of the triangle is a V-shaped groove.
Thereby, the deposition from this V-shaped groove can be improved.

In FIG. 1, only the two wiring layers 12 and 16 are shown. However, in the present embodiment, it is possible to form a wiring layer in the upper layer to form three or more wiring layers.
In that case, it is preferable that each wiring layer provided above the second layer from the bottom has the same configuration as that of the contact layer 15 and the second wiring layer 16 in FIG.

The semiconductor device of the present embodiment can be manufactured, for example, as described below.
First, the first wiring layer 12 is formed in a recess (groove) formed on the upper surface of the insulating layer 11.
Thereafter, as shown in FIG. 3A, the insulating layer 13 is formed on the insulating layer 11 and the first wiring layer 12. As described above, the insulating layer 13 may have a structure in which two or more different types of insulating layers such as a silicon nitride layer (for a hard mask or the like) and a silicon oxide layer are stacked.

Next, a resist is formed on the insulating layer 13 and patterned by exposure and development to form a resist mask 51 having a pattern having an opening 51A corresponding to the contact hole as shown in FIG. 3B. To do.
At this time, as shown in a plan view in FIG. 5, the planar shape of the opening 51A of the resist mask 51 is a triangle.

  Next, the insulating layer 13 is etched using the resist mask 51 to form a contact hole 14 reaching the first wiring layer 12 as shown in FIG. 3C. The bottom surface of the contact hole 14 is the top surface of the first wiring layer 12 and is a substantially flat surface.

  Next, by forming a resist on the insulating layer 13 and patterning the resist by exposure and development, a resist mask having a pattern having an opening 52A corresponding to the second wiring layer as shown in FIG. 3D. 52 is formed.

  Next, by etching the upper portion of the insulating layer 13 using the resist mask 52, as shown in FIG. 4E, the recess 13A corresponding to the second wiring layer is formed in the insulating layer 13.

Next, although not shown, a barrier metal for plating is formed on the entire surface. As the barrier metal, for example, Ta or TaN can be used.
Further, although not shown, a thin seed film of the same material as the plating material is formed on the barrier metal. For example, when the plating material is copper, a copper film is formed as a seed film.
Thereafter, by performing electroplating, a plating layer is deposited on the seed film, and as shown in FIG. 4F, the inside of the contact hole 14 and the recess 13A of the insulating layer 13 is filled to form a plating layer 18. be able to. Of the plating layer 18, the portion inside the contact hole 14 becomes the contact layer 15, and the portion inside the recess 13 </ b> A of the insulating layer 13 becomes the second wiring layer 16.

Subsequently, the plating layer 18 above the insulating layer 13 is removed by a CMP (Chemical Mechanical Polishing) method or the like. As a result, as shown in FIG. 4G, the contact layer 15 and the second wiring layer 16 made of a plating layer remain.
In this way, the semiconductor device shown in FIG. 1 can be manufactured.

According to the configuration of the semiconductor device of the present embodiment described above, the contact layer 15 made of a plating layer and electrically connecting the first wiring layer 12 and the second wiring layer 16 has a triangular planar shape. It is formed in a certain contact hole 14. As a result, the contact angle between the side surfaces of the contact hole 14 is an acute angle, and a V-shaped groove is formed on the side wall of the contact hole 14. Therefore, when electrolytic plating is performed, the V-shaped groove is formed. Can improve the deposition rate. For this reason, the plating rate from the bottom of the contact hole 14 is increased, and the bottom is quickly filled with the plating layer.
Therefore, since the embedding property of the plating layer can be improved and the embedding void can be hardly generated in the contact hole 14, the contact layer that electrically connects the first wiring layer 12 and the second wiring layer 16. The connection reliability of 15 can be improved.

Further, even if the width of the contact hole 14 is reduced, it is possible to embed a plating layer in the contact hole 14 satisfactorily without generating a buried void.
Therefore, the width of the contact hole 14 can be reduced to reduce the size of the chip including the contact hole 14, and the cost of the chip can be reduced.

Next, FIG. 6 shows a cross-sectional view of a modified example of the semiconductor device of the first embodiment.
As shown in FIG. 6, a semiconductor substrate 17 made of a semiconductor such as silicon is formed in the middle of the insulating layer 13 in FIG. 1, and a contact hole 14 and a contact layer 15 are formed through the semiconductor substrate 17. Has been.
As a material for the semiconductor substrate 17, various semiconductors such as germanium and compound semiconductors such as GaAs can be used in addition to silicon.

  In the case of manufacturing a semiconductor device having this configuration, the etching material and conditions for forming the contact hole 14 may be changed as appropriate between when the insulating layer 13 is etched and when the semiconductor substrate 17 is etched. Good.

  Next, another example of the planar shape of the contact hole 14 in the semiconductor device of the present embodiment will be described.

For example, when the planar contact hole 101 as shown in FIG. 7A is formed, the convex portions have acute angles, but the internal angle between the convex portions is 180 degrees or more. As described above, since the level of the plating additive selectively adheres and suppresses the plating at the inner angle of 180 degrees or more, the deposition of the plating layer is delayed.
Therefore, as shown in FIG. 7B, in a portion where the inner angle α is 180 degrees or more, instead of the two straight lines 102 sandwiching the inner angle α, the arc 103 is in contact with the two straight lines 102. As a result, the contact hole 104 having a planar shape shown in FIG. 7C is formed, and the internal angle of 180 degrees or more is eliminated.
In FIG. 7A, the planar shape has six acute angles. However, even if the number of acute angles is another number (three or more), such as a star shape (five acute angles), the shape is 180. It is possible to replace an internal angle of more than degrees with an arc.

Further, as the semiconductor device is further miniaturized, even if it is designed to make an acute angle at the corner of the planar shape of the contact hole, the corner is rounded in the actually formed pattern. Even when the corners are rounded in this way, it is possible to form a plating layer without generating voids.
For example, consider a case where the planar shape of the contact hole is designed to be a triangle composed of three sides 41, 42, 43 as shown in FIG. 8A. In this case, the radius of curvature r of the corner shown in FIG. 8B is made smaller than half the length L of the shortest side 42 among the three sides of the triangle. That is, r <L / 2.
This makes it possible to form a plating layer without generating voids even when the corners are rounded.

Further, when the planar shape shown in FIGS. 7 and 8 is applied, for example, a spindle-shaped planar shape can be considered in addition to the polygonal shape. Then, if the spindle-shaped tip is sharpened at an acute angle or the radius of curvature is made sufficiently smaller than other portions, the deposition rate from the spindle-shaped tip can be increased.
However, if the spindle length / width ratio is increased too much, the spindle width direction closes earlier than the spindle length direction. Therefore, considering the deposition rate of the plating layer and the spindle type dimension, The width and width are set to an appropriate ratio.

FIG. 9 is a perspective view of a contact hole having still another configuration.
As shown in FIG. 9, the lower portion 14A of the contact hole 14 including the vicinity of the bottom where the embedded void is likely to be generated by the plating method has a shape having a V-shaped groove on the side wall as a planar pattern such as a triangle. On the other hand, the upper portion 14B of the contact hole 14 does not form a V-shaped groove on the side wall as a flat pattern such as a circle so that plating is not promoted from the side wall.
That is, the shape of the contact hole 14 is changed between the lower part 14A and the upper part 14B.
With this configuration, it is possible to further bring out the function of concentrating the plating additive accelerator (accelerator) in the concave portion and the function of concentrating the leveler in the convex portion, so that the embedding performance by the electrolytic plating method can be improved. High contact holes can be realized.

In FIG. 9, the planar shape of the upper part 14B of the contact hole 14 is circular.
Even if the upper part of the contact hole is formed into a planar shape consisting of a single curve like an ellipse, the same effect as in the case where the contact hole is made circular can be obtained.
Alternatively, the upper portion of the contact hole may have a planar shape in which the radius of curvature of the corner portion of the planar shape below the contact hole is increased. By adopting this planar shape, it is difficult to promote plating from the side wall although it is not as circular or elliptical.

  When manufacturing the configuration described in FIGS. 7 to 9, the shape of the resist mask opening for forming the contact hole 14 by etching is selected in accordance with the planar shape of the contact hole 14 or the shape of the side wall. .

<3. Second Embodiment>
FIG. 10 shows a schematic configuration diagram (cross-sectional view) of the semiconductor device according to the second embodiment.
In this semiconductor device, a lower first wiring layer 12 and an upper second wiring layer 19 are electrically connected by a contact layer 15 embedded in a contact hole 14.

The first wiring layer 12 is formed by embedding a metal layer in a recess (groove) formed on the upper surface of the insulating layer 11.
The second wiring layer 19 and the contact layer 15 are each made of a plating layer. However, in the present embodiment, the second wiring layer 19 and the contact layer 15 are constituted by separately formed plating layers.
The contact hole 14 is formed so as to penetrate the insulating layer 13 in the vertical direction.
The second wiring layer 19 is formed on the insulating layer 13.

As the material of the metal layer of the first wiring layer 12, various metals and alloys used for wiring and electrodes can be used.
As a material for the plating layer of the second wiring layer 19 and the contact layer 15, a metal material that can be formed by copper or other plating can be used.
For example, a silicon oxide layer is used as the insulating layer 13, but two or more different insulating layers such as a silicon nitride layer and a silicon oxide layer may be stacked.

  Note that circuit elements such as transistors and capacitors are formed in portions not shown, and the circuit elements and the first wiring layer 12 or the second wiring layer 19 are electrically connected.

In the present embodiment, for example, as shown in the plan view of the semiconductor device in FIG. 10 in FIG. 11, the planar shape of the contact hole 14 is a triangle. In FIG. 11, only the first wiring layer 12, the contact hole 14, the contact layer 15, and the second wiring layer 19 are shown, and the surrounding insulating layers 11 and 13 are omitted.
As described above, since the planar shape of the contact hole 14 is a triangle, the side wall portion of the contact hole 14 that corresponds to the corner of the triangle is a V-shaped groove.
Thereby, the deposition from this V-shaped groove can be improved.

In FIG. 10, only the two wiring layers 12 and 19 are shown. However, in this embodiment, it is possible to form a wiring layer in the upper layer to form three or more wiring layers.
In that case, each wiring layer provided above the second layer from the bottom is preferably configured similarly to the configuration of the contact layer 15 and the second wiring layer 19 in FIG.

The semiconductor device of the present embodiment can be manufactured, for example, as described below.
First, the insulating layer 11, the first wiring layer 12, and the insulating layer 13 are formed in the same manner as in FIG. 3A of the first embodiment. As described above, the insulating layer 13 may have a structure in which two or more different insulating layers such as a silicon nitride layer and a silicon oxide layer for a hard mask are stacked.

Next, a resist is formed on the insulating layer 13 and patterned by exposure and development to form a resist mask 53 having a pattern having an opening 53A corresponding to the contact hole as shown in FIG. 12A. To do.
At this time, although not shown, the shape of the opening 53A of the resist mask 53 is a triangle.

  Next, the insulating layer 13 is etched using the resist mask 53, thereby forming a contact hole 14 reaching the first wiring layer 12, as shown in FIG. 12B. The bottom surface of the contact hole 14 is the top surface of the first wiring layer 12 and is a substantially flat surface.

Next, although not shown, a barrier metal for plating is formed on the entire surface. As the barrier metal, for example, Ta or TaN can be used.
Further, although not shown, a thin seed film of the same material as the plating material is formed on the barrier metal. For example, when the plating material is copper, a copper film is formed as a seed film.
Subsequently, the seed film on the upper surface of the insulating layer 13 is removed, and the seed film is left only in the contact hole 14.
Thereafter, by performing electrolytic plating, a plating layer is deposited on the seed film, and as shown in FIG. 12C, the inside of the contact hole 14 can be filled to form a contact layer 15 made of the plating layer. . If necessary, an unnecessary plating layer other than the inside of the contact hole 14 is removed. For example, the surface is polished by a CMP (Chemical Mechanical Polishing) method, and a portion of the plating layer above the upper surface of the insulating layer 13 is removed.

Next, a barrier metal and a seed film thereon are sequentially formed on the surface. Thereafter, the second wiring layer 19 made of a plating layer is formed by performing electrolytic plating.
Thereafter, by using the resist mask, the second wiring layer 19 is etched with an etchant (so-called subtractive method), thereby patterning the second wiring layer 19 into a predetermined pattern as shown in FIG. 12D.
In this way, the semiconductor device shown in FIG. 10 can be manufactured.

According to the configuration of the semiconductor device of the present embodiment described above, the contact layer 15 that is made of a plating layer and electrically connects the first wiring layer 12 and the second wiring layer 19 has a triangular planar shape. It is formed in a certain contact hole 14. Thereby, like the first embodiment, the plating rate from the bottom of the contact hole 14 is increased, and the bottom is quickly filled with the plating layer.
Therefore, since the embedding property of the plating layer can be improved and the embedding void can be hardly generated in the contact hole 14, the contact layer that electrically connects the first wiring layer 12 and the second wiring layer 19. The connection reliability of 15 can be improved.

Further, even if the width of the contact hole 14 is reduced, it is possible to embed a plating layer in the contact hole 14 satisfactorily without generating a buried void.
Therefore, the width of the contact hole 14 can be reduced to reduce the size of the chip including the contact hole 14, and the cost of the chip can be reduced.

Next, sectional views of modifications of the semiconductor device of the second embodiment are shown in FIGS.
As shown in FIG. 13, a semiconductor substrate 17 made of a semiconductor such as silicon is formed in the middle of the insulating layer 13 in FIG. 10, and a contact hole 14 and a contact layer 15 are also formed through the semiconductor substrate 17. Has been.
As a material for the semiconductor substrate 17, various semiconductors such as germanium and compound semiconductors such as GaAs can be used in addition to silicon.

  In the case of manufacturing a semiconductor device having this configuration, the etching material and conditions for forming the contact hole 14 may be changed as appropriate between when the insulating layer 13 is etched and when the semiconductor substrate 17 is etched. Good.

The configuration shown in FIG. 14 is a configuration in which a second wiring layer 20 made of a conductor layer formed by vapor deposition or sputtering is formed instead of the second wiring layer 19 made of a plating layer in FIG. It is.
In this case, as a material for the conductor layer of the second wiring layer 20, various conductor materials such as metal, alloy, polycrystalline silicon, conductive oxide (for example, indium tin oxide) may be used. Is possible.
Other configurations are the same as those shown in FIG.

Furthermore, the planar shape of the contact hole and the shape of the side wall can be modified as in the configuration described with reference to FIGS.
When manufacturing these structures, the shape of the opening of the resist mask for forming the contact hole by etching is selected corresponding to the planar shape of the contact hole and the shape of the side wall.

<4. Third Embodiment>
FIG. 15 shows a schematic configuration diagram (cross-sectional view) of a semiconductor device according to the third embodiment.
In this semiconductor device, a lower first wiring layer 12 and an upper second wiring layer 21 are electrically connected by a contact layer 15 embedded in a contact hole 14.

The first wiring layer 12 is formed by embedding a metal layer in a recess (groove) formed on the upper surface of the insulating layer 11.
The second wiring layer 21 and the contact layer 15 are each made of a plating layer. However, in the present embodiment, the second wiring layer 21 and the contact layer 15 are constituted by separately formed plating layers.
The contact hole 14 is formed so as to penetrate the insulating layer 13 in the vertical direction.
The second wiring layer 21 is formed on the insulating layer 13.

As the material of the metal layer of the first wiring layer 12, various metals and alloys used for wiring and electrodes can be used.
As a material of the plating layer of the second wiring layer 21 and the contact layer 15, a metal material that can be formed by copper or other plating can be used.
For example, a silicon oxide layer is used as the insulating layer 13, but two or more different insulating layers such as a silicon nitride layer and a silicon oxide layer may be stacked.

  Note that circuit elements such as transistors and capacitors are formed in portions not shown, and the circuit elements and the first wiring layer 12 or the second wiring layer 21 are electrically connected.

In the present embodiment, for example, as shown in the plan view of the semiconductor device of FIG. 15 in FIG. 16, the planar shape of the contact hole 14 is a triangle. In FIG. 16, only the first wiring layer 12, the contact hole 14, the contact layer 15, and the second wiring layer 21 are shown, and the surrounding insulating layers 11 and 13 are omitted.
As described above, since the planar shape of the contact hole 14 is a triangle, the side wall portion of the contact hole 14 that corresponds to the corner of the triangle is a V-shaped groove.
Thereby, the deposition from this V-shaped groove can be improved.

In FIG. 15, only two wiring layers 12 and 21 are shown. However, in the present embodiment, it is possible to form a wiring layer in an upper layer to form three or more wiring layers.
In that case, each wiring layer provided above the second layer from the bottom can have the same configuration as that of the contact layer 15 and the second wiring layer 21 in FIG.

The semiconductor device of the present embodiment can be manufactured, for example, as described below.
First, the insulating layer 11, the first wiring layer 12, and the insulating layer 13 are formed in the same manner as in FIG. 3A of the first embodiment. As described above, the insulating layer 13 may have a structure in which two or more different insulating layers such as a silicon nitride layer and a silicon oxide layer for a hard mask are stacked.

  Next, the same steps as those shown in FIGS. 12A to 12C of the second embodiment are performed to form a contact layer 15 made of a plating layer in the contact hole 14 formed in the insulating layer 13.

Next, although not shown, a barrier metal for plating is formed on the entire surface. As the barrier metal, for example, Ta or TaN can be used.
Further, although not shown, a thin seed film of the same material as the plating material is formed on the barrier metal. For example, when the plating material is copper, a copper film is formed as a seed film.
Next, a resist is formed on the surface, and the resist is patterned by exposure and development to form a resist mask 54 having a pattern having an opening 54A corresponding to the second wiring layer, as shown in FIG. 17A. At this time, in the portion of the resist mask 54, there is a barrier metal and a seed film between the insulating layer 13 and the resist mask 54.
Thereafter, by performing electroplating, a plating layer is deposited on the portion of the seed film not covered with the resist mask 54. Thereby, as shown in FIG. 17B, the second wiring layer 21 made of a plating layer can be formed in the opening 54A of the resist mask 54.

Thereafter, the resist mask 54 is removed, leaving the second wiring layer 21 as shown in FIG. 17C.
In this way, the semiconductor device shown in FIG. 15 can be manufactured.

According to the configuration of the semiconductor device of the present embodiment described above, the contact layer 15 that is made of a plating layer and electrically connects the first wiring layer 12 and the second wiring layer 21 has a triangular shape in plan view. It is formed in a certain contact hole 14. Thereby, like the first embodiment and the second embodiment, the plating rate from the bottom of the contact hole 14 is increased, and the bottom is quickly filled with the plating layer.
Therefore, since the embedding property of the plating layer can be improved and the embedding void can be hardly generated in the contact hole 14, the contact layer that electrically connects the first wiring layer 12 and the second wiring layer 21. The connection reliability of 15 can be improved.

Further, even if the width of the contact hole 14 is reduced, it is possible to embed a plating layer in the contact hole 14 satisfactorily without generating a buried void.
Therefore, the width of the contact hole 14 can be reduced to reduce the size of the chip including the contact hole 14, and the cost of the chip can be reduced.

Next, FIG. 18 shows a cross-sectional view of a modification of the semiconductor device of the third embodiment.
As shown in FIG. 18, a semiconductor substrate 17 made of a semiconductor such as silicon is formed in the middle of the insulating layer 13 in FIG. 15, and the contact hole 14 and the contact layer 15 are formed through the semiconductor substrate 17. Has been.
As a material for the semiconductor substrate 17, various semiconductors such as germanium and compound semiconductors such as GaAs can be used in addition to silicon.

  In the case of manufacturing a semiconductor device having this configuration, the etching material and conditions for forming the contact hole 14 may be changed as appropriate between when the insulating layer 13 is etched and when the semiconductor substrate 17 is etched. Good.

Furthermore, the planar shape of the contact hole and the shape of the side wall can be modified as in the configuration described in FIGS. 7 to 9 with respect to the third embodiment described above.
When manufacturing these structures, the shape of the opening of the resist mask for forming the contact hole by etching is selected corresponding to the planar shape of the contact hole and the shape of the side wall.

In FIG. 15, the contact layer 15 and the second wiring layer 21 are each composed of a separately formed plating layer. However, as in the first embodiment, the contact layer and the second wiring layer 21 are formed. It is also possible to adopt a configuration in which the layer is formed of a plating layer at the same time.
In the case of manufacturing this configuration, after forming the contact hole 14 in the insulating layer 13, the barrier metal and the seed film are sequentially formed without filling the inside of the contact hole 14. Next, a resist mask having the same pattern as the resist mask 54 illustrated in FIG. 17A is formed. Thereafter, by performing electrolytic plating, the contact layer and the second wiring layer are simultaneously formed by the plating layer. Then, after removing the resist mask, the seed film remaining on the insulating layer 13 is removed.
This manufacturing method is the same as the so-called semi-additive method used for manufacturing printed circuit boards, build-up substrates, and the like.

<5. Fourth Embodiment>
In each of the above-described embodiments, the contact hole is formed by forming a through hole in the insulating layer 13 so as to reach the lower wiring layer 11.
In the present technology, it is also possible to form a contact layer by forming a contact hole which is a non-through hole and filling the non-through hole to form a plating layer.
An embodiment in that case is shown below.

FIG. 19 shows a schematic configuration diagram (cross-sectional view) of a semiconductor device according to the fourth embodiment.
In this semiconductor device, an insulating layer 33 including three wiring layers 32 is formed on a semiconductor substrate 31.
The three wiring layers 32 are electrically connected to circuit elements (transistors, capacitors, etc.) constituting the semiconductor device at portions not shown.

  In the present embodiment, a non-penetrating contact hole 34 that penetrates through the insulating layer 33 and the wiring layer 32 inside thereof and reaches the middle of the semiconductor substrate 31 is formed, and the inside of the contact hole 34 is filled. A contact layer 35 made of a plating layer is formed. With the contact layer 35, the three wiring layers 32 and the semiconductor substrate 31 are electrically connected.

The contact hole 34 does not penetrate to the lower surface of the semiconductor substrate 31 and has a round bottom with a U-shaped cross section. In each of the first to third embodiments, the side wall of the contact hole 14 is perpendicular or nearly perpendicular to the horizontal plane. However, in this embodiment, the side wall of the contact hole 34 is inclined and is The width of the contact hole 34 increases as the time goes.
When the plating layer is formed in the hole having the round bottom as described above, the planar shape of the hole is usually a circle or a quadrangle, so that the conformal deposit becomes strong as described above, and a buried void may be formed. There is a feature.

On the other hand, in the present embodiment, for example, as shown in the plan view of the semiconductor device of FIG. 19 in FIG. 20, the planar shape of the contact hole 34 is a triangle. As described above, since the planar shape of the contact hole 34 is a triangle, the side wall portion of the contact hole 34 that corresponds to the corner of the triangle is a V-shaped groove.
Thereby, the deposition from this V-shaped groove can be improved.

The semiconductor device of the present embodiment can be manufactured, for example, as described below.
First, the three wiring layers 32 and the insulating layer 33 are formed on the semiconductor substrate 31.
Thereafter, a resist is formed on the insulating layer 33, and the resist is patterned by exposure and development or the like, thereby forming a resist mask 61 having a pattern having an opening 61A corresponding to the contact hole as shown in FIG. 21A. .
At this time, although not shown, the shape of the opening 61A of the resist mask 61 is a triangle.

Next, using the resist mask 61, the insulating layer 33, the wiring layer 32, and the semiconductor substrate 31 are etched from the side of the insulating layer 33 including the wiring layer 32, respectively.
As a result, as shown in FIG. 21B, a non-through hole contact hole 34 having a bottom is formed inside the semiconductor substrate 31.

Next, although not shown, a barrier metal for plating and a seed film are sequentially formed on the entire surface.
Subsequently, by performing electrolytic plating, it is possible to fill the inside of the contact hole 34 and form a contact layer 35 made of a plating layer.
Next, an unnecessary plating layer remaining on the insulating layer 33 is removed.
In this way, the semiconductor device shown in FIG. 19 can be manufactured.

Furthermore, the planar shape of the contact hole and the shape of the side wall can be modified as in the configuration described with reference to FIGS.
When manufacturing these structures, the shape of the opening of the resist mask for forming the contact hole by etching is selected corresponding to the planar shape of the contact hole and the shape of the side wall.

According to the present embodiment described above, the contact layer 35 made of a plating layer and electrically connecting the wiring layer 32 and the semiconductor substrate 31 is formed in the contact hole 34 having a triangular planar shape. Thereby, like the previous embodiments, the plating rate from the bottom of the contact hole 34 can be increased, and the bottom can be quickly filled with the plating layer.
Therefore, even if the contact hole 34 has a U-shaped cross section, by increasing the plating speed from the bottom of the contact hole 34 and improving the embeddability of the plating layer, it becomes difficult to generate embedded voids in the contact hole 34. be able to. Thereby, the connection reliability of the contact layer 35 that electrically connects the wiring layer 32 and the semiconductor substrate 31 can be improved.

Further, even if the width of the contact hole 34 is reduced, it is possible to fill the contact hole 34 with a good plating layer without generating a buried void.
Therefore, the width of the contact hole 34 can be reduced to reduce the size of the chip including the contact hole 34, and the cost of the chip can be reduced.

Next, schematic configuration diagrams of a semiconductor device according to a modification of the fourth embodiment are shown in FIGS. 22A to 22C.
Each of the configurations shown in FIGS. 22A to 22C is a configuration in which a contact hole 36 is formed from the semiconductor substrate 31 side to the wiring layer 33 and a contact layer 37 made of a plating layer is formed therein. In other words, the contact hole 34 is formed in the semiconductor substrate 31 from the wiring layer 33 side, which is opposite to the fourth embodiment.
In the configuration shown in FIG. 22A, the contact hole 36 penetrates the one wiring layer 32.
In the configuration shown in FIGS. 22B and 22C, the contact hole 36 penetrates the two wiring layers 32.

In these configurations, for example, although not shown, the planar shape of the contact hole 36 is a triangle. As described above, by making the planar shape of the contact hole 36 triangular, as in the fourth embodiment, the plating rate from the bottom of the contact hole 36 can be increased and the bottom can be quickly filled with the plating layer. it can.
Therefore, even if the contact hole 36 has a U-shaped cross section, by increasing the plating speed from the bottom of the contact hole 36 and improving the embeddability of the plating layer, it becomes difficult to generate embedded voids in the contact hole 36. be able to. Thereby, the connection reliability of the contact layer 37 which electrically connects the wiring layer 32 and the semiconductor substrate 31 can be improved.

In addition, with respect to the configuration shown in FIG. 19 and each configuration shown in FIGS. 22A to 22C, the semiconductor substrate 31 and the insulating layer 33 are further polished and ground from the back surface (lower surface in the drawing) side, It is also possible to expose the contact layers 35 and 37 on the back surface side.
Then, after the contact layers 35 and 37 are exposed on the back surface side, it is possible to connect the contact layers 35 and 37 on the back surface side to form a wiring layer, a pad, or the like.
In this way, the present technology can be applied even when the contact layer is exposed from the opposite side after the non-through hole is filled and the contact layer made of the plating layer is formed, and the conductor layer is connected to the contact layer. Is possible. And by applying this technique and making the shape of the side wall of the contact hole into a shape such as a triangular planar shape, it is possible to prevent voids from being generated in the plating layer formed in the contact hole.

The semiconductor device according to the present technology including the semiconductor device of each of the embodiments described above can be applied to various semiconductor devices.
For example, the present invention can be applied to a configuration in which a wiring layer of a CMOS image sensor (CIS) and a bump formed on the back surface of a substrate are electrically connected by a contact layer made of a plating layer.
Further, for example, the present invention can be applied to a configuration in which a multilayer wiring layer and a circuit element are three-dimensionally stacked and the wiring layers of each layer are electrically connected by a contact layer made of a plating layer.

In addition, this indication can also take the following structures.
(1) It is a planar shape including two or more wiring layers and a shape in which at least the bottom surface is composed of two or more surfaces and the outwardly convex acute angle or the acute angle tip portion is replaced with a curve. A semiconductor device comprising: a contact hole; and a contact layer formed of a plating layer, filled in the contact hole and connected to the wiring layer.
(2) The semiconductor device according to (1), wherein the planar shape of at least the bottom of the contact hole is a triangle or a shape obtained by replacing a tip of a corner of the triangle with a curve.
(3) The planar shape of at least the bottom portion of the contact hole is a shape in which two sides sandwiching the inwardly-convex corner are replaced with arcs among the polygon having the acute angle and the inwardly-convex corner. The semiconductor device according to (1).
(4) The semiconductor device according to any one of (1) to (3), wherein a planar shape of an upper portion of the contact hole is a circle or an ellipse.
(5) In the above (1), the planar shape of the lower part including the bottom part of the contact hole is a triangle or the tip of the corner of the triangle is replaced with a curve, and the planar shape of the upper part of the contact hole is circular. The semiconductor device described.
(6) It further includes a semiconductor substrate and an insulating layer including the wiring layer therein, and the contact hole is formed in the wiring layer and the semiconductor substrate, and the insulating layer between the wiring layer and the semiconductor substrate. The semiconductor device according to any one of (1) to (5), wherein the semiconductor device is formed.
(7) A step of forming a wiring layer and an insulating layer including the wiring layer therein; and an acute angle or a convex angle outwardly formed on the insulating layer, at least at the bottom, with two or more side surfaces. The wiring layer has a planar shape including two or more shapes obtained by replacing the acute-angled tip with a curve, a step of forming a contact hole reaching the wiring layer, and filling the inside of the contact hole by electrolytic plating, Forming a contact layer so as to be connected to the semiconductor device.
(8) The method for manufacturing a semiconductor device according to (7), wherein in the step of forming the contact layer, an upper wiring layer connected to the contact layer is formed simultaneously with the contact layer by electrolytic plating.
(9) The method of manufacturing a semiconductor device according to (7), further including a step of forming an upper wiring layer connected to the contact layer on the contact layer after forming the contact layer.
(10) The method for manufacturing a semiconductor device according to (8), wherein a step of forming a recess for forming the upper wiring layer in the insulating layer is performed before the step of forming the contact layer.
(11) The semiconductor device according to (8), wherein a step of forming a resist mask having a pattern for forming the upper wiring layer on the insulating layer is performed before the step of forming the contact layer. Production method.
(12) forming a wiring layer and an insulating layer including the wiring layer on the semiconductor substrate; the wiring layer and the semiconductor substrate; and the insulating layer between the wiring layer and the semiconductor substrate. In addition, at least at the bottom, a contact hole is formed in which the side surface is composed of two or more surfaces, and the shape is a planar shape including two or more acute angles that are convex outward or the tip of the acute angle is replaced with a curve. And a step of forming a contact layer so as to fill the inside of the contact hole and connect to the wiring layer and the semiconductor substrate by electrolytic plating.

  The present technology is not limited to the above-described embodiments, and various other configurations can be taken without departing from the gist of the present technology.

11, 13, 33 Insulating layer, 12 First wiring layer, 14, 34, 36 Contact hole, 15, 35, 37 Contact layer, 16, 19, 20, 21 Second wiring layer, 17, 31 Semiconductor substrate, 18 plating layers, 32 wiring layers

Claims (12)

A wiring layer;
A contact hole having a planar shape including two or more at least at the bottom, the side surface comprising two or more surfaces, and an acute angle convex outward or a shape in which the tip of the acute angle is replaced with a curve;
A semiconductor device comprising: a contact layer made of a plating layer, formed to fill the inside of the contact hole, and connected to the wiring layer.   2. The semiconductor device according to claim 1, wherein the planar shape of at least the bottom of the contact hole is a triangle or a shape in which a tip of a corner of the triangle is replaced with a curve.   The planar shape of at least the bottom portion of the contact hole is a shape in which two sides sandwiching the inwardly convex corner are replaced with arcs among the polygon having the acute angle and the inwardly convex corner. 2. The semiconductor device according to 1.   The semiconductor device according to claim 1, wherein a planar shape of an upper portion of the contact hole is a circle or an ellipse.   2. The semiconductor device according to claim 1, wherein the planar shape of the lower part including the bottom of the contact hole is a triangle or a shape obtained by replacing the tip of the corner of the triangle with a curve, and the planar shape of the upper part of the contact hole is a circle. .   A semiconductor substrate; and an insulating layer including the wiring layer therein, wherein the contact hole is formed in the wiring layer and the semiconductor substrate, and the insulating layer between the wiring layer and the semiconductor substrate. The semiconductor device according to claim 1. Forming a wiring layer and an insulating layer containing the wiring layer inside;
The insulating layer has a planar shape including two or more shapes in which at least the bottom surface is composed of two or more surfaces and the outwardly convex acute angle or the sharp tip portion is replaced with a curve. Forming a contact hole reaching the layer;
Forming a contact layer so as to fill the inside of the contact hole and connect to the wiring layer by electrolytic plating.   8. The method of manufacturing a semiconductor device according to claim 7, wherein in the step of forming the contact layer, an upper wiring layer connected to the contact layer is formed simultaneously with the contact layer by electrolytic plating.   8. The method of manufacturing a semiconductor device according to claim 7, further comprising a step of forming an upper wiring layer connected to the contact layer on the contact layer after forming the contact layer.   The method for manufacturing a semiconductor device according to claim 8, wherein a step of forming a recess for forming the upper wiring layer in the insulating layer is performed before the step of forming the contact layer.   9. The method of manufacturing a semiconductor device according to claim 8, wherein a step of forming a resist mask having a pattern for forming the upper wiring layer on the insulating layer is performed before the step of forming the contact layer. Forming a wiring layer and an insulating layer including the wiring layer on the semiconductor substrate;
The wiring layer and the semiconductor substrate, and the insulating layer between the wiring layer and the semiconductor substrate, at least at the bottom, have two or more side surfaces and have an acute angle or acute angle tip that protrudes outward. Forming a contact hole, which is a planar shape including two or more shapes in which a part is replaced with a curve;
Forming a contact layer so as to fill the inside of the contact hole and connect to the wiring layer and the semiconductor substrate by electrolytic plating.