JP2012169317A - Method for manufacturing silicon carbide semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a method for manufacturing a silicon carbide semiconductor device which can be manufactured through a non-complicated process and is high in dielectric strength.SOLUTION: A method for manufacturing a silicon carbide semiconductor device of the present invention includes: (a) a step of preparing a SiC substrate 1 comprising a first conductivity type silicon carbide semiconductor, as a base; (b) a step of forming a recessed structure 4 surrounding an element region using a resist pattern 3 on the SiC substrate 1; and (c) a step of forming an ion implantation layer 6 as a second conductivity type impurity layer within the surfaces of a recessed bottom surface and a recessed side surface of the recessed structure 4 by impurity implantation via the resist pattern 3, after the step (b). In the step (c), the impurity implantation is performed by oblique-rotating ion implantation.

Description

  The present invention relates to a method for manufacturing a silicon carbide semiconductor device, and more particularly to a method for manufacturing a termination structure of a silicon carbide semiconductor device.

  As a next-generation switching element capable of realizing high breakdown voltage, low loss, and high heat resistance, a semiconductor element using silicon carbide is considered promising and is expected to be applied to a power semiconductor device such as an inverter.

  However, many problems to be solved remain in the silicon carbide semiconductor device. One of them is due to electric field concentration in the terminal part of the silicon carbide semiconductor device (for example, the end part of a Schottky electrode of a Schottky barrier diode or the end part of a pn diode or MOSFET (Metal Oxide Semiconductor Field Effect Transistor) pn junction). This is a problem that the withstand voltage characteristic of the silicon carbide semiconductor device is deteriorated.

  Typical examples of the termination structure for relaxing the electric field generated at the termination portion of the silicon carbide semiconductor device include a guard ring (GR) structure, a JTE (Junction Termination Extension) structure, and an FLR (Field Limiting Ring) structure. . These are impurity diffusion layers formed so as to surround the element region. In general, the JTE structure is provided for the purpose of reducing the surface electric field, and has a structure in which the impurity concentration gradually decreases from the terminal portion of the silicon carbide semiconductor device to the outside. On the other hand, the FLR structure is composed of a plurality of impurity diffusion layers having the same concentration.

  For example, Patent Document 1 below discloses a termination structure in which GR and JTE are combined. The termination structure of Patent Document 1 is a structure in which a JTE having an impurity concentration lower than that of the GR is disposed outside the GR. Further, in Patent Document 1, by forming GR and JTE under a recess structure provided on the surface of the silicon carbide semiconductor layer, the distance between the bottom end portion of GR and JTE that is likely to cause electric field concentration and the surface of the silicon carbide semiconductor layer. A technique for prolonging the length and further relaxing the electric field on the surface of the silicon carbide semiconductor layer has been proposed.

International Publication No. 2009/116444

  As described above, in the conventional silicon carbide semiconductor device, the breakdown voltage structure is realized by using two types of implantation conditions of GR / JTE.

  Here, in order to realize the GR / JTE structure under two kinds of implantation conditions, a step of forming a mask for injecting impurities into each corresponding position is required. Further, in order to form those masks, it is necessary to form a reference (alignment mark) for aligning the positions of the respective masks in the previous process. The alignment mark is formed by etching the silicon carbide semiconductor surface.

  As described above, in the conventional silicon carbide semiconductor device, at least three masks (for alignment mark formation, GR formation, and JTE formation) are required, and impurity implantation has to be performed under different conditions. For this reason, the number of processes increases, and problems such as deterioration of characteristics due to mask variations in each process, a decrease in yield, and an increase in cost occur.

  As a method for improving these problems, it is conceivable to use one mask. That is, the termination structure is a GR-only structure or an FLR structure, and the number of implantation steps is one. Furthermore, the termination structure can be formed with one mask by making the step of forming the alignment mark and the step of forming the above-described implantation mask a common step.

  In these silicon carbide semiconductor devices, by applying one kind of implantation condition, the recess structure is provided with a termination structure in which impurities are implanted at one kind of concentration.

  Here, in the case of a silicon carbide semiconductor device, the implanted impurities are activated with little diffusion. Therefore, in the case of only the GR structure, as a matter of course, in the case of the GR / JTE structure, when one kind of implantation condition that cannot be optimized as much as two kinds of implantation conditions is applied, a high-concentration impurity layer is very close to the recess structure. Will be formed. Further, the impurity concentration of the guard ring is formed at a relatively high concentration in order to ensure the breakdown voltage characteristics of the element.

  For this reason, when a high voltage is applied to the cathode, the depletion layer of the impurity layer is less elongated and a high electric field is likely to be generated.

  In particular, a strong electric field is generated at the corner portion of the recess structure. For example, when the dielectric breakdown strength of the polyimide film that is the surface sealing material is exceeded, there is a problem of causing dielectric breakdown. In addition, when electric charges accumulate outside the polyimide film, the electric field strength in the recesses fluctuates, causing a dielectric breakdown. In addition, when the device is incorporated in a module for power conversion, it is necessary to cover it with another insulator. In this process, charges accumulate on the surface of an insulator such as polyimide, causing a decrease in dielectric strength. It was. Further, the diffusion of the implanted impurity is insufficient, and the corner portion of the recess structure may not be covered with the implanted layer.

  The present invention has been made to solve the above-described problems, and an object of the present invention is to provide a method for manufacturing a silicon carbide semiconductor device that does not require a complicated manufacturing process and has high dielectric strength.

  The method for manufacturing a silicon carbide semiconductor device according to the present invention includes: (a) a step of preparing a base made of a first conductivity type silicon carbide semiconductor; and (b) a recess structure surrounding an element region on the base. And (c) after the step (b), the impurity of the second conductivity type is formed in the recess bottom surface and the recess side surface in the recess structure by impurity implantation through the resist pattern. A step of forming a layer, and the step (c) is a step of performing the impurity implantation by oblique rotation ion implantation.

  The method for manufacturing a silicon carbide semiconductor device according to the present invention includes the step of forming the impurity layer of the second conductivity type by obliquely rotating ion implantation in the recess bottom surface and the recess side surface in the recess structure. It is possible to manufacture a silicon carbide semiconductor device having a high dielectric strength with a simple manufacturing process.

FIG. 5 is a cross sectional view showing a manufacturing step for the silicon carbide semiconductor device of the first embodiment. FIG. 5 is a cross sectional view showing a manufacturing step for the silicon carbide semiconductor device of the first embodiment. FIG. 5 is a cross sectional view showing a manufacturing step for the silicon carbide semiconductor device of the first embodiment. FIG. 5 is a cross sectional view showing a manufacturing step for the silicon carbide semiconductor device of the first embodiment. FIG. 5 is a cross sectional view showing a manufacturing step for the silicon carbide semiconductor device of the first embodiment. It is a figure which shows the simulation result of the maximum electric field strength of a recess corner part. FIG. 11 is a cross sectional view showing a manufacturing step for the silicon carbide semiconductor device of the second embodiment. FIG. 11 is a cross sectional view showing a manufacturing step for the silicon carbide semiconductor device of the second embodiment. FIG. 11 is a cross sectional view showing a manufacturing step for the silicon carbide semiconductor device of the second embodiment. FIG. 11 is a cross sectional view showing a manufacturing step for the silicon carbide semiconductor device of the second embodiment. FIG. 11 is a cross sectional view showing a manufacturing step for the silicon carbide semiconductor device of the second embodiment. FIG. 11 is a cross sectional view showing a manufacturing step for the silicon carbide semiconductor device of the second embodiment. It is sectional drawing which shows the structure of the silicon carbide semiconductor device which concerns on the premise technique of this invention.

(Prerequisite technology)
FIG. 13 is a cross-sectional view showing a configuration of a silicon carbide semiconductor device which is a prerequisite technology of the present invention.

  In the silicon carbide semiconductor device according to the prerequisite technology of the present invention, SiC epitaxial layer 2 is formed on the first main surface of SiC substrate 1, and recess structure 4 is formed on the first main surface of SiC epitaxial layer 2. Further, Al ions are implanted from the recess structure 4, and the lower portion of the bottom surface of the recess structure 4 becomes an ion implantation layer 6.

  A Schottky electrode 8 is formed on the surface of SiC epitaxial layer 2 so as to overlap a part of ion implantation layer 6, and surface electrode 9 is formed on Schottky electrode 8. Further, a protective layer 10 of a polyimide film is formed on the SiC epitaxial layer 2 so as to cover the ion implantation layer 6.

  On the second main surface (back surface) of SiC substrate 1, ohmic electrode 7 and back surface electrode 11 are provided.

  Schottky electrode 8 is in Schottky junction with SiC epitaxial layer 2. An object is to alleviate the electric field in the termination region by forming the ion implantation layer 6 in the termination region of the Schottky electrode 8 and smoothly changing the impurity concentration.

  However, since the impurity implanted into SiC is activated with little diffusion unlike in Si, the impurity concentration of the ion-implanted layer 6 decreases particularly in the lateral direction. Since the ion implantation layer 6 is formed with a high impurity concentration in order to ensure the breakdown voltage characteristics, a depletion layer in the impurity layer when a high voltage is applied between the back electrode 11 and the front electrode 9 is used. There is little elongation and high electric fields are likely to occur. Therefore, a strong electric field is generated particularly in the corner portion of the bottom surface of the recess structure 4, and dielectric breakdown occurs when the dielectric breakdown strength of the protective layer 10 such as the SiC substrate 1 or the polyimide film is exceeded.

  Therefore, in the silicon carbide semiconductor device of the present invention, electric field relaxation is achieved by smoothing the impurity concentration in the side surface direction of ion implantation layer 6.

(Embodiment 1)
<Configuration>
1 to 4 are sectional views showing a manufacturing process of a Schottky Barrier diode (SBD) which is a silicon carbide semiconductor device according to the first embodiment, and FIG. 5 is a sectional view showing the structure thereof.

  As shown in FIG. 5, in the SBD of the present embodiment, n-type SiC epitaxial layer 2 is formed on the first main surface (surface) of SiC substrate 1. The SiC substrate 1 is a 4H—SiC substrate whose first main surface has an off angle from the (0001) silicon surface, and is an n-type substrate containing an impurity such as nitrogen (N). The SiC epitaxial layer 2 is an n-type containing an impurity such as nitrogen (N), and a recess structure 4 is formed on the surface.

  In the vicinity of the side surface and the bottom surface of the recess structure 4, an ion implantation region 6 activated by implanting a p-type impurity such as aluminum (Al) is formed.

  A Schottky electrode 8 that forms a Schottky junction with the SiC epitaxial layer 2 is formed on the surface of the SiC epitaxial layer 2, and a surface electrode 9 is formed on the surface of the Schottky electrode 8 so as to cover the ion implantation region 6. The ion implantation region 6 is a termination region of the Schottky electrode 8.

  A protective layer 10 such as a polyimide film is provided as a surface sealing material on the SiC epitaxial layer 2 and the Schottky electrode 8.

  On the second main surface (back surface) of SiC substrate 1, ohmic electrode 7 and back surface electrode 11 are provided.

<Manufacturing process>
The manufacturing process of the SBD of the present embodiment will be described with reference to FIGS.

First, SiC epitaxial layer 2 is epitaxially grown on the first main surface of SiC substrate 1 (underlying). For example, the doping concentration is 5 × 10 ¹⁵ / cm ³ and the film thickness is 10 μm. Next, an oxide film (not shown) is formed on the SiC epitaxial layer 2, and a resist pattern 3 for forming a p-type termination structure is formed (FIG. 1).

  The resist pattern 3 also includes a formation pattern of an alignment mark (not shown) used in a later impurity implantation step, and the alignment mark and the recess structure 4 are simultaneously formed in the SiC epitaxial layer 2 by etching (FIG. 2). ). As a result, the number of resist pattern formations can be reduced. The recess structure 4 forms a termination structure by implanting an impurity layer to be described later, and thus is formed so as to surround the element region.

  Thereafter, Al ions, which are p-type impurities, are obliquely implanted, for example, at an acceleration voltage of 700 kV and an implantation angle of 55 ° into the terminal portions in the four directions of the square SBD element in plan view. An ion implantation layer 6 (impurity layer) is formed therein (FIG. 3). That is, oblique rotation ion implantation is performed on each of the end portions of the four sides while the wafer (underlying) is rotated 90 ° intermittently. Here, the description is made on the assumption that the element region is square, but even if the element region has an arbitrary shape, the same oblique ion implantation is performed while appropriately rotating the wafer corresponding to each side of the element region. .

  Thereafter, in order to activate the implanted Al ions, SiC substrate 1 and SiC epitaxial layer 2 are heated at 1500 ° C. or higher (FIG. 4).

  Next, for example, a nickel (Ni) film is formed on the back surface of the SiC substrate 1, and NiSi is formed by heating using RTA (Rapid Thermal Annealing) to form the ohmic electrode 7. Next, a Schottky electrode 8 made of, for example, titanium (Ti) is formed on the surface of the SiC epitaxial layer 2. The Schottky electrode 8 is formed so as to cover a part of the recess structure 4. Thereafter, an Al film is formed, and patterning of the electrode is performed by a resist pattern and wet etching to form the surface electrode 9.

  Next, a surface sealing material such as polyimide is applied onto the SiC epitaxial layer 2 and the Schottky electrode 8 and baked to form the protective layer 10.

  Finally, the back electrode 11 is formed on the ohmic electrode 7. For example, by forming a Ni layer and an Au layer as the back electrode, the solder wettability can be improved when the back surface of the element is die-bonded with solder. Thus, the SBD of this embodiment shown in FIG. 5 is formed.

  In the oblique rotation ion implantation, the ion implantation is performed while intermittently rotating the wafer. However, even if the ion implantation is performed while continuously rotating the wafer, the ion implantation is performed on the side surfaces of all the recess structures 4. Things are possible. In any method, in the oblique rotation ion implantation, the ion implantation layer 6 of about 0.3 to 0.5 μm can be expanded from the recess end. Thereby, the maximum electric field strength at the end of the recess structure 4 can be relaxed.

  FIG. 6 is a diagram of simulation results showing the effect. The horizontal axis indicates the amount of misalignment between the end of the recess structure 4 and the end of the ion implantation layer 6, and the vertical axis indicates the maximum electric field strength at the end of the recess structure 4. ing. 6A is a view of the end of the recess structure 4 on the Schottky interface side, and FIG. 6B is a view of the end of the recess structure 4 on the side opposite to the Schottky interface side. The dielectric breakdown strength of SiC and polyimide is 3 MV / cm and 2 MV / cm, respectively. According to FIG. 6, by expanding the end of the ion implantation layer 6 from the end of the recess structure 4 by about 0.3 μm, Maximum electric field strength can be lowered below their breakdown strength.

<Effect>
According to the first embodiment of the present invention, in the method for manufacturing a silicon carbide semiconductor device, (a) a step of preparing SiC substrate 1 as a base made of a first conductivity type silicon carbide semiconductor; and (b) SiC. On the substrate 1, a recess structure 4 surrounding the element region is formed by using the resist pattern 3, and (c) after step (b), impurity implantation through the resist pattern 3 is performed after the step (b). A step of forming an ion implantation layer 6 as a second conductivity type impurity layer in the surface of the recess bottom surface and the side surface of the recess, and step (c) is a step of performing impurity implantation by oblique rotation ion implantation. Even in the case of using a SiC substrate in which the impurity to be implanted hardly diffuses, the ion implantation layer 6 can be reliably formed on the side surface of the recess structure 4. Therefore, the electric field concentration in the vicinity of the side surface of recess structure 4 can be relaxed, and a stable breakdown voltage of the silicon carbide semiconductor device can be realized.

  According to the first embodiment of the present invention, in the method for manufacturing a silicon carbide semiconductor device, the rotation of the oblique rotation ion implantation in step (c) is intermittently performed on SiC substrate 1 corresponding to each side of the element region. Since the rotation or the continuous rotation of the SiC substrate 1 is included, the ion implantation layer 6 can be reliably formed on the side surfaces of all the recess structures 4 formed around the element region. Therefore, the electric field concentration in the vicinity of the side surface of recess structure 4 can be relaxed, and a stable breakdown voltage of the silicon carbide semiconductor device can be realized.

  According to the first embodiment of the present invention, in the method for manufacturing a silicon carbide semiconductor device, in step (b), the alignment mark used in the impurity implantation in step (c) is formed using a resist pattern 3 as a recess structure. 4, the number of resist pattern formations can be omitted once, and deterioration in characteristics and yield due to variations in a plurality of resist patterns are suppressed.

  Further, according to the first embodiment of the present invention, after the step (d), the step of forming the Schottky electrode 8 so as to cover a part of the recess structure 4 is provided after the step (c). The ion implantation layer 6 formed at the terminal end 8 can alleviate the electric field concentration near the side surface of the recess structure 4, thereby realizing a stable breakdown voltage of the silicon carbide semiconductor device.

(Embodiment 2)
<Configuration>
7 to 11 are cross-sectional views showing the manufacturing process of the SBD which is the silicon carbide semiconductor device according to the second embodiment, and FIG. 12 is a cross-sectional view showing the structure thereof. FIG. 12 is a reprint of FIG. 5, and the configuration of the SBD of the present embodiment is the same as that of the first embodiment, and thus description thereof is omitted.

<Manufacturing process>
The manufacturing process of the SBD of the present embodiment will be described with reference to FIGS.

First, SiC epitaxial layer 2 is epitaxially grown on the first main surface of SiC substrate 1 (underlying). For example, the doping concentration is 5 × 10 ¹⁵ / cm ³ and the film thickness is 10 μm. Next, an oxide film (not shown) is formed on the SiC epitaxial layer 2, and a resist pattern 3 for forming a p-type termination structure is formed (FIG. 7).

  The resist pattern 3 includes a formation pattern of a mark pattern used in the subsequent steps, and the mark pattern and the recess structure 4 are simultaneously formed in the SiC epitaxial layer 2 by etching (FIG. 8). The recess structure 4 forms a termination structure by implanting an impurity layer to be described later, and thus is formed so as to surround the element region.

  Thereafter, when the resist pattern 3 is heated together with the SiC substrate 1, the resist pattern 3 is contracted due to overheating, and the end portion is tapered (FIG. 9).

  Next, when Al ions 5 are implanted perpendicularly to the bottom surface of the recess structure 4 using the contracted resist pattern 3, Al ions 5 are implanted into the SiC epitaxial layer 2 even near the opening where the thickness of the resist pattern 3 is reduced. Is done. Therefore, it is possible to form the ion implantation layer 6 up to the side surface of the recess structure 4 without performing oblique implantation (FIG. 10).

  Then, in order to activate the implanted Al ions, SiC substrate 1 and SiC epitaxial layer 2 are heated at 1500 ° C. or higher (FIG. 11).

  Thereafter, the ohmic electrode 7, the front electrode 8, the protective layer 10, and the back electrode 11 are formed as in the first embodiment, and the SBD of the present embodiment shown in FIG. 12 is formed.

  Although the vertical implantation is performed in the ion implantation step, oblique rotation implantation may be performed using the contracted resist pattern 3. In this case, the ion implantation layer 6 can be formed even further on the side surface of the recess structure 4.

<Effect>
A method for manufacturing a silicon carbide semiconductor device according to a second embodiment of the present invention includes: (a) a step of preparing SiC substrate 1 as a base made of a first conductivity type silicon carbide semiconductor; and (b) on SiC substrate 1. 2B, the step of forming the recess structure 4 surrounding the element region using the resist pattern 3 and the step (b ′), after the step (b), the SiC substrate 1 is heated so that the opening of the resist pattern 3 is tapered. And (c) after step (b ′), by ion implantation through the resist pattern 3, an ion implantation layer is formed as a second conductivity type impurity layer in the recess bottom surface and the side surface of the recess in the recess structure 4. Therefore, the ion implantation layer 6 is also formed in the surface of the recess side surface through the tapered portion of the resist pattern 3 where the thickness is reduced. Therefore, the electric field concentration in the vicinity of the side surface of recess structure 4 can be relaxed, and a stable breakdown voltage of the silicon carbide semiconductor device can be realized.

  Further, since the step (c) is a step of implanting impurities perpendicularly to the bottom surface of the recess structure 4, the ion implantation layer 6 is also formed in the surface of the recess side surface by a simple method without performing oblique ion implantation. Can be formed.

  1 SiC substrate, 2 SiC epitaxial layer, 3 resist pattern, 4 recess structure, 5 ion beam, 6 ion implantation layer, 7 ohmic electrode, 8 Schottky electrode, 9 surface electrode, 10 protective layer, 11 back electrode.

Claims (6)

(A) preparing a base made of a silicon carbide semiconductor of the first conductivity type;
(B) forming a recess structure surrounding the element region on the base using a resist pattern;
(C) After the step (b), a step of forming an impurity layer of a second conductivity type in the surface of the recess bottom surface and the recess side surface in the recess structure by impurity implantation through the resist pattern. ,
The step (c) is a step of performing the impurity implantation by oblique rotation ion implantation.
A method for manufacturing a silicon carbide semiconductor device. The rotation of the oblique rotation ion implantation in the step (c) includes intermittent rotation of the base corresponding to each side of the element region, or continuous rotation of the base.
A method for manufacturing a silicon carbide semiconductor device according to claim 1. The step (b) is a step of forming an alignment mark used in the impurity implantation of the step (c) simultaneously with the recess structure, using the resist pattern.
A method for manufacturing a silicon carbide semiconductor device according to claim 1 or 2. (D) After the step (c), the method further includes a step of forming a Schottky electrode so as to cover a part of the recess structure.
The manufacturing method of the silicon carbide semiconductor device in any one of Claims 1-3. (A) preparing a base made of a silicon carbide semiconductor of the first conductivity type;
(B) forming a recess structure surrounding the element region on the base using a resist pattern;
(B ′) after the step (b), the step of heating the base to make the opening of the resist pattern into a tapered shape;
(C) After the step (b ′), a step of forming an impurity layer of the second conductivity type in the surface of the recess bottom surface and the recess side surface in the recess structure by impurity implantation through the resist pattern. Prepare
A method for manufacturing a silicon carbide semiconductor device. The step (c) is a step of implanting impurities perpendicular to the bottom surface of the recess.
A method for manufacturing a silicon carbide semiconductor device according to claim 5.

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