JP2012165036A - Spread spectrum clock generator - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a spread spectrum clock generator that reduces residual peak noise and prevents a jitter increase.SOLUTION: In the spread spectrum clock generator of an embodiment, a charge pump circuit 1 has a variable current source whose output current magnitude depends on a setting, and outputs a charge current for controlling a voltage applied to a VCO 11 for a period depending on a phase difference detected by a phase comparator 14.

Description

  Embodiments described herein relate generally to a spread spectrum clock generator.

  A spread spectrum clock generator is used as one of the countermeasures against the electromagnetic wave radiation problem that has become conspicuous as the clock frequency of a semiconductor integrated circuit increases.

  In the spread spectrum clock generator, the normal frequency division ratio N is periodically set to N + α (α is a frequency divider) that divides the output of a VCO (Voltage Controlled Oscillator) of a PLL (Phase Locked Loop) circuit. The value determined by the modulation depth) is alternately changed to N-α. At this time, since the gain of a normal PLL is constant, the larger the amount of phase difference output from the phase comparator, the larger the amount of change in the voltage input to the VCO, and (N + α) divided frequency, (N−α) ) Electromagnetic energy peaks remain at two frequency division frequencies, and the noise reduction effect is reduced.

  In addition, the charge pump to which the output of the phase comparator is input has a problem that the jitter increases at the peak frequency because the phase control sensitivity increases when the phase error amount is large.

JP 2006-2111479 A

  Therefore, the problem to be solved by the present invention is to provide a spread spectrum clock generator capable of reducing the residual peak noise and preventing an increase in jitter.

  In the spread spectrum clock generator of the embodiment, the charge pump circuit has a variable current source whose output current amount changes according to the setting, and the voltage applied to the VCO for a period according to the phase difference detected by the phase comparator A charge current for controlling the output is output.

1 is a block diagram showing an example of the configuration of a spread spectrum clock generator according to a first embodiment of the present invention. FIG. 3 is a circuit diagram showing an example of the configuration of a charge pump circuit and a charge current amount control unit used in the spread spectrum clock generator of the first embodiment. Operation | movement explanatory drawing of the charge current amount control part shown in FIG. FIG. 6 is a circuit diagram showing an example of another configuration of the variable current source in the charge pump circuit used in the spread spectrum clock generator of the first embodiment. The figure which shows the ideal phase error amount in the intermediate | middle time of the period which changes the division ratio of a program divider. The block diagram which shows the example of a structure of the spread spectrum clock generator concerning the 2nd Embodiment of this invention. A circuit diagram showing an example of composition of a charge pump circuit used with a spread spectrum clock generator of a 2nd embodiment. The block diagram which shows the example of a structure of the auxiliary current control part used with the spread spectrum clock generator of 2nd Embodiment. Operation | movement explanatory drawing of the auxiliary current control part shown in FIG. The block diagram which shows the example of a structure of the spread spectrum clock generator concerning the 3rd Embodiment of this invention. The block diagram which shows the example of a structure of the auxiliary current control part used with the spread spectrum clock generator of 2nd Embodiment. Operation | movement explanatory drawing of the auxiliary current control part shown in FIG.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. In the drawings, the same or corresponding parts are denoted by the same reference numerals, and the description thereof will not be repeated.

(First embodiment)
FIG. 1 is a block diagram showing an example of the configuration of a spread spectrum clock generator according to the first embodiment of the present invention.

  The spread spectrum clock generator of this embodiment has, as its basic configuration, a VCO 11, a programmable frequency divider 12 that divides the output clock CK0 of the VCO 11, and a frequency divider 13 that divides the reference clock signal CK by M. The phase comparator 14 that detects the phase difference between the output B of the programmable frequency divider 12 and the output A of the frequency divider 13, and the VCO 11 for a period according to the phase difference UP or DN detected by the phase comparator 14. A charge pump circuit 1 that outputs a charge current for controlling the voltage to be applied, and an LPF (low-pass filter) 15 that generates a voltage to be applied to the VCO 11 by smoothing the output of the charge pump circuit 1. A PLL circuit is provided.

  Furthermore, the spread spectrum clock generator of this embodiment includes a counter 16 that counts the number of frequency-divided clocks B output from the programmable frequency divider 12, and the programmable frequency divider 12 every time the counter 16 counts a certain period. And a frequency division ratio changing unit 17 for changing the frequency division ratio. The frequency division ratio changing unit 17 includes a switching unit 171 that switches a variation amount (+1, ± 0, −1) of the frequency division ratio of the programmable frequency divider 12 according to the count value CNT of the counter 16, and a normal frequency division ratio And an adder 172 that adds a fluctuation amount set by the switching unit 171 to N and outputs a division ratio to be supplied to the programmable frequency divider 12.

  The frequency division ratio changing unit 17 periodically increases or decreases the frequency division ratio of the programmable frequency divider 12, so that the spread spectrum clock generator of the present embodiment generates a clock whose frequency is modulated.

  In the spread spectrum clock generator of this embodiment, the charge pump circuit 1 has a variable current source whose output current amount changes according to the setting, and a charge current amount control that changes the charge current amount per unit time of the charge pump circuit 1. Part 2.

  The charge current amount control unit 2 changes the charge current amount per unit time of the charge pump circuit 1 by changing the setting for the variable current source of the charge pump circuit 1 according to the count value CNT of the counter 16.

  FIG. 2 shows an example of specific circuit configurations of the charge pump circuit 1 and the charge current amount control unit 2.

  The charge pump circuit 1 is turned on by the PMOS transistor PT whose conduction is controlled by a signal obtained by inverting the phase difference signal UP detected by the phase comparator 14 by the inverter IV and the phase difference DN detected by the phase comparator 14. Are connected in series, the variable current source VIG1 is connected to the PMOS transistor PT, and the variable current source VIG2 is connected to the NMOS transistor NT.

  The variable current source VIG1 includes three constant current sources IG11, IG12, and IG13 that can be connected in parallel, and switches SW11 and SW12 that change the number of parallel connections.

  Similarly, the variable current source VIG2 includes three constant current sources IG21, IG22, and IG23 that can be connected in parallel, and switches SW21 and SW22 that change the number of parallel connections.

  The switches SW11 and SW21 are turned on / off by the output signal S1 of the charge current amount control unit 2, and the switches SW12 and SW22 are turned on / off by the output signal S2 of the charge current amount control unit 2. .

  The variable current source VIG1 is a single connection of the constant current source IG11 when both the switches SW11 and SW12 are off. However, when the switch SW11 is turned on, the constant current source IG12 is connected in parallel to the constant current source IG11. When SW12 is turned on, the constant current source IG13 is further connected in parallel.

  Similarly, the variable current source VIG2 is a single connection of the constant current source IG21 when both the switches SW21 and SW22 are off, but when the switch SW21 is turned on, the constant current source IG22 is connected in parallel to the constant current source IG21. When the switch SW22 is further turned on, the constant current source IG23 is further connected in parallel.

  The charge current amount control unit 2 includes a comparator 211 that compares the count value CNT of the counter 16 with a threshold value C1, and a comparator 212 that compares the count value CNT of the counter 16 with a threshold value C2 (C2> C1). ing.

  The output signal S1 of the comparator 211 turns off the switches SW11 and SW21 when CNT <C1, and turns on the switches SW11 and SW21 when CNT ≧ C1.

  The output signal S2 of the comparator 212 turns off the switches SW12 and SW22 when CNT <C2, and turns on the switches SW12 and SW22 when CNT ≧ C2.

  As the count of the counter 16 advances by the control of the charge current amount control unit 2 as described above, the number of the constant current sources connected in parallel to the variable current source VIG1 and the variable current source VIG2 increases, and the variable current source VIG1 and the variable current source VIG1 The amount of current of the current source VIG2 increases.

  FIG. 3 shows the relationship between the phase error amount detected by the phase comparator 14 and the charge current amount per unit time of the charge pump circuit 1 with respect to the count value CNT of the counter 16.

  In the example shown in FIG. 3, the counter 16 is a counter having a repetition cycle of (K + 1). When the count value CNT is 0, the frequency division ratio of the programmable frequency divider 12 is (N + 1), and the count value CNT is 1. It is assumed that the frequency dividing ratio of the programmable frequency divider 12 is set to N during .about.K.

  Therefore, the phase error amount detected by the phase comparator 14 is the largest immediately after the division ratio of the programmable frequency divider 12 is set to (N + 1), and then the phase error amount gradually decreases. Here, the count value CNT is divided into periods of 0 to (C1-1), C1 to (C2-1), and C2 to K, and the phase error amount of each period is “large”, “medium”, and “small”. And

  In the present embodiment, the count values C1 and C2 for classifying the phase error amount are set as threshold values to be set in the charge current amount control unit 2 comparators 211 and 212.

  Therefore, the charge current amount per unit time of the charge pump circuit 1 is “small” during the period where the count value CNT is 0 to (C1-1), and “medium” during the period where the count value CNT is C1 to (C2-1). ", The period of the count value CNT from C2 to K changes to" large ".

PMOS transistor PT and NMOS transistor NT of charge pump circuit 1
As the amount of phase error detected by the phase comparator 14 increases, the conduction time becomes longer. Therefore, the output charge current amount of the charge pump circuit 1 is a value obtained by integrating the charge current amount per unit time of the charge pump circuit 1 with the phase error amount.

  In a general charge pump circuit, since the amount of charge current per unit time is fixed, the larger the phase error amount, the larger the output charge current amount of the charge pump circuit.

  However, in the charge pump circuit 1 of the present embodiment, the charge current amount per unit time is “small” while the phase error amount detected by the phase comparator 14 is “large”, and the phase error amount is “medium”. This period changes to “medium” and the period when the phase error amount is “small” to “large”.

  Therefore, the output charge current amount of the charge pump circuit 1 has a low correlation with the phase error amount, and the phase control sensitivity of the PLL circuit of this embodiment is flattened.

  As the variable current source VIG1 and the variable current source VIG2, a circuit including one constant current source and a variable resistor connected to the constant current source and having a resistance value controlled by the charge current amount control unit 2 is used. You may do it.

  FIG. 4 shows an example of a circuit of the variable current source VIG1 configured using a variable resistor. In this example, an R-2R ladder circuit as a variable resistor is connected to the constant current source IG1. The R-2R ladder circuit shunts the current I of the constant current source IG1 into 1/2 · I, 1/4 · I, and 1/8 · I. In the example illustrated in FIG. 4, the switches SW11 and SW12 are controlled by the output signals S1 and S2 of the charge current amount control unit 2. When the switch SW11 is turned on, the shunt current 1/4 · I is added to the shunt current 1/2 · I, and when the switch SW12 is turned on, the shunt current 1/8 · I is added.

  According to the present embodiment, the charge current amount per unit time of the charge pump circuit 1 can be changed according to the count value CNT of the counter 16, so that the phase of the output charge current amount of the charge pump circuit 1 can be changed. The correlation with the error amount can be lowered. Therefore, the amount of change in the frequency of the VCO 11 immediately after changing the frequency division ratio of the programmable frequency divider 12 to (N ± 1) can be reduced, and the residual peak noise can be reduced. Further, since the phase control sensitivity of the PLL circuit is flattened, the jitter immediately after (N ± 1) frequency division can be reduced.

(Second Embodiment)
In the first embodiment, the output B of the programmable frequency divider 12 and the output A of the frequency divider 13 are changed by changing the amount of charge current per unit time of the charge pump circuit 1 according to the count value CNT of the counter 16. The phase difference is reduced at a constant rate of change. Ideally, when the count value CNT of the counter 16 is 0, the phase difference corresponding to one cycle of the output clock CK0 of the maximum VCO 11 is preferably just 0 when the count value CNT of the counter 16 becomes K. . In this case, as shown in FIG. 5, when the count value CNT of the counter 16 is an intermediate value of the count cycle (K + 1), the phase error amount detected by the phase comparator 14 is ½ of the output clock CK0 of the VCO 11. Ideally, it is a period.

  That is, as shown in FIG. 5A, when the initial frequency division ratio of the programmable frequency divider 12 is (N + 1), the error amount of the phase error signal UP detected by the phase comparator 14 is the counter When the count value CNT of 16 is 0, the phase error amount corresponding to the cycle T of the output clock CK0 of the VCO 11 is shown. This is ideally ½ · T when the count value CNT of the counter 16 is ½ (K + 1).

  Similarly, when the initial frequency division ratio of the programmable frequency divider 12 is (N−1), it is detected by the phase comparator 14 when the count value CNT of the counter 16 is ½ (K + 1). Ideally, the error amount of the phase error signal DN is 1/2 · T.

  Therefore, in this embodiment, the error amount of the phase error signals UP and DN when the count value CNT of the counter 16 is an intermediate value of the count cycle is compared with the half cycle of the output clock CK0 of the VCO 11, and the phase transition amount is excessive. An example of a spread spectrum clock generator that can determine the shortage, correct the charge current amount per unit time of the charge pump circuit according to the determination result, and adjust the phase transition amount thereafter.

  FIG. 6 is a block diagram showing an example of the configuration of the spread spectrum clock generator according to the second embodiment of the present invention.

  The present embodiment is different from the first embodiment in that the charge pump circuit 1A has auxiliary current sources connected in parallel to the variable current sources VIG1 and VIG2, and the output current amount of the auxiliary current source. The auxiliary current amount control unit 3 for controlling the above is provided. Here, blocks having the same functions as those shown in FIG. 1 are denoted by the same reference numerals as those in FIG. 1, and detailed descriptions thereof are omitted.

  FIG. 7 is a circuit diagram showing an example of a specific circuit configuration of the charge pump circuit 1A.

  In the charge pump circuit 1A shown in FIG. 7, the auxiliary current source HIG1 is connected in parallel to the variable current source VIG1 and the auxiliary current source is connected in parallel to the variable current source VIG2 with respect to the configuration of the charge pump circuit 1 shown in FIG. HIG2 is connected.

  The auxiliary current source HIG1 has two constant current sources IG31 and IG32 that can be connected in parallel, and switches SW31 and SW32 that change the number of parallel connections.

  Similarly, the auxiliary current source HIG2 has two constant current sources IG41 and IG42 that can be connected in parallel, and switches SW41 and SW42 that change the number of parallel connections.

  The switches SW31 and SW41 are turned on / off by the output signal H1 of the auxiliary current amount control unit 3, and the switches SW32 and SW42 are turned on / off by the output signal H2 of the auxiliary current amount control unit 3. .

  FIG. 8 shows an example of the configuration of the auxiliary current amount control unit 3.

  In the example illustrated in FIG. 8, the auxiliary current amount control unit 3 includes a comparator 311 that compares the signal width of the phase error signal UP output from the phase comparator 14 with a half cycle of the output clock CK0 of the VCO 11, and a phase comparator. 14 for comparing the signal width of the phase error signal DN output from 14 with the half cycle of the output clock CK0 of the VCO 11, and the comparator 311 when the count value CNT of the counter 16 is 1/2 (K + 1) or And a determination unit 32 that determines whether the phase transition amount is excessive or insufficient based on the output of the comparator 312.

  The determination unit 32 determines the signal levels of the output signals H1 and H2 based on the determination of whether the phase transition amount is excessive or insufficient, controls on / off of each switch of the auxiliary current sources HIG1 and HIG2, and supplies the auxiliary current sources HIG1 and HIG1, Adjust the output current amount of HIG2.

  FIG. 9 shows the relationship between the determination of the determination unit 32 of the auxiliary current amount control unit 3 and the on / off control of the switches of the auxiliary current sources HIG1 and HIG2 by the output signals H1 and H2. Here, in the initial state, the output signal H1 is set to turn on the switch to be controlled, and the output signal H2 is set to turn off the switch to be controlled. That is, in the initial state, the auxiliary current source HIG1 outputs the current of the constant current source IG31, and the auxiliary current source HIG2 outputs the current of the constant current source IG41.

  As shown in FIG. 9A, the determination unit 32 compares the phase width of the phase error signal UP output from the phase comparator 14 with the half cycle of the output clock CK0 of the VCO 11 with respect to the phase transition amount. When it is wide, it is judged as “insufficient”, when it is equal, “appropriate”, and when it is narrow, it is judged as “excess”.

  FIG. 9B shows the relationship between this determination and the on / off state of the switches controlled by the output signals H1 and H2.

  When the determination is “insufficient”, the output signals H1 and H2 respectively turn on the switches to be controlled. Thereby, the auxiliary current source HIG1 outputs an addition current of the constant current source IG31 and the constant current source IG32, and the auxiliary current source HIG2 outputs an addition current of the constant current source IG41 and the constant current source IG42. That is, each output current increases compared to the initial state. As a result, the phase transition rate increases and the shortage of the phase transition amount is resolved.

  When the determination is “appropriate”, the output signals H1 and H2 control the respective switches so as to maintain the initial state. Thereby, the current phase transition rate is maintained.

  When the determination is “excess”, the output signals H1 and H2 turn off the switches to be controlled. As a result, no current is output from the auxiliary current sources HIG1 and HIG2. That is, each output current decreases compared to the initial state. As a result, the phase transition rate decreases, and the excess of the phase transition amount is resolved.

  In this embodiment, it is determined whether or not the phase error amount is a half cycle of the output clock CK0 of the VCO 11 at an intermediate point of the cycle in which the phase error amount for one cycle of the output clock CK0 of the VCO 11 is provided. The determination result is fed back to the charge current control per unit time of the charge pump circuit 1A. Therefore, the charge current amount per unit time of the charge pump circuit is corrected, and the subsequent phase transition rate is optimized. As a result, smoother spread spectrum characteristics can be obtained.

  In addition, since the above-described feedback control always works during the spread spectrum operation, it is possible to prevent the PLL characteristics from being affected by temperature fluctuations or the like.

  If the steady phase difference suddenly increases due to disturbance or the like, the phase transition amount is determined at, for example, about three points before and after the intermediate time point, and comprehensively determined from the determination result. Good.

(Third embodiment)
In the second embodiment, in the determination by the determination unit 32 of the auxiliary current amount control unit 3, the phase error amount indicated by the phase error signals UP and DN output from the phase comparator 14 is the half cycle of the output clock CK0 of the VCO 11. Is equal to the phase transition amount is determined to be “appropriate”. That is, there is one determination point. Therefore, this “appropriate” determination is a fairly critical determination. For this reason, when the phase error amount approaches the half cycle of the output clock CK0 of the VCO 11, the determination of “insufficient” and “excess” may appear alternately, and the charge current amount per unit time of the charge pump circuit 1A oscillates. May change. Therefore, in the present embodiment, an example of a spread spectrum clock generator capable of setting a width in which the phase transition amount is determined to be “appropriate” is shown.

  FIG. 10 is a block diagram showing an example of the configuration of a spread spectrum clock generator according to the third embodiment of the present invention.

  Although the basic configuration of this embodiment is the same as that of the second embodiment, in this embodiment, the output clock CK0 of the VCO 11 is sequentially delayed by the delay units 4 and 5, and the clock having a phase different from that of the clock CK0. CK1 and CK2 are generated, and the clock CK1 is used as a clock to be input to the program frequency divider 12. Note that the program frequency divider 12 performs a frequency dividing operation in synchronization with the falling edge of the clock CK1.

  As a result, the clock CK0 becomes a clock whose phase is advanced with respect to the input clock CK1 of the program frequency divider 12, and the clock CK2 becomes a clock whose phase is delayed.

  Therefore, the auxiliary current amount control unit 3A of the present embodiment determines the phase transition amount using the clock CK0 and the clock CK2. In this case, the sum of the delay times of the delay units 4 and 5 is a width for determining that the phase transition amount is “appropriate”.

  FIG. 11 shows an example of the circuit configuration of the auxiliary current amount control unit 3A.

  In the example shown in FIG. 11, the auxiliary current amount control unit 3A outputs the output of the frequency divider 13 with the register 331 that takes in the output A of the frequency divider 13 with the output clock CK0 of the VCO 11 and the clock CK2 output from the delay device 5. A register 332 for capturing A, a selector 341 for selecting either the normal output Q or the inverted output QN of the register 331, a selector 342 for selecting either the normal output Q or the inverted output QN of the register 332, and a counter And a determination unit 35 that determines whether the phase transition amount is excessive or insufficient based on the output Q1 of the selector 341 and the output Q2 of the selector 342 when the count value CNT of 16 indicates 1/2 (K + 1).

  The selection of the selectors 341 and 342 is switched by a switching signal Y output from the switching unit 171 of the frequency division ratio changing unit 17. That is, when the switching signal Y is +1 (the division ratio of the program divider 12 is N + 1), the normal output Q of the registers 331 and 332 is selected, and the switching signal Y is −1 (the program divider 12 When the frequency division ratio is N−1), the inverted output QN of the registers 331 and 332 is selected. This switching is based on the phase relationship between the output A of the frequency divider 13 and the output B of the program frequency divider 12 when the frequency division ratio of the program frequency divider 12 is (N + 1) and (N−1). It is for dealing with reversal.

  Next, the operation of the auxiliary current amount control unit 3A will be described with reference to FIG. Here, a case where the program frequency divider 12 performs (N + 1) frequency division will be described as an example. The waveforms shown in FIGS. 12A to 12C are waveforms at the time when the count value CNT of the counter 16 shows 1/2 (K + 1).

  As shown in FIG. 12A, when the phase transition amount is insufficient, the output A of the frequency divider 13 rises earlier than the rise of the clock CK0. Therefore, the normal output Q (Q1) of the register 331 and the normal output Q (Q2) of the register 332 are both “H”.

  On the other hand, as shown in FIG. 12B, when the rising edge of the output A of the frequency divider 13 is later than the rising edge of the clock CK0 and earlier than the rising edge of the clock CK2, the normal output Q (Q1) of the register 331. Becomes “L”, and the normal output Q (Q2) of the register 332 becomes “H”. As described above, when the rising edge of the output A of the frequency divider 13 is between the rising edge of the clock CK0 and the rising edge of the clock CK2, and the outputs of the register 331 and the register 332 have different values, the determination unit 35 determines the phase transition amount. Is determined to be “appropriate”.

  Further, as shown in FIG. 12C, when the phase transition amount is excessive, the output A of the frequency divider 13 rises later than the rise of the clock CK2. Accordingly, the normal output Q (Q1) of the register 331 and the normal output Q (Q2) of the register 332 are both “L”.

  FIG. 12D shows the relationship between the signal levels of Q1 and Q2 input to the determination unit 35, the determination of the phase transition amount, and the on / off state of the switches controlled by the output signals H1 and H2.

  The determination unit 35 determines that the phase transition amount is “insufficient” when both of the input Q1 and Q2 signal levels are “H”, and when Q1 is “L” and Q2′H, When it is determined as “appropriate” and both the signal levels of Q1 and Q2 are “L”, it is determined as “excess”.

  Note that the relationship between the determination of the phase transition amount and the ON / OFF state of the switch controlled by the output signals H1 and H2 is the same as in the second embodiment, and thus the description thereof is omitted here.

  According to the present embodiment as described above, by setting the delay time of the delay units 4 and 5, it is possible to arbitrarily set the width in which the phase transition amount is determined to be “appropriate”. For this reason, when the phase error amount approaches the half cycle of the output clock CK0 of the VCO 11, it is possible to prevent the charge current amount per unit time of the charge pump circuit 1A from changing unnecessarily.

  According to the spread spectrum clock generator of at least one embodiment described above, residual peak noise can be reduced and an increase in jitter can be prevented.

  Moreover, although some embodiment of this invention was described, these embodiment is shown as an example and is not intending limiting the range of invention. These novel embodiments can be implemented in various other forms, and various omissions, replacements, and changes can be made without departing from the scope of the invention. These embodiments and modifications thereof are included in the scope and gist of the invention, and are included in the invention described in the claims and the equivalents thereof.

1, 1A Charge pump circuit 2 Charge current amount control unit 3, 3A Auxiliary current amount control unit 4, 5 Delay devices 211, 212, 311, 312 Comparator 32, 35 Determination unit 331, 332 Register 341, 342 Selector VIG1, VIG2 Variable current sources HIG1, HIG2 Auxiliary current sources IG1, IG11 to IG13, IG21 to IG23, IG31, IG32, IG41, IG42 Constant current sources SW11, SW12, SW21, SW22, SW31, SW32, SW41, SW42 Switch PT PMOS transistor NT NMOS Transistor IV Inverter R, 2R Resistor 11 VCO
12 Programmable frequency divider 13 Frequency divider 14 Phase comparator 15 LPF
16 Counter 17 Dividing ratio changing unit 171 Switching unit

Claims (5)

A VCO, a programmable frequency divider that divides the output clock of the VCO, a frequency divider that divides a reference clock signal, and a phase difference between the output of the programmable frequency divider and the output of the frequency divider are detected. A PLL circuit having a phase comparator for counting, a counter for counting the number of frequency-divided clocks output from the programmable frequency divider, and a frequency divider for the programmable frequency divider every time the counter counts a certain period A spread ratio clock generator for generating a clock whose frequency is modulated by periodically increasing or decreasing the frequency dividing ratio of the programmable frequency divider,
A charge pump having a variable current source whose output current amount changes according to a setting, and outputs a charge current for controlling a voltage applied to the VCO for a period corresponding to a phase difference detected by the phase comparator Circuit,
A spread spectrum clock, comprising: charge current amount control means for changing the setting of the variable current source according to a count value of the counter and changing a charge current amount per unit time of the charge pump circuit. generator. The charge current amount control means includes:
2. The output current amount of the variable current source is decreased at the start of counting of the counter, and the output current amount of the variable current source is increased as the count value of the counter increases. Spread spectrum clock generator. The charge pump circuit is connected in parallel to the variable current source, and has an auxiliary current source that outputs a constant current in an initial state;
The time point when the count value of the counter shows a predetermined value is an observation time point, and based on the observation time phase difference that is the phase difference between the output of the programmable frequency divider and the output of the frequency divider at the observation time point The spread spectrum clock generator according to claim 1 or 2, further comprising auxiliary current amount control means for controlling an output current amount of the auxiliary current source. The variable current source is
A plurality of constant current sources;
4. The spread spectrum clock according to claim 1, further comprising: a switch group that changes a number of parallel connections of the plurality of constant current sources by switching control by the charge current amount control unit. 5. generator. The variable current source is
A constant current source;
The spread spectrum clock generator according to any one of claims 1 to 3, further comprising a variable resistor connected to the constant current source and having a resistance value controlled by the charge current amount control means.

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