WO2018131084A1

WO2018131084A1 - Pll circuit

Info

Publication number: WO2018131084A1
Application number: PCT/JP2017/000541
Authority: WO
Inventors: 裕貴柳原; 恒次堤; 下沢　充弘
Original assignee: 三菱電機株式会社
Priority date: 2017-01-11
Filing date: 2017-01-11
Publication date: 2018-07-19
Also published as: JPWO2018131084A1; JP6556383B2

Abstract

With a conventional PLL circuit, circuit characteristics change dynamically due to temperature changes and degradation over time, and therefore there was the problem that it was difficult to find suitable application parameters for DAC. This PLL circuit comprises: frequency dividers for dividing oscillation signals; a phase frequency comparator for comparing a reference signal with oscillation signals divided by the frequency dividers, and outputting signals according to the difference thereof; a loop filter that blocks high frequency components of signals output by the phase frequency comparator, and outputs signals for which the high frequency components are blocked; an oscillator that changes the oscillating frequency according to the output signals of the loop filter, and outputs oscillation signals; a digital signal processor for finding the frequency of the oscillation signals; a parameter control circuit for finding control parameters on the basis of the frequency of the oscillation signal found by the digital signal processor; and a digital analog converter that outputs analog signals to the loop filter or the oscillator according to the control parameters, and corrects the time change of the oscillating frequency.

Description

PLL circuit

The present invention relates to a PLL (Phase Locked Loop) circuit.

When using a PLL to output a signal whose frequency changes steeply like a sawtooth wave, the PLL cannot follow the set waveform at the point where the frequency changes sharply, and it takes time to output the correct frequency again. There is a problem. In order to solve this, PLLs shown in the following non-patent documents have been proposed. This PLL connects the control terminal of the VCO (Voltage Controlled Oscillator) with a DAC (Digital-to-Analog-Converter) through a switch, turns on the switch at a point where the frequency changes sharply, and connects the DAC to the control terminal of the VCO. By applying this output, the time until the PLL outputs the correct frequency again is shortened.

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However, due to variations in circuit characteristics (VCO control voltage-frequency characteristics, DAC control code-output voltage characteristics, etc.), appropriate application parameters (applied voltage, application time, etc.) for this method to operate correctly are There is a problem in that it is difficult to obtain an appropriate applied parameter because the circuit characteristics dynamically change due to temperature changes and aging deterioration.

The PLL circuit of the present invention compares a frequency divider that divides an oscillation signal whose frequency changes with time, a reference signal and an oscillation signal that is divided by the frequency divider, and outputs a signal corresponding to the difference. The frequency comparator and the phase filter output the high-frequency component of the signal output from the phase filter, a loop filter that outputs the signal from which the high-frequency component is blocked, and the oscillation signal is changed according to the output signal of the loop filter. An output oscillator, a digital signal processor for obtaining the frequency of the oscillation signal, a parameter control circuit for obtaining a control parameter based on the frequency of the oscillation signal obtained by the digital signal processor, and an analog signal to the loop filter or the oscillator according to the control parameter And a digital-to-analog converter that corrects the time variation of the oscillation frequency of the oscillator.

According to the present invention, there is an effect that an appropriate applied parameter can be obtained dynamically in accordance with a change in circuit characteristics due to a temperature change or aged deterioration.

1 is a configuration diagram illustrating a configuration example of a PLL circuit according to a first embodiment of the present invention. It is a conceptual diagram showing the relationship between the applied voltage of DAC12 which concerns on Embodiment 1 of this invention, and convergence time. It is a block diagram which shows the modification of the PLL circuit of Embodiment 1 of this invention. It is a block diagram which shows one structural example of the PLL circuit which concerns on Embodiment 2 of this invention. It is a block diagram which shows the modification of the PLL circuit which concerns on Embodiment 2 of this invention.

Embodiment 1.
FIG. 1 is a block diagram showing a configuration example of a PLL circuit according to Embodiment 1 of the present invention. The PLL circuit includes a PFD (Phase Frequency Detector) 1, a CP (Charge Pump) 2, an LF (Loop Filter) 3, a VCO 4, a frequency divider 5, a ΔΣ modulator 6, a chirp generation circuit 7, a parameter control circuit 8, a frequency A conversion circuit 9, an ADC (Analog to Digital Converter) 10, a DSP (Digital Signal Processor) 11, a DAC 12, and a switch 13 are provided.

PFD1 (an example of a phase frequency comparator) is a PFD that compares the phases of the reference signal and the output signal of the frequency divider 5 and outputs a signal corresponding to the phase difference to CP2. The reference signal is supplied from a signal source such as a crystal oscillator.

CP2 is a charge pump circuit that converts the output signal of PFD1 into a current and outputs the converted current to LF3.

LF3 (an example of a loop filter) is an LF that blocks a high-frequency component included in the current converted by CP2, and outputs the blocked signal to the VCO 4.

VCO 4 (an example of an oscillator) is a VCO that changes the oscillation frequency in accordance with a signal output by LF 3.

The frequency divider 5 (an example of a frequency divider) divides the oscillation signal output from the VCO 4 in accordance with the frequency division ratio setting signal output from the ΔΣ modulator 6 and supplies the divided signal to the PFD 1 and the ΔΣ modulator 6. This is the output frequency divider.

The ΔΣ modulator 6 (an example of the ΔΣ modulator) operates using the output signal of the frequency divider 5 as a clock, generates a frequency division ratio setting signal according to the output signal of the chirp generation circuit 7, and generates the generated frequency division ratio This is a ΔΣ modulator that outputs a setting signal to the frequency divider 5.

The chirp generation circuit 7 outputs a chirp signal linearly changing with respect to time to the ΔΣ modulator 6 corresponding to the frequency division ratio of the PLL circuit, and at the timing when the frequency of the PLL circuit changes sharply. This is a circuit that outputs a signal to the parameter control circuit 8. For example, the chirp generation circuit 7 is a digital circuit, and an ASIC (Application Specific Integrated Circuit), an FPGA (Field-Programmable Gate Array), a microcomputer, or the like is used.

The parameter control circuit 8 is a parameter control circuit 8 that generates control parameters for controlling the DAC 12 and the switch 13 and outputs the generated parameters to the DAC 12 and the switch 13. The parameter control circuit 8 outputs a signal for controlling ON / OFF of the switch 13 in synchronization with a signal indicating a timing at which the frequency of the PLL circuit output from the chirp generation circuit 7 changes sharply. The parameter control circuit 8 outputs a control signal indicating the output voltage of the DAC 12 to the DAC 12. For example, the parameter control circuit 8 is a digital circuit, and an ASIC, FPGA, microcomputer, or the like is used.

The frequency conversion circuit 9 is a frequency conversion circuit that converts the frequency of the output signal of the VCO 4 and outputs the frequency-converted signal to the ADC 10. The frequency conversion circuit 9 includes a frequency divider 21 that divides the reference signal, a frequency divider 22 that divides the output signal of the VCO, a signal that the frequency divider 21 divides, and a signal that the frequency divider 22 divides. Is provided. The frequency dividing ratio of the frequency divider 21 may be 1. In this case, the frequency divider 21 may be deleted and the reference signal may be input directly to the mixer 23.

The ADC 10 is an ADC that converts the analog signal frequency-converted by the frequency conversion circuit 9 into a digital signal and outputs the converted digital signal to the DSP 11.

The DSP 11 (an example of a digital signal processor) obtains the instantaneous frequency of the output signal of the VCO 4 from the digital signal converted by the ADC 10, and an error between the desired frequency and the obtained instantaneous frequency in the chirp signal (modulated wave) output from the VCO 4. Is a DSP that calculates a convergence time when becomes a predetermined value or less, and outputs the calculated convergence time to the parameter control circuit 8. As a method for obtaining the instantaneous frequency, for example, there is a method of orthogonally demodulating an input signal, obtaining an instantaneous phase, and calculating the instantaneous frequency from the instantaneous phase.

Note that, at the point where the frequency of the modulation wave changes sharply, the PLL circuit cannot follow the sudden change in frequency, and an error between the desired frequency and the actual frequency increases, but the desired frequency and the actual frequency gradually increase. Will match. The desired frequency is a frequency corresponding to the chirp signal generated by the chirp generation circuit 7, that is, a frequency obtained by multiplying the frequency of the reference signal by the frequency division ratio indicated by the chirp signal. Here, the time until the desired frequency and the actual frequency match with a certain error is called the convergence time. In other words, the convergence time is the time until the error between the desired frequency (desired chirp signal) and the actual frequency (actual chirp signal) falls within a predetermined value.

The DAC 12 (an example of a digital-analog converter) is a DAC that generates an analog signal in accordance with a control signal from the parameter control circuit 8 and outputs the generated analog signal to the switch 13.

The switch 13 (an example of a switch) is a switch that switches between ON and OFF according to the control signal of the parameter control circuit 8 and controls whether or not the output signal of the DAC 12 is transmitted to the VCO 4.

Next, the operation of the PLL circuit according to the first embodiment of the present invention will be described.

First, the chirp generation circuit 7 generates a signal proportional to a desired modulation wave and outputs it to the ΔΣ modulator 6. For example, if the desired modulation wave is a sawtooth wave, the chirp generation circuit 7 generates a sawtooth wave. In addition, the chirp generation circuit 7 outputs a pulse signal that rises at a timing when the output frequency of the PLL circuit changes sharply to the parameter control circuit 8. This pulse signal is called a frequency jump signal. The frequency jump signal is a 1-bit digital signal, and the rising timing means the timing when the output frequency of the present PLL circuit changes sharply.

The ΔΣ modulator 6 applies ΔΣ modulation to a signal proportional to the desired modulation wave generated by the chirp generation circuit 7 and outputs the result to the frequency divider 5. The signal proportional to the desired modulation wave generated by the chirp generation circuit 7 includes a decimal number, but the frequency divider 5 realizes a fractional division ratio by converting it into an integer with a ΔΣ modulator and performing ΔΣ modulation.

The frequency divider 5 divides the signal of the VCO 4 in accordance with the frequency division ratio signal output from the ΔΣ modulator 6.

PFD 1 outputs a signal corresponding to the phase difference between the reference signal and the output of frequency divider 5 to CP 2.

CP2 outputs a current corresponding to the output of PFD1 to LF3.

LF3 cuts off the high frequency component of the signal output from CP2, and outputs the signal that cut off the high frequency component to VCO4.

The VCO 4 outputs an oscillation signal according to the applied control voltage.

The frequency conversion circuit 9 converts the frequency of the input VCO 4 signal and outputs it to the ADC 10.

The ADC 10 samples the input at regular intervals, converts it to a digital signal, and outputs it to the DSP 11.

The DSP 11 orthogonally demodulates the signal output from the ADC 10 to obtain an instantaneous phase, and calculates an instantaneous frequency from the instantaneous phase. The DSP 11 calculates an error between a desired frequency and an actual frequency in the modulated wave. In general, the PLL circuit cannot follow the steep change in frequency at the point where the frequency of the modulation wave changes sharply, and an error between the desired frequency and the actual frequency becomes large. The DSP 11 compares the time change of the detected actual frequency of the PLL with the time change of the desired frequency, calculates the convergence time until the error between the two becomes a predetermined value or less, and sets the convergence time to the parameter control circuit 8. Output to. The DSP 11 stores parameters such as the slope and length of the chirp signal necessary for obtaining the desired frequency in an internal memory, calculates the desired frequency with reference to these parameters, and calculates the actual frequency. Used to calculate frequency error. Alternatively, the chirp signal itself may be stored.

The parameter control circuit 8 obtains the output voltage of the DAC 12 from the convergence time output from the DSP 11 and outputs the obtained output voltage to the DAC 12. The parameter control circuit 8 turns on the switch 13 in synchronization with the frequency jump signal output from the chirp generation circuit 7 and turns off the switch 13 when the ON time of the switch 13 obtained from the convergence time elapses. Here, the ON time is a time during which the switch 13 is ON. The signal output from the parameter control circuit 8 to the switch 13 is a 1-bit digital signal, which means “1” means switch ON and “0” means switch OFF. As will be described later, the parameter control circuit 8 may calculate the set time of the DAC 12 and the ON time of the switch 13 from the convergence time, or a table showing the relationship between the convergence time, the set time of the DAC 12 and the ON time of the switch 13. May be stored in the memory, and the set time of the DAC 12 and the ON time of the switch 13 may be obtained from the table.

The DAC 12 sets the output voltage according to the control signal output from the parameter control circuit 8 and outputs the set voltage to the switch 13.

The switch 13 controls ON / OFF according to the control signal output from the parameter control circuit 8, and outputs the output voltage of the DAC 12 to the VCO 4 while the switch 13 is ON. When it is OFF, the output signal of the DAC 12 is blocked.

VCO 4 outputs an oscillation frequency according to a composite voltage of the output voltage of LF 4 and the output voltage of DAC 12 while switch 13 is ON.

After the switch 13 is turned off, the DSP 11 measures the convergence time until the error between the desired frequency and the actual frequency is equal to or less than a predetermined value, and converges to the parameter control circuit 8 in the same manner as described above. Output time.

The parameter control circuit 8 changes two parameters of the output voltage of the DAC 12 and the ON time of the switch 13 according to the convergence time. The parameter control circuit 8 outputs the output voltage of the DAC 12 to the DAC 12 as needed. Then, the parameter control circuit 8 turns on the switch 13 in synchronization with the next frequency jump signal, and turns off the switch 13 when the ON time of the switch 13 elapses. After that, the convergence time is measured again by the DSP 11, and the parameter control circuit 8 changes two parameters of the output voltage of the DAC 12 and the ON time of the switch 13 according to the convergence time.

By repeating this flow, the parameter control circuit 8 searches for a parameter that minimizes the convergence time.

FIG. 2 is a conceptual diagram showing the relationship between the voltage applied to DAC 12 and the convergence time according to Embodiment 1 of the present invention.
As shown in FIG. 2, when the application amount from the DAC 12 is too large (see FIG. 2A) and too small (see FIG. 2C), the application amount by the DAC 12 is appropriate (FIG. 2). Compared to (b)), the convergence time becomes longer. That is, by observing the convergence time and searching for a parameter that minimizes the convergence time, an appropriate application parameter can be obtained. For example, the following two methods can be used to search for a parameter that minimizes the convergence time.

The first method sweeps two parameters, the output voltage of the DAC 12 and the ON time of the switch 13, over the entire range, stores each convergence time, and creates a table of convergence times corresponding to the parameter values. It is a technique. Finally, the parameter control circuit 8 employs a parameter value that minimizes the convergence time, and generates a modulated wave.

The second method is the gradient descent method, which is a minimization algorithm. The parameter control circuit 8 calculates the gradient from the change in convergence time with respect to the change in each parameter, and reaches the minimum value by changing the parameter so as to decrease the gradient. The parameter control circuit 8 employs the parameter value and generates a modulated wave.

As described above, according to the first embodiment of the present invention, the convergence time is fed back and the applied voltage and the applied time are adjusted, so that it is dynamically appropriate according to changes in circuit characteristics due to temperature changes and aging deterioration. There is an effect that the applied parameter can be obtained. By performing feedback so as to minimize the convergence time, it is possible to minimize the invalid time that deviates from the desired frequency and to increase the proportion of the time that is effective as a signal.

Note that the PLL circuit of the first embodiment may be configured such that the output of the VCO 4 is input to the frequency divider and the output of the frequency divider is input to the frequency divider 5 and the frequency divider 22.

FIG. 3 is a configuration diagram showing a modification of the PLL circuit according to the first embodiment of the present invention.
In the configuration shown in FIG. 3, the operating frequency of the frequency divider 5 and the frequency divider 22 is lowered, so that the frequency division ratio is also reduced. Since the frequency divider has a feature that the power consumption increases as it operates at a higher frequency, providing the frequency divider 31 (an example of a second frequency divider) reduces the overall power consumption. In addition, since the frequency dividing ratio of the frequency divider 5 and the frequency divider 22 is reduced, the overall circuit scale is reduced by providing the frequency divider 31.

If a DAC capable of setting the output impedance to high impedance is used as the DAC 12, the same operation is performed by setting the output impedance of the DAC 12 to high impedance instead of turning off the switch 13 without using the switch 13. be able to. In that case, the parameter control circuit 8 controls whether or not the output impedance of the DAC 12 is set to high impedance instead of the switch 13.

A configuration in which the voltage output from the DAC 12 is changed over time is also conceivable. In this case, the parameter control circuit 8 controls the time waveform of the output voltage of the DAC 12. At this time, since the time waveform needs to be synchronized with the frequency jump signal output from the chirp generation circuit 7, the parameter control circuit 8 controls the output voltage of the DAC 12 in synchronization with the frequency jump signal.

Embodiment 2.
FIG. 4 is a block diagram showing a configuration example of a PLL circuit according to Embodiment 2 of the present invention.
In the configuration of the second embodiment, the DAC 12 and the switch 13 of the first embodiment are deleted, the newly added CP41 (an example of a charge pump circuit) is connected to the output terminal of CP2, and the parameter control circuit 8 In this configuration, the CP 41 is controlled. The difference from the first embodiment is that, while the first embodiment uses the DAC 12 and the switch 13 to apply a voltage to the output terminal of the LF3, the second embodiment has the CP41 connected to the input terminal of the LF3. Applying current.

CP 41 is a charge pump circuit that applies a current to LF 3 in accordance with a control signal from parameter control circuit 8.

Next, the operation of the PLL circuit according to the second embodiment of the present invention will be described.
Since operations other than the parameter control circuit 8 and CP41 are the same as those in the first embodiment, the parameter control circuit 8 and CP41 will be mainly described.

The parameter control circuit 8 obtains the set current of the CP 41 and the ON time of the CP 41 from the convergence time output from the DSP 11. The parameter control circuit 8 outputs a set current to the CP 41 as needed, and outputs a control signal for turning on the CP 41 in synchronization with the frequency jump signal output from the chirp generation circuit 7. Then, the parameter control circuit 8 outputs a signal for turning off the CP 41 when the ON time of the CP 41 elapses. The control signal output by the parameter control circuit 8 is a 1-bit digital signal. When “1”, it means ON, and when it is “0”, it means OFF. The parameter control circuit 8 searches for the output current and ON time of the CP 41 so as to minimize the convergence time measured by the DSP 11 in the same manner as in the first embodiment, and operates using the parameters obtained thereafter. To do.

CP 41 applies a current to LF 3 for a predetermined time according to the control signal of parameter control circuit 8. In the point where the frequency changes sharply, the CP 41 injects an appropriate charge into the LF 3 to shorten the time until the correct frequency is output again.

LF3 cuts off the high frequency component of the output current of CP2 and the output current of CP41 and outputs it to VCO4 during the ON time.

VCO 4 controls the oscillation frequency according to the output signal of LF 3 and outputs an oscillation signal.

As described above, according to the second embodiment of the present invention, the convergence time is fed back and the applied current and the applied time of the CP 41 are adjusted. Therefore, according to the change in the circuit characteristics due to the temperature change and the aging deterioration, There is an effect that an appropriate applied parameter can be obtained. When an active filter is used as the loop filter, the output voltage of the loop filter cannot be directly applied from the outside to obtain a desired value, and the first embodiment cannot be used. However, in the configuration using CP41, the loop filter Since charges are injected into the input, it can be used in an active filter.

In the PLL circuit according to the second embodiment, the frequency divider 31 is loaded on the feedback path of the VCO 4, the oscillation signal of the VCO 4 is output to the frequency divider 31, and the signal divided by the frequency divider 31 is divided. 5 may be output.

FIG. 5 is a block diagram showing a modification of the PLL circuit according to Embodiment 2 of the present invention.
By inserting the frequency divider 31 as shown in FIG. 5, the power consumption as a whole can be reduced and the circuit scale can be reduced for the same reason as described in the first embodiment.

1 PFD, 2 CP, 3 LF, 4 VCO, 5 divider, 6 ΔΣ modulator, 7 chirp generation circuit, 8 parameter control circuit, 9 frequency conversion circuit, 10 ADC, 11 DSP, 12 DAC, 13 switch, 21 Frequency divider, 22 divider, 23 mixer, 31 divider, 41 CP.

Claims

A frequency divider that divides an oscillation signal whose frequency changes over time;
A phase frequency comparator that compares a reference signal and the oscillation signal divided by the divider and outputs a signal corresponding to the difference;
A loop filter that blocks a high-frequency component of the signal output by the phase frequency comparator, and outputs a signal that blocks the high-frequency component;
According to the output signal of the loop filter, an oscillator that changes the oscillation frequency and outputs the oscillation signal;
A digital signal processor for determining the frequency of the oscillation signal;
A parameter control circuit for obtaining a control parameter based on the frequency of the oscillation signal obtained by the digital signal processor;
A digital-to-analog converter that outputs an analog signal to the loop filter or the oscillator according to the control parameter, and corrects a temporal change in the oscillation frequency of the oscillator;
A PLL circuit comprising:
The digital signal processor compares the time change of the oscillation frequency set in the oscillator via the frequency division ratio of the frequency divider and the time change of the frequency of the oscillation signal output from the oscillator to compare the oscillation Obtaining a convergence time for a signal, and outputting the convergence time to the parameter control circuit;
The PLL circuit according to claim 1, wherein the parameter control circuit obtains the control parameter from the convergence time.
A switch that is provided between the loop filter or the oscillator and the digital-analog converter, and that passes or cuts off a voltage output by the digital-analog converter;
The parameter control circuit obtains an ON time of the switch and an output voltage of the digital-analog converter from the convergence time, controls the switch based on the ON time, and uses the output voltage as the control parameter. The PLL circuit according to claim 2, wherein the digital-analog converter is controlled.
A chirp generation circuit that generates a chirp signal indicating a frequency change of the oscillation signal, and outputs a timing at which the frequency of the chirp signal changes to the parameter control circuit;
A ΔΣ modulator that ΔΣ modulates the chirp signal;
With
The frequency divider divides the oscillation signal according to the chirp signal that is ΔΣ-modulated,
The PLL circuit according to claim 3, wherein the parameter control circuit turns on the switch according to the timing.
3. The PLL circuit according to claim 2, wherein a current is output to the loop filter using a charge pump circuit instead of the digital-analog converter.
6. The PLL circuit according to claim 5, wherein the parameter control circuit controls an applied current and an applied time of the charge pump circuit according to the convergence time.
A second frequency divider provided between the oscillator and the frequency divider, which divides the oscillation signal output by the oscillator and outputs the frequency-divided oscillation signal to the frequency divider; The PLL circuit according to claim 4 or 6, wherein