JPWO2018131084A1 - PLL circuit - Google Patents

Abstract

In the conventional PLL circuit, since the circuit characteristics dynamically change due to temperature change and aging deterioration, there is a problem that it is difficult to obtain an appropriate application parameter of the DAC. The PLL circuit according to the present invention comprises a frequency divider for dividing an oscillation signal, and a phase frequency comparator for comparing a reference signal with the oscillation signal divided by the frequency divider and outputting a signal according to the difference. A loop filter that cuts off high frequency components of the signal output from the phase frequency comparator and outputs a signal obtained by cutting off the high frequency components; an oscillator that changes an oscillation frequency according to an output signal of the loop filter and outputs an oscillation signal; An analog signal is output to a loop filter or an oscillator according to a control parameter, and a parameter control circuit for obtaining a control parameter based on the frequency of the oscillation signal obtained by the digital signal processor. And a digital-to-analog converter that corrects the time change of the frequency.

Description

  The present invention relates to a PLL (Phase Locked Loop) circuit.

  When using a PLL to output a signal whose frequency changes sharply like a sawtooth wave, the PLL can not follow the setting waveform at the point where the frequency changes sharply, and it takes time to output the correct frequency again There is a problem of In order to solve this, PLL shown in the following nonpatent documents is proposed. The PLL connects a control terminal of a VCO (Voltage Controlled Oscillator) to a DAC (Digital to Analog Converter) via a switch, turns on the switch at a point where the frequency changes sharply, and turns on the DAC control terminal of the VCO. By applying the output of the PLL, the time until the PLL outputs the correct frequency again is shortened.

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  However, due to variations in circuit characteristics (VCO control voltage-frequency characteristics, DAC control code-output voltage characteristics, etc.), appropriate application parameters (application voltage, application time, etc.) are required for this method to operate correctly. There is a problem that it is difficult to obtain an appropriate applied parameter because the circuit characteristic changes dynamically depending on the individual and the circuit characteristics dynamically change due to temperature change and aging deterioration.

  The PLL circuit of the present invention compares a frequency divider that divides an oscillation signal whose frequency changes with time with a reference signal and an oscillation signal that is divided by the divider, and outputs a signal corresponding to the difference between the reference signal and the oscillation signal. The oscillation frequency is changed according to the frequency comparator, the loop filter that cuts off the high frequency component of the signal output from the phase frequency comparator, and outputs the signal from which the high frequency component is blocked, and the output signal of the loop filter. Analog signal to the loop filter or oscillator according to the control parameter, the parameter control circuit which determines the control parameter based on the frequency of the oscillator to output, the digital signal processor which determines the frequency of the oscillation signal, the digital signal processor And a digital-to-analog converter that corrects the time change of the oscillation frequency of the oscillator.

  According to the present invention, it is possible to dynamically obtain an appropriate applied parameter according to a change in circuit characteristics due to a temperature change or aging deterioration.

It is a block diagram which shows one structural example of the PLL circuit which concerns on Embodiment 1 of this invention. It is a conceptual diagram showing the relationship of the applied voltage of DAC12 and convergence time which concern on Embodiment 1 of this invention. It is a block diagram which shows one modification of the PLL circuit of Embodiment 1 of this invention. It is a block diagram which shows one structural example of the PLL circuit which concerns on Embodiment 2 of this invention. It is a block diagram which shows the modification of the PLL circuit which concerns on Embodiment 2 of this invention.

Embodiment 1
FIG. 1 is a block diagram showing an example of configuration of a PLL circuit according to Embodiment 1 of the present invention. The PLL circuit includes PFD (Phase Frequency Detector) 1, CP (Charge Pump) 2, LF (Loop Filter) 3, VCO 4, divider 5, ΔΣ modulator 6, chirp generation circuit 7, parameter control circuit 8, frequency. A conversion circuit 9, an ADC (analog to digital converter) 10, a DSP (digital signal processor) 11, a DAC 12, and a switch 13 are provided.

  The PFD 1 (an example of a phase frequency comparator) is a PFD that compares the phase of the reference signal with that of the output signal of the frequency divider 5 and outputs a signal corresponding to the phase difference to CP2. The reference signal is supplied from a signal source such as a crystal oscillator.

  CP2 is a charge pump circuit that converts the output signal of PFD1 into a current and outputs the converted current to LF3.

  The LF 3 (an example of a loop filter) is an LF that shuts off a high frequency component included in the current converted by the CP 2 and outputs the shut off signal to the VCO 4.

  The VCO 4 (an example of an oscillator) is a VCO that changes the oscillation frequency according to the signal output from the LF 3.

  The frequency divider 5 (an example of the frequency divider) divides the oscillation signal output from the VCO 4 in accordance with the division ratio setting signal output from the ΔΣ modulator 6, and divides the divided signal into the PFD 1 and the ΔΣ modulator 6. It is a divider to output.

  The ΔΣ modulator 6 (an example of the ΔΣ modulator) operates using the output signal of the frequency divider 5 as a clock, generates a division ratio setting signal according to the output signal of the chirp generation circuit 7, and generates the division ratio This is a ΔΣ modulator that outputs the setting signal to the frequency divider 5.

  The chirp generation circuit 7 outputs a chirp signal linearly changing with time corresponding to the division ratio of the present PLL circuit to the Δ 変 調 modulator 6, and at the same time, the timing at which the frequency of the present PLL circuit changes sharply. It is a circuit that outputs the signal shown to the parameter control circuit 8. For example, the chirp generation circuit 7 is a digital circuit, and an application specific integrated circuit (ASIC), a field-programmable gate array (FPGA), a microcomputer, or the like is used.

  The parameter control circuit 8 is a parameter control circuit 8 that generates control parameters for controlling the DAC 12 and the switch 13 and outputs the generated parameter to the DAC 12 and the switch 13. The parameter control circuit 8 outputs a signal for controlling ON / OFF of the switch 13 in synchronization with a signal output from the chirp generation circuit 7 and indicating a timing at which the frequency of the present PLL circuit changes sharply. The parameter control circuit 8 also outputs a control signal indicating the output voltage of the DAC 12 to the DAC 12. For example, the parameter control circuit 8 is a digital circuit, and an ASIC, an FPGA, a microcomputer or the like is used.

  The frequency conversion circuit 9 is a frequency conversion circuit that frequency-converts the output signal of the VCO 4 and outputs the frequency-converted signal to the ADC 10. The frequency conversion circuit 9 includes a divider 21 that divides the reference signal, a divider 22 that divides the output signal of the VCO, and a signal that is divided by the divider 21 and a signal that is divided by the divider 22. And a mixer 23 for mixing the The division ratio of the frequency divider 21 may be 1, and in this case, the frequency divider 21 may be deleted and the reference signal may be directly input to the mixer 23.

  The ADC 10 is an ADC that converts an analog signal frequency-converted by the frequency conversion circuit 9 into a digital signal and outputs the converted digital signal to the DSP 11.

  The DSP 11 (an example of a digital signal processor) obtains the instantaneous frequency of the output signal of the VCO 4 from the digital signal converted by the ADC 10, and an error between the desired frequency and the determined instantaneous frequency in the chirp signal (modulated wave) output by the VCO 4 The DSP is a DSP that calculates a convergence time at which the value is less than a predetermined value, and outputs the calculated convergence time to the parameter control circuit 8. As a method of obtaining an instantaneous frequency, for example, there is a method of performing quadrature demodulation on an input signal, obtaining an instantaneous phase, and calculating an instantaneous frequency from the instantaneous phase.

  At the point where the frequency of the modulation wave changes sharply, the PLL circuit can not follow the abrupt change of the frequency, and the error between the desired frequency and the actual frequency increases, but the desired frequency and the actual frequency gradually Will match. The desired frequency is the frequency corresponding to the chirp signal generated by the chirp generation circuit 7, that is, the frequency obtained by multiplying the frequency of the reference signal by the division ratio indicated by the chirp signal. Here, the time until the desired frequency and the actual frequency coincide with each other is referred to as convergence time. In other words, the convergence time refers to the time until the error between the desired frequency (the desired chirp signal) and the actual frequency (the actual chirp signal) falls within a predetermined value.

  The DAC 12 (an example of a digital-to-analog converter) is a DAC that generates an analog signal according to the control signal of the parameter control circuit 8 and outputs the generated analog signal to the switch 13.

  The switch 13 (an example of a switch) is a switch that switches between ON and OFF according to a control signal of the parameter control circuit 8 and controls whether or not the output signal of the DAC 12 is transmitted to the VCO 4.

  Next, the operation of the PLL circuit according to the first embodiment of the present invention will be described.

  First, the chirp generation circuit 7 generates a signal proportional to a desired modulation wave, and outputs the signal to the ΔΣ modulator 6. For example, if the desired modulation wave is a sawtooth wave, the chirp generation circuit 7 generates a sawtooth wave. Further, the chirp generation circuit 7 outputs, to the parameter control circuit 8, a pulse signal that rises at the timing when the output frequency of the present PLL circuit changes sharply. This pulse signal is called a frequency jump signal. The frequency jump signal is a 1-bit digital signal, and the rising timing means the timing at which the output frequency of the present PLL circuit changes sharply.

  The ΔΣ modulator 6 performs ΔΣ modulation on a signal proportional to the desired modulation wave generated by the chirp generation circuit 7, and outputs the signal to the frequency divider 5. Although the signal proportional to the desired modulation wave generated by the chirp generation circuit 7 includes decimals, the frequency divider 5 realizes decimal division ratio by integer conversion and Δ 整数 modulation with the ΔΣ modulator.

  The divider 5 divides the signal of the VCO 4 in accordance with the division ratio signal output from the ΔΣ modulator 6.

  The PFD 1 outputs a signal according to the phase difference between the reference signal and the output of the frequency divider 5 to CP2.

  CP2 outputs a current according to the output of PFD1 to LF3.

  The LF 3 shuts off the high frequency component of the signal output by the CP 2 and outputs a signal obtained by cutting off the high frequency component to the VCO 4.

  The VCO 4 outputs an oscillation signal according to the applied control voltage.

  The frequency conversion circuit 9 converts the frequency of the signal of the input VCO 4 and outputs the converted signal to the ADC 10.

  The ADC 10 samples the input at fixed intervals, converts it into a digital signal, and outputs the digital signal to the DSP 11.

  The DSP 11 quadrature demodulates the signal output from the ADC 10 to obtain an instantaneous phase, and calculates an instantaneous frequency from the instantaneous phase. The DSP 11 calculates the error between the desired frequency and the actual frequency in the modulated wave. At a point where the frequency of the modulation wave changes sharply, generally, the PLL circuit can not follow the abrupt change of the frequency, and the error between the desired frequency and the actual frequency becomes large. The DSP 11 compares the time change of the actual frequency of the detected PLL with the time change of the desired frequency, calculates the convergence time until the error between the two is less than a predetermined value, and the convergence time is controlled by the parameter control circuit 8 Output to Note that the DSP 11 stores parameters such as the inclination and length of the chirp signal necessary to obtain the desired frequency in an internal memory, and calculates the desired frequency with reference to these parameters. Used for calculation of error with frequency. Alternatively, the chirp signal itself may be stored.

  The parameter control circuit 8 obtains the output voltage of the DAC 12 from the convergence time output by the DSP 11, and outputs the obtained output voltage to the DAC 12. The parameter control circuit 8 turns on the switch 13 in synchronization with the frequency jump signal output from the chirp generation circuit 7 and turns off the switch 13 when the on time of the switch 13 obtained from the convergence time passes. Here, the ON time is a time during which the switch 13 is ON. The signal output from the parameter control circuit 8 to the switch 13 is a 1-bit digital signal, which is a signal indicating that the switch is ON when "1" and OFF when "0". Although described later, the parameter control circuit 8 may calculate the setting time of the DAC 12 and the ON time of the switch 13 from the convergence time, or a table showing the relationship between the convergence time and the setting time of the DAC 12 and the ON time of the switch 13 May be stored in the memory, and the setting time of the DAC 12 and the ON time of the switch 13 may be determined from the table.

  The DAC 12 sets the output voltage in accordance with the control signal output from the parameter control circuit 8, and outputs the set voltage to the switch 13.

  The switch 13 controls ON / OFF in accordance with the control signal output from the parameter control circuit 8 and outputs the output voltage of the DAC 12 to the VCO 4 while the switch 13 is ON. In the case of OFF, the output signal of the DAC 12 is shut off.

  The VCO 4 outputs an oscillation frequency according to a combined voltage of the output voltage of the LF 4 and the output voltage of the DAC 12 while the switch 13 is ON.

  After the switch 13 is turned off, the DSP 11 measures the convergence time until the error between the desired frequency and the actual frequency becomes less than or equal to the predetermined value, as in the operation described above, and converges on the parameter control circuit 8 Output time

  The parameter control circuit 8 changes two parameters of the output voltage of the DAC 12 and the ON time of the switch 13 according to the convergence time. The parameter control circuit 8 outputs the output voltage of the DAC 12 to the DAC 12 as needed. Then, the parameter control circuit 8 turns on the switch 13 in synchronization with the next frequency jump signal, and turns off the switch 13 when the on time of the switch 13 elapses. Thereafter, the convergence time is measured again by the DSP 11, and the parameter control circuit 8 changes two parameters of the output voltage of the DAC 12 and the ON time of the switch 13 according to the convergence time.

  By repeating this flow, the parameter control circuit 8 searches for a parameter whose convergence time is minimum.

FIG. 2 is a conceptual diagram showing the relationship between the applied voltage and the convergence time of the DAC 12 according to the first embodiment of the present invention.
As shown in FIG. 2, when the application amount from the DAC 12 is too large (see FIG. 2A) and when it is too small (see FIG. 2C), the application amount by the DAC 12 is appropriate (FIG. 2) The convergence time is longer than in (b). That is, by observing the convergence time and searching for a parameter that minimizes the convergence time, an appropriate applied parameter can be obtained. For example, the following two methods may be mentioned as a method of searching for a parameter that minimizes the convergence time.

  The first method sweeps two parameters of the output voltage of the DAC 12 and the ON time of the switch 13 over the entire range, stores the respective convergence times, and creates a table of convergence times corresponding to the values of the parameters. It is a method. Finally, the parameter control circuit 8 adopts the value of the parameter that minimizes the convergence time, and generates a modulated wave.

  The second method is gradient descent, which is a minimization algorithm. The parameter control circuit 8 calculates the gradient from the change of the convergence time with respect to each change of the parameter, and reaches the minimum value by changing the parameter so as to go down the gradient. The parameter control circuit 8 adopts the value of the parameter and generates a modulated wave.

  As described above, according to the first embodiment of the present invention, the convergence time is fed back to adjust the applied voltage and the application time, so that it is dynamically appropriate according to the change of the circuit characteristics due to the temperature change and the aged deterioration. The effect is obtained that the applied parameters can be determined. By performing feedback to minimize the convergence time, it is possible to minimize the ineffective time offset from the desired frequency and to increase the proportion of the effective time as a signal.

  In the PLL circuit of the first embodiment, the output of the VCO 4 may be input to the divider and the output of the divider may be input to the divider 5 and the divider 22.

FIG. 3 is a block diagram showing a modification of the PLL circuit of the embodiment 1 of the invention.
In the configuration of FIG. 3, since the operating frequencies of the frequency divider 5 and the frequency divider 22 decrease, the frequency division ratio also decreases. The frequency divider is characterized in that the power consumption is larger as it operates at a higher frequency. Therefore, by providing the frequency divider 31 (an example of the second frequency divider), the power consumption as a whole is reduced. Further, since the division ratio of the frequency divider 5 and the frequency divider 22 is reduced, the overall circuit size is reduced by providing the frequency divider 31.

  If a DAC capable of setting the output impedance to high impedance is used as the DAC 12, the same operation is performed by setting the output impedance of the DAC 12 to high impedance instead of turning off the switch 13, even without using the switch 13. be able to. In that case, the parameter control circuit 8 controls whether to make the output impedance of the DAC 12 high impedance instead of the switch 13.

  In addition, a configuration in which the voltage output from the DAC 12 is temporally changed is also conceivable. In this case, the parameter control circuit 8 controls the time waveform of the output voltage of the DAC 12. At this time, since the time waveform needs to be synchronized with the frequency jump signal output from the chirp generation circuit 7, the parameter control circuit 8 controls the output voltage of the DAC 12 in synchronization with the frequency jump signal.

Second Embodiment
FIG. 4 is a block diagram showing an example of configuration of a PLL circuit according to Embodiment 2 of the present invention.
In the configuration of the second embodiment, the DAC 12 and the switch 13 of the first embodiment are deleted, and the output terminal of CP41 (an example of a charge pump circuit) newly added is connected to the output terminal of CP2, and the parameter control circuit 8 It is configured to control the CP41. The difference from the first embodiment is that the first embodiment applies a voltage to the output terminal of the LF 3 using the DAC 12 and the switch 13, whereas the second embodiment applies the CP41 to the input terminal of the LF 3. It is to apply current.

  The CP 41 is a charge pump circuit that applies a current to the LF 3 in accordance with the control signal of the parameter control circuit 8.

Next, the operation of the PLL circuit according to the second embodiment of the present invention will be described.
The operations other than the parameter control circuit 8 and the CP 41 are the same as in the first embodiment, so the parameter control circuit 8 and the CP 41 will be mainly described.

  The parameter control circuit 8 obtains the set current of the CP 41 and the ON time of the CP 41 from the convergence time output by the DSP 11. The parameter control circuit 8 outputs a set current to the CP 41 as needed, and outputs a control signal to turn on the CP 41 in synchronization with the frequency jump signal output from the chirp generation circuit 7. Then, the parameter control circuit 8 outputs a signal to turn off the CP 41 when the on time of the CP 41 elapses. The control signal output from the parameter control circuit 8 is a 1-bit digital signal, which means "on" if it is "1", and "off" if it is "0". The parameter control circuit 8 searches for the output current of the CP 41 and the ON time to minimize the convergence time measured by the DSP 11 in the same manner as in the first embodiment, and uses the parameters obtained thereafter for operation. Do.

  The CP 41 applies a current to the LF 3 for a fixed time according to the control signal of the parameter control circuit 8. At a point where the frequency changes sharply, CP 41 injects an appropriate charge into LF 3 to shorten the time for outputting the correct frequency again.

  The LF 3 shuts off high frequency components of the output current of the CP 2 and the output current of the CP 41 in the ON time, and outputs the high frequency components to the VCO 4.

  The VCO 4 controls the oscillation frequency according to the output signal of the LF 3 and outputs an oscillation signal.

  As described above, according to the second embodiment of the present invention, the convergence time is fed back to adjust the applied current and application time of the CP 41. Therefore, dynamically according to the change of the circuit characteristics due to the temperature change and the aged deterioration. An effect is obtained that an appropriate applied parameter can be obtained. When an active filter is used as a loop filter, the output voltage of the loop filter can not be applied directly from the outside to make it into a desired value, and Embodiment 1 can not be used. Because it will inject charge into the input, it can also be used with an active filter.

  In the PLL circuit of the second embodiment, the frequency divider 31 is loaded on the feedback path of the VCO 4, the oscillation signal of the VCO 4 is output to the frequency divider 31, and the frequency divided signal of the frequency divider 31 is divided. It may be output to 5.

FIG. 5 is a block diagram showing a modification of the PLL circuit according to the second embodiment of the present invention.
By inserting the frequency divider 31 as shown in FIG. 5, the power consumption as a whole can be reduced and the circuit scale can be reduced for the same reason as described in the first embodiment.

  1 PFD, 2 CP, 3 LF, 4 VCO, 5 divider, 6 ΔΣ modulator, 7 chirp generation circuit, 8 parameter control circuit, 9 frequency conversion circuit, 10 ADC, 11 DSP, 12 DAC, 13 switches, 21 Divider, 22 divider, 23 mixer, 31 divider, 41 CP.

The PLL circuit of the present invention compares a reference signal and an output signal from the frequency divider with a first frequency divider that divides an oscillation signal whose frequency changes with time, and outputs the reference signal and the output signal from the frequency divider. A phase frequency comparator that outputs a signal according to the phase difference between the two, a loop filter that cuts off the high frequency component of the signal output by the phase frequency comparator and that cuts off the high frequency component, and an output signal of the loop filter Therefore, after changing the oscillation frequency, an oscillator that outputs the oscillation signal, a frequency conversion circuit that converts the frequency of the oscillation signal from the oscillator and outputs it, and the frequency of the oscillation signal from the oscillator changes rapidly, the convergence time to the actual frequency error between the frequency is equal to or less than the predetermined value is calculated based on the output from the frequency converting circuit, a digital signal processor for outputting a signal indicating a convergence time Frequency of the oscillation signal from the oscillator is synchronized with the signal indicating the timing of changes sharply, and on / off control signal for controlling the on / off according to the signal indicating the convergence time from the digital signal processor, a digital signal processor A parameter control circuit that outputs an output voltage control signal for controlling an output voltage according to a signal indicating a convergence time of the digital signal processor so as to minimize the convergence time, and an output voltage control signal from the parameter control circuit The digital-to-analog converter which outputs the output voltage is set according to the on / off control signal from the parameter control circuit, and the output voltage from the digital-to-analog converter is transmitted to the oscillator And a switch for controlling whether or not

Claims (7)

A frequency divider that divides an oscillation signal whose frequency changes with time;
A phase frequency comparator that compares a reference signal with the oscillation signal divided by the divider and outputs a signal according to the difference;
A loop filter for blocking a high frequency component of the signal output from the phase frequency comparator and outputting a signal obtained by blocking the high frequency component;
An oscillator that changes an oscillation frequency according to an output signal of the loop filter and outputs the oscillation signal;
A digital signal processor for determining the frequency of the oscillation signal;
A parameter control circuit for obtaining a control parameter based on the frequency of the oscillation signal obtained by the digital signal processor;
A digital-to-analog converter that outputs an analog signal to the loop filter or the oscillator according to the control parameter, and corrects a time change of the oscillation frequency of the oscillator;
PLL circuit equipped with The digital signal processor compares the temporal change of the oscillation frequency set in the oscillator via the division ratio of the divider with the temporal change of the frequency of the oscillation signal output by the oscillator and performs the oscillation. Determining a convergence time for the signal, and outputting the convergence time to the parameter control circuit;
The PLL circuit according to claim 1, wherein the parameter control circuit determines the control parameter from the convergence time. A switch provided between the loop filter or the oscillator and the digital-to-analog converter, for passing or blocking a voltage output from the digital-to-analog converter;
The parameter control circuit determines the ON time of the switch and the output voltage of the digital-to-analog converter from the convergence time, controls the switch based on the ON time, and uses the output voltage as the control parameter. The PLL circuit according to claim 2, which controls a digital-to-analog converter. A chirp generation circuit that generates a chirp signal indicating a change in frequency of the oscillation signal, and outputs a timing at which the frequency changes in the chirp signal to the parameter control circuit;
A ΔΣ modulator that ΔΔ modulates the chirp signal;
Equipped with
The divider divides the oscillation signal in accordance with the Δ 変 調 modulated chirp signal,
The PLL circuit according to claim 3, wherein the parameter control circuit turns on the switch according to the timing.   The PLL circuit according to claim 2, wherein a current is output to the loop filter using a charge pump circuit instead of the digital-to-analog converter.   The PLL circuit according to claim 5, wherein the parameter control circuit controls an applied current and an applied time of the charge pump circuit according to the convergence time.   A second frequency divider is provided between the oscillator and the frequency divider, which divides the oscillation signal output from the oscillator and outputs the oscillation signal divided as described above to the frequency divider. The PLL circuit according to claim 4 or 6, characterized in that:

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