JP6312197B2 - Clock generation circuit - Google Patents

Description

  The present invention relates to a clock generation circuit, and more particularly to a clock generation circuit including a PLL circuit having a spread spectrum function.

  The clock generation circuit typically includes a PLL circuit for generating a clock necessary for the operation of an electronic device including a logic circuit such as a microprocessor (MPU). Such a PLL circuit includes, for example, a phase detection circuit, a charge pump circuit, a loop filter, a voltage controlled oscillator (VCO), and a frequency divider, and includes a reference clock and a reference clock. Operates so as to maintain a locked state in which the frequency and phase of the signal are kept equal.

  In general, in a PLL circuit, for example, variations in various characteristics such as jitter characteristics and response characteristics occur due to variations in element characteristics due to manufacturing processes. For example, when variations occur in the amount of drive current of the charge pump circuit, there is a problem that jitter (phase noise) in the PLL circuit increases and response characteristics deteriorate. Various parasitic elements parasitic in the chip also contribute to deterioration of jitter characteristics and response characteristics.

  In addition, with the recent increase in clock frequency, the PLL circuit needs to have a wide range of loop bandwidth from the viewpoint of propagation of the high-frequency component of the reference clock itself and the high-frequency component caused by each circuit element in the circuit. There is. That is, this means that a high response characteristic is required for the PLL circuit. On the other hand, the wider the loop bandwidth range of the PLL circuit, that is, the higher the response characteristic required for the PLL circuit, the greater the jitter and the more unstable the operation of the PLL circuit. For this reason, in general, the loop bandwidth of the PLL circuit is ideally set to a value of about one-tenth of the frequency of the reference clock in consideration of the balance between response characteristics and jitter characteristics. Yes.

  Therefore, the PLL circuit eliminates the above-described variations in the element characteristics of the manufacturing process and the characteristics caused by the parasitic elements, and further, in order to cope with the higher frequency of the clock, the response characteristics and the jitter characteristics It is required to be designed so as to realize high response characteristics and suppression of jitter generation while considering the balance.

  As a method for realizing higher response characteristics of the PLL circuit and suppressing the occurrence of jitter, there is a method of controlling the amount of drive current of the charge pump circuit according to the phase difference between the reference clock and the reference clock.

  For example, Patent Document 1 below eliminates the occurrence of jitter in the PLL circuit and the increase in lock time according to the phase difference between the reference clock and the reference clock, and improves the problem that high-frequency component noise is superimposed on the control voltage signal. A PLL circuit having a function is disclosed. Specifically, the PLL circuit of Patent Document 1 includes a voltage-controlled oscillation circuit, a phase detection circuit, a charge pump circuit, a loop filter circuit, a pulse counter that counts the number of reference clock pulses, and a current of a charge pump. A charge pump drive capability switching circuit that controls the capability; a pulse waveform shaping circuit that shapes the waveform of the output signal of the phase detection circuit; and a waveform selection circuit that selects characteristics of the pulse waveform shaping circuit. The PLL circuit adjusts each characteristic of the PLL circuit by switching the current capability of the charge pump immediately after power-on, and by shaping the waveform of the output signal of the phase comparator in other cases. As a result, the PLL circuit realizes a function of eliminating the occurrence of jitter and an increase in lock time, and improving the problem of high-frequency component noise superimposed on the control voltage signal.

  Further, the higher frequency of the clock based on the demand for higher speed of the electronic device causes the problem of the increase of electromagnetic interference EMI (EMI: Electromagnetic Interference) in addition to the problem of the increase in jitter described above. The higher frequency of the clock further increases the influence of EMI on the LSI itself, its peripheral circuits, other electronic devices, etc., so the importance of SSCG (Spread Spectrum Clock Generator) technology that effectively reduces EMI The nature is increasing.

  The SSCG technology is a clock generation technology to which a spread spectrum function is added. As a clock generation technique having a spread spectrum function, an analog method using a PLL circuit and a digital method using a delay circuit are typically known. Specifically, the SSCG technology modulates the frequency of the clock so that the spectrum of electromagnetic interference (EMI: Electromagnetic Interference) radiated by an electronic device or the like is not concentrated in a specific frequency band. It is possible to disperse energy in a predetermined frequency band and suppress the peak value.

  When the clock generation circuit has a spread spectrum function, jitter is likely to occur. Therefore, it is necessary to suppress the occurrence of the jitter.

  For example, the following Patent Document 2 varies the frequency division ratio of the programmable frequency divider in accordance with the number of times of counting the reference clock, and based on the period of the frequency division ratio of the programmable frequency divider, the drive current of the charge pump circuit is changed. A clock generation circuit for controlling the amount is disclosed. Specifically, the clock generation circuit of Patent Document 2 includes a PLL circuit having a voltage-controlled oscillation circuit, a programmable frequency divider, a frequency divider, a phase comparator, and a charge pump circuit, a counter, A frequency division ratio changing means; and a means for controlling the amount of drive current of the charge pump circuit. The clock generation circuit has a spread spectrum function that periodically increases or decreases the frequency division ratio of the programmable frequency divider to generate a frequency-modulated clock. Thereby, the clock generation circuit realizes a function of suppressing the occurrence of jitter and reducing the residual peak noise.

Japanese Unexamined Patent Publication No. 2000-224035 JP 2012-165036 A

  Measures against EMI are extremely important in PLL circuits that require high response characteristics as the clock frequency increases. However, when the spread spectrum function is used for the PLL circuit in order to eliminate the EMI, the modulation is always performed on the reference clock, and therefore the skew of the reference clock with respect to the reference clock is in a state where the spread spectrum function is not used. Will increase. As a result, there is a problem that the response characteristic of the PLL circuit having the spread spectrum function is worse than that of the PLL circuit not using the function. In addition, in a PLL circuit having a spread spectrum function, it is difficult to adjust the timing between clock signals in the design of a logic circuit connected to the subsequent stage of the PLL circuit and the entire semiconductor integrated circuit including them. The number of circuit elements required for the semiconductor integrated circuit increases, and the circuit scale and design man-hour of the semiconductor integrated circuit increase.

  The conventional PLL circuit disclosed in Patent Document 1 described above achieves high responsiveness and suppression of jitter generation while eliminating variations in characteristics due to variations in element characteristics due to manufacturing processes. Although the amount of drive current of the charge pump circuit is controlled based on the phase difference between the reference clock and the reference clock, the spread spectrum function is not provided. Therefore, no consideration has been given to the skew of the reference clock, which increases due to the addition of the spread spectrum function.

  In addition, the clock generation circuit disclosed in Patent Document 2 described above has considered the influence on the jitter characteristic due to the fluctuation period of the frequency modulation of the reference clock by the spread spectrum function in suppressing the deterioration of the jitter characteristic. No consideration has been given to the influence of other factors (for example, temperature changes, variations in device characteristics due to manufacturing processes, fluctuations in output load, EMI, etc.).

  Therefore, the present invention provides a clock generation circuit capable of reducing an increase in skew of a reference clock with respect to a reference clock caused by spread spectrum frequency modulation while suppressing spread of jitter characteristics while performing a spread spectrum function. The purpose is to do.

  The present invention for solving the above problems includes the following technical features or invention specific matters.

  That is, the present invention according to a certain aspect is a clock generation circuit that generates and outputs an output clock based on a spread-spectrum frequency-modulated reference clock, and the level of the reference clock and the reference clock corresponding to the output clock. A phase comparator that detects a phase difference, a charge pump circuit that outputs a drive signal in which the amount of current is controlled based on the phase difference detected by the phase comparator and a predetermined current control signal, and the charge pump circuit The voltage control oscillation circuit that outputs the output clock having a frequency corresponding to the output drive signal, and the predetermined current control based on a temporal variation of a skew value between the reference clock and the reference clock A skew adjustment circuit that generates a signal and outputs the predetermined current control signal to the charge pump circuit. Tsu is a click generating circuit.

  Here, the skew adjustment circuit may measure a skew value between the reference clock and the reference clock according to a predetermined counter clock.

  The skew adjustment circuit may generate and output the predetermined current control signal based on an elapsed time from the maximum value to the minimum value of the skew value.

  Further, the skew adjustment circuit counts the number of times the skew value is measured from the maximum value to the minimum value, and determines the elapsed time based on the counted number. Also good.

  Furthermore, the skew adjustment circuit controls the current control signal to increase the amount of drive current of the charge pump circuit when the counted number is greater than a predetermined number, and the counted number is the predetermined number. When the number is less than the number of times, the current control signal may be controlled so as to reduce the amount of drive current of the charge pump circuit.

  The skew adjustment circuit may stop measuring the skew value when the modulation polarity of the spread spectrum frequency modulation is negative.

  The charge pump circuit controls a current amount of the drive signal by supplying current to a charge pump output line for outputting the drive signal from a power supply line based on the predetermined current control signal. May be.

  The charge pump circuit controls a current amount of the drive signal by drawing a current from a charge pump output line for outputting the drive signal to a ground line based on the predetermined current control signal. Also good.

According to another aspect of the present invention, there is provided a clock generation circuit for generating and outputting an output clock based on a spread spectrum frequency modulated reference clock, wherein the reference clock and a reference clock corresponding to the output clock are output. A phase comparator for detecting a phase difference; a charge pump circuit for outputting a drive signal in which a current amount is controlled based on the phase difference detected by the phase comparator and a predetermined current control signal; and the charge pump circuit When the modulation polarity of the spread spectrum frequency modulation is positive, the reference clock is output as a reference signal when the voltage control oscillation circuit outputs the output clock having a frequency corresponding to the drive signal output from the reference signal, and the reference outputs the clock as a reference signal, the when the modulation polarity is negative, the reference clock to the reference signal Output as the output to that input switching circuit said reference clock as the reference signal, based on the temporal variation of the skew value between the reference signal and the reference signal, the predetermined current control signal And a skew adjustment circuit that generates and outputs the predetermined current control signal to the charge pump circuit.

The input switching circuit selects the reference clock as the reference signal when the modulation polarity is positive, and selects the reference clock as the reference signal when the modulation polarity is negative; wherein said reference clock when the modulation polarity is positive is selected as the reference signal, the second selection circuit modulation polarity selects the reference clock for negative as the reference signal, may be provided.

  According to the present invention, a clock generation circuit including a PLL circuit having a spread spectrum function can reduce an increase in skew of a reference clock with respect to a reference clock while suppressing deterioration of jitter characteristics.

  Other technical features, objects, effects, and advantages of the present invention will become apparent from the following embodiments described with reference to the accompanying drawings.

It is a figure which shows an example of a structure of the clock generation circuit which concerns on one Embodiment of this invention. FIG. 2 is a diagram showing a schematic circuit diagram of a configuration of a PLL circuit and a skew adjustment circuit shown in FIG. 1. FIG. 3 is a schematic circuit diagram showing a configuration of a charge pump circuit shown in FIG. 2. It is the figure which showed the relationship between various characteristics and elapsed time in the clock generation circuit which concerns on embodiment of this invention by numerical calculation simulation. It is a figure which shows the other example of schematic circuit structure of the skew adjustment circuit in the clock generation circuit which concerns on embodiment of this invention.

  Next, embodiments of the present invention will be described with reference to the drawings.

  FIG. 1 is a diagram illustrating an example of a configuration of a clock generation circuit according to an embodiment of the present invention. As shown in the figure, the clock generation circuit 1 includes, for example, an SSCG circuit 10, a PLL circuit 20, and a skew adjustment circuit 30.

  The SSCG circuit 10 performs spread spectrum frequency modulation on the input clock ICLK based on a predetermined modulation profile, and outputs the modulated signal to the PLL circuit 20 and the skew adjustment circuit 30 as the reference clock RCLK. Further, the SSCG circuit 10 outputs the frequency modulation polarity with respect to the input clock ICLK to the skew adjustment circuit 30 as the modulation polarity signal MCNT. Specifically, when the polarity of the frequency modulation is “positive”, the SSCG circuit 10 changes the potential of the modulation polarity signal MCNT to the potential of the power supply line VDD, that is, “H”. Further, when the polarity of the frequency modulation is not “positive”, the SSCG circuit 10 changes the potential of the modulation polarity signal MCNT to the potential of the ground line GND, that is, “L”. The modulation profile is a characteristic representing the amount of change in frequency with respect to elapsed time in frequency modulation of the input clock in the SSCG circuit 10. The modulation profile is determined by, for example, parameters of circuit elements constituting the SSCG circuit 10 and the circuit configuration of the circuit. The SSCG circuit 10 may be configured by either an analog method using a PLL circuit or a digital method using a delay circuit.

  The PLL circuit 20 receives the reference clock RCLK from the SSCG circuit 10, adjusts the drive current of the charge pump circuit 22 described later based on the current control signal ICNT input from the skew adjustment circuit 30, and uses the clock at a desired frequency. And the modulated clock is output as the output clock OCLK. Further, the PLL circuit 20 divides the output clock OCLK to generate a reference clock FCLK, and feeds back the clock to the phase comparator 21 (see FIG. 2) to output the reference clock RCLK with respect to the phase. The phase of the clock OCLK is synchronized and the reference clock FCLK is output to the skew adjustment circuit 30.

  The skew adjustment circuit 30 receives the reference clock RCLK from the SSCG circuit 10 and the reference clock FCLK from the PLL circuit 20, and based on the phase difference between the reference clock RCLK and the reference clock FCLK, the PLL circuit 20 is described later. The amount of drive current in the internal charge pump circuit 22 is determined, and the amount of drive current is output to the PLL circuit 20 as a current control signal ICNT. The skew adjustment circuit 30 receives the clock modulation polarity signal MCNT from the SSCG circuit 10 and performs the above-described operation when the potential of the signal is “H”, that is, the modulation polarity of the SSCG circuit 10 is “positive”. When the potential of the signal is “L”, that is, when the modulation polarity is not “positive”, the above-described operation is stopped.

  FIG. 2 is a diagram showing a schematic circuit diagram of the configuration of the PLL circuit and the skew adjustment circuit shown in FIG. As shown in the figure, the PLL circuit 20 includes, for example, a phase comparator 21, a charge pump circuit 22, a low-pass filter 23, a voltage controlled oscillation circuit 24, and a frequency divider 25.

  The phase comparator 21 receives the reference clock RCLK from the SSCG circuit 10 and the reference clock FCLK from the frequency divider 25, compares the phases of the clocks, and compares the phase difference between the clocks according to the comparison result. A pair of phase error signals UP and DN are output to the charge pump circuit 22.

  The charge pump circuit 22 converts the phase error signals UP and DN output from the phase comparator 21 into a signal current based on the current control signal ICNT output from the skew adjustment circuit 30, and converts the signal current into a drive signal. As ICP, it outputs to the low pass filter 23. In the charge pump circuit 22, increase or decrease in the potential of the charge pump output line W_ICP is determined by the phase error signals UP and DN, and the current flowing through the output line is determined by the current control signal ICNT. Further, the charge pump circuit 22 holds the gates of transistors TR3 and TR4, which will be described later, at a predetermined potential based on the bias power supplies VB1 and VB2.

  The low-pass filter 23 receives the drive signal ICP output from the charge pump circuit 22, smoothes the signal and converts it to a signal potential, and the voltage control oscillation is performed by using the converted signal as the potential control signal VCNT. Output to the circuit 24.

  The voltage-controlled oscillation circuit 24 receives the potential control signal VCNT output from the low-pass filter 23, oscillates at a frequency corresponding to the potential of the signal, generates an output clock OCLK, and sends the signal to the frequency divider 25. And outputs the signal as an output signal of the clock generation circuit 1 to the outside.

  The frequency divider 25 receives the output clock OCLK output from the voltage controlled oscillation circuit 24, generates a reference clock FCLK by performing frequency division by a predetermined frequency, and outputs the clock to the phase comparator 21. .

  As shown in the figure, the skew adjustment circuit 30 includes, for example, a ring oscillator 31, a ring clock counter 32, a comparator 33, a cycle counter 34, and a charge pump current control circuit 35. .

  The ring oscillator 31 is an oscillation circuit configured by connecting, for example, an odd number of delay elements (inverters) (not shown) in a ring shape. The ring oscillator 31 oscillates at a predetermined frequency and outputs a counter clock RGCLK to the ring clock counter 32.

  The ring clock counter 32 receives the reference clock RCLK output from the SSCG circuit 10 at the measurement start terminal STA, receives the reference clock FCLK output from the PLL circuit 20 at the measurement end terminal END, and receives the reference clock FCLK for the reference clock RCLK. Is delayed by the counter clock RGCLK output from the ring oscillator 31. The ring clock counter 32 outputs the skew obtained by the count as a skew count signal SCNT to the comparator 33 from the output terminal OUT. The ring clock counter 32 receives the modulation polarity signal MCNT from the SSCG circuit 10 at the enable terminal EN and performs the above-described operation only when the potential of the signal is “H”, and the potential of the signal is “L”. In some cases, the operation of the circuit is stopped.

  The comparator 33 is composed of, for example, a plurality of registers and a comparison circuit (not shown). The comparator 33 receives the skew count signal SCNT from the ring clock counter 32, and controls the count clock PLS and the reset signal RES according to the time variation of the skew value of the reference clock FCLK with respect to the reference clock RCLK held by the signal, Those signals are output to the cycle counter 34.

  Specifically, the comparator 33 receives the skew count signal SCNT from the ring clock counter 32, and stores the skew value of the reference clock FCLK with respect to the reference clock RCLK indicated by the signal in an internal register. The comparator 33 compares the (M−2) to M-th values of the count number stored in the internal register, and the (M−1) -th value of the count number is the (M−2) of the count number. ) And the Mth value, that is, when it is determined that the count value is a maximum value, the output of the count clock PLS is started and the potential of the reset signal RES is changed to “L”. The comparator 33 also determines that the (M−1) th value of the count number is smaller than the (M−2) th and Mth values of the count number, that is, the count value is a minimum value. When it is determined that there is, the output of the count clock PLS is stopped, the potential of the reset signal RES is changed to “H”, and the internal register and the number of comparisons are reset. The count clock PLS alternates every time the skew signal SCNT is input from the ring clock counter 32 to the comparator 33 while the clock is output to the cycle counter 34. Further, immediately after power-on, the comparator 33 resets the internal register and the number of comparisons, and changes the potential of the reset signal RES to “H”.

  Based on the reset signal RES input from the comparator 33, the cycle counter 34 counts the number of rising or falling edges of the count clock PLS input from the circuit, and uses the count as the loop bandwidth count signal BCNT. , Output to the charge pump current control circuit 35. Specifically, the cycle counter 34 counts the number of rising or falling edges of the count clock PLS while the potential of the reset signal RES is “L”. Next, when the potential of the reset signal RES becomes “H”, the cycle counter 34 outputs the count number as the loop bandwidth count signal BCNT to the charge pump current control circuit 35 to reset the count number. Subsequently, the cycle counter 34 stops its operation while the potential of the reset signal RES is “H”, and performs the same operation as described above when the potential of the signal becomes “L” again.

  The charge pump current control circuit 35 receives the loop bandwidth count signal BCNT from the cycle counter 34, determines the amount of drive current of the charge pump circuit 22 according to the count number of the count clock PLS held by the signal, The amount of drive current is output to the PLL circuit 20 as a current control signal ICNT.

  Specifically, the charge pump current control circuit 35 determines whether the count frequency of the count clock PLS held by the loop bandwidth count signal BCNT is greater than, less than or equal to a predetermined number (for example, 5 times). When the charge pump current control circuit 35 determines that the count number is greater than the predetermined number, the charge pump current control circuit 35 considers that the loop bandwidth range of the PLL circuit 20 is wide, that is, the response characteristic is lower than appropriate, and the drive current of the charge pump circuit 22 The current control signal ICNT is controlled so as to increase. On the other hand, when the charge pump current control circuit 35 determines that the count number is smaller than the predetermined number of times, the charge pump current control circuit 35 regards that the loop bandwidth range of the PLL circuit 20 is narrow, that is, the response characteristic is higher than appropriate, and The current control signal ICNT is controlled so as to reduce the drive current. Further, when the charge pump current control circuit 35 determines that the count number is the same as the predetermined number, the range of the loop bandwidth of the PLL circuit 20 is considered to be appropriate, that is, the response characteristic is appropriate, and the charge pump The current control signal ICNT is controlled so as to maintain the drive current of the circuit 22.

  FIG. 3 is a schematic circuit diagram of the charge pump circuit shown in FIG. As shown in the figure, the charge pump circuit 22 includes, for example, a transistor TR1, a transistor TR2, N transistors TR3, N transistors TR4, N power switches SWP, and N power switches SWN. It is comprised including.

  The transistor TR1 includes, for example, a P-type MOSFET. That is, the drain of the transistor TR1 is connected to the node (p), the source is connected to the source of the transistor TR2 and the charge pump output line W_ICP, and the gate is connected to the phase error input terminal W_UP. Thus, the transistor TR1 switches on / off of current supply from the power supply line VDD to the charge pump output line W_ICP based on the phase error signal UP input from the phase comparator 21.

  The transistor TR2 includes, for example, an N-type MOSFET. That is, the drain of the transistor TR2 is connected to the node (q), the source is connected to the source of the transistor TR1 and the charge pump output line W_ICP, and the gate is connected to the phase error input terminal W_DN. Thereby, the transistor TR2 switches on / off of current extraction from the charge pump output line W_ICP to the ground line GND based on the phase error signal DN input from the phase comparator 21.

  Each of the plurality of transistors TR3 includes a P-type MOSFET, for example. That is, the drain of the transistor TR3 is connected to the power supply line VDD, the source of the transistor TR3 (0) is connected to the node (p), the sources of the transistors TR3 (1) to (n) are connected to the power switch SWP, and the gate Is connected to the bias power supply VB1. Thus, the transistor TR3 supplies a predetermined current based on the bias power supply VB1 from the power supply line VDD to the charge pump output line W_ICP through the transistor TR1.

  Each of the plurality of transistors TR4 includes, for example, an N-type MOSFET. That is, the drain of the transistor TR4 is connected to the ground line GND, the source of the transistor TR4 (0) is connected to the node (q), the sources of the transistors TR4 (1) to (n) are connected to the power switch SWN, and the gate Is connected to the bias power supply VB2. Thus, the transistor TR4 draws a predetermined current based on the bias power supply VB2 from the charge pump output line W_ICP to the ground line GND via the transistor TR2.

  Each of the plurality of power switches SWP includes, for example, an N-type MOSFET. That is, the power switches SWP (1) to (n) are provided between the transistors TR3 (1) to (n) and the node (p), respectively, and current control signal lines W_ICPCNT (1) are respectively connected to the control terminals of the switches. ) To (n) are connected. As a result, the power switch SWP adjusts the amount of current supplied to the output line when the current is supplied from the power line VDD to the charge pump output line W_ICP based on the current control signal ICNT input from the skew adjustment circuit 30. To do.

  Each of the plurality of power switches SWN includes, for example, an N-type MOSFET. That is, the power switches SWN (1) to (n) are provided between the transistors TR4 (1) to (n) and the node (q), respectively, and current control signal lines W_ICPCNT (1) are respectively connected to the control terminals of the switches. ) To (n) are connected. As a result, the power switch SWN adjusts the amount of current drawn from the output line when the current is drawn from the charge pump output line W_ICP to the ground line GND based on the current control signal ICNT input from the skew adjustment circuit 30. To do.

  In this example, the transistors TR1 and TR3 are configured by P-type MOSFETs, but are not limited thereto, and may be N-type MOSFETs, bipolar transistors, or the like. The transistors TR2 and TR4 and the power switches SWP and SWN are N-type MOSFETs, but are not limited thereto, and may be P-type MOSFETs or bipolar transistors. Also good.

  As described above, it is generally ideal that the loop bandwidth of the PLL circuit is a value of about one tenth of the frequency of the reference clock. Therefore, the loop bandwidth of the clock generation circuit 1 according to the present invention is also adjusted to be a value of about 1/10 of the frequency of the reference clock RCLK. That is, the clock generation circuit 1 acquires the loop bandwidth from the temporal variation of the skew of the reference clock FCLK with respect to the reference clock RCLK, compares the acquired loop bandwidth with the frequency of the reference clock RCLK, and based on the comparison result. Thus, the loop bandwidth is adjusted by adjusting the amount of drive current of the charge pump circuit 22.

  FIG. 4 is a diagram showing the relationship between various characteristics and elapsed time in the clock generation circuit according to the embodiment of the present invention by numerical calculation simulation. In the figure, the horizontal axis indicates the elapsed time, and the vertical axis indicates the variation in the frequency of the reference clock RCLK, the logic of the modulation polarity signal MCNT, and the skew of the reference clock FCLK with respect to the reference clock RCLK.

  The upper part of the figure shows the relationship between the amount of change in the frequency of the reference clock RCLK and the elapsed time, that is, the characteristics of the modulation profile in the SSCG circuit 10. As shown in the upper part of the figure, the modulation profile in the SSCG circuit 10 is, for example, a triangular wave. That is, the SSCG circuit 10 repeatedly performs frequency increase modulation and frequency decrease modulation on the input signal ICLK at a predetermined time interval, and outputs the signal to the PLL circuit 20 and the skew adjustment circuit 30 as the reference clock RCLK. Further, the SSCG circuit 10 changes the logic of the modulation polarity signal MCNT based on the predetermined time interval described above. That is, the SSCG circuit 10 changes the logic of the modulation polarity signal MCNT to “H” during the period from the point (a) to the point (e) where the frequency increase modulation is performed on the reference clock RCLK, and the reference clock RCLK is changed to the reference clock RCLK. On the other hand, the logic of the modulation polarity signal MCNT is changed to “L” in the section from the point (e) to the point (f) where the frequency drop modulation is performed.

  As shown in the lower part of the figure, the skew of the reference clock FCLK with respect to the reference clock RCLK varies based on the modulation profile in the SSCG circuit 10. That is, the skew becomes a “positive” value in a section where the frequency increase modulation is performed with respect to the reference clock RCLK (for example, a section from the point (a) to the point (e)), and the skew is a frequency with respect to the reference clock RCLK. The value is “negative” in the section where the downward modulation is performed (for example, the section from the point (e) to the point (f)). The skew value is repeatedly increased and decreased until the loop bandwidth in the clock generation circuit 1 and the frequency of the reference clock RCLK have a predetermined relationship. Since the loop bandwidth in the clock generation circuit 1 is the tracking speed of the reference clock FCLK with respect to the reference clock RCLK, the loop bandwidth can be obtained from the temporal variation of the skew value. Here, the elapsed time in the section from the maximum value of one skew to the next maximum value (for example, point (b) to point (d)) is equal to the period of the loop bandwidth. In addition, the elapsed time in the section from the maximum value to the next minimum value (for example, the point (b) to the point (c)) is half of the period of the loop bandwidth. equal.

  The clock generation circuit 1 measures the elapsed time in a section (for example, the point (b) to the point (c)) until the skew value reaches the next minimum value from one maximum value, and the elapsed time is calculated. By comparing with the period of the reference clock RCLK, it is determined how much the loop bandwidth is deviated from the ideal value described above. Specifically, the clock generation circuit 1 measures the elapsed time in the interval by counting with the reference clock RCLK. The number of counts is approximately equal to a value obtained by dividing the period of the loop bandwidth by 2 and dividing it by the period of the reference clock RCLK. Since the ideal value of the period of the loop bandwidth in the circuit is 10 times the period of the reference clock RCLK, in order for the clock generation circuit 1 to obtain the ideal characteristics described above, the number of counts is, for example, five. It is required to be. Therefore, the clock generation circuit 1 determines whether the count number is larger, smaller, or the same as a predetermined number (for example, five times), and the drive current of the charge pump circuit 22 is determined according to the comparison result. Adjust the amount. In the present example, the comparison target of the number of counts is, for example, five. However, the present invention is not limited to this, and another value may be used to cope with various factors.

  The clock generation circuit 1 repeatedly performs the above-described operation and adjusts the loop bandwidth of the circuit to the above-described ideal value, thereby obtaining a response characteristic that takes into account the balance with the jitter characteristic. That is, the clock generation circuit 1 obtains sufficiently high response characteristics while suppressing deterioration of jitter characteristics. Here, since the skew of the reference clock FCLK with respect to the reference clock RCLK in the clock generation circuit 1 increases or decreases according to the response characteristic of the circuit, when the clock generation circuit 1 obtains a high response characteristic, the skew of the circuit is Decrease. Therefore, the clock generation circuit 1 according to the present invention increases the skew of the reference clock FCLK relative to the reference clock RCLK due to the frequency modulation of the reference clock RCLK by the spread spectrum function, and reduces the loop bandwidth from the peak section of the skew fluctuation. By acquiring and adjusting the loop bandwidth, it is possible to reduce the jitter characteristics while suppressing deterioration.

  FIG. 5 is a diagram showing another example of the schematic circuit configuration of the skew adjustment circuit in the clock generation circuit according to the embodiment of the present invention. That is, the skew adjustment circuit 30 ′ according to the present embodiment includes a ring clock counter 32 ′ instead of the ring clock counter 32 in the skew adjustment circuit 30 described above. Also, the skew adjustment circuit 30 ′ according to the present embodiment has a configuration in which an input switching circuit 36 is added to the configuration of the skew adjustment circuit 30 described above.

  The input switching circuit 36 includes, for example, selection circuits MUX1 and MUX2. The input switching circuit 36 uses one of the reference clock RCLK input from the SSCG circuit 10 and the reference clock FCLK input from the PLL circuit 20 based on the modulation polarity signal MCNT input from the SSCG circuit 10. As the signal REF, either one is used as a reference signal FEB, and both of these signals are output to a ring clock counter 32 ′ described later.

  The selection circuit MUX1 includes a multiplexer, for example. The selection circuit MUX1 receives the reference clock RCLK at the input terminal A1, receives the reference clock FCLK at the input terminal A2, and determines which of the reference clock RCLK and the reference clock FCLK based on the modulation polarity signal MCNT input to the selection terminal SEL. Is selected as the reference signal REF, and this signal is output from the output terminal Y to the ring clock counter 32 ′ described later. Specifically, the selection circuit MUX1 selects the reference clock RCLK when the potential of the modulation polarity signal MCNT is “H”, and selects the reference clock FCLK when the potential of the modulation polarity signal MCNT is “L”. The signal is output to the ring clock counter 32 ′.

  The selection circuit MUX2 is also configured to include a multiplexer, for example. The selection circuit MUX2 receives the reference clock FCLK at the input terminal A1, receives the reference clock RCLK at the input terminal A2, and determines which of the reference clock FCLK and the reference clock RCLK based on the modulation polarity signal MCNT input to the selection terminal SEL. Is selected as the reference signal FEB, and the signal is output from the output terminal Y to a ring clock counter 32 ′ described later. Specifically, the selection circuit MUX2 selects the reference clock FCLK when the potential of the modulation polarity signal MCNT is “H”, and selects the reference clock RCLK when the potential of the modulation polarity signal MCNT is “L”. The signal is output to the ring clock counter 32 ′.

  Unlike the ring clock counter 32 described above, the value of the enable terminal EN is always fixed to “H” in the ring clock counter 32 ′. Specifically, the ring clock counter 32 ′ receives the reference signal REF output from the input switching circuit 36 at the measurement start terminal STA and the reference signal FEB at the measurement end terminal END, and delays the reference signal FEB with respect to the reference signal REF. The time, that is, the skew is counted by the counter clock RGCLK output from the ring oscillator 31. The ring clock counter 32 ′ outputs the signal from the output terminal OUT to the comparator 33 using the skew obtained by the counting as the skew count signal SCNT. The ring clock counter 32 ′ performs the above-described operation regardless of the modulation polarity of the SSCG circuit 10.

  According to the present embodiment, not only the delay time of the reference clock FCLK with respect to the reference clock RCLK but also the delay time of the reference clock RCLK with respect to the reference clock FCLK can be measured. That is, according to the present embodiment, even when the modulation polarity controlled by the SSCG circuit 10 is “negative”, the increase in the skew of the reference clock FCLK relative to the reference clock RCLK due to the above-described spread spectrum function is represented by jitter characteristics. It becomes possible to reduce it while suppressing the deterioration.

  Each of the above embodiments is an example for explaining the present invention, and is not intended to limit the present invention only to these embodiments. The present invention can be implemented in various forms without departing from the gist thereof.

  For example, in the method disclosed herein, steps, operations, or functions may be performed in parallel or in a different order, as long as the results do not conflict. The steps, operations, and functions described are provided as examples only, and some of the steps, operations, and functions may be omitted and combined with each other without departing from the spirit of the invention. There may be one, and other steps, operations or functions may be added.

  Further, although various embodiments are disclosed in this specification, specific features (technical matters) in one embodiment are added to other embodiments while appropriately improving the other features, or other Specific features in the embodiments can be replaced, and such forms are also included in the gist of the present invention.

  The present invention can be widely used in the field of semiconductor integrated circuits including amplifiers using MOSFETs.

DESCRIPTION OF SYMBOLS 1 ... Clock generation circuit 10 ... SSCG circuit 20 ... PLL circuit 21 ... Phase comparator 22 ... Charge pump circuit 23 ... Low pass filter 24 ... Voltage control oscillation circuit 25 ... Divider 30 ... Skew adjustment circuit 31 ... Ring oscillator 32 ... Ring Clock counter 33 ... Comparator 34 ... Cycle counter 35 ... Charge pump current control circuit 36 ... Input switching circuit

Claims (10)

A clock generation circuit that generates and outputs an output clock based on a spread spectrum frequency modulated reference clock,
A phase comparator for detecting a phase difference between the reference clock and a reference clock corresponding to the output clock;
A charge pump circuit that outputs a drive signal in which the amount of current is controlled based on the phase difference detected by the phase comparator and a predetermined current control signal;
A voltage controlled oscillation circuit that outputs the output clock having a frequency according to the drive signal output from the charge pump circuit;
A skew adjustment circuit that generates the predetermined current control signal based on a temporal variation of a skew value between the reference clock and the reference clock and outputs the predetermined current control signal to the charge pump circuit. When,
A clock generation circuit comprising:   The clock generation circuit according to claim 1, wherein the skew adjustment circuit measures a skew value between the reference clock and the reference clock according to a predetermined counter clock.   The clock generation circuit according to claim 1, wherein the skew adjustment circuit generates and outputs the predetermined current control signal based on an elapsed time from the maximum value to the minimum value of the skew value.   The skew adjustment circuit counts the number of times the skew value is measured before the skew value reaches the minimum value from the maximum value, and determines the elapsed time based on the counted number. 3. The clock generation circuit according to 3. The skew adjustment circuit includes:
If the counted number is greater than a predetermined number, the current control signal is controlled to increase the amount of drive current of the charge pump circuit;
5. The clock generation circuit according to claim 4, wherein when the counted number is less than the predetermined number, the current control signal is controlled so as to reduce an amount of drive current of the charge pump circuit.   The clock generation circuit according to claim 1, wherein the skew adjustment circuit stops measuring the skew value when a modulation polarity of the spread spectrum frequency modulation is negative.   The charge pump circuit controls a current amount of the drive signal by supplying a current to a charge pump output line for outputting the drive signal from a power supply line based on the predetermined current control signal. Item 2. The clock generation circuit according to Item 1. The charge pump circuit controls a current amount of the drive signal by drawing a current from a charge pump output line for outputting the drive signal to a ground line based on the predetermined current control signal.
The clock generation circuit according to claim 1. A clock generation circuit that generates and outputs an output clock based on a spread spectrum frequency modulated reference clock,
A phase comparator for detecting a phase difference between the reference clock and a reference clock corresponding to the output clock;
A charge pump circuit that outputs a drive signal in which the amount of current is controlled based on the phase difference detected by the phase comparator and a predetermined current control signal;
A voltage controlled oscillation circuit that outputs the output clock having a frequency according to the drive signal output from the charge pump circuit;
When the modulation polarity of the spread spectrum frequency modulation is positive, and outputs the reference clock as a reference signal, and outputs the reference clock as a reference signal, the when the modulation polarity is negative, the reference clock as the reference signal output, an input switching circuit you outputs said reference clock as the reference signal,
A skew adjustment circuit that generates the predetermined current control signal based on a temporal variation of a skew value between the reference signal and the reference signal, and outputs the predetermined current control signal to the charge pump circuit. When,
A clock generation circuit comprising: The input switching circuit is
A first selection circuit that selects the reference clock as the reference signal when the modulation polarity is positive, and selects the reference clock as the reference signal when the modulation polarity is negative;
The modulation polarity selecting the reference clock for positive as the reference signal, and a second selection circuit for selecting as said reference signal to said reference clock when the modulation polarity is negative,
The clock generation circuit according to claim 9.