JP2017199999A - PLL circuit and clock generation circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To facilitate suppression of jitter caused by an influence of disturbance while ensuring a modulation width of an output signal in a PLL circuit that receives an input of a frequency-modulated reference clock signal.SOLUTION: The present PLL circuit is a PLL circuit that generates an output clock signal on the basis of a modulated reference clock signal, and comprises: a loop band control circuit that receives an input of data or a signal indicating a modulated frequency of the reference clock signal and outputs a loop band setting signal setting a loop band of the PLL circuit corresponding to the modulated frequency; and a loop band changing circuit that changes the loop band of the PLL circuit according to the loop band setting signal output from the loop band control circuit.SELECTED DRAWING: Figure 1

Description

  The present invention relates to a PLL circuit and a clock generation circuit.

  In recent years, SSCG (Spread Spectrum Clock Generator) has been used as one of the solutions for suppressing EMI (Electro Magnetic Interference) noise radiated from electronic devices. The SSCG distributes the frequency at which EMI noise is generated by applying frequency modulation to a clock to reduce EMI, and can be used as a reference clock for a PLL circuit, for example.

  For example, an SSCG that has a frequency modulation function that switches the set value of the frequency of the output clock every predetermined period and switches the modulation control set value when the frequency modulation function is turned off, thereby reducing the lock-up time. It is known (see, for example, Patent Document 1). In addition, the charge pump has a voltage controlled oscillator that oscillates at a frequency corresponding to the control voltage based on the set modulation sensitivity, and is based on the combination of the set modulation sensitivity value and the multiplication factor of the frequency divider. A PLL circuit that changes the value of the control current is known (for example, see Patent Document 2).

  In a PLL circuit, if the loop band is wide, jitter due to the influence of disturbances or the like increases, so there is a demand for making the loop band as narrow as possible. However, in a PLL circuit to which a frequency-modulated reference clock signal is input, if the loop band is narrowed, it cannot follow the frequency-modulated reference clock, and the modulation width of the output signal of the PLL circuit is reduced, thereby reducing the EMI. May not be sufficient.

  As described above, in the conventional technique, it is difficult to suppress the jitter due to the influence of the disturbance while securing the modulation width of the output signal in the PLL circuit to which the frequency-modulated reference clock signal is input. It was.

  The embodiments of the present invention have been made in view of the above problems, and in a PLL circuit to which a frequency-modulated reference clock signal is input, the influence of disturbance is secured while ensuring the modulation width of the output signal. An object of the present invention is to make it easy to suppress jitter due to the above.

  In order to solve the above-described problem, a PLL circuit according to an embodiment of the present invention is a PLL circuit that generates an output clock signal based on a modulated reference clock signal, and data indicating a modulation frequency of the reference clock signal. Or a loop band control circuit that outputs a loop band setting signal that sets a loop band of the PLL circuit corresponding to the modulation frequency, and a loop band setting signal that is output from the loop band control circuit. A loop band changing circuit for changing a loop band of the PLL circuit.

  According to an embodiment of the present invention, in a PLL circuit to which a frequency-modulated reference clock signal is input, it is possible to easily suppress jitter due to the influence of a disturbance while ensuring a modulation width of an output signal. Can do.

1 is a block diagram of a PLL circuit according to a first embodiment. It is a figure which shows the example of the phase difference detection circuit which concerns on 1st Embodiment. It is a figure which shows the example of the timing chart of the phase difference detection circuit which concerns on 1st Embodiment. It is a figure which shows the example of the output timing of signal PDET which concerns on 1st Embodiment. It is a figure which shows the example of the modulation frequency detection circuit which concerns on 1st Embodiment. It is a figure which shows the example of the loop band control circuit which concerns on 1st Embodiment. It is a figure which shows the example of the charge pump which concerns on 1st Embodiment. It is a figure for demonstrating a loop zone | band. It is a block diagram of a PLL circuit according to a second embodiment. It is a figure which shows the example of the loop band control circuit which concerns on 2nd Embodiment. It is a figure which shows the example of the loop filter which concerns on 2nd Embodiment. It is a block diagram of a PLL circuit according to a third embodiment. It is a figure which shows the example of the loop band control circuit which concerns on 3rd Embodiment. FIG. 10 is a block diagram of a clock generation circuit according to a fourth embodiment.

  Embodiments of the present invention will be described below with reference to the accompanying drawings.

<System configuration>
[First Embodiment]
<Configuration of PLL circuit>
(Overall configuration)
FIG. 1 is a block diagram of a PLL circuit according to the first embodiment. A PLL (Phase Locked Loop) circuit 100 receives a modulated reference clock signal R and outputs an output clock signal synchronized with the inputted reference clock signal R. The modulated reference clock signal R is generated and input by, for example, an SSCG (Spread Spectrum Clock Generator).

  The PLL circuit 100 according to the present embodiment includes a phase comparator 110, a charge pump 120, a loop filter 130, a VCO (Voltage Controlled Oscillator) 140, a frequency dividing circuit 150, and the like, as in a general PLL circuit.

  The PLL circuit 100 according to the present embodiment includes a phase difference detection circuit 160, a modulation frequency detection circuit 170, a loop band control circuit 180, and the like in addition to the above-described components.

  The phase comparator 110 detects a phase difference between the reference clock signal R and the feedback frequency-divided clock signal V output from the frequency dividing circuit 150, and outputs an up signal UP, a down signal DN, and the like corresponding to the detected phase difference. Output a signal. For example, when the phase of the feedback frequency-divided clock signal V is delayed with respect to the reference clock signal R, the phase comparator 110 outputs an up signal UP that instructs to control the frequency higher to the charge pump 120 or the like. To do. The phase comparator 110 outputs a down signal DN to the charge pump 120 or the like to instruct to control the frequency to be low when the phase of the feedback divided clock signal V is advanced with respect to the reference clock signal R. To do.

  The charge pump 120 receives a signal such as an up signal UP and a down signal DN output from the phase comparator 110, and has a function of a charge pump that flows out or flows in a control current CPOUT corresponding to the input signal.

  Furthermore, the charge pump 120 according to the present embodiment changes the loop band of the PLL circuit 100 by changing the value of the control current CPOUT in accordance with the loop band setting signal ICP output from the loop band control circuit 180. Functions as a loop band changing circuit. A specific configuration of the charge pump 120 will be described later.

  Loop filter 130 smoothes control current CPOUT output from charge pump 120 and outputs a control voltage.

  The VCO 140 is a voltage controlled oscillator that outputs an output clock signal having a frequency corresponding to the control voltage output from the loop filter 130.

  The frequency dividing circuit 150 divides the output clock signal output from the VCO 140 by a preset frequency dividing ratio, and outputs the divided feedback frequency divided clock signal V to the phase comparator 110.

  With the above configuration, the PLL circuit 100 generates and outputs an output clock signal synchronized with the modulated clock R.

  Further, the PLL circuit 100 detects the modulation frequency of the reference clock signal R by the phase difference detection circuit 160, the modulation frequency detection circuit 170, and the loop band control circuit 180, and outputs a loop band setting signal ICP corresponding to the detected modulation frequency. Output to the charge pump 120.

  For example, the phase difference detection circuit 160 indicates that the phase difference between the reference clock signal R and the feedback divided clock signal V is equal to or less than a predetermined value based on the output signal of the phase comparator 110. A detection signal PDET is output.

  The modulation frequency detection circuit 170 outputs FDATA, which is data or a signal indicating the modulation frequency of the reference clock signal R, to the loop band control circuit 180 based on the period of the phase difference data PDET output from the phase difference detection circuit 160. To do.

  The loop band control circuit 180 receives FDATA from the modulation frequency detection circuit 170 and outputs a loop band setting signal ICP for setting a loop band corresponding to the modulation frequency indicated by FDATA to the charge pump 120.

  For example, the loop band control circuit 180 is preset with a plurality of loop band setting signals ICP corresponding to the modulation frequency of the reference clock signal R. When FDATA is input from the modulation frequency detection circuit 170, the loop band control circuit 180 selects a loop band setting signal ICP corresponding to the modulation frequency indicated by FDATA from among a plurality of preset loop band setting signals ICP. Is output to the charge pump 120.

  In the loop band control circuit 180, for example, the loop band setting for setting the loop band of the PLL circuit 100 so as to secure a modulation width necessary for the modulation frequency of the reference clock signal R and to make the loop band as narrow as possible. The signal ICP is preset.

  With the above configuration, the PLL circuit 100 changes the value of the control current CPOUT output from the charge pump 120 according to the modulation frequency of the reference clock signal R, and is automatically set to the loop band corresponding to the modulation frequency. It becomes like this.

  Thus, according to the present embodiment, in the PLL circuit 100 to which the frequency-modulated reference clock signal is input, it is easy to suppress jitter due to the influence of disturbances and the like while ensuring the modulation width of the output signal. .

(Configuration of phase difference detection circuit)
FIG. 2 is a diagram illustrating an example of the phase difference detection circuit according to the first embodiment. In FIG. 2, a phase difference detection circuit 160 includes delay amount generation circuits 201 and 202 that delay an input signal by a predetermined delay amount Td, AND circuits 211 and 212, DFFs (D-type flip-flops) 221, 222, And a NOR circuit 230.

  The delay amount generation circuit 201 receives an up signal UP (hereinafter referred to as “signal UP”) output from the phase comparator 110, and outputs an output signal obtained by delaying the signal UP by a predetermined delay amount Td. The data is output to one input of the AND circuit 211.

  In the AND circuit 211, the output signal of the delay amount generation circuit 201 is input to one input, the signal UP is input to the other input, and a signal UPD that is an AND (logical product) of the two input signals is received. Output to the D terminal of the DFF 221.

  The DFF 221 reads the value of the signal UPD input to the D terminal in response to the rising of the feedback frequency-divided clock signal V (hereinafter referred to as “signal V”) input to the CK terminal. This is a D-type flip-flop circuit that holds the value until the rise. The DFF 221 outputs a signal UPDET indicating the held value to one input terminal of the NOR circuit 230.

  The delay amount generation circuit 202 receives a down signal DN (hereinafter referred to as “signal DN”) output from the phase comparator 110, and outputs an output signal obtained by delaying the signal DN by a predetermined delay amount Td. The data is output to one input of the AND circuit 212.

  In the AND circuit 212, the output signal of the delay amount generation circuit 202 is input to one input, the signal DN is input to the other input, and a signal DND that is an AND (logical product) of the two input signals. Is output to the D terminal of the DFF 222.

  The DFF 222 reads the value of the signal DND input to the D terminal according to the rising edge of the reference clock R input to the CK terminal, and holds the value until the next rising edge of the reference clock R. Circuit. Further, the DFF 222 outputs a signal DNDET indicating the held value to the other input terminal of the NOR circuit 230.

  In the NOR circuit 230, the signal UPDET output from the DFF 221 is input to one input terminal, and the signal DNDET output from the DFF 222 is input to the other input terminal, and NOR (negative logic) of the two input signals is input. Sum)) is output.

(Timing chart of phase difference detection circuit)
Next, the operation of the phase difference detection circuit 160 will be described using a timing chart. FIG. 3 is a diagram illustrating an example of a timing chart of the phase difference detection circuit according to the first embodiment.

  FIG. 3A shows an example of a timing chart when the phase of the reference clock signal R is earlier (advanced) than the phase of the signal V.

  In FIG. 3A, the reference clock signal R, the signal V, the signal UP, and the signal DN are the same as those in the conventional PLL circuit. Specifically, the signal UP rises when the reference clock signal R rises, and the signal DN rises when the signal V rises. Further, after both the reference clock signal R and the signal V rise, the signal UP and the signal DN fall.

  The signal UPD rises with a predetermined delay amount Td from the rise of the signal R, and falls together with the signal UP and the signal DN. Further, the signal UPDET outputs the value of the signal UPD at the rising timing of the signal V and holds the value until the next rising timing of the signal V.

  As a result, as shown before and after time t1 in FIG. 3A, DT1, which is the difference between the pulse width of the signal UP and the pulse width of the signal DN, is larger than the delay amount Td generated by the delay amount generation circuit 201. When the signal V rises, the H level is output as the UPDET signal.

  On the other hand, as shown before and after the time t2 in FIG. 3B, when DT2, which is the difference between the pulse width of the signal UP and the pulse width of the signal DN, is smaller than the delay amount Td generated by the delay amount generation circuit 201. In response to the rise of the signal V, the L level is output as the UPDET signal.

  FIG. 3B shows an example of a timing chart when the phase of the reference clock signal R is later (delayed) than the phase of the signal V.

  Also in FIG. 3B, the signal UP rises when the reference clock signal R rises, and the signal DN rises when the signal V rises. Further, after both the reference clock signal R and the signal V rise, the signal UP and the signal DN fall.

  Further, the signal DND rises with a predetermined delay amount Td from the rising of the signal DN, and falls together with the signal UP and the signal DN. Further, the signal DNDET outputs the value of the signal DND at the rising timing of the signal R and holds the value until the next rising timing of the signal R.

  Thus, as shown before and after time t3, when DT3, which is the difference between the pulse width of the signal UP and the pulse width of the signal DN, is larger than the delay amount Td generated by the delay amount generation circuit 201, the reference clock signal R The H level is output to the DNDET signal in response to the rising edge.

  On the other hand, as shown before and after time t4 in FIG. 3B, when DT4, which is the difference between the pulse width of the signal UP and the pulse width of the signal DN, is smaller than the delay amount Td generated by the delay amount generation circuit 201. In response to the rising edge of the reference clock signal R, the L level is output to the UPDET signal.

  As shown in FIG. 2, the phase difference data PDET, which is an output signal of the phase difference detection circuit 160, is NOR between the signal UPDET and the signal DNDET. Becomes H level.

  Here, if the predetermined delay amount generated by the delay amount generation circuits 201 and 202 is the delay amount Td, the difference between the pulse width of the UP signal and the pulse width of the DN signal, that is, the reference clock signal R and the signal V The phase difference data PDET becomes H level when the phase difference between and becomes less than the delay amount Td.

  That is, the phase difference between the reference clock signal R and the signal V at which the phase difference data PDET becomes H level is determined by the delay amount Td of the delay amount generation circuits 201 and 202.

  In this way, the phase difference detection circuit 160 determines whether the difference between the pulse width of the signal UP from the phase comparator 110 and the pulse width of the signal DN and the predetermined delay amount Td is a reference clock signal. This is performed at the rise of R and the rise of signal V.

(Signal PDET)
FIG. 4 is a diagram illustrating an example of the output timing of the signal PDET according to the first embodiment. As shown in FIG. 4, the reference clock signal R, which is an SSCG output signal, has a 30 kHz sine wave profile as shown in FIG. 4 as an example, where the vertical axis is the output frequency F and the horizontal axis is the time t. Become. Here, it is assumed that the reference clock signal R is frequency-modulated by, for example, plus or minus 1% with respect to the center frequency F0.

  In the example of FIG. 4, the reference clock signal R returns to the center frequency F0 at intervals of 30 kHz. The signal V operates following the reference clock signal R, and is an output signal of the phase difference detection circuit 160 when the phase difference between the reference clock signal R and the signal V is equal to or less than the delay amount Td. The phase difference data PDET becomes H level. Thereby, for example, as shown in the period dt1 of FIG. 4, when the amount of change in the frequency of the reference clock R is a predetermined value or less, the H level is output as the phase difference data PDET.

  This period dt1 during which the phase difference data PDET is at the H level can be changed by setting the delay amount Td. Further, as shown in FIG. 4, the timing at which the phase difference data PDET becomes H level is twice (for example, 60 kHz) the modulation frequency (for example, 30 kHz) of the reference clock signal R.

  With the above configuration, the phase difference detection circuit 160 generates the phase difference detection signal PDET indicating that the phase difference between the reference clock signal R and the signal V is equal to or smaller than a predetermined value twice the reference clock signal R. Output at a frequency of.

(Modulation frequency detection circuit)
FIG. 5 is a diagram illustrating an example of the modulation frequency detection circuit according to the first embodiment. The modulation frequency detection circuit 170 is realized by, for example, a frequency counter 501 as shown in FIG. In the example of FIG. 5, the frequency counter 501 uses the reference clock signal R to count the frequency of the phase difference detection signal PDET output from the phase difference detection circuit 160 and detect the value of the modulation frequency of the reference clock signal R. . For example, as described with reference to FIG. 4, when the frequency of the phase difference detection signal PDET is 60 kHz, the value of the modulation frequency of the reference clock signal R is ½, 30 kHz.

  The modulation frequency detection circuit 170 outputs FDATA that is data or a signal indicating the value of the modulation frequency of the detected reference clock signal R to the loop band control circuit 180. Here, the following description will be made assuming that FDATA is data indicating the value of the modulation frequency of the reference clock signal R.

(Loop bandwidth control circuit)
FIG. 6 is a diagram illustrating an example of a loop band circuit according to the first embodiment. As shown in FIG. 6, the loop band control circuit 180 is configured to output a preset loop band setting signal ICP according to the value of FDATA indicating the modulation frequency of the reference clock R.

  Further, the loop band control circuit 180 sets the loop band of the PLL circuit 100 so that, for example, a modulation width necessary for the modulation frequency of the reference clock signal R is secured and the loop band is set as narrow as possible. It is assumed that the signal ICP is set in advance.

  The FDATA indicating the modulation frequency of the reference clock R may be other data that changes in accordance with the modulation frequency of the reference clock R. For example, FDATA indicating the modulation frequency of the reference clock R may be a count value of the phase difference detection signal PDET counted by the frequency counter 501 of the modulation frequency detection circuit 170.

  In the example of FIG. 6, when the FDATA indicating the modulation frequency of the reference clock R is 30 kHz, the loop band control circuit 180 outputs a loop band setting signal ICP [2: 0] = 010.

  With the above configuration, the loop band control circuit 180 can output the loop band setting signal ICP corresponding to a plurality of preset frequency ranges.

(Charge pump)
FIG. 7 is a diagram illustrating an example of the charge pump according to the first embodiment. The charge pump 120 has a plurality of constant current sources 701 to 708.

  The constant current source 701 is connected in series with the switch 721 between the power supply voltage + V and CPOUT, and flows the current I into CPOUT when the signal UP becomes H level.

  The constant current source 702 is connected in series with the switch 731 between CPOUT and the ground potential GND, and causes the current I to flow out of CPOUT when the signal DN becomes H level.

  The constant current source 703 is connected in series with the switch 711 and the switch 722 between the power supply voltage + V and CPOUT. When the ICP0 of the loop band setting signal ICP [2: 0] output from the loop band control circuit 180 is “1”, the constant current source 703 causes the current I0 to flow into CPOUT when the signal UP becomes H level.

  The constant current source 704 is connected in series with the switch 732 and the switch 712 between CPOUT and the ground potential GND. When the ICP0 of the loop band setting signal ICP [2: 0] output from the loop band control circuit 180 is “1”, the constant current source 704 causes the current I0 to flow out from CPOUT when the signal DN becomes H level.

  The constant current source 705 is connected in series with the switch 713 and the switch 723 between the power supply voltage + V and CPOUT. When the loop band setting signal ICP [2: 0] ICP1 output from the loop band control circuit 180 is “1”, the constant current source 705 causes the current I1 to flow into CPOUT when the signal UP becomes H level.

  The constant current source 706 is connected in series with the switch 733 and the switch 714 between CPOUT and the ground potential GND. When the loop band setting signal ICP [2: 0] ICP1 output from the loop band control circuit 180 is “1”, the constant current source 706 causes the current I1 to flow out from CPOUT when the signal DN becomes H level.

  The constant current source 707 is connected in series with the switch 715 and the switch 724 between the power supply voltage + V and CPOUT. When the ICP2 of the loop band setting signal ICP [2: 0] output from the loop band control circuit 180 is “1”, the constant current source 707 causes the current I2 to flow into CPOUT when the signal UP becomes H level.

  The constant current source 708 is connected in series with the switch 734 and the switch 716 between CPOUT and the ground potential GND. When the loop band setting signal ICP [2: 0] ICP2 output from the loop band control circuit 180 is “1”, the constant current source 708 causes the current I2 to flow out from CPOUT when the signal DN becomes H level.

  With the above configuration, when the UP signal becomes H level, the charge pump 120 has a current having a current value set by the loop band setting signal ICP [2: 0] flowing into CPOUT. Further, when the DN signal becomes H level, the charge pump 120 causes the current of the current value set by the loop band setting signal ICP [2: 0] to flow out from CPOUT.

  For example, when ICP0 is at H level, ICP1 is at L level, and ICP2 is at L level, the current value set by the loop band setting signal ICP [2: 0] is I + I0. When ICP0 is H level, ICP1 is H level, and ICP2 is L level, the current value set by the loop band setting signal ICP [2: 0] is I + I0 + I1.

  Thus, the charge pump 120 changes the current value flowing into and out of CPOUT by the loop band setting signal ICP [2: 0].

  In FIG. 7, the loop band setting signal ICP has been described as having 3 bits, but the loop band setting signal ICP may have another bit number of 1 bit or more.

(About loop bandwidth)
FIG. 8 is a diagram for explaining the loop band.

  FIG. 8A shows an example of a block diagram of a general PLL circuit. FIG. 8B shows an example of the loop filter 803 of the PLL circuit shown in FIG. FIG. 8C shows a Bode diagram of the PLL circuit shown in FIG.

  In FIG. 8C, the zero point F1 is represented by F1 = 1 / (2π × R × C1). The pole point F2 is expressed by F2 = 1 / (2π × R × C2).

  The loop band Fc of the PLL circuit is expressed by the following equation (1).

Fc = Kv × Icp × R / (2π × N) (1)
In Equation (1), Kv is the VCO gain (Hz / V) of the VCO 804, and Icp is the charge pump current of the charge pump 802. N is the frequency dividing number of the frequency dividing circuit 805.

  In the Bode diagram shown in FIG. 8C, in order for the PLL circuit to converge to the frequency Fc stably, the relationship of F1 <Fc <F2 is necessary, and F1 is set so that the phase margin is sufficiently large. , F2 needs to be set.

  Further, when the reference clock signal is modulated, the loop bandwidth Fc of the PLL circuit is sufficiently higher than the modulation frequency of the reference clock signal in order to ensure the modulation width with the output clock signal (for example, 10 times or more) must be set.

  In the PLL circuit 100 according to the first embodiment shown in FIGS. 1 to 7, the loop band Fc is changed by changing the current value of the control current CPOUT of the charge pump according to the modulation frequency of the reference clock signal R. be able to.

  For example, as shown in FIG. 6, when the loop band control signal ICP [2: 0] is preset according to a plurality of frequency ranges and the modulation frequency of the reference clock signal R is low, the loop band Fc is It is set to be low (narrow). Thereby, an increase in jitter due to the influence of disturbance or the like can be reduced. On the other hand, when the modulation frequency of the reference clock signal R is high, the loop band Fc is set to be high (wide). Thereby, even when the modulation frequency of the reference clock signal R is high, the modulation width of the output clock signal can be secured.

  As described above, the PLL circuit 100 according to the present embodiment detects the period when the phase difference between the reference clock signal R and the feedback frequency-divided clock signal V is equal to or less than a predetermined value, so that the modulation frequency of the reference clock signal R is detected. Is detected. Further, the PLL circuit 100 can set an appropriate loop band Fc by making the value of the control current CPOUT of the charge pump 120 variable and setting the control current CPOUT according to the detected modulation frequency.

  As a result, according to the PLL circuit 100 according to the present embodiment, in the PLL circuit 100 to which the frequency-modulated reference clock signal R is input, the jitter due to the influence of disturbance or the like is suppressed while ensuring the modulation width of the output signal. Easy to do.

[Second Embodiment]
In the first embodiment, the example of changing the loop band Fc by changing the control current of the charge pump 120 has been described. However, the charge pump 120 is an example of a loop band changing circuit that changes the loop band. It is.

  For example, as shown in Expression (1), the loop band Fc can be changed by changing the resistance value R of the loop filter. In this case, it is possible to set the loop filter to a suitable time constant by changing the capacitance values C1 and C2 of the loop filter together with the resistance value R of the loop filter.

  In the second embodiment, an example in which the loop band changing circuit is a loop filter will be described.

<Configuration of PLL circuit>
(Overall configuration)
FIG. 9 is a block diagram of a PLL circuit according to the second embodiment. In FIG. 9, the configurations of the phase comparator 110, the VCO 140, the frequency dividing circuit 150, the phase difference detection circuit 160, the modulation frequency detection circuit 170, and the like are the same as those in the first embodiment. The explanation will focus on the differences.

  In the charge pump 910 according to the present embodiment, the value of the control current CPOUT is fixed. The loop filter 920 according to the present embodiment functions as a loop band changing circuit that changes the loop band by changing the constant of the loop filter 920 in accordance with the loop band setting signal LF from the loop band control circuit 930. To do.

  Furthermore, the loop band control circuit 930 according to the present embodiment outputs a loop band setting signal LF for setting a constant of the loop filter 920 as a loop band setting signal for setting the loop band of the PLL circuit 900.

(Loop bandwidth control circuit)
FIG. 10 is a diagram illustrating an example of a loop band control circuit according to the second embodiment. As shown in FIG. 10, the loop band control circuit 930 is configured to output a preset loop band setting signal LF according to the value of FDATA indicating the modulation frequency of the reference clock R.

  Further, the loop band control circuit 930 has a loop band setting for setting the loop band of the PLL circuit 900 so that, for example, a modulation width necessary for the modulation frequency of the reference clock signal R is secured and the loop band is as narrow as possible. It is assumed that the signal LF is set in advance.

  Note that FDATA indicating the modulation frequency of the reference clock R is another data that changes in accordance with the modulation frequency of the reference clock R, for example, the phase difference detection signal PDET counted by the frequency counter 501 of the modulation frequency detection circuit 170. May be a count value.

  In the example of FIG. 10, the loop band control circuit 930 is configured to output a loop band setting signal LF [2: 0] = 010 when FDATA indicating the modulation frequency of the reference clock R is 30 kHz.

  With the above configuration, the loop band control circuit 930 can output the loop band setting signal LF corresponding to a plurality of preset frequency ranges.

(Loop filter)
FIG. 11 is a diagram illustrating an example of a loop filter according to the second embodiment. The loop filter 920 includes a plurality of resistance elements 1111 to 1113 that constitute the constant R of the loop filter 920, a plurality of capacitance elements 1121 to 1123 that constitute the constant C1, and a plurality of capacitance elements 1131 to 1133 that constitute the constant C2. .

  The resistance element 1111 is connected in series with the switch 1141, and forms a constant R of the loop filter 920 when LF0 of the loop band setting signal LF [2: 0] output from the loop band control circuit 930 is “1”. It functions as one of the resistance elements.

  The resistance element 1112 is connected in series with the switch 1151, and configures a constant R of the loop filter 920 when LF1 of the loop band setting signal LF [2: 0] output from the loop band control circuit 930 is “1”. It functions as one of the resistance elements.

  The resistance element 1113 is connected in series with the switch 1161 and constitutes a constant R of the loop filter 920 when LF2 of the loop band setting signal LF [2: 0] output from the loop band control circuit 930 is “1”. Function as a resistive element.

  With the above configuration, the loop band control circuit 930 can change the value of the constant R of the loop filter 920 by the loop band setting signal LF [2: 0].

  The capacitive element 1121 is connected in series with the switch 1142, and when the LF0 of the loop band setting signal LF [2: 0] output from the loop band control circuit 930 is “1”, configures the constant C1 of the loop filter 920. It functions as one of the capacitor elements.

  The capacitive element 1122 is connected in series with the switch 1152, and forms the constant C1 of the loop filter 920 when LF1 of the loop band setting signal LF [2: 0] output from the loop band control circuit 930 is “1”. It functions as one of the capacitor elements.

  Capacitance element 1123 is connected in series with switch 1162 and constitutes constant C1 of loop filter 920 when LF2 of loop band setting signal LF [2: 0] output from loop band control circuit 930 is “1”. It functions as one of the capacitor elements.

  With the above configuration, the loop band control circuit 930 can change the value of the constant C1 of the loop filter 920 by the loop band setting signal LF [2: 0].

  The capacitive element 1131 is connected in series with the switch 1143, and forms the constant C2 of the loop filter 920 when LF0 of the loop band setting signal LF [2: 0] output from the loop band control circuit 930 is “1”. It functions as one of the capacitor elements.

  The capacitive element 1132 is connected in series with the switch 1153, and forms the constant C2 of the loop filter 920 when LF1 of the loop band setting signal LF [2: 0] output from the loop band control circuit 930 is “1”. It functions as one of the capacitor elements.

  The capacitive element 1133 is connected in series with the switch 1163, and configures a constant C2 of the loop filter 920 when LF2 of the loop band setting signal LF [2: 0] output from the loop band control circuit 930 is “1”. It functions as one of the capacitor elements.

  With the above configuration, the loop band control circuit 930 can change the value of the constant C2 of the loop filter 920 by the loop band setting signal LF [2: 0].

  As indicated by the above-described equation (1), the loop band Fc of the PLL circuit 900 can be changed by changing the resistance value R of the loop filter. Further, it is desirable to change the capacitance values C1 and C2 to appropriate values when changing the loop band Fc by changing the resistance value R of the loop filter.

  With the above configuration, the PLL circuit 900 according to the present embodiment is set to a constant of the loop filter 920 according to the modulation frequency of the reference clock signal R, as in the PLL circuit 100 according to the first embodiment, and is appropriately set. The loop band Fc can be set.

  As described above, also in the PLL circuit 900 according to the second embodiment, it is easy to suppress jitter due to the influence of a disturbance or the like while ensuring the modulation width of the output signal.

[Third Embodiment]
The second embodiment can be implemented in combination with the first embodiment. 3rd Embodiment demonstrates the example in the case of implementing combining 1st Embodiment and 2nd Embodiment.

<Configuration of PLL circuit>
(Overall configuration)
FIG. 12 is a block diagram of a PLL circuit according to the third embodiment. In FIG. 12, the configurations of the phase comparator 110, the charge pump 120, the VCO 140, the frequency dividing circuit 150, the phase difference detection circuit 160, the modulation frequency detection circuit 170, and the like are the same as those in the first embodiment. In FIG. 12, the configuration of the loop filter 920 is the same as that of the second embodiment. Here, the description will focus on differences from the first embodiment and the second embodiment.

  In the present embodiment, the loop band control circuit 1210 sets the loop band of the PLL circuit 1200 corresponding to the modulation frequency of the reference clock signal R according to FDATA indicating the modulation frequency of the reference clock signal R. , LF is output.

  In the present embodiment, the charge pump 120, the loop filter 920, and the loop band changing circuit that changes the loop band of the PLL circuit 1200 according to the loop band setting signals ICP and LF output from the loop band control circuit 1210 are provided. Is included.

(Loop bandwidth control circuit)
FIG. 13 is a diagram illustrating an example of a loop bandwidth control circuit according to the third embodiment. As shown in FIG. 13, the loop band control circuit 1210 has loop band setting signals ICP [2: 0] and LF [2: 0] set in advance according to the value of FDATA indicating the modulation frequency of the reference clock R. Is configured to output.

  Further, the loop band control circuit 1210 has a loop band setting for setting the loop band of the PLL circuit 1200 so that, for example, a modulation width necessary for the modulation frequency of the reference clock signal R is secured and the loop band is as narrow as possible. Signals ICP and LF are set in advance.

  The FDATA indicating the modulation frequency of the reference clock R may be other data that changes in accordance with the modulation frequency of the reference clock R. For example, FDATA indicating the modulation frequency of the reference clock R may be a count value of the phase difference detection signal PDET counted by the frequency counter 501 of the modulation frequency detection circuit 170.

  In the example of FIG. 13, when the FDATA indicating the modulation frequency of the reference clock R is 30 kHz, the loop band control circuit 930 sets the loop band setting signals ICP [2: 0] = 010 and LF [2: 0] = 010. It is configured to output. Note that the value of ICP [2: 0] may be different from the value of LF [2: 0].

  With the above configuration, the PLL circuit 1200 according to the present embodiment is set to an appropriate loop band Fc according to the modulation frequency of the reference clock signal R, similarly to the PLL circuits according to the first and second embodiments. Can do.

  As described above, also in the PLL circuit 1200 according to the third embodiment, it is easy to suppress jitter due to the influence of a disturbance or the like while ensuring the modulation width of the output signal.

[Fourth Embodiment]
FIG. 14 is a block diagram of a clock generation circuit according to the fourth embodiment. A clock generation circuit 1400 illustrated in FIG. 14 includes, for example, a PLL circuit having a phase comparator 110, a charge pump 120, a loop filter 920, a VCO 140, a frequency dividing circuit 150, and a loop band control circuit 1210, and an SSCG 1410. Yes.

  The phase comparator 110, the charge pump 120, the loop filter 920, the VCO 140, the frequency dividing circuit 150, and the loop band control circuit 1210 are the same as, for example, each component shown in the third embodiment.

  The SSCG 1410 is a spread spectrum clock oscillator that generates a frequency-modulated reference clock R. The SSCG 1410 according to this embodiment includes a modulation frequency notification unit 1411 that notifies the loop band control circuit 1210 of FDATA that is data or a signal indicating the modulation frequency of the reference clock signal R generated by the SSCG 1410.

  The modulation frequency notification unit 1411 is realized by, for example, a program executed by the control circuit of the SSCG 1410, hardware (logic circuit), or the like.

  Accordingly, in the clock generation circuit 1400 illustrated in FIG. 14, for example, FDATA indicating the modulation frequency of the reference clock signal R is acquired from the SSCG 1410 instead of the phase difference detection circuit 160 and the modulation frequency detection circuit 170 illustrated in FIG. 12. be able to.

  As a result, the clock generation circuit 1400 can obtain the same effects as those of the first to third embodiments regardless of the phase difference detection circuit 160 and the modulation frequency detection circuit 170.

100, 900, 1200 PLL circuit 180, 930, 1210 Loop band control circuit 110 Phase comparator 120 Charge pump (an example of a loop band changing circuit)
140 VCO (Voltage Controlled Oscillator)
150 frequency dividing circuit 160 phase difference detection circuit 170 modulation frequency detection circuit 701 to 708 constant current source 920 loop filter (an example of a loop band changing circuit)
1400 Clock Generation Circuit 1410 SSCG (Spread Spectrum Clock Oscillator)
1411 Modulation frequency notification unit

JP 2012-80478 A Japanese Patent Laid-Open No. 2001-160752

Claims (10)

A PLL circuit that generates an output clock signal based on a modulated reference clock signal,
A loop band control circuit that receives data or a signal indicating the modulation frequency of the reference clock signal and outputs a loop band setting signal that sets a loop band of the PLL circuit corresponding to the modulation frequency;
A loop band changing circuit for changing a loop band of the PLL circuit in accordance with the loop band setting signal output from the loop band control circuit;
A PLL circuit. A phase comparator for detecting a phase difference between the reference clock signal and a feedback frequency-divided clock signal of the PLL circuit;
A phase difference detection circuit that outputs a phase difference detection signal indicating that a phase difference between the reference clock signal and the feedback frequency-divided clock signal is equal to or less than a predetermined value based on an output signal of the phase comparator When,
Based on the period of the phase difference detection signal output from the phase difference detection circuit, the modulation frequency of the reference clock signal is detected, and data or a signal indicating the detected modulation frequency is output to the loop band control circuit. A modulation frequency detection circuit;
The PLL circuit according to claim 1. A charge pump for flowing out or inflowing a control current based on an output signal of the phase comparator;
A loop filter for smoothing the control current and outputting a control voltage;
A voltage controlled oscillator that outputs the output clock signal having a frequency according to the control voltage;
A frequency dividing circuit that divides the output clock signal output by the voltage controlled oscillator and outputs the feedback divided clock signal to the phase comparator;
The PLL circuit according to claim 2, comprising: The loop band changing circuit includes the charge pump,
The charge pump is
4. The PLL circuit according to claim 3, wherein a value of a control current of the charge pump is changed according to the loop band setting signal. The charge pump is
Having a plurality of constant current sources,
The PLL circuit according to claim 4, wherein a control current of the charge pump is output using the constant current source according to the loop band setting signal among the plurality of constant current sources. The loop band changing circuit includes a loop filter of the PLL circuit,
The loop filter is
The PLL circuit according to claim 3, wherein a constant of the loop filter is changed according to the loop band setting signal. The phase comparator is
An up signal or a down signal corresponding to a phase difference between the reference clock signal and the feedback frequency-divided clock signal of the PLL circuit;
The phase difference detection circuit includes:
The difference between the pulse width of the up signal and the pulse width of the down signal from the phase comparator and a predetermined delay amount are determined based on the rising edge of the reference clock signal and the feedback frequency-divided clock. 7. The PLL circuit according to claim 3, wherein the PLL circuit is performed at a rising edge of the signal. The modulation frequency detection circuit includes:
The PLL circuit according to claim 2, further comprising a counter that counts the phase difference detection signal output from the phase difference detection circuit. The loop bandwidth control circuit is
The PLL circuit according to any one of claims 1 to 8, wherein the PLL band setting signal corresponding to a modulation frequency of the reference clock signal among a plurality of the preset loop band setting signals is output. A PLL circuit according to claim 1;
A spread spectrum clock oscillator for generating a modulated reference clock signal input to the PLL circuit;
Have
The spread spectrum clock oscillator is:
A clock generation circuit having a modulation frequency notification unit that notifies the PLL circuit of data or a signal indicating a modulation frequency of the reference clock signal to be generated.

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