JP2012156517A - Manufacturing method of semiconductor integrated circuit device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a method to reduce pickup failures or die bonding process failures by rapidly reducing the thickness of a chip at a chip pickup process after dicing or a die bonding process in an assembling process from among manufacturing processes of a semiconductor integrated circuit device.SOLUTION: When a chip is vacuum-sucked by using a collet to conduct die bonding, the vacuum suction of the suction collet is terminated early (suction off step 206), thereby avoiding the occurence of voids or the likes due to the bending of the chip occurring during the die bonding (bonding step 208).

Description

  The present invention relates to a technique effective when applied to a die bonding technique or a chip peeling technique in a method for manufacturing a semiconductor integrated circuit device (or a semiconductor device).

  In Japanese Patent Application Laid-Open No. 2005-322815 (Patent Document 1), a collet is bonded with a convex elastic collet, the collet is released from vacuum, and is brought to atmospheric pressure, and the collet is removed in a state where the suction force to the chip is lost. An increasing die bonding technique is disclosed.

  Japanese Laid-Open Patent Publication No. 10-004258 (Patent Document 2) discloses a chip mounting technique in which a through hole is formed on one side surface of a collet for mounting a chip or the like to prevent sucking of solder during mounting. Has been.

  In Japanese Unexamined Patent Publication No. 2006-165188 (Patent Document 3), a vacuum suction hole is provided only around the periphery of a collet tip rubber tip (hardness JIS-A60) having elasticity so as not to leave a void in the thin film tip. A technique for die bonding with a chip protruding downward is disclosed.

  Japanese Unexamined Patent Publication No. 2004-022995 (Patent Document 4) or Japanese Unexamined Patent Publication No. 2005-150311 (Patent Document 5) discloses a collet having convex elasticity.

  Japanese Laid-Open Patent Publication No. 2005-093838 (Patent Document 6) or US Patent Publication No. 2005-0061856 (Patent Document 7) discloses a die bonding technique for performing temporary crimping and main crimping on separate stages. Yes.

  In Japanese Patent Application Laid-Open No. 2005-9166 (Patent Document 8) or US Patent Publication No. 2005-0200142 (Patent Document 9), whether or not a component is adsorbed with respect to an adsorption nozzle such as a mounter of an electronic component is determined. It is disclosed that the detection is performed by a change in the detection flow rate of the sensor.

  Japanese Laid-Open Patent Publication No. 2003-133791 (Patent Document 10), Japanese Laid-Open Patent Publication No. 2004-23027 (Patent Document 11), or Japanese Laid-Open Patent Publication No. 2007-103777 (Patent Document 12) includes an electronic component mounter, etc. In Japanese Patent Application Laid-Open No. 2004-259542, it is disclosed that when an electronic component is sucked and transported by a suction nozzle, whether or not the component is correctly sucked is detected by a change in flow rate detected by an air flow sensor.

  In Japanese Patent Application Laid-Open No. 2004-186352 (Patent Document 13) or US Patent Publication No. 2006-0252233 (Patent Document 14), regarding the pickup of a thin film chip after wafer dicing, ultrasonic vibration is applied from below the dicing tape. When the chip is peeled off from the adhesive sheet (dicing tape) by applying the suction collet from above, the suction flow rate of the suction collet is measured to determine whether the chip is completely peeled off the dicing tape and adsorbed on the suction collet. Confirmation is disclosed.

  Japanese Patent Application Laid-Open No. 2005-1117019 (Patent Document 15) or US Pat. No. 7,115,482 (Patent Document 16) discloses a method of picking up a thin film chip after wafer dicing using a multistage push-up mechanism from below the dicing tape. It is disclosed that the chip is peeled off from the pressure-sensitive adhesive sheet (dicing tape) from above by an adsorbing collet.

JP 2005-322815 A JP-A-10-004258 JP 2006-165188 A JP 2004-022995 A Japanese Patent Application Laid-Open No. 2005-150311 JP 2005-093838 A US Patent Publication No. 2005-0061856 Japanese Patent Laid-Open No. 2005-9166 US Patent Publication No. 2005-0200142 Japanese Patent Laid-Open No. 2003-133791 Japanese Patent Laid-Open No. 2004-23027 JP 2007-103777 A JP 2004-186352 A US Patent Publication No. 2006-0252233 JP 2005-1117019 A U.S. Pat. No. 7,115,482

  In the chip pick-up process or die bonding process after dicing in the assembly process of the manufacturing process of a semiconductor integrated circuit device, reduction of pick-up defects or die bonding process defects is an important issue due to rapid chip thinning. It has become. In particular, according to the study by the present inventor, it is highly possible that the curvature of the periphery of the chip due to the peeling operation causes cracking or chipping of the chip, and voids due to vacuum suction of the collet during die bonding. It became clear that the outbreak could not be ignored. The present invention has been made to solve these problems.

  An object of the present invention is to provide a manufacturing process of a highly reliable semiconductor integrated circuit device.

  The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

  The following is a brief description of an outline of typical inventions disclosed in the present application.

  That is, in the present invention, when the chip is peeled off by vacuum suction with a suction collet from a dicing tape (adhesive tape) or the like, or when the chip is vacuum suctioned with a collet for die bonding, the vacuum suction of the suction collet is early. To avoid the generation of voids and the like due to the curved state due to vacuum suction of the chip during die bonding.

  The effects obtained by the representative ones of the inventions disclosed in the present application will be briefly described as follows.

  That is, when die bonding is performed by vacuum suction of a chip with a collet, the vacuum suction of the suction collet is released at an early stage and landing is performed at atmospheric pressure, thereby providing a die bonding process with less void generation. be able to.

It is a perspective view of the semiconductor chip used for the manufacturing method of the semiconductor integrated circuit device which is one embodiment of this invention. It is a side view which shows the grinding process of a semiconductor wafer. It is a side view which shows the process of affixing a dicing tape on a semiconductor wafer. It is a side view which shows the dicing process of a semiconductor wafer. It is a top view which shows the state which fixed the semiconductor wafer and the dicing tape to the wafer ring, and has arrange | positioned the pressing plate above it and arrange | positioned the expand ring below. It is sectional drawing which shows the state which fixed the semiconductor wafer and the dicing tape to the wafer ring, has arrange | positioned the press plate above it, and has arrange | positioned the expand ring below. It is sectional drawing which shows the state which gave the tension | tensile_strength of the dicing tape by pinching | interposing a dicing tape with a wafer ring with a pressing plate and an expand ring. It is principal part sectional drawing of the chip | tip peeling apparatus explaining the peeling method of the semiconductor chip which affixed the dicing tape. It is sectional drawing which shows the adsorption | suction piece of a chip | tip peeling apparatus. It is an expanded sectional view near the upper surface of a suction piece. It is an expansion perspective view of the upper surface vicinity of an adsorption | suction piece. It is an expanded sectional view of the upper surface vicinity of the adsorption | suction piece explaining the peeling method of a semiconductor chip. It is an expanded sectional view of the upper surface vicinity of the adsorption | suction piece explaining the peeling method of a semiconductor chip. It is an expanded sectional view of the upper surface vicinity of the adsorption | suction piece explaining the peeling method of a semiconductor chip. It is an expansion perspective view of the upper surface vicinity of the adsorption | suction piece explaining the peeling method of a semiconductor chip. It is sectional drawing of the adsorption | suction piece explaining the peeling method of a semiconductor chip. It is an expanded sectional view of the upper surface vicinity of the adsorption | suction piece explaining the peeling method of a semiconductor chip. It is an expansion perspective view of the upper surface vicinity of the adsorption | suction piece explaining the peeling method of a semiconductor chip. It is sectional drawing of the adsorption | suction piece explaining the peeling method of a semiconductor chip. It is an expanded sectional view of the upper surface vicinity of the adsorption | suction piece explaining the peeling method of a semiconductor chip. It is an expansion perspective view of the upper surface vicinity of the adsorption | suction piece explaining the peeling method of a semiconductor chip. It is sectional drawing of the adsorption | suction piece explaining the peeling method of a semiconductor chip. It is an expanded sectional view of the upper surface vicinity of the adsorption | suction piece explaining the peeling method of a semiconductor chip. It is sectional drawing which shows a mode that the semiconductor chip peeled in FIG. 23 is conveyed to a die-bonding part. It is sectional drawing which shows the place which the semiconductor chip peeled in FIG. 23 conveyed to the die-bonding part, and landed on the wiring board. It is sectional drawing which shows the place which the semiconductor chip peeled in FIG. 23 bonded to the wiring board in the die bonding part. It is sectional drawing of the wiring board which shows the pelletizing process of a semiconductor chip. It is sectional drawing of the wiring board which shows the lamination | stacking of a semiconductor chip, and a wire bonding process. It is sectional drawing of the wiring board which shows the resin sealing process of a semiconductor chip. (A)-(c) is sectional drawing of the upper surface vicinity of the adsorption | suction piece explaining the other example of the peeling method of a semiconductor chip. (A) And (b) is explanatory drawing for demonstrating the principle of the peeling method of a semiconductor chip. (A) And (b) is a top view which shows the structure of each example of a rubber chip, a pushing-up block, and a collet main body. (a) And (b) is a top view which shows the structure of a rubber chip, each other example of a raising block, and a collet main body. It is sectional drawing explaining the state of the AA cross section of FIG. 33 or FIG. It is sectional drawing explaining the state of the BB cross section of FIG. 33 or FIG. (a) And (b) is a top view which shows the structure of each further another example of a rubber chip, a pushing-up block, and a collet main body. It is sectional drawing explaining the state of the AA cross section of FIG. It is sectional drawing explaining the state of the BB cross section of FIG. It is a processing flowchart which shows the peeling process 1 in the manufacturing method of the semiconductor integrated circuit device which is one embodiment of this invention. It is a schematic cross-sectional flowchart which shows the peeling process 1 in the manufacturing method of the semiconductor integrated circuit device which is one embodiment of this invention. It is a processing flowchart which shows the peeling process 2 in the manufacturing method of the semiconductor integrated circuit device which is one embodiment of this invention. It is a schematic cross section flowchart which shows the peeling process 2 in the manufacturing method of the semiconductor integrated circuit device which is one embodiment of this invention. It is a processing flowchart which shows the peeling process 3 in the manufacturing method of the semiconductor integrated circuit device which is one embodiment of this invention. It is a schematic cross-sectional flowchart which shows the peeling process 3 in the manufacturing method of the semiconductor integrated circuit device which is one embodiment of this invention. It is a processing flowchart which shows the peeling process 4 in the manufacturing method of the semiconductor integrated circuit device which is one embodiment of this invention. It is an apparatus principal part top view for demonstrating the structure of the peeling apparatus used for the peeling process 4 in the manufacturing method of the semiconductor integrated circuit device which is one embodiment of this invention. It is a schematic cross-sectional flowchart which shows the peeling process 4 in the manufacturing method of the semiconductor integrated circuit device which is one embodiment of this invention. 1 is a schematic cross-sectional flow diagram showing an initial parameter automatic setting method 1 in a method for manufacturing a semiconductor integrated circuit device according to an embodiment of the present invention. It is a processing flowchart which shows the initial parameter automatic setting method 1 in the manufacturing method of the semiconductor integrated circuit device which is one embodiment of this invention. It is a processing flowchart which shows the initial parameter automatic setting method 2 in the manufacturing method of the semiconductor integrated circuit device which is one embodiment of this invention. It is a step flow figure explaining the die-bonding procedure in the manufacturing method of the semiconductor integrated circuit device which is one embodiment of this invention. 6 is a time chart for explaining a die bonding procedure in the method for manufacturing a semiconductor integrated circuit device according to one embodiment of the present invention. FIG. 3 is a schematic cross-sectional flow diagram 1 illustrating a die bonding procedure in a method for manufacturing a semiconductor integrated circuit device according to an embodiment of the present invention; FIG. 4 is a schematic cross-sectional flow diagram 2 illustrating a die bonding procedure in the method for manufacturing a semiconductor integrated circuit device according to one embodiment of the present invention. FIG. 9 is a schematic cross-sectional flow diagram 3 illustrating a die bonding procedure in the method for manufacturing a semiconductor integrated circuit device according to one embodiment of the present invention. FIG. 6 is a schematic cross-sectional flow diagram 4 illustrating a die bonding procedure in the method for manufacturing a semiconductor integrated circuit device according to one embodiment of the present invention. FIG. 7 is a schematic cross-sectional flow diagram 5 illustrating a die bonding procedure in the method for manufacturing a semiconductor integrated circuit device according to one embodiment of the present invention. FIG. 7 is a schematic cross-sectional flow diagram 6 illustrating a die bonding procedure in the method for manufacturing a semiconductor integrated circuit device according to one embodiment of the present invention. FIG. 9 is a schematic cross-sectional flow diagram 7 illustrating a die bonding procedure in the method for manufacturing a semiconductor integrated circuit device according to one embodiment of the present invention; FIG. 9 is a schematic cross-sectional flow diagram 8 illustrating a die bonding procedure in the method for manufacturing a semiconductor integrated circuit device according to one embodiment of the present invention; It is a hardness comparison figure between each standard regarding the material of the rubber chip used for die bonding in the manufacturing method of the semiconductor integrated circuit device which is one embodiment of the present invention. It is a schematic top view which shows the structure of the chip | tip peeling & die bonding integrated apparatus used for the step die bonding method in the manufacturing method of the semiconductor integrated circuit device which is one embodiment of this invention. FIG. 3 is a first cross-sectional step flow diagram showing the flow of the step-die bonding method in the method of manufacturing a semiconductor integrated circuit device according to one embodiment of the present invention; FIG. 6 is a second cross-sectional step flow diagram showing the flow of the step die bonding method in the method of manufacturing a semiconductor integrated circuit device according to one embodiment of the present invention; FIG. 4 is a third cross-sectional step flow diagram showing the flow of the step-die bonding method in the method of manufacturing a semiconductor integrated circuit device according to one embodiment of the present invention. It is a step flow figure explaining the modification of the die bonding procedure in the manufacturing method of the semiconductor integrated circuit device which is one embodiment of this invention. It is sectional drawing of the collet used for the modification of the die bonding procedure in the manufacturing method of the semiconductor integrated circuit device which is one embodiment of this invention.

[Outline of Embodiment]
First, an outline of a typical embodiment of the invention disclosed in the present application will be described.

1. A method of manufacturing a semiconductor integrated circuit device including the following steps:
(A) supplying a plurality of chips to a chip pickup unit of a chip processing apparatus;
(B) In a state where the surface of the first chip of the plurality of chips of the chip pickup unit is vacuum-sucked to the lower surface of the rubber chip of the suction collet, the first chip is placed in the die of the chip processing apparatus.・ Transfer process to the bonding part;
(C) After the step (b), the surface of the first chip is mainly held by physical adsorption between the lower surface of the rubber chip (or adsorption without using a vacuum source, the same applies hereinafter). In a state, the back surface side of the first chip is landed on the upper surface of the wiring substrate placed on the die bonding portion of the chip processing apparatus;
(D) After the step (c), by pressing the front surface of the first chip downward with the lower surface of the rubber chip, the first chip is brought into contact with the back surface of the first chip. Fixing to the upper surface of the wiring board via an adhesive member layer between the upper surfaces of the wiring board;

  2. In the method of manufacturing a semiconductor integrated circuit device according to the item 1, vacuum suction is turned off in the steps (c) to (d) (adsorption without using vacuum adsorption, that is, adsorption without using a vacuum source, same as below).

  3. In the method of manufacturing a semiconductor integrated circuit device according to the item 1 or 2, the rubber chip has a vacuum suction hole in the central portion (it is not always necessary to have a vacuum suction hole in the central portion. Even when a leak is detected, at least a plurality of groups of vacuum suction holes having different distances from the center are required (the same applies hereinafter).

4). In the method for manufacturing a semiconductor integrated circuit device according to any one of Items 1 to 3, the step (b) includes the following sub-steps:
(B1) lowering the first chip toward the upper surface of the wiring board at a first speed;
(B2) Subsequent to the step (b1), the step of lowering the first chip toward the upper surface of the wiring board at a second speed lower than the first speed;
Further, the step (c) includes the following substeps:
(C1) A step of lowering the first chip toward the upper surface of the wiring board at the second speed until landing.

  5). 5. In the method of manufacturing a semiconductor integrated circuit device according to any one of items 1 to 4, the rubber chip includes elastomer as a main component and has a hardness of 10 or more and less than 70.

  6). 5. In the method of manufacturing a semiconductor integrated circuit device according to any one of items 1 to 4, the rubber chip has an elastomer as a main component and has a hardness of 15 or more and less than 55.

  7). 5. In the method of manufacturing a semiconductor integrated circuit device according to any one of items 1 to 4, the rubber chip has an elastomer as a main component and has a hardness of 20 or more and less than 40.

  8). 8. The method of manufacturing a semiconductor integrated circuit device according to 1 to 7, wherein the elastomer is a thermosetting elastomer.

  9. 9. The method for manufacturing a semiconductor integrated circuit device according to any one of 1 to 8, wherein the elastomer is a silicone-based elastomer.

  10. 10. The method for manufacturing a semiconductor integrated circuit device according to any one of 1 to 9, wherein the adhesive member layer is a DAF member layer.

11. The method for manufacturing a semiconductor integrated circuit device according to any one of 1 to 10 further includes the following steps:
(E) A step of irradiating UV light from the adhesive tape side of the plurality of chips whose back surfaces are fixed to the adhesive tape before the step (b).

12 A method of manufacturing a semiconductor integrated circuit device including the following steps:
(A) A step of supplying a plurality of chips divided into individual chip regions to a chip processing apparatus with their back surfaces fixed to an adhesive tape while maintaining the two-dimensional arrangement of the original wafer.
(B) The surface of the first chip of the plurality of chips is vacuum-sucked to the lower surface of the rubber chip of the suction collet, and the adhesive tape on the back surface of the first chip is vacuumed to the upper surface of the lower substrate. A step of peeling the adhesive tape from the back surface of the first chip in the adsorbed state;
Here, the rubber chip has an elastomer as a main component and has a hardness of 15 or more and less than 55.

  13. In the method of manufacturing a semiconductor integrated circuit device according to the item 12, the hardness is 20 or more and less than 40.

  14 14. The method for manufacturing a semiconductor integrated circuit device according to the item 12 or 13, wherein the elastomer is a thermosetting elastomer.

  15. 15. The method for manufacturing a semiconductor integrated circuit device according to any one of 12 to 14, wherein the elastomer is a silicone-based elastomer.

16. A method of manufacturing a semiconductor integrated circuit device including the following steps:
(A) supplying a plurality of chips to a chip pickup unit of a chip processing apparatus;
(B) In a state where the surface of the first chip of the plurality of chips of the chip pickup unit is vacuum-sucked to the lower surface of the rubber chip of the suction collet, the first chip is placed in the die of the chip processing apparatus.・ Transfer process to the bonding part;
(C) After the step (b), with the surface of the first chip adsorbed to the lower surface of the rubber chip, the back surface side of the first chip is Landing on the upper surface of the wiring board placed on the die bonding part;
(D) After the step (c), by pressing the front surface of the first chip downward with the lower surface of the rubber chip, the first chip is brought into contact with the back surface of the first chip. Fixing to the upper surface of the wiring board via an adhesive member layer between the upper surfaces of the wiring board;
Here, the rubber chip has an elastomer as a main component and has a hardness of 15 or more and less than 55.

  17. In the method for manufacturing a semiconductor integrated circuit device according to the item 16, the hardness of the elastomer is 20 or more and less than 40.

  18. 18. In the method for manufacturing a semiconductor integrated circuit device according to 16 or 17, the elastomer is a thermosetting elastomer.

  19. 19. In the method for manufacturing a semiconductor integrated circuit device according to any one of items 16 to 18, the elastomer is a silicone-based elastomer.

  20. 20. In the method of manufacturing a semiconductor integrated circuit device according to any one of items 16 to 19, a vacuum hole is provided in a vacuum suction system in the suction collet body, and vacuum suction is performed in a leaked state therethrough.

  21. 21. In the method for manufacturing a semiconductor integrated circuit device according to any one of 16 to 20, the adhesive member layer is a DAF member layer.

22. The method for manufacturing a semiconductor integrated circuit device according to any one of the items 16 to 21, further comprising the following steps:
(E) A step of irradiating UV light from the adhesive tape side of the plurality of chips whose back surfaces are fixed to the adhesive tape before the step (b).

23. A method of manufacturing a semiconductor integrated circuit device including the following steps:
(A) A chip pick-up unit of a chip processing apparatus with a plurality of chips divided into individual chip regions, with their back surfaces fixed to an adhesive tape, with the two-dimensional arrangement of the original wafer almost unchanged. Supplying to
(B) The surface of the first chip of the plurality of chips is vacuum-sucked to the lower surface of the rubber chip of the suction collet, and the adhesive tape on the back surface of the first chip is vacuumed to the upper surface of the lower substrate. Peeling the adhesive tape from the back surface of the first chip in the adsorbed state;
(C) After the step (b), in a state where the surface of the first chip is adsorbed to the lower surface of the rubber chip of the adsorption collet, the first chip is attached to the die of the chip processing apparatus. Transferring to the bonding part;
(D) After the step (c), with the front surface of the first chip adsorbed to the lower surface of the rubber chip, the back surface side of the first chip is placed on the die of the chip processing apparatus. Landing on the upper surface of the wiring board placed on the bonding part;
(E) After the step (d), by pressing the front surface of the first chip downward with the lower surface of the rubber chip, the first chip is placed on the back surface of the first chip. Fixing to the upper surface of the wiring board via an adhesive member layer between the upper surfaces of the wiring board;
Here, the rubber chip has an elastomer as a main component and has a hardness of 15 or more and less than 55.

  24. 24. In the method of manufacturing a semiconductor integrated circuit device according to the item 23, the hardness is 20 or more and less than 40.

  25. 25. In the method for manufacturing a semiconductor integrated circuit device according to the item 23 or 24, the elastomer is a thermosetting elastomer.

  26. 26. In the method for manufacturing a semiconductor integrated circuit device according to any one of the items 23 to 25, the elastomer is a silicone-based elastomer.

  27. 27. In the method of manufacturing a semiconductor integrated circuit device according to any one of 23 to 26, a vacuum hole is provided in a vacuum suction system in the suction collet body, and vacuum suction is performed in a leaked state therethrough.

  28. 28. In the method for manufacturing a semiconductor integrated circuit device according to any one of the items 23 to 27, the adhesive member layer is a DAF member layer.

29. 29. The method for manufacturing a semiconductor integrated circuit device according to any one of items 23 to 28, further includes the following steps:
(E) A step of irradiating UV light from the adhesive tape side of the plurality of chips whose back surfaces are fixed to the adhesive tape before the step (b).

30. A method of manufacturing a semiconductor integrated circuit device including the following steps:
(A) supplying a plurality of chips to a chip pickup unit of a chip processing apparatus;
(B) In a state where the surface of the first chip of the plurality of chips of the chip pickup unit is vacuum-sucked to the lower surface of the rubber chip of the suction collet, the first chip is placed in the die of the chip processing apparatus.・ Transfer process to the bonding part;
(C) After the step (b), with the front surface of the first chip adsorbed to the lower surface of the rubber chip, the back surface side of the first chip is placed on the die of the chip processing apparatus. Landing on the upper surface of the wiring board placed on the bonding part;
(D) After the step (c), by pressing the front surface of the first chip downward with the lower surface of the rubber chip, the first chip is brought into contact with the back surface of the first chip. Fixing to the upper surface of the wiring board via an adhesive member layer between the upper surfaces of the wiring board;
Here, the rubber chip has a vacuum suction hole in the center portion, and an elastomer as a main component, and the hardness thereof is 10 or more and less than 70.

  31. In the method for producing a semiconductor integrated circuit device according to the item 30, the elastomer is a thermosetting elastomer.

  32. 32. In the method for manufacturing a semiconductor integrated circuit device according to the item 30 or 31, the elastomer is a silicone elastomer.

  33. 33. In the method for manufacturing a semiconductor integrated circuit device according to any one of items 30 to 32, a vacuum hole is provided in a vacuum suction system in the suction collet body, and vacuum suction is performed in a leaked state therethrough.

  34. 34. In the method for manufacturing a semiconductor integrated circuit device according to any one of 30 to 33, the adhesive member layer is a DAF member layer.

35. 35. The method for manufacturing a semiconductor integrated circuit device according to any one of 30 to 34, further comprising the following steps:
(E) A step of irradiating UV light from the adhesive tape side of the plurality of chips whose back surfaces are fixed to the adhesive tape before the step (b).

  36. 36. In the method for manufacturing a semiconductor integrated circuit device according to any one of Items 30 to 35, adsorption of the rubber chip to the lower surface in the step (c) is mainly performed by physical adsorption.

  37. 37. In the method for manufacturing a semiconductor integrated circuit device according to any one of Items 30 to 36, vacuum suction is turned off in the steps (c) to (d).

38. A method of manufacturing a semiconductor integrated circuit device including the following steps:
(A) supplying a plurality of chips to a chip pickup unit of a chip processing apparatus;
(B) In a state where the surface of the first chip of the plurality of chips of the chip pickup unit is vacuum-sucked to the lower surface of the rubber chip of the suction collet, the first chip is placed in the die of the chip processing apparatus.・ Transfer process to the bonding part;
(C) After the step (b), with the surface of the first chip adsorbed to the lower surface of the rubber chip, the back surface side of the first chip is Landing on the upper surface of the wiring board placed on the die bonding part;
(D) After the step (c), by pressing the front surface of the first chip downward with the lower surface of the rubber chip, the first chip is brought into contact with the back surface of the first chip. Fixing to the upper surface of the wiring board via an adhesive member layer between the upper surfaces of the wiring board;
Here, the vacuum suction system in the suction collet body is provided with a leak hole, and vacuum suction is performed in a leaked state therethrough.

  39. 38. In the method for manufacturing a semiconductor integrated circuit device according to the item 38, the rubber chip has a vacuum suction hole in a central portion and has an elastomer as a main component and has a hardness of 10 or more and less than 70.

  40. 40. In the method for manufacturing a semiconductor integrated circuit device according to the item 38 or 39, the adhesive member layer is a DAF member layer.

41. The method for manufacturing a semiconductor integrated circuit device according to any one of the items 38 to 40, further comprising the following steps:
(E) A step of irradiating UV light from the adhesive tape side of the plurality of chips whose back surfaces are fixed to the adhesive tape before the step (b).

  42. 42. In the method for manufacturing a semiconductor integrated circuit device according to any one of the items 38 to 41, the rubber chip is attracted to the lower surface in the step (c) mainly by physical adsorption.

  43. In the method for manufacturing a semiconductor integrated circuit device according to any one of the items 38 to 42, vacuum suction is turned off in the steps (c) to (d).

44. A method of manufacturing a semiconductor integrated circuit device including the following steps:
(A) supplying a plurality of chips to a chip pickup unit of a chip processing apparatus;
(B) In a state where the surface of the first chip of the plurality of chips of the chip pickup unit is vacuum-sucked to the lower surface of the rubber chip of the suction collet, the first chip is placed in the die of the chip processing apparatus.・ Transfer process to the bonding part;
(C) After the step (b), the back surface side of the first chip is mainly held in a state where the front surface of the first chip is held by physical adsorption with the lower surface of the rubber chip. And landing on the upper surface of the wiring board placed on the die bonding part of the chip processing apparatus;
(D) After the step (c), by pressing the front surface of the first chip downward with the lower surface of the rubber chip, the first chip is brought into contact with the back surface of the first chip. Fixing to the upper surface of the wiring board via an adhesive member layer between the upper surfaces of the wiring board;
(E) In a state where the surface of the second chip of the plurality of chips of the chip pickup unit is vacuum-sucked to the lower surface of the rubber chip of the suction collet, the second chip is placed in the chip processing apparatus. Transferring to the die bonding part of
(F) After the step (e), the back surface side of the second chip is mainly held in a state where the front surface of the second chip is held by physical adsorption with the lower surface of the rubber chip. And landing on the upper surface of the wiring board placed on the die bonding portion of the chip processing apparatus;
(G) After the step (f), by pressing the surface of the second chip downward with the lower surface of the rubber chip, the second chip is brought into contact with the back surface of the first chip. Fixing to the upper surface of the wiring board via the adhesive member layer between the upper surfaces of the wiring board;
(H) After the step (g), the surface side of the first and second chips is collectively pressed by a member different from the collet, thereby proceeding with thermocompression bonding with the upper surface of the wiring board. Process.

  45. 44. In the method of manufacturing a semiconductor integrated circuit device according to the item 44, the rubber chip has a vacuum suction hole in the central portion and has an elastomer as a main component and has a hardness of 10 or more and less than 70.

  46. 46. In the method for manufacturing a semiconductor integrated circuit device according to the item 44 or 45, the adhesive member layer is a DAF member layer.

47. 47. The method for manufacturing a semiconductor integrated circuit device according to any one of 44 to 46, further comprising the following steps:
(E) A step of irradiating UV light from the adhesive tape side of the plurality of chips whose back surfaces are fixed to the adhesive tape before the step (b).

  48. 48. In the method for manufacturing a semiconductor integrated circuit device according to any one of the items 44 to 47, adsorption of the rubber chip to the lower surface in the steps (c) and (f) is mainly based on physical adsorption.

  49. 49. In the method for manufacturing a semiconductor integrated circuit device according to any one of 44 to 48, vacuum suction is turned off in steps (c) to (d) and (f) to (g).

  50. 49. In the method for manufacturing a semiconductor integrated circuit device according to any one of 44 and 46 to 49, the rubber chip has an elastomer as a main component and has a hardness of 10 or more and less than 70.

  Next, an outline of another embodiment of the invention disclosed in the present application will be described.

51. A method of manufacturing a semiconductor integrated circuit device including the following steps:
(A) A step of supplying a plurality of chips divided into individual chip regions to a chip processing apparatus with their back surfaces fixed to an adhesive tape while maintaining the two-dimensional arrangement of the original wafer.
(B) The surface of the first chip of the plurality of chips is vacuum-sucked to the lower surface of the rubber chip of the suction collet, and the adhesive tape on the back surface of the first chip is vacuumed to the upper surface of the lower substrate. A step of peeling the adhesive tape from the back surface of the first chip in the adsorbed state;
Here, the step (b) includes the following substeps:
(B1) monitoring the curved state of the first chip before the first chip is completely peeled from the adhesive tape by measuring the flow rate of the vacuum adsorption system of the adsorption collet;
Further, here, the rubber chip has an elastomer as a main component and has a hardness of 10 or more and less than 70.

52. 52. In the method for manufacturing a semiconductor integrated circuit device according to the item 51, the step (b) further includes the following substeps:
(B2) A step of continuing or interrupting the peeling operation based on the monitor information of the substep (b1);
(B3) A step of restarting the peeling operation based on the monitor information of the sub-step (b1) when the peeling operation is interrupted.

53. 52. In the method for manufacturing a semiconductor integrated circuit device according to the item 51 or 52, the step (b) further includes the following substeps:
(B4) A step of continuing or decelerating the peeling operation based on the monitor information of the substep (b1);
(B5) A step of accelerating the peeling operation again based on the monitor information of the substep (b1) when the peeling operation is decelerated.

54. 54. In the method for manufacturing a semiconductor integrated circuit device according to any one of the items 51 to 53, the step (b) further includes the following substeps:
(B6) A step of continuing the peeling operation based on the monitor information of the sub-step (b1) or retracting the peeling operation until the curved state of the first chip is within an allowable range.

55. 55. In the method for manufacturing a semiconductor integrated circuit device according to any one of the items 51 to 54, the step (b) further includes the following substeps:
(B7) A step of continuing the peeling operation or decelerating the peeling operation until the bending state of the first chip is within an allowable range based on the monitor information of the substep (b1).

56. 56. In the method for manufacturing a semiconductor integrated circuit device according to any one of the items 51 to 55, the step (b) further includes the following substeps:
(B8) raising the suction collet until the curved state of the first tip exceeds an allowable range;
(B9) After the sub-step (b8), based on the monitor information of the sub-step (b1), the suction collet continues to rise, or the suction collet is in the bent state of the first chip. Lowering until it falls within the allowable range.

57. 57. In the method for manufacturing a semiconductor integrated circuit device according to any one of 51 to 56, the step (b) further includes the following substeps:
(B10) raising the suction collet until the curved state of the first tip exceeds an allowable range;
(B11) After the sub-step (b10), based on the monitor information of the sub-step (b1), the suction collet continues to rise, or the suction collet is in the bent state of the first chip. Waiting until it falls within the allowable range.

58. 58. In the method of manufacturing a semiconductor integrated circuit device according to any one of 51 to 57, the step (b) further includes the following substeps:
(B12) raising the suction collet until the curved state of the first tip exceeds an allowable range;
(B13) After the sub-process (b12), based on the monitor information of the sub-process (b1), the suction collet continues to rise, or the suction collet has the curved state of the first chip. Decelerating until it falls within the allowable range;

59. 59. In the method for manufacturing a semiconductor integrated circuit device according to any one of the items 51 to 58, the step (b) further includes the following substeps:
(B14) a step of raising the push-up block constituting the main part of the lower base together with the adsorption collet;
(B15) After the step (b14), of the push-up block and the suction collet, only the push-up block is lowered until the curved state of the first tip exceeds an allowable range;
(B16) After the lower step (b15), based on the monitor information of the lower step (b1), the lowering of the push-up block is continued, or the push-up block is changed to the curved state of the first chip. The step of raising until it falls within the allowable range.

60. 60. In the method for manufacturing a semiconductor integrated circuit device according to any one of the items 51 to 59, the step (b) further includes the following substeps:
(B17) a step of raising the push-up block constituting the main part of the lower base together with the adsorption collet;
(B18) After the step (b17), of the push-up block and the suction collet, only the push-up block is lowered until the curved state of the first tip exceeds an allowable range;
(B19) After the lower step (b18), based on the monitor information of the lower step (b1), the lowering of the push-up block is continued, or the push-up block is changed to the curved state of the first chip. Waiting until it falls within the allowable range.

61. 60. In the method for manufacturing a semiconductor integrated circuit device according to any one of the items 51 to 60, the step (b) further includes the following substeps:
(B20) a step of raising the push-up block constituting the main part of the lower base together with the adsorption collet;
(B21) After the step (b20), of the push-up block and the suction collet, only the push-up block is lowered until the curved state of the first tip exceeds an allowable range;
(B22) After the sub-step (b21), based on the monitor information of the sub-step (b1), the descent of the push-up block is continued or the descent of the push-up block is changed to the curvature of the first chip. Decelerating until the state falls within the allowable range;

62. 62. In the method for manufacturing a semiconductor integrated circuit device according to any one of 61 to 61, the step (b) further includes the following substeps:
(B23) sliding the slide plate forming the main part of the lower base so that the overlap with the first chip is reduced until the curved state of the first chip exceeds an allowable range;
(B24) A step of causing the slide plate to wait until the curved state of the first chip falls within the allowable range based on the monitor information in the substep (b1).

63. In the method for manufacturing a semiconductor integrated circuit device according to any one of the items 61 to 62, the step (b) further includes the following substeps:
(B25) A step of continuing or interrupting the peeling operation based on the monitor information of the substep (b1);
(B26) In the case where the peeling operation is interrupted, the peeling operation is restarted based on the monitor information of the sub-step (b1), or the curved state of the first chip is within the allowable range. Retreating the peeling operation until

64. 64. In the method for manufacturing a semiconductor integrated circuit device according to any one of the items 61 to 63, the step (b) further includes the following substeps:
(B27) A step of continuing or decelerating the peeling operation based on the monitor information of the substep (b1);
(B28) In the case where the peeling operation is decelerated, the peeling operation is reaccelerated based on the monitor information of the substep (b1), or the curved state of the first chip is within an allowable range. Retreating the peeling operation until

65. In the method for manufacturing a semiconductor integrated circuit device according to any one of the items 61 to 64, the step (b) further includes the following substeps:
(B29) raising the suction collet until the curved state of the first tip exceeds an allowable range;
(B30) After the sub-step (b29), based on the monitor information of the sub-step (b1), the suction collet continues to rise, or the suction collet is in the bent state of the first chip. Waiting until it is within the tolerance range;
(B31) In the case where the suction collet is made to wait until the curved state of the first chip is within the allowable range, the suction collet is raised based on the monitor information of the substep (b1). Resuming or lowering the suction collet until the curved state of the first tip is within the allowable range.

66. 68. In the method for manufacturing a semiconductor integrated circuit device according to any one of the items 61 to 65, the step (b) further includes the following substeps:
(B32) a step of raising the push-up block constituting the main part of the lower base together with the adsorption collet;
(B33) After the step (b32), of the push-up block and the suction collet, only the push-up block is lowered until the curved state of the first tip exceeds an allowable range;
(B34) After the lower step (b33), based on the monitor information of the lower step (b1), the lowering of the push-up block is continued, or the push-up block is changed to the curved state of the first chip. Waiting until it is within the tolerance range;
(B35) When the push-up block is on standby until the curved state of the first tip is within the allowable range, the push-up block is lowered based on the monitor information in the sub-step (b1). Resuming or raising the push-up block until the curved state of the first tip is within the tolerance.

67. In the method for manufacturing a semiconductor integrated circuit device according to any one of the items 61 to 66, the step (b) further includes the following substeps:
(B36) raising the suction collet until the curved state of the first tip exceeds an allowable range;
(B37) After the sub-process (b36), based on the monitor information of the sub-process (b1), the suction collet continues to rise, or the suction collet is in the bent state of the first chip. Decelerating until it is within the allowable range;
(B38) In the case where the suction collet is decelerated until the curved state of the first chip falls within the allowable range, the suction collet is increased based on the monitor information in the sub-step (b1). Resuming or lowering the suction collet until the curved state of the first tip is within the allowable range.

68. 68. In the method for manufacturing a semiconductor integrated circuit device according to any one of the items 61 to 67, the step (b) further includes the following substeps:
(B39) a step of raising the push-up block constituting the main part of the lower base together with the adsorption collet;
(B40) After the step (b39), the step of lowering only the push-up block out of the push-up block and the suction collet until the curved state of the first tip exceeds an allowable range;
(B41) After the lower step (b40), based on the monitor information of the lower step (b1), the descent of the push-up block is continued or the descent of the push-up block is changed to the curvature of the first tip. Decelerating until the condition is within the tolerance range;
(B42) In the case where the push-up block is kept waiting until the curved state of the first tip is within the allowable range, the push-up block is lowered based on the monitor information of the substep (b1). Resuming or raising the push-up block until the curved state of the first tip is within the tolerance.

  69. 69. In the method for manufacturing a semiconductor integrated circuit device according to any one of 61 to 68, a die bonding adhesive layer is formed in advance on the back surface of the first chip.

  70. 70. In the method for manufacturing a semiconductor integrated circuit device according to any one of Items 51 to 69, the elastomer has a hardness of 15 or more and less than 55.

  71. 70. In the method for manufacturing a semiconductor integrated circuit device according to any one of the items 51 to 69, the hardness of the elastomer is 20 or more and less than 40.

[Description format, basic terms, usage in this application]
1. In the present application, the description of the embodiment may be divided into a plurality of parts for convenience, if necessary, but these are not independent from each other unless otherwise specified. Regardless of the description before and after the description, each part of a single example, one part is the other part of the details, or part or all of the modified examples. Moreover, as a general rule, the same part is not repeated. In addition, each component in the embodiment is not indispensable unless specifically stated otherwise, unless it is theoretically limited to the number, and obviously not in context.

  2. Similarly, in the description of the embodiment, etc., regarding the material, composition, etc., “X consisting of A” etc. is an element other than A unless specifically stated otherwise and clearly not in context. It is not excluded that one of the main components. For example, as for the component, it means “X containing A as a main component”. For example, “silicon member” is not limited to pure silicon, but also includes SiGe alloys, other multi-component alloys containing silicon as a main component, and members containing other additives. Needless to say.

  3. Similarly, suitable examples of graphics, positions, attributes, and the like are given, but it is needless to say that the present invention is not strictly limited to those cases unless explicitly stated otherwise, and unless otherwise apparent from the context.

  4). In addition, when a specific number or quantity is mentioned, a numerical value exceeding that specific number will be used unless specifically stated otherwise, unless theoretically limited to that number, or unless otherwise clearly indicated by the context. There may be a numerical value less than the specific numerical value.

  5). “Wafer” usually refers to a single crystal silicon wafer on which a semiconductor integrated circuit device (same as a semiconductor device or an electronic device) is formed, but also an epitaxial wafer, a composite wafer such as an insulating substrate and a semiconductor layer, etc. Needless to say.

  6). The term “chip” or “die” generally refers to a completely separated wafer separation process (blade dicing, laser dicing or other pelletizing process), but in this application, the chip area before separation is the same for convenience. Shown in terms. For example, in the so-called DBG (Dicing before Grinding) process, after half-cut dicing, it is ground and finally separated into chips. move on. Including such cases, for example, if the “wafer” is separated, it is not strictly a wafer, but before the chips are separated, it is a chip area and not a chip. Therefore, regardless of before and after separation, these are collectively referred to as “wafer”, “chip” or “die”.

  7). The term “wiring board” generally refers to an organic wiring board, ceramic wiring board, lead frame, etc., other chips, wafers, and other thin film integrated circuit devices. That is, in recent years, a lamination technique of laminating several tens of chips on a chip with an adhesive has been widely used, and the invention disclosed in this application is applied to a wide range including them.

  8). The “lower substrate” is generally called an “adsorption piece”, but forms the center of the chip peeling mechanism of the “chip processing apparatus” and is fixed to the adhesive sheet (almost in the two-dimensional arrangement of the original wafer). The chip group fixed to the adhesive sheet is fixed in position by vacuum-adsorbing the adhesive sheet. Further, the central portion is a “push-up block” in a certain device, and a “slide plate” in another device. The “lower substrate” is composed of the central portion and the peripheral portion, and the peripheral portion functions to suck and fix the chip and the adhesive tape around the pickup target chip. Both the central part and the peripheral part are structured to be sucked by vacuum through suction holes and gaps, and are almost always sucked except for the alignment.

  9. The “adsorption collet” has conventionally been composed of a single piece of metal (stainless steel, etc.), ceramic, polymer, etc., but the thin film wafer or thin film chip (mainly having a thickness of 150 micrometers or less, mainly handled by the present application) 100 μm or less), a rubber chip mainly composed of a polymer such as an elastomer that directly touches the chip and a suction collet body or a rubber chip holder for holding the chip so that the chip does not crack. It is made up of. The rubber chip generally includes a thermosetting elastomer such as fluoro rubber, nitrile rubber, and silicone rubber, or an elastic polymer material such as thermoplastic elastomer as a main component. In the specific explanation, the vertical movement of the collet and push-up block is advanced with respect to the lower substrate periphery (assuming that it does not move), but in principle this is a relative movement. it is conceivable that.

  10. The hardness of the rubber chip is displayed in accordance with International Standards Organization ISO Standard 7619 Durometer Type A (US Standard Shore A; JIS K 6253).

[Details of the embodiment]
The embodiment will be further described in detail. In the drawings, the same or similar parts are denoted by the same or similar symbols or reference numerals, and description thereof will not be repeated in principle.

  The technique for controlling the peeling operation by monitoring the flow rate of the collet vacuum system is described in detail in Japanese Patent Application No. 2007-160922 (filing date: 2007.7.619) of the present inventors. Yes.

(Embodiment 1)
1. Overall process / equipment explanation (mainly Figures 1 to 30)
The present embodiment is applied to the manufacture of a semiconductor package in which a chip is mounted on a wiring board, and the manufacturing method will be described in the order of steps with reference to FIGS.

  In addition, as a typical prior application in the related technical field by the inventors of the present application, Japanese Patent Application No. 2006-143277 (filing date: May 23, 2006) and corresponding US application No. 11/735411 (application) Sun: April 12, 2007).

  First, after an integrated circuit is formed on a main surface of a wafer 1A made of single crystal silicon as shown in FIG. 1 according to a known manufacturing process, each of a plurality of chip formation regions 1A ′ partitioned by grid-like scribe lines is provided. An electrical test is performed on the formed integrated circuit to determine whether it is acceptable. The chip formation region 1A 'of the wafer 1A used in the present embodiment has a square planar shape having the same vertical and horizontal lengths. In the present embodiment, a square chip will be described as an example for convenience of drawing, but it goes without saying that a more general rectangular chip can be processed in exactly the same way. In the case of a rectangle, a block, collet, or other planar shape shown in FIG. 33 or FIG. 36 is more suitable.

Next, as shown in FIG. 2, a back grind tape 3 for protecting the integrated circuit is attached to the integrated circuit forming surface (the lower surface side in the drawing) of the wafer 1A. Then, in this state, the back surface (upper surface side in the figure) of the wafer 1A is ground with a grinder, and subsequently, the damaged layer on the back surface caused by this grinding is removed by a method such as wet etching, dry polishing, plasma etching or the like. Accordingly, the thickness of the wafer 1A is reduced to 100 μm or less, for example, about 90 μm to 15 μm. The processing methods such as wet etching, dry polishing, and plasma etching are slower in processing speed in the wafer thickness direction than grinding speed by the grinder, but the damage to the wafer is compared with grinding by the grinder. In addition, the damage layer inside the wafer generated by grinding by the grinder can be removed, and there is an effect that the wafer 1A and the chip are hardly broken.

  Next, after the back grind tape 3 is removed, as shown in FIG. 3, the dicing tape 4 is attached to the back surface (the surface opposite to the integrated circuit forming surface) of the wafer 1A. The part is fixed to the wafer ring 5. The dicing tape 4 is a pressure-sensitive type in which a pressure-sensitive adhesive is applied to the surface of a tape base material made of polyolefin (PO), polyvinyl chloride (PVC), polyethylene terephthalate (PET), etc. to provide tackiness. An adhesive tape or UV curable adhesive tape is cut into a circle.

  Next, as shown in FIG. 4, the wafer 1 </ b> A is diced using a known dicing blade 6 to divide each of the plurality of chip formation regions 1 </ b> A ′ into square chips 1. At this time, since each divided chip 1 needs to be left on the circular dicing tape 4, the dicing tape 4 is cut by about half of the thickness direction. When a UV curable adhesive tape is used as the dicing tape 4, the dicing tape 4 is irradiated with ultraviolet rays prior to the chip 1 peeling step described below to reduce the pressure-sensitive adhesive's adhesive strength. .

  Next, as shown in FIG. 5 (plan view) and FIG. 6 (cross-sectional view), the pressing plate 7 is disposed above the dicing tape 4 fixed to the wafer ring 5, and the expanding ring 8 is disposed below. Then, as shown in FIG. 7, by pressing the pressing plate 7 against the upper surface of the wafer ring 5, the peripheral portion on the back surface of the dicing tape 4 is pressed against the expanding ring 8. If it does in this way, since the dicing tape 4 receives the strong tension | tensile_strength which goes to the periphery from the center part, it will be extended without slack in the horizontal direction.

  Next, in this state, the expand ring 8 is positioned on the stage 101 of the chip peeling apparatus 100 shown in FIG. 8 and held horizontally. At the center of the stage 101, a suction piece 102 that is moved in the horizontal and vertical directions by a drive mechanism (not shown) is disposed. The dicing tape 4 is held such that the back surface thereof faces the upper surface of the suction piece 102.

  9 is a cross-sectional view of the suction piece 102, FIG. 10 is an enlarged cross-sectional view of the vicinity of the upper surface of the suction piece 102, and FIG. 11 is an enlarged perspective view of the vicinity of the upper surface of the suction piece 102.

  There may be a case where a plurality of suction ports 103 and a plurality of concentric grooves 104 are provided around the upper surface of the suction piece 102 or only a plurality of suction holes. The inside of each of the suction port 103 and the groove 104 is decompressed by a suction mechanism (not shown) when the suction piece 102 is raised and its upper surface is brought into contact with the back surface of the dicing tape 4. At this time, the back surface of the dicing tape 4 is sucked downward and comes into close contact with the upper surface of the suction piece 102.

  When the dicing tape 4 is sucked downward, if the width or depth of the groove 104 is large, the dicing tape 4 below the chip 1 adjacent to the chip 1 to be peeled is sucked into the groove 104. The interface between the adjacent chip 1 and the dicing tape 4 below the chip 1 may peel off in the upper region of the groove 104. In particular, in the dicing tape 4 using a pressure sensitive adhesive having a relatively weak adhesive force, such peeling is likely to occur. If such a phenomenon occurs, the adjacent chip 1 may fall off from the dicing tape 4 during the operation of peeling the chip 1 to be peeled from the dicing tape 4, which is not preferable. Therefore, in order to prevent such a phenomenon from occurring, the width and depth of the groove 104 are made as small as possible, and a gap as much as possible is provided between the dicing tape 4 below the adjacent chip 1 and the upper surface of the suction piece 102. It is effective to prevent the occurrence of the problem, and it is also effective to increase the suction holes and not provide the grooves.

  Three blocks 110 a to 110 c that push up the dicing tape 4 upward are incorporated in the central portion of the suction piece 102. In the three blocks 110a to 110c, the second block 110b having a smaller outer shape is arranged inside the first block 110a having the largest outer shape, and the third block 110c having the smallest outer shape is further arranged inside thereof. Is arranged. As will be described later, the three blocks 110a to 110c include a first compression coil spring 111a interposed between the outer block 110a and the intermediate block 110b, and the intermediate block 110b and the inner block 110c. It is connected to the second compression coil spring 111b having a larger spring constant than the first compression coil spring 111a and the inner block 110c, and moves up and down in conjunction with a pusher 112 that moves up and down by a drive mechanism (not shown). It is like that.

  Of the three blocks 110a to 110c, the outer block 110a having the largest outer shape may be one having a smaller outer shape than the chip 1 to be peeled (for example, about 0.5 mm to 3 mm). . For example, when the chip 1 is a square, it is desirable to make it a square that is slightly smaller than that. Further, as will be described in other embodiments described later, when the chip 1 is rectangular, it is desirable to make it a rectangle slightly smaller than that. As a result, the corner portion that is the outer periphery of the upper surface of the block 110a is positioned slightly inward of the outer edge of the chip 1, so that a location that is a starting point when the chip 1 and the dicing tape 4 are separated (chip 1) Can be concentrated on the outermost peripheral portion).

  Further, the upper surface of the block 110a is preferably a flat surface or a surface having a large local radius in order to secure a contact area with the dicing tape 4. When the contact area between the upper surface of the block 110a and the dicing tape 4 is small, a large bending stress is concentrated on the peripheral portion of the chip 1 supported from below by the upper surface of the block 110a, so that the peripheral portion of the chip 1 may be broken. .

  The intermediate block 110b arranged inside the block 110a has an outer shape smaller by about 1 mm to 3 mm than the block 110a. The block 110c having the smallest outer shape disposed further inside than the block 110b has an outer shape that is smaller by about 1 mm to 3 mm than the intermediate block 110b. In the present embodiment, the shape of each of the intermediate block 110b and the inner block 110c is formed in a columnar shape in consideration of the ease of processing and the like. Also good. The heights of the upper surfaces of the three blocks 110a to 110c are equal to each other in the initial state (when the blocks 110a to 110c are not in operation), and are also equal to the height of the upper peripheral portion of the suction piece 102.

  As shown in FIG. 10 in an enlarged manner, gaps (S) are provided between the periphery of the suction piece 102 and the outer block 110a and between the three blocks 110a to 110c. The inside of these gaps (S) is decompressed by a suction mechanism (not shown). When the back surface of the dicing tape 4 comes into contact with the upper surface of the suction piece 102, the dicing tape 4 is sucked downward and the block 110a. It adheres to the upper surface of ~ 110c.

In order to peel the chip 1 from the dicing tape 4 using the chip peeling device 100 having the suction piece 102 as described above, first, as shown in FIG. The center part (blocks 110 a to 110 c) of the suction piece 102 is moved directly below the chip 1) located at the center of the figure, and the suction collet 105 is moved above the chip 1. At the center of the bottom surface of the suction collet 105 supported by a moving mechanism (not shown), a suction port 106 whose inside is depressurized is provided, and selectively sucks only one chip 1 to be peeled off. It can be held. In FIG. 12 to FIG. 31, the detailed structure of the collet 105 is omitted for the sake of simplicity. This detailed structure will be described in detail after FIG.

Next, as shown in FIG. 13, the suction piece 102 is raised and its upper surface is brought into contact with the back surface of the dicing tape 4, and the inside of the suction port 103, the groove 104 and the gap (S) described above is decompressed. As a result, the dicing tape 4 in contact with the chip 1 to be peeled adheres to the upper surfaces of the blocks 110a to 110c. Further, the dicing tape 4 that is in contact with another chip 1 adjacent to the chip 1 is in close contact with the periphery of the upper surface of the suction piece 102. At this time, if the suction piece 102 is pushed up slightly (for example, about 400 μm), further tension is applied to the dicing tape 4 to which the horizontal tension is applied by the pressing plate 7 and the expanding ring 8 described above. Therefore, the suction piece 102 and the dicing tape 4 can be more closely attached.

  Further, the suction collet 105 is lowered almost simultaneously with the raising of the suction piece 102, the bottom surface of the suction collet 105 is brought into contact with the upper surface of the chip 1 to be peeled, and the chip 1 is sucked, and the chip 1 is lightly pressed downward. wear. As described above, when the chip 1 is sucked upward using the suction collet 105 when the dicing tape 4 is sucked downward using the suction piece 102, the dicing tape 4 and the chip 1 are peeled off by pushing up the blocks 110a to 110c. Can be promoted.

  Next, as shown in FIG. 14, the three blocks 110 a to 110 c are pushed upward simultaneously to apply an upward load to the back surface of the dicing tape 4, and the chip 1 and the dicing tape 4 are pushed up. At this time, the back surface of the chip 1 is supported by the upper surfaces (contact surfaces) of the blocks 110a to 110c via the dicing tape 4 to reduce bending stress applied to the chip 1, and the outer periphery (corner portion) of the upper surface of the block 110a. ) Is arranged on the inner side of the outer periphery of the chip 1, the stress that peels off is concentrated on the interface where the chip 1 and the dicing tape 4 are peeled off, and the peripheral portion of the chip 1 is efficiently removed from the dicing tape 4. Peel off. At this time, the dicing tape 4 below the other chip 1 adjacent to the chip 1 to be peeled is sucked downward and brought into close contact with the periphery of the upper surface of the suction piece 102 so that the peripheral edge of the chip 1 The peeling of the dicing tape 4 can be promoted. FIG. 15 is an enlarged perspective view showing the vicinity of the upper surface of the suction piece 102 at this time (illustration of the chip 1 and the dicing tape 4 is omitted).

  The push-up amount (stroke) of the blocks 110a to 110c is, for example, about 0.2 mm to 0.4 mm, but it is desirable to increase or decrease according to the size of the chip 1. That is, when the size of the chip 1 is large, the contact area between the chip 1 and the dicing tape 4 is large, and hence the adhesive force between the two is also large, so it is necessary to increase the push-up amount. On the other hand, when the size of the chip 1 is small, the contact area between the chip 1 and the dicing tape 4 is small, and therefore the adhesive force between the two is also small, so that even if the push-up amount is small, the chip 1 is easily peeled off. Note that the pressure-sensitive adhesive applied to the dicing tape 4 has a difference in adhesive strength depending on the manufacturer and product type. Therefore, even when the sizes of the chips 1 are the same, it is necessary to increase the push-up amount when a pressure-sensitive adhesive having a large adhesive force is used.

  When the blocks 110a to 110c are pushed upward to apply a load to the back surface of the chip 1, bending stress in a direction perpendicular to the outer periphery of the chip is applied to the outermost peripheral portion of the chip 1 in a direction parallel to the outer periphery of the chip. It is desirable to make it smaller than the bending stress. At the outermost peripheral portion of the chip 1, fine cracks generated when the wafer 1A is diced using the dicing blade 6 described above remain. Therefore, if a strong bending stress is applied to the outermost peripheral portion of the chip 1 along the direction orthogonal to the outer periphery of the chip 1 when the blocks 110a to 110c are pushed upward, there is a risk that the chip 1 may break due to the growth of cracks. is there. In the present embodiment, a uniform load is applied slightly inward from the outermost peripheral portion of the chip 1 using the block 110a having an upper surface that is slightly smaller than the size of the chip 1, thus avoiding the above-described problems. The entire periphery of the chip 1 can be evenly peeled from the dicing tape 4.

In order to push up the three blocks 110a to 110c at the same time, as shown in FIG. 16, the pusher 112 is pushed up to push up the inner block 110c connected to the pusher 112. Thereby, the intermediate block 110b is pushed up by the spring force of the compression coil spring 111b interposed between the inner block 110c and the intermediate block 110b, and further the compression interposed between the outer block 110a and the intermediate block 110b. Since the outer block 110a is pushed up by the spring force of the coil spring 111a, the three blocks 110a to 110c are pushed up simultaneously. And when a part (surface shown by the arrow of a figure) of the outside block 110a contacts the peripheral part of the adsorption | suction piece 102, the raise of blocks 110a-110c stops. At this time, most of the region of the chip 1 to be peeled is supported by the upper surfaces of the three blocks 110a to 110c, and in the region outside the outer periphery (corner) of the upper surface of the block 110a, the chip Separation at the interface between 1 and the dicing tape 4 proceeds efficiently.

  When the three blocks 110a to 110c are pushed upward simultaneously, the pusher 112 pushes up the block 110c with such a weak force that the compression coil spring 111a having a weak spring force does not contract. In this way, the intermediate block 110b and the inner block 110c do not protrude further upward until a part of the outer block 110a comes into contact with the peripheral portion of the suction piece 102.

  Further, the compression coil spring 111 a needs to have a spring force that can lift the block 110 a against at least the tension of the dicing tape 4. When the spring force of the compression coil spring 111a is smaller than the tension of the dicing tape 4, the outer block 110a does not lift up even if the pusher 112 is pushed up, and the chip 1 cannot be supported by the upper surface of the outer block 110a. In this case, since sufficient stress cannot be concentrated on the starting point of separation between the chip 1 and the dicing tape 4, the chip 1 is cracked due to a decrease in peeling speed or excessive bending stress applied to the chip 1. May cause problems.

  Next, as shown in FIG. 17, the middle block 110 b and the inner block 110 c are pushed upward simultaneously to push up the dicing tape 4. As a result, the position of the outer periphery (corner portion) of the upper surface of the block 110b that supports the chip 1 moves further inward compared to the state where it is supported by the block 110a, so that the chip 1 and the dicing tape 4 are peeled off. It progresses from the area outside the outer periphery of the upper surface of the block 110b toward the center of the chip 1. FIG. 18 is an enlarged perspective view showing the vicinity of the upper surface of the suction piece 102 at this time (illustration of the chip 1 and the dicing tape 4 is omitted).

  In order to push the two blocks 110b and 110c upward simultaneously, as shown in FIG. 19, the pusher 112 is pushed up to further push up the block 110c connected to the pusher 112. At this time, since the intermediate block 110b is pushed up by the spring force of the compression coil spring 111b, the two blocks 110b and 110c are pushed up simultaneously. Then, when a part of the intermediate block 110b (the surface indicated by the arrow in the drawing) comes into contact with the outer block 110a, the ascent of the blocks 110b and 110c stops. The force by which the pusher 112 pushes up the block 110c is such that the compression coil spring 111a having a weak spring force contracts but the compression coil spring 111b having a strong spring force does not contract. Accordingly, the inner block 110c does not protrude further upward until a part of the intermediate block 110b comes into contact with the outer block 110a.

  When the two blocks 110b and 110c are pushed upward, in order to promote the peeling between the chip 1 and the dicing tape 4, the inside of the gap (S) between the blocks 110a to 110c is decompressed to The contacting dicing tape 4 is sucked downward. Further, the inside of the groove 104 is decompressed, and the dicing tape 4 in contact with the periphery of the upper surface of the suction piece 102 is brought into close contact with the upper surface of the suction piece 102 (FIG. 17).

  Next, as shown in FIG. 20, the inner block 110c is further pushed upward to push up the back surface of the dicing tape 4, and the back surface of the chip 1 is supported by the top surface of the block 110c. FIG. 21 is an enlarged perspective view showing the vicinity of the upper surface of the suction piece 102 at this time (illustration of the chip 1 and the dicing tape 4 is omitted). In order to push up the inner block 110c upward, as shown in FIG. 22, the block 110c is pushed up with such a strong force that the compression coil spring 111b contracts. Thereby, in the area | region outside the outer periphery (corner | corner part) of the upper surface of the block 110c which is contacting the dicing tape 4, peeling with the chip | tip 1 and the dicing tape 4 advances.

  Subsequently, as shown in FIG. 23, the block 110c is pulled down and the suction collet 105 is pulled up, whereby the work of peeling the chip 1 from the dicing tape 4 is completed.

  It is necessary to reduce the area of the upper surface of the block 110c to such an extent that the chip 1 is peeled from the dicing tape 4 only by the suction force of the suction collet 105 when the block 110c is pushed upward. When the area of the upper surface of the block 110c is large, the contact area between the chip 1 and the dicing tape 4 is increased, and the adhesive force between the two is also increased. Can not be peeled from.

  On the other hand, when the area of the upper surface of the block 110c is reduced, when the block 110c pushes up the back surface of the dicing tape 4, a strong load is intensively applied to the narrow region (center portion) of the chip 1; The chip 1 may break. Therefore, when pushing up the block 110c, the pushing speed is reduced, the time during which the upper surface of the block 110c is in contact with the dicing tape 4 is shortened, or the pushing amount (stroke) of the block 110c is reduced (for example, 0.2 mm). It is desirable to prevent a strong load from being applied to the narrow region of the chip 1.

  Further, as one method for increasing the suction force of the suction collet 105, it is effective to slow the pulling-up speed of the suction collet 105. If the suction collet 105 is rapidly pulled up while a part of the chip 1 is in close contact with the dicing tape 4, a gap is formed between the bottom surface of the suction collet 105 and the top surface of the chip 1, and the degree of vacuum inside the suction collet 105 decreases. Therefore, the force for sucking the chip 1 is reduced. On the other hand, when the pulling speed of the suction collet 105 is decreased, the time required for peeling the chip 1 from the dicing tape 4 becomes longer. Therefore, the pulling speed of the suction collet 105 is made variable, and when pulling is started, the pulling speed is slowed to secure a sufficient suction force. It is better to prevent time delays. It is also an effective method for increasing the suction force of the suction collet 105 to make the area of the bottom surface of the suction collet 105 larger than the area of the upper surface of the block 110c.

  In this way, by increasing the suction force of the suction collet 105, even if the contact area between the chip 1 and the dicing tape 4 is relatively large, the chip 1 is attached to the dicing tape 4 only by the suction force of the suction collet 105. Therefore, the peeling time can be shortened, and the above-described problem that occurs when the area of the upper surface of the block 110c is reduced can be avoided.

  Further, if the block 110c is pulled downward while the chip 1 is pressed down by the suction collet 105, the suction collet 105 also moves downward, so that the chip 1 may hit the block 110c and break. Therefore, when lowering the block 110c downward, it is desirable to pull up the suction collet 105 immediately before that, or at least fix the position so that the suction collet 105 does not move downward.

  Thus, the chip 1 peeled off from the dicing tape 4 is sucked and held by the suction collet 105 and conveyed to the next process (pellet attaching process) (generally from the pickup stage of the same apparatus to the die bonding stage 132 or Conveyed to the die bonding unit 300). When the suction collet 105 that has transported the chip 1 to the next process returns to the chip peeling device 100 (chip peeling unit), the next chip 1 is removed from the dicing tape 4 according to the procedure shown in FIGS. It is peeled off. Thereafter, the chips 1 are peeled off from the dicing tape 4 one by one according to the same procedure.

  Next, the pelletizing process (die bonding process) will be described. As shown in FIG. 24, the chip 1 conveyed to the pelletizing process is bonded to the adhesive or the adhesive member layer 10 (usually before the wafer is divided into chips, for example, when dicing tape is applied or before, on the back surface of the wafer. A DAF, that is, a die-bonding double-sided pressure-sensitive adhesive sheet or a die-bonding adhesive layer called “die-attach film” is attached, or a liquid adhesive is applied or dropped onto a wiring board immediately before die bonding ( (In other words, an adhesive member layer is interposed between the chip and the wiring board during die bonding.) The DAF is generally stretched so as to be sandwiched between the back surface of the wafer and the dicing tape. When picking up a chip, it is picked up with the chip. It is not necessary to form anew adhesive layer should have previously pasted to Lum during die bonding is advantageous mass production.) Via a are mounted on the wiring board 11. That is, the chip 1 peeled off from the dicing tape 4 is adsorbed by physical adsorption with the vacuum suction turned off to the adsorption collet 105, and is about 100 to 150 degrees Celsius (the glass transition temperature of the organic wiring board is generally 240 degrees Celsius). Therefore, the substrate heating temperature can be about 100 to 200 degrees Celsius, but in order to minimize the deformation of the substrate, it is preferably about 100 to 150 degrees Celsius, at least. , It is necessary to be lower than the glass transition temperature of the substrate) and is lowered toward the wiring substrate 11 on the die bonding stage 132 heated.

  As shown in FIG. 25, when it is confirmed that the chip 1 has landed on the wiring board 11, the collet 105 presses the chip 1 with a predetermined pressure and keeps vacuum suction off for a predetermined time (for example, 1 Stay in that position (seconds to seconds). During this time, thermocompression bonding proceeds.

  Thereafter, as shown in FIG. 26, the collet 105 is retracted from the chip 1 while the vacuum suction is turned off.

  The chip 1 that has been subjected to the thermocompression bonding is electrically connected to the electrode 13 of the wiring board 11 via the Au wire 12 as shown in FIG. By doing so, since the landing is performed in a state where the vacuum suction is turned off, even if the thin film chip is bent at the time of peeling and adsorption, the bending is released at the time of landing. No bending or undesired stress remains.

  Next, as shown in FIG. 28, the second chip 14 is laminated on the chip 1 mounted on the wiring substrate 11 via an adhesive 10 or the like, and the electrodes of the wiring substrate 11 are connected via Au wires 15. 16 is electrically connected. The second chip 14 is a silicon chip on which an integrated circuit different from the chip 1 is formed. After being peeled off from the dicing tape 4 by the method described above, the second chip 14 is transported to the pelletizing process and stacked on the chip 1. .

  Thereafter, the wiring substrate 11 is transferred to a molding process, and the chips 1 and 14 are sealed with a molding resin 17 as shown in FIG.

  In this embodiment, the case where the chip 1 to be peeled is slightly larger than the outer block 110a has been described. However, for example, as shown in FIG. If it is smaller than the outer block 110a and larger than the intermediate block 110b, as shown in FIG. 30 (b), the intermediate block 110b is first pushed up to peel off the peripheral edge of the chip 1 from the dicing tape 4, and then As shown in FIG. 30 (c), the inner block 110 c can be pushed up to peel the center portion of the chip 1 from the dicing tape 4. In this case, for example, a spacer is sandwiched between the suction piece 102 and the outer block 110a so that the outer block 110a does not lift even when the pusher 112 is pushed up.

  In this embodiment, the method of peeling chips using three blocks (110a to 110c) has been described. However, the number of blocks is not limited to three, and chips to be peeled off. If the size of 1 is large, 4 or more blocks may be used. Further, when the size of the chip 1 to be peeled is very small, two blocks may be used.

2. Detailed explanation of the area around the pickup (mainly Figs. 31 to 38)
31 to 38, the peeling operation control, the detailed structure of the collet 105, and the relationship between them and the lower substrate 102 (adsorption piece) will be described.

FIG. 31 is a conceptual diagram (FIG. 31 a), a time chart (FIG. 31 b), and a cross-sectional view (FIG. 31 b) schematically showing the pickup unit and its control system. The pick-up operation starts when the target chip 1 on the dicing tape 4 is positioned on the suction piece 102 and the collet 105. When the positioning is completed, the dicing tape 4 is sucked onto the upper surface of the suction piece 102 by evacuating through the suction hole 103 and the gap S of the suction piece 102. In this state, a command of the pickup unit control system 144 causes the vacuum suction system 107 (for example, suction pressure minus 80 to 90 kilopascals, suction flow rate 7 L / min.) To be a valve 143 (this three-way valve is when vacuum suction is off, The vacuum supply source side is closed and the collet side is opened to the atmosphere), and a vacuum is supplied from the factory vacuum supply source via the vacuum supply pipe 141 so that the collet 105 faces the device surface of the chip 1. Descent while evacuating and land. Here, when the push-up block 110 which is the main part of the suction piece 102 rises, the chip 1 rises while being sandwiched between the collet 105 and the push-up block 110, but the peripheral portion of the dicing tape 4 is vacuumed to the suction piece peripheral portion 102a. Since it remains adsorbed, tension is generated around the chip 1, and as a result, the dicing tape 4 is peeled off around the chip. However, at this time, the periphery of the chip receives a stress on the lower side and is curved. As a result, a gap is formed between the lower surface of the collet and air flows into the vacuum suction system 107 of the collet 105. As a result, the suction amount output of the gas flow rate sensor 21 provided in the vacuum suction system 107 increases. Here, for example, when the raising of the push-up block 110 is stopped and the standby state is maintained by a command from the pickup unit control system 144, the dicing tape 4 is peeled off, and the curved state of the chip 1 is relaxed to be within the allowable range. Often return. FIG. 31b shows the transition of the suction amount output (digital output signal and analog output signal) of the gas flow rate sensor 21 in such a process. When the collet is lowered, a large amount of suction is shown corresponding to the open state. When landing at t ₁ , the flow rate decreases rapidly and becomes almost “0” at t ₂ . Since the push-up block some time to start increasing tension is small leak does not occur, it comes when the leak starts due to the curvature of the chip to t _3. The leak that stops the ascending of the block 110 and maintains the standby state is eliminated, and the flow rate returns to almost “0” again at t ₄ . The gas flow rate sensor 21 may be anything as long as it can measure the gas flow rate or the physical quantity corresponding thereto. Needless to say, the shape and dimensions of the rubber chip are substantially the same as the shape and dimensions of the target chip (rectangular if the chip is rectangular) from the viewpoint of preventing cracks and the like around the chip ( It does not exclude making it larger or slightly smaller). Regarding this, the push-up block is the same, and in this embodiment, an example slightly smaller than the chip is shown to promote peripheral peeling, but it is needless to say that it is not limited to this. Alternatively, it may be slightly larger.

  32 to 38, the detailed structure of the suction collet 105, particularly the lower end thereof, that is, the rubber chip 125 and its variations, and the relationship between them and the lower base 102 (suction piece) will be described. FIG. 32 a is a top view of the push-up block 110 corresponding to the description of FIGS. 1 to 30 and shows the positional relationship between the push-up block 110 and the rubber chip 125. The shape of the rubber chip 125 is almost the same as the chip to be picked up. FIG. 32b is a bottom view of the collet body 105 (or rubber chip holder). There is a vacuum suction hole 122 (for example, 4 mm in diameter) in the center, and vacuum suction grooves 121 are provided in the direction of each axis and diagonal. The rubber chip 125 is provided with vacuum suction holes 106a to 106i corresponding to the vacuum suction groove 121 and the push-up blocks 110a to 110c (for example, a diameter of 0.8 mm).

  FIG. 33 shows a variation of the rubber chip 125, and the two inner push-up blocks 110 b and 110 c have substantially the same top shape as the chip 1. By doing so, stress concentration at the corner portion of the chip can be relaxed. The structure of the rubber tip shown in FIG. 32 or 33 is very important in the peeling process. In particular, when the vacuum suction hole 106a is provided in the central portion (including the region near the center), even if the chip is bent by the tension of the adhesive tape, the holding state of the chip can be maintained by the vacuum suction hole 106a in the central portion. Assuming that the chip is 10 mm square (chip thickness 25 microns, DAF thickness 25 microns), the first block (segment) is, for example, 8.6 mm square, the second block is 6.3 mm square, and the third block is 4.0 mm. It becomes a corner.

  34 is a schematic cross-sectional view of the AA cross section of FIGS. 32 and 33 in a state where the collet 105 is landed, and FIG. 35 is a schematic cross-sectional view of the BB cross section of FIGS. 32 and 33. At this time, the lower side of the dicing tape 4 is adsorbed through a gap S between the suction hole 103 and the lower base main part 110 provided in the lower base peripheral part 102a. At this time, the upper side of the dicing tape 4 is vacuum-sucked through the vacuum suction hole 106.

  FIG. 36 shows still another variation of the rubber chip 125 that can detect leaks more finely. That is, a large number of vacuum suction holes 106a to 106w are arranged in the rubber chip 125 corresponding to each sub-block of the push-up block 110 and the innermost part of the suction piece 102a. In such an arrangement, at least one or a plurality of suction holes are provided corresponding to the individual segments (in addition to the outermost segment outside) of each push-up block, so that the accuracy of detecting the peeling state due to leakage is improved. be able to. Further, in the case of a combination with a rubber tip made of a relatively soft elastomer, the adsorption force can be distributed over the entire tip, so that no stress is concentrated locally even if the tip is curved.

  37 is a schematic cross-sectional view of the AA cross section of FIG. 36 with the collet 105 landed, and FIG. 38 is a schematic cross-sectional view of the BB cross section of FIG.

  In addition, the center hole 106a in FIGS. 31, 32, and 36 is not necessarily essential. For example, in the slide-type peeling method as shown in FIG. 46, it is not particularly important that the suction hole is at the center. In addition, when there are a large number of suction holes as shown in FIG. 36, an intermediate hole group (such as 106t) can be substituted even if it is not centered.

3. Details of each stripping process (mainly Figures 39 to 47)
The following exfoliation processes can be applied to the entire process described in Section 1 as appropriate, and can be applied singly or in combination.

3-1. Push-up block standby / retraction process ("peeling process 1", FIGS. 39 to 40)
FIG. 39 is a process flow diagram showing specific processing steps for a method of using leak detection when each of the sub-blocks 110a to 110c of the push-up block 110 is pushed up sequentially and the dicing tape 4 is peeled off. FIG. 40 is a cross-sectional flowchart of the main part. Based on these, the progress of specific steps will be described. In each of the following examples, as can be clearly described, an example is given in which each of the peeling element processes leaks first and does not leak the second time.
(1) The dicing tape 4 is vacuum-sucked on the upper surface of the lower base 102 (tape suction step 31).
(2) The collet 105 lands on the upper surface (generally, but not limited to, the device surface) of the chip 1 while vacuuming (collet landing step 32). The landed state is shown in FIG. 40a.
(3) The push-up block 110 rises all at once (first step ascending step 33). The chip 1 and the collet 105 are also pushed up accordingly. At this time, since the lower substrate peripheral portion 102a does not move, the tension for peeling off the dicing tape 4 on the outer periphery of the chip 1 works. Also, at this step, monitoring of leaks is started.
(4) The presence of a leak is detected (leak detection step 34; see FIG. 40b). If there is no leak, the process immediately proceeds to step (9). FIG. 40b shows a state when the leak 133 is detected.
(5) The ascending operation in (3) is decelerated (including stop) for a predetermined time or until there is no leak (see FIG. 40c). That is, the “standby step”. During this time, monitoring of leakage is continuously or intermittently performed. If there is no leak, the process proceeds to step (7). However, this step can be omitted when the process moves from (4) to the next step (6). This may shorten the processing time. The same applies to the following examples. In general, peeling from an adhesive tape is a rheological phenomenon, and even if it is difficult to peel off at a high speed, it often peels easily when time is applied while applying a weak tension. Therefore, stop standby and deceleration standby are often effective.
(6) Return to before step (3) starts. Alternatively, the process of (3) is reversed until there is no leak in the leak monitor. That is, the push-up block 110 is collectively lowered. That is, the “retreat step”. This is the same in the following examples, but it is effective when the tip is bent and the tension is relaxed, and as a result, peeling does not proceed in one direction over time. When returning to the original state as described above, the adhesive tape again adheres to the back surface of the chip, but it is generally considered that the adhesive force during re-adhesion is weaker than the adhesive force during initial adhesion. Moreover, the adhesive force at the time of re-adhesion is greatly reduced in the case of UV irradiation with a UV curable tape.
(7) The push-up block 110 rises all at once (first step rise).
(8) No leak is detected. FIG. 40c shows a state in which the leak has disappeared. If “No leak” does not occur even after repeating a predetermined number of times, depending on the setting, the chip is skipped, or the initial increase is reduced so that no leak occurs, or an alarm is displayed ( Or send alarm signal to host) Select one or more to stop.
(9) The push-up blocks 110b and 110c are raised together (second step raising step 35). At this time, the push-up block 110a and the lower base peripheral portion 102a do not move.
(10) There is a leak (leak detection step 36). If there is no leak, the process immediately proceeds to step (15).
(11) The ascending operation in (9) is decelerated (including stop) for a predetermined time or until there is no leak. That is, the “standby step”. During this time, monitoring of leakage is continuously or intermittently performed. If there is no leak, the process proceeds to step (13). However, this step can be omitted when the process proceeds from (10) to the next step (12). This may shorten the processing time.
(12) Return before step (9) starts. Alternatively, the process of (9) is reversed until there is no leak in the leak monitor. That is, the push-up blocks 110b and 110c are lowered at once.
(13) The second stage is raised again (second stage is raised again).
(14) No leak. If “No leak” does not occur even after repeating a predetermined number of times, depending on the setting, the chip is skipped, or the initial increase is reduced so that no leak occurs, or an alarm is displayed ( Or send alarm signal to host) Select one or more to stop.
(15) Raise the final stage, that is, the push-up block 110c alone (final stage ascending step 37). Of course, the chip 1 and the collet 105 are raised accordingly.
(16) There is a leak (leak detection step 38). If there is no leak, the process immediately proceeds to step (21).
(17) The ascending operation of (15) is decelerated (including stop) for a predetermined time or until there is no leak. That is, the “standby step”. During this time, monitoring of leakage is continuously or intermittently performed. If there is no leak, the process proceeds to step (19). However, this step can be omitted when the process proceeds from (16) to the next step (18). This may shorten the processing time.
(18) Return to before the start of step (15). Alternatively, the process of (15) is reversed until there is no leak in the leak monitor. That is, the push-up block 110c is lowered alone. Of course, the tip 1 and the collet 105 are lowered accordingly.
(19) Re-raise the last stage (last stage re-rise).
(20) No leak. If “No leak” does not occur even after repeating a predetermined number of times, depending on the setting, the chip is skipped, or the initial increase is reduced so that no leak occurs, or an alarm is displayed ( Or send alarm signal to host) Select one or more to stop.
(21) The collet rises and completely peels off (complete peeling step 39).

  Note that the vacuum for suction on the collet side and on the lower substrate side remains pulled up from step (1), (2) to step (21). That is, it remains ON.

  The merit of this peeling process is that any shape of chip can be pushed up corresponding to the shape.

3-2. Collet standby / retraction process (“Peeling Process 2”, FIGS. 41 to 42)
FIG. 41 is a process flow diagram showing specific processing steps for a method of using leak detection when the dicing tape 4 is peeled off mainly by repeatedly raising and lowering the collet 105. FIG. 42 is a cross-sectional flow diagram of the main part. Based on these, the progress of specific steps will be described.
(1) The dicing tape 4 is vacuum-sucked on the upper surface of the lower base 102 (tape suction step 41).
(2) The collet 105 lands on the upper surface (generally, but not limited to the device surface) of the chip 1 by vacuum suction (collet landing step 42). The landed state is shown in FIG.
(3) The push-up block 110 rises all at once (first step ascending step 43; see FIG. 42b). The chip 1 and the collet 105 are also pushed up accordingly. At this time, since the lower substrate peripheral portion 102a does not move, the tension for peeling off the dicing tape 4 on the outer periphery of the chip 1 works. Also, at this step, monitoring of leaks is started.
(4) The presence of a leak is detected (leak detection step 44). If there is no leak, the process immediately proceeds to step (9).
(5) The ascending operation in (3) is decelerated (including stop) for a predetermined time or until there is no leak. That is, the “standby step”. During this time, monitoring of leakage is continuously or intermittently performed. If there is no leak, the process proceeds to step (7). However, this step can be omitted when the process moves from (4) to the next step (6). This may shorten the processing time.
(6) Return to before step (3) starts. Alternatively, the process of (3) is reversed until there is no leak in the leak monitor. That is, the push-up block 110 is collectively lowered. That is, the “retreat step”.
(7) The push-up block 110 rises all at once (first stage re-rise).
(8) No leak is detected. If “No leak” does not occur even after repeating a predetermined number of times, depending on the setting, the chip is skipped, or the initial increase is reduced so that no leak occurs, or an alarm is displayed ( Or send alarm signal to host) Select one or more to stop.
(9) The collet 105 is raised in a state where the chip 1 is vacuum-sucked (collet single ascending step 45; see FIGS. 42c and d).
(10) The presence of a leak is detected (leak detection step 46). If there is no leak, it is completely peeled off.
(11) The ascending operation in (9) is decelerated (including stop) for a predetermined time or until there is no leak. That is, the “standby step”. During this time, monitoring of leakage is continuously or intermittently performed. If there is no leak, the process proceeds to step (13). However, this step can be omitted when the process proceeds from (10) to the next step (12). This may shorten the processing time.
(12) Step (9) Return to the state before the start (Collet descent step 47; see FIG. 42e). Alternatively, the process of (9) is reversed until there is no leak in the leak monitor. That is, the collet 105 is lowered. That is, the “retreat step”.
(13) The push-up blocks 110b and 110c are moved up collectively (second step up step 48). At this time, the push-up block 110a and the lower base peripheral portion 102a do not move.
(14) There is a leak (leak detection step 49). If there is no leak, the process immediately proceeds to step (19).
(15) The ascending operation of (13) is decelerated (including stop) for a predetermined time or until there is no leak. That is, the “standby step”. During this time, monitoring of leakage is continuously or intermittently performed. If there is no leak, the process proceeds to step (17). However, this step can be omitted when shifting from (14) to the next step (16). This may shorten the processing time.
(16) Return to before step (13). Alternatively, the process of (13) is reversed until there is no leak in the leak monitor. That is, the push-up blocks 110b and 110c are lowered at once.
(17) The second stage is raised again (second stage is raised again).
(18) No leak. If “No leak” does not occur even after repeating a predetermined number of times, depending on the setting, the chip is skipped, or the initial increase is reduced so that no leak occurs, or an alarm is displayed ( Or send alarm signal to host) Select one or more to stop.
(19) The collet 105 is raised with the chip 1 being vacuum-sucked (collet single ascending step 50).
(20) The presence of a leak is detected (leak detection step 51). If there is no leak, it is completely peeled off.
(21) The ascending operation of (19) is decelerated (including stop) for a predetermined time or until there is no leak. That is, the “standby step”. During this time, monitoring of leakage is continuously or intermittently performed. If there is no leak, the process proceeds to step (23). However, this step can be omitted when shifting from (20) to the next step (22). This may shorten the processing time.
(22) Step (19) Return to the state before the start (Collet descent step 52). Alternatively, the process of (19) is reversed until there is no leak in the leak monitor. That is, the collet 105 is lowered. That is, the “retreat step”.
(23) Raise the final stage, that is, the push-up block 110c alone (final stage ascending step 53). Of course, the chip 1 and the collet 105 are raised accordingly.
(24) There is a leak (leak detection step 54). If there is no leak, the process immediately proceeds to step (29).
(25) The ascending operation of (23) is decelerated (including stop) for a predetermined time or until there is no leak. That is, the “standby step”. During this time, monitoring of leakage is continuously or intermittently performed. If there is no leak, the process proceeds to step (27). However, this step can be omitted when the process proceeds from (24) to the next step (26). This may shorten the processing time.
(26) Return to before step (23) starts. Alternatively, the process of (23) is moved backward until there is no leak in the leak monitor. That is, the push-up block 110c is lowered alone. Of course, the tip 1 and the collet 105 are lowered accordingly.
(27) Re-raise the final stage (final stage re-rise).
(28) No leak. If “No leak” does not occur even after repeating a predetermined number of times, depending on the setting, the chip is skipped, or the initial increase is reduced so that no leak occurs, or an alarm is displayed ( Or send alarm signal to host) Select one or more to stop.
(29) The collet rises and completely peels off (complete peeling step 55).

  It should be noted that the vacuum for suction on the collet side and the lower substrate side remains pulled up from step (1), (2) to step (29). That is, it remains ON.

  The merit of this stripping process is that when stripping can be easily performed, stripping can be performed relatively easily mainly by only the movement of the collet.

3-3. Only the push-up block has a lowering peeling process ("Peeling Process 3", FIGS. 43 to 44)
FIG. 43 shows a process in which peeling is progressed by raising only the push-up block 110 while the push-up block 110 is once lifted and the collet 105 sucks the chip 1. FIG. 44 is a cross-sectional flow diagram of the main part. Based on these, the progress of specific steps will be described.
(1) The dicing tape 4 is vacuum-sucked on the upper surface of the lower base 102 (tape suction step 61).
(2) The collet 105 lands on the upper surface (generally, but not limited to the device surface) of the chip 1 while vacuuming (collet landing step 62). The landed state is shown in FIG. 44a.
(3) The push-up block 110 ascends collectively (first step ascending step 63; see FIG. 44b). The chip 1 and the collet 105 are also pushed up accordingly. At this time, since the lower substrate peripheral portion 102a does not move, the tension for peeling off the dicing tape 4 on the outer periphery of the chip 1 works. Also, at this step, monitoring of leaks is started.
(4) The presence of a leak is detected (leak detection step 64). If there is no leak, the process immediately proceeds to step (9).
(5) The ascending operation in (3) is decelerated (including stop) for a predetermined time or until there is no leak. That is, the “standby step”. During this time, monitoring of leakage is continuously or intermittently performed. If there is no leak, the process proceeds to step (7). However, this step can be omitted when the process moves from (4) to the next step (6). This may shorten the processing time.
(6) Return to before step (3) starts. Alternatively, the process of (3) is reversed until there is no leak in the leak monitor. That is, the push-up block 110 is collectively lowered. That is, the “retreat step”.
(7) The push-up block 110 rises all at once (first stage re-rise).
(8) No leak is detected. If “No leak” does not occur even after repeating a predetermined number of times, depending on the setting, the chip is skipped, or the initial increase is reduced so that no leak occurs, or an alarm is displayed ( Or send alarm signal to host) Select one or more to stop.
(9) With the collet 105 vacuum-adsorbing the chip 1, only the push-up block 110 is lowered (push-up block single descent step 65; see FIG. 44c).
(10) The presence of a leak is detected (leak detection step 46). If there is no leak, the process proceeds to (13).
(11) The descending operation of (9) is decelerated (including stop) for a predetermined time or until there is no leak. That is, the “standby step”. During this time, monitoring of leakage is continuously or intermittently performed. If there is no leak, the process proceeds to step (13). However, this step can be omitted when the process proceeds from (10) to the next step (12). This may shorten the processing time.
(12) Step (9) Return to the state before the start (push-up block re-raising step 67; see FIG. 44d). Alternatively, the process of (9) is reversed until there is no leak in the leak monitor. That is, only the push-up block 110 is lowered. That is, the “retreat step”.
(13) The push-up blocks 110b and 110c are moved up collectively (second step up step 68). At this time, the push-up block 110a and the lower base peripheral portion 102a do not move.
(14) There is a leak (leak detection step 69). If there is no leak, the process immediately proceeds to step (19).
(15) The ascending operation of (13) is decelerated (including stop) for a predetermined time or until there is no leak. That is, the “standby step”. During this time, monitoring of leakage is continuously or intermittently performed. If there is no leak, the process proceeds to step (17). However, this step can be omitted when shifting from (14) to the next step (16). This may shorten the processing time.
(16) Return to before step (13). Alternatively, the process of (13) is reversed until there is no leak in the leak monitor. That is, the push-up blocks 110b and 110c are lowered at once.
(17) With the collet 105 vacuum-adsorbing the chip 1, only the push-up blocks 110b and 110c are lowered (push-up block collective single descent step 70).
(18) The presence of a leak is detected (leak detection step 71). If there is no leak, the process proceeds to (21).
(19) The descending operation of (17) is decelerated (including stop) for a predetermined time or until there is no leak. That is, the “standby step”. During this time, monitoring of leakage is continuously or intermittently performed. If there is no leak, the process proceeds to step (21). However, this step can be omitted when the process proceeds from (18) to the next step (20). This may shorten the processing time.
(20) Step (17) Return to the state before the start (push-up block re-raising step 72). Alternatively, the process of (17) is reversed until there is no leak in the leak monitor. That is, only the push-up blocks 110b and 110c are lowered. That is, the “retreat step”.
(21) Raise the final stage, that is, the push-up block 110c alone (final stage ascending step 73). Of course, the chip 1 and the collet 105 are raised accordingly.
(22) There is a leak (leak detection step 74). If there is no leak, the process immediately proceeds to step (27).
(23) The ascent operation of (21) is decelerated (including stop) for a predetermined time or until there is no leak. That is, the “standby step”. During this time, monitoring of leakage is continuously or intermittently performed. If there is no leak, the process proceeds to step (27). However, this step can be omitted when moving from (22) to the next step (24). This may shorten the processing time.
(24) Return to before step (21). Alternatively, the process of (21) is reversed until there is no leak in the leak monitor. That is, the push-up block 110c is lowered together with other blocks. Of course, the tip 1 and the collet 105 are lowered accordingly.
(25) Re-raise the final stage (final stage re-rise).
(26) No leak. If “No leak” does not occur even after repeating a predetermined number of times, depending on the setting, the chip is skipped, or the initial increase is reduced so that no leak occurs, or an alarm is displayed ( Or send alarm signal to host) Select one or more to stop.
(27) The collet rises and completely peels off (complete peeling step 75).

  Note that the vacuum for suction on the collet side and on the lower substrate side remains pulled from step (1), (2) to step (27). That is, it remains ON.

  The merit of this peeling process is that the total stroke of the push-up block can be shortened.

3-4. Slide peeling process (“Peeling Process 4”, FIGS. 45 to 47)
In the peeling device up to the previous section, there was a push-up block 110 at the bottom of the chip 1, but in other devices, as shown in FIG. 46b, instead, the slide plate 183 slides in the horizontal direction, There is a thing which advances peeling. The structure will be described with reference to FIG. FIG. 46A is a top view seen from the target chip 1 side. The suction piece 102 is provided with a recess portion 181 for accommodating the slide plate 183. The bottom surface of the recess portion 181 has a vacuum suction hole 182. Like the other devices, the suction piece 102 around the recess portion 181 is provided. Is provided with a vacuum suction hole 103. FIG. 45 is a process flow diagram showing specific processing steps for a method using leak detection when the dicing tape 4 is peeled off by this apparatus. FIG. 47 is a cross-sectional flowchart of the main part. The progress of specific steps will be described with reference to FIGS.
(1) The dicing tape 4 is vacuum-sucked on the upper surface of the lower base 102 (tape suction step 81).
(2) The collet 105 lands on the upper surface (generally, but not limited to the device surface) of the chip 1 while performing vacuum suction (collet landing step 82). The landed state is shown in FIG. 47a.
(3) The presence of a collet leak is detected (leak detection step 83; FIG. 47b).
(4) Wait (flow rate set value arrival waiting step 84; FIG. 47c). When the leak amount is within the allowable range, the process proceeds to the next step.
(5) The slide plate 183 is started to slide in a direction in which the overlap with the chip 1 is reduced (slide step 85; FIG. 47d). Slide as it is until a collet leak is detected.
(6) The presence of a leak is detected.
(7) Decrease the slide speed until the leak falls within the allowable range (or stop and wait). That is, it is a standby step 86.
(8) No leak detection.
(9) The slide is resumed, the slide stroke end is reached, and the collet starts to rise (slide end & collet raising step 87).
(10) The presence of a leak is detected (leak detection step 88).
(11) Decrease the collet rising speed until the leak falls within an allowable range (or stop and wait). That is, it is a standby step 89.
(12) No leak is detected.
(13) Collet rises and completely peels off (complete peeling step 90)
The merit of this stripping process is that it can be executed with a relatively simple step configuration.

4). Details of each peel teaching process (mainly FIGS. 48 to 50 and FIG. 31)
The following teaching processes can be applied to the various stripping processes described in Section 3, the various collet structures described in Section 2, and the overall process described in Section 1, as appropriate, and can be applied alone or in combination. .

  Note that the following teaching is performed using either non-defective product chips, defective product chips, or non-product chips (the top is a chip with the same shape as the surrounding product and the pattern is not completely formed). Is possible. Further, even if the product chip has a pseudo pickup (a pickup that does not completely peel off), it will return to its original state if it is not completely peeled off.

4-1. Push-up block operation teaching ("teaching method 1", FIGS. 48 to 49 and FIG. 31)
FIG. 48 is an explanatory diagram for explaining the principle of leak detection and automatic acquisition of process parameters using it, that is, the teaching process. 48a, 48b, and 48c are cross-sectional flowcharts of the main part, and FIG. 48d is a timing chart showing the relationship with the principle of leak detection explained in FIG. Based on these, the progress of specific steps will be described.
(1) Align so that the target chip 1 comes to the center of the suction piece (lower base) 102 and the suction collet 105. Here, the flow rate detection is turned on (detection operation start step, that is, teaching start step 151).
(2) The dicing tape 4 is vacuum-sucked on the upper surface of the lower base 102 (tape suction step 152).
(3) The collet 105 lands on the upper surface (generally, but not limited to the device surface) of the chip 1 while performing vacuum suction (collet landing step 153). The landed state is shown in FIG. 48a.
(4) The entire push-up block (push-up jig) rises with the upper surface aligned at a sufficiently slow speed (initial speed) (push-up block ascending step 154).
(5) The presence of a leak is detected (leak detection step 157). The push-up height (“leak detection start height”) is stored.
(6) The entire push-up block is aligned at a sufficiently slow speed (initial speed) and descends until the leak is within an allowable range. The height (“leak detection end height”) is stored. In other words, this is stored as “provisional first-stage raised height” (push-up degree storage step 158).
(7) Of the push-up blocks, only the push-up blocks (push-up jigs) 110b and 110c rise with the upper surfaces aligned at a sufficiently slow speed (initial speed) (second-stage push-up block ascending step).
(8) The presence of a leak is detected (leak detection step 159). The push-up height (“leak detection start height”) is stored.
(9) Of the push-up blocks, only the push-up blocks (push-up jigs) 110b and 110c are lowered at a sufficiently slow speed (initial speed) until the upper surfaces are aligned and the leak is within the allowable range. The height (“leak detection end height”) is stored. That is, this is stored as “provisional second-stage raised height” (push-up degree storage step 160).
(10) Of the push-up blocks, only the push-up block (push-up jig) 110c rises at a sufficiently slow speed (initial speed) (third-stage push-up block ascending step).
(11) The presence of a leak is detected. The push-up height (“leak detection start height”) is stored.
(12) Of the push-up blocks, only the push-up block (push-up jig) 110c is aligned at the sufficiently slow speed (initial speed) and descends until the leak is within the allowable range. The height (“leak detection end height”) is stored. In other words, this is stored as “provisional third stage rising height”.
(13) Here, it is confirmed that only the push-up block (push-up jig) 110c is lifted (additional lift 162) to check whether there is no leak (leak detection step 161) at the “provisional third stage lift height”. To do.
(14) By this, the “set provisional third stage rising height” that is finally free of leak, that is, “top dead center” (third stage rising height setting value) is stored (top dead center setting step). 155).
(15) “Temporary first-stage raised height”, “provisional second-stage raised height” and “set provisional third-stage raised height” are set as stop heights (stop height setting step 156 ).
(16) Next, the pickup in any of the corresponding sections 3 is executed at the stop height set in (15). Then, every time, the rising speed is gradually increased or decreased, and the optimum speed is stored and changed. This is possible even with non-product chips, but it is efficient to carry out while picking up product chips.

4-2. Slide operation teaching ("Teaching method 2", FIGS. 46 to 47 and FIG. 50)
Here, a teaching method of slide speed in the apparatus configuration described in Section 3-4 will be described. FIG. 50 is a process flow diagram thereof. The progress of specific steps will be described with reference to FIGS. 46 to 47 and FIG.
(1) Align so that the target chip 1 comes to the center of the suction piece (lower base) 102 and the suction collet 105. Here, the flow rate detection is turned on (detection operation start step, that is, teaching start step 171).
(2) The dicing tape 4 is vacuum-sucked on the upper surface of the lower base 102 (tape suction step 172).
(3) The collet 105 lands on the upper surface (generally, but not limited to the device surface) of the chip 1 while performing vacuum suction (collet landing step 173).
(4) The slide operation is started with respect to the first chip at a sufficiently slow speed (initial speed) (slide start step 174). If there is no leak, slide to the stroke end (stroke end step 176). In the case of product chips, the process proceeds to the completion of peeling. The slide speed is memorized.
(5) The slide operation is started with respect to the second chip at a slightly faster speed. If there is no leak, slide to the end of the stroke. In the case of product chips, the process proceeds to the completion of peeling. The slide speed is memorized.
(6) This is repeated to detect the presence of leak in the nth chip (leak detection step 175).
(7) The slide speed for the nth chip is stored.
(8) Wait until the leak reaches an allowable range and store the waiting time.
(9) The slide operation is resumed, and if a leak is detected, the process returns to (8), and if there is no leak, the process proceeds to the next.
(10) Slide to the stroke end. Here, when the optimum speed is selected or calculated from the speeds stored in (7) or earlier, the following steps are not necessary.
(11) If necessary, further increase the speed and repeat (6) and (10), and set and store the optimum speed from the data obtained there (optimum speed storage step 177).

5. Preferred combinations and characteristics of each stripping process Each stripping process in Section 3 has been described in a typical example, classified into its type, but in practice, it may be selected appropriately or combined with each other. It can be expected that pickup efficiency is improved and product reliability is improved. For example, the collet rising segment of section 3-2 (FIG. 41, steps 45 to 47 or 50 to 52), ie, the set of steps is picked up after step 67 of stripping process 3 or in parallel with the appropriate step of stripping process 4 It is effective for time saving.

6). Explanation of chip transfer, physical adsorption landing and die bonding process (mainly see FIGS. 51 to 60)
In general, processing from chip separation to completion of landing on the wiring board is executed while the chip is vacuum-sucked to the suction collet. However, in this case, in the case of a thin film chip (especially one having a thickness of 100 micrometers or less), the chip remains locally deformed by vacuum suction (see FIGS. 54 to 56 for chip distortion due to vacuum suction). ) Since it will land and be bonded and fixed to the substrate, voids and strain are likely to remain after bonding. This tendency is particularly strong in the method in which an adhesive layer (method using DAF) is formed in advance on the back surface of the chip. In addition, when the device surface, that is, the main part of the chip, such as the main part of the transistor or the surface on which the multilayer wiring is formed (the main surface opposite to the back surface) is adsorbed upward (so-called face-up product), the device In terms of reliability, it is important to bond without leaving voids, strains or deformations. In general, peripheral voids are partially eliminated in the molding process, but those near the center are not eliminated.

  In this section, in order to solve these problems, a case will be described in which a method of turning off vacuum suction at an early stage is applied to a landing portion on a wiring board in the bonding process described in another section or the vicinity thereof. In the following embodiments, turning off vacuum adsorption is completely turned off and only physical adsorption is used (FIG. 31), unless specifically stated otherwise, and unless otherwise apparent from the context. The three-way switching valve 143 is switched in accordance with the instruction of the pickup unit control system 144 to indicate that the vacuum suction system of the suction collet is disconnected from the vacuum supply source and is open to the atmosphere). The same applies to the other sections, but the landing technique in this section is an alternative or detailed process of that part of the process described in the other sections, and is not essential for the processes described in the other sections. It goes without saying that there is nothing.

Here, a detailed flow of a process from chip separation to die bonding will be described mainly with reference to FIGS. As described above, in FIG. 51, first, a pickup operation is started in the pickup unit (pickup operation start step 201 in FIG. 51, hereinafter the same FIG. 51). First, the dicing tape 4 is attracted to the lower base 102 (DC tape adsorption step 202). Collet 105 at time t ₁₁ in FIG. 52 starts to decrease and come on the chip 1 of interest. Switches to slow descent at time _{t 12.} Then, evacuation of the collet 105 is started at time _{t 13.} Came the collet 105 is lowered while vacuum suction at time _{t 14,} lands on the chip 1 (collet adsorption start step 203). FIG. 53 shows an outline of a cross section at this time. Immediately after, increase in operating and collet 105 Choke time _{t 15} is started. Although the boosting operation at the time t ₁₆ returns to the block Choke time ended t ₁₇ origional (t ₁₅ between -t ₁₇ for example 100 ms), the collet 105 if there is no problem to complete the peeling as it continues to rise . After complete peeling, at time t ₁₈ , the collet 105 increases its ascent speed and reaches a predetermined translational height at time t ₁₉ . That is, the collet 105 ascends while being held by the vacuum suction by the rubber chip 125 (pickup step 204). FIG. 54 shows an outline of the cross section at this time. After rising to a predetermined height, the collet 105 moves above the die bonding position, that is, above the wiring substrate 11 on the bonding stage 132 (moving above the bonding position) 205. FIG. 55 shows an outline of the cross section at this time. From time t ₂₀ , the collet 105 starts to descend while being held by the vacuum suction with the rubber tip 125. FIG. 56 shows an outline of the cross section at this time. It switched to the low speed drop at time _{t 21.} This is the final landing position. Is evacuated off the collet at time t ₂₂ (suction off step 206), the chip 1 is lowered while being held only in a substantially intermolecular force (physical adsorption) to rubber tip 125. FIG. 57 shows an outline of the cross section at this time (a comparison between FIGS. 54 to 56 and FIG. 57 shows that the distortion due to the vacuum suction of the chip is eliminated in FIG. 57). Chip 1 at time _{t 23} is landed on the wiring substrate 11 (the landing step 207; between t ₂₁ -t ₂₃ eg speed 20 mm / sec; Time about 30 milliseconds). 52, when descending by a route such as efg (the time between fg is, for example, speed 2 mm / sec; time is about 40 milliseconds), the time when the final landing posture in that method is entered, that is, the “f” point The vacuum suction should be turned off immediately after (may be turned off at other timings). When landing is confirmed at time t24, a bonding load (for example, 5N) is applied to the collet 105 (bonding step 208). FIG. 58 shows an outline of the cross section at this time. Bonding is completed in time t25 (the time for example, about one second between t ₂₃ -t _25), collet starts to rise. FIG. 59 shows an outline of the cross section at this time. The predetermined parallel movement altitude is reached at time t26. FIG. 60 shows an outline of the cross section at this time. Thereafter, the collet 105 moves to the pickup unit again for the next chip peeling.

  Here, in this process, since the route abc is taken in FIG. 52, that is, the vacuum suction is turned off before landing (including weakening as compared with the parallel movement), the route adc is taken in FIG. Compared to the case, since there is no deformation or stress due to adsorption on the chip 1 at the time of landing, bonding characteristics are improved. Further, since unnecessary force due to adsorption is not applied to the chip 1 at the time of landing, as a result of smoothly learning on the surface to be bonded of the wiring board, voids and undesired distortion do not remain. Such an effect is particularly effective for a process using DAF (including a type attached to the back surface of a wafer and a type previously attached to a dicing tape) in which chip deformation during die bonding is likely to be a problem.

  Although not necessarily indispensable, since the vacuuming is turned off after switching from the high speed descent to the low speed descent (final landing speed), the tip 1 does not fall due to the switching impact force (however, sufficient physical Under the condition that the adsorption is secured, the vacuum adsorption may be turned off before the speed is switched, and it may be better not to switch the speed). That is, since the mass of the chip is relatively small, the physical adsorption force is generally considered to be stronger than the gravity, but the impact force is generally considered to be comparable to the physical adsorption force.

  It should be noted that even if the vacuuming is turned on and off, it is not always necessary to completely turn it off (open to the atmosphere). For example, if the suction pressure when turned on is, for example, minus 80 to 90 kilopascals, It is sufficient that the pressure of the electrode is sufficiently low in absolute value, for example, about several percent or less (however, a thin film chip is more effective in a completely off state where vacuum adsorption is not used, that is, effective only in physical adsorption) This is effective for improving the die bonding characteristics, ie, reducing the voids, and when expressed in terms of pressure, it is, for example, about 0.05 to 0.0005 kilopascals or less in absolute value. It is easier to control when the switch is completely off, and it is advantageous in terms of speed of pressure response.) Further, it may be switched between strong and weak without being completely turned off. That is, it is also effective to set the suction strength to 30% or less, desirably 15% or less, at the time of ON. Considering stable chip holding, a negative pressure, that is, a weak suction state (not weak discharge) is desirable even when it is not completely turned off.

  The landing method described in this section is particularly effective in combination with a collet die bonding method having a low elastic rubber tip described in the next section. This is because when the vacuum suction is performed on the low-elasticity rubber chip, the stress applied to the chip is dispersed in a wide range, so that the chip deformation is quickly recovered when the vacuum suction is turned off. Further, when the vacuum suction is turned off at least during the thermocompression bonding, the bonding pressure is sufficiently dispersed through the low elastic rubber chip, which is particularly effective for eliminating local deformation of the chip and voids.

  In addition, the landing method described in this section is a die bonding method using a collet having a rubber chip for a thin film chip (a chip having a chip thickness of 150 micrometers or less, or 100 micrometers or less, and even a chip thickness of 50 micrometers or less). Especially effective in combination. This is because the thin film chip is likely to be locally deformed, and if it is landed as it is, a closed space is easily formed between the thin film chip and the surface of the wiring board.

  Further, the landing method described in this section is particularly effective in combination with each peeling and die bonding method using a collet having a rubber chip described in Section 3. This is because when the chip is peeled off while repeatedly bending and recovering, the chip is often adsorbed while leaving a strain.

7). Explanation of low-elastic rubber tip material (mainly see Fig. 61)
As the material of the rubber chip, it is first effective to select from among thermosetting elastomers because it is easy to select a material having low hardness. For example, Geltec Alpha Gel (registered trademark of Geltec), that is, a silicone-based gel-like elastomer containing silicone as a main component is also a suitable candidate from the viewpoint of preventing contamination of the chip. . Of these series, theta gel (registered trademark of Geltech), theta 5 (hardness of about 56), theta 6 (hardness of about 14), and theta 8 (hardness of about 28) are more preferred. Further, theta 8 (hardness of about 28) is particularly suitable among theta gels.

  Other materials can be selected from thermosetting elastomers such as fluorine rubber, heat-resistant nitrile rubber, natural rubber, isoprene rubber, styrene-butadiene rubber, and neoprene rubber.

  Furthermore, in consideration of recycling, there are options such as a polyimide-based thermoplastic elastomer as a thermoplastic resin.

  A hardness range of 10 or more and less than 70 is suitable for using elasticity. Within that range, a hardness of 15 or more and less than 55 is particularly suitable for utilizing elasticity. A range of hardness of 20 or more and less than 40 is particularly suitable for handling a thin film chip. However, other ranges are not excluded. Among the embodiments of the present application, there is an application field in which a conventional hard collet such as an elastomer having a height of about 80, a metal, a ceramic, or a rubber chip is suitable. Needless to say, examples of physical adsorption and detection of chip curvature due to leakage are not particularly limited to this range.

  When a rubber chip having low elasticity is used in this way, it is easy to follow the unevenness (since the top surface of the chip is not necessarily flat), it is difficult to leak during peeling, and the peeling effect can be enhanced.

  In addition, when a rubber chip having low elasticity is used in this way, even if the chip is temporarily bent in the peeling process, the rubber chip is also deformed to a considerable extent in accordance with that, so that the stress is dispersed, and the chip is damaged or stressed. Can be prevented from remaining.

  Further, when such a low-elasticity rubber chip is used, impact during landing can be reduced in die bonding. Therefore, it is particularly effective for face-up products.

  Furthermore, when such a low-elastic rubber chip is used, residual strain during pressure bonding can be reduced in die bonding. Therefore, it is particularly effective for a process using DAF or the like.

  In addition, when using a rubber chip with low elasticity in this way, even if vacuum suction is turned off before landing in die bonding, the contact area with the chip surface is large, so that sufficient physical adsorption force can be secured. it can.

  Further, when such a low-elasticity rubber chip is used, damage to the chip during crimping can be reduced regardless of whether or not vacuum suction is turned off before landing in die bonding.

  Generally, the physical adsorption force is caused by van der Waals force, but the reach distance is in the range of 0.2 nm to 10 nm. The physical adsorption force between the upper surface of the semiconductor chip and the rubber chip belongs to a relatively weak category due to London force (attraction between induced dipoles) among van der Waals forces. Therefore, it is necessary to make as much area as possible within the reach. For that purpose, it is necessary to prepare a member excellent in copying property. Moreover, since an impact is likely to cause a drop, a material having as high an impact absorption as possible is preferable.

  Since the rubber chip has a relatively poor thermal conductivity, in general, in die bonding by a collet using a rubber chip, heating is performed from the wiring substrate side, that is, the bonding stage side.

8. Description of the two-stage die bonding process (mainly refer to FIGS. 62 to 65)
In the above description, the method of completing the thermocompression bonding with one bonding tool (collet 105) has been shown. However, a plurality of chips (for example, five) are temporarily attached with the first bonding tool (collet 105), and then, If the plurality of chips are finally pressure-bonded with the second bonding tool, the throughput can be increased several times. In addition, in the temporary pressure bonding combined with the low-elasticity rubber chip described in section 7, even when operated at a high speed, there is little damage to the chip, so that high speed temporary pressure bonding can be executed. This will be described in detail below.

  FIG. 62 shows a configuration of the peeling / die bonding integrated device 400 in a top view. The chip peeling part 100 (pickup part) described above is on the left side of the figure, and the die bonding part 300 is on the right side. The temporary bonding part 300a is provided with a temporary bonding stage 132a. On the other hand, the main press bonding part 300b is provided with a vertically long main press bonding stage 132b.

  The AA cross section of FIG. 62 is shown in FIGS. 63 to 65, and the two-stage die bonding process will be described. As shown in FIG. 63, the peeled chip 1j is transferred by the collet 105 above the wiring substrate 11a on the temporary bonding stage 132a. Next, as shown in FIG. 64, the collet 105 descends and temporary pressure bonding (pressure bonding state in which the position is fixed by the adhesive member layer) is performed in a short time (pressurization time, for example, about 0.1 second). At this time, if the timing is correct, the main press bonding tool 305 performs the main press bonding of the chips 1a to 1e to the substrate 11b. Since the main pressure bonding requires more time than the temporary pressure bonding (for example, pressurization time of about 4 seconds), the collet 105 reciprocates between the pick-up unit 100 and the temporary bonding unit 300a several times during this time, and the chips 1f to 1j Temporary pressure bonding can be completed (see FIG. 65). When completed, the collet 105 moves to the peeling stage for the next chip 1k peeling.

  In addition, as described above, the temporary press-bonding stage and the main press-bonding stage are about 100 to 150 degrees Celsius (the glass transition temperature of the organic wiring board is generally about 240 to 330 degrees Celsius, The heating temperature can be about 100 to 200 degrees Celsius, but is preferably about 100 to 150 degrees Celsius in order to minimize the deformation of the substrate, but at least below the glass transition temperature of the substrate. It is necessary to be warm). The main bonding tool 305 is also heated to the same temperature or a temperature higher by about 50 degrees Celsius. Therefore, unlike the temporary crimping collet, the lower end portion of the final crimping bonding tool 305 can be composed of a member having a relatively good heat conduction, and silicon or the like constituting the chip has a relatively good heat conduction. Since it is a member and can perform efficient heating, the progress of thermocompression bonding can be performed smoothly.

9. Description of modification of collet vacuum suction system (mainly see FIGS. 66, 67 and 52)
The vacuum suction system of the collet 105 described so far is a completely closed type (the valve 143 in FIG. 31 is connected to a vacuum source when it is on, and is disconnected from the vacuum source when it is off and is open to the atmosphere. However, what is described here is an improved type in which a leak hole 221 is provided in a region relatively close to the rubber tip of the collet body 105, as shown in FIG. This has the effect of speeding up the pressure response of the collet tip when adsorption is turned off (of course, the vacuum suction system of the collet 105 described so far is also disconnected from the vacuum source and released into the atmosphere when off. In general, however, switching between the vacuum source and the atmosphere release is performed by the switching valve 143 placed closer to the vacuum source than the collet tip, so a slight delay is inevitable. It took about 40 to 100 milliseconds, that is, if a leak path is permanently installed at the tip of the collet, even if the leak path is relatively thin, only the conductance of the vacuum channel to the switching valve 143 is required. Pressure response is faster). Moreover, the leak path (for example, the leak path has a hole diameter of about 0.3 mm, the ultimate flow rate when only the leak path is opened is 0.4 L / min, and the ultimate pressure is 84 KPa. (The arrival flow rate when all the suction holes are opened is about 7.0 L / min.)), So that the impact on the chip due to the impact when the vacuum suction system is closed by the chip can be mitigated. That is, when a relatively soft elastomer as described in section 7 is used as a rubber tip, the vacuum sealability is very good, and the vacuum recovers from the state in which the tip is bent and leaks. There is concern that the impact when closing is relatively large. However, in this case, since there is always a leak path, the vacuum suction system is not completely closed, so that it is considered that there is little possibility that a strong impact is applied to the chip. In addition, if there is a leak hole, the response is fast, so even if the vacuum suction is turned off immediately before landing, the chip distortion can be sufficiently prevented at the time of landing. In addition, when a rubber tip made of a low elastic member is used, the recovery from the curvature is performed more smoothly in combination with the recovery force of the low elastic member.

The detailed procedure will be described below with reference to FIG. As described above, in FIG. 66, first, a pickup operation is started in the pickup section (pickup operation start step 211 in FIG. 66, hereinafter the same FIG. 66). First, the dicing tape 4 is adsorbed to the lower base 102 (DC tape adsorbing step 212). Collet 105 at time t ₁₁ in FIG. 52 starts to decrease and come on the chip 1 of interest. Switches to slow descent at time _{t 12.} Then, evacuation of the collet 105 is started at time _{t 13.} Came the collet 105 is lowered while vacuum suction at time _{t 14,} lands on the chip 1 (collet adsorption start step 213). Immediately after, increase in operating and collet 105 Choke time _{t 15} is started. The time boosting operation at t ₁₆ is returned to the block Choke time ended t ₁₇ original collet 105 if there is no problem to complete the peeling as it continues to rise. After complete peeling, at time t ₁₈ , the collet 105 increases its ascent speed and reaches a predetermined translational height at time t ₁₉ . That is, the collet 105 ascends while being held by the vacuum suction by the rubber chip 125 (pickup step 214). After rising to a predetermined height, the collet 105 moves above the die bonding position, that is, above the wiring substrate 11 on the bonding stage 132 (step 215 for moving above the bonding position). From time t ₂₀ , the collet 105 starts to descend while being held by the vacuum suction with the rubber tip 125. It switched to the low speed drop at time _{t 21.} This is the final landing position. Is evacuated off the collet at time t ₂₂ (suction off step 216), the chip 1 is lowered while being held only in a substantially intermolecular force (physical adsorption) to rubber tip 125. Chip 1 at time _{t 23} is landed on the wiring board 11 (landing step 217). When landing is confirmed at time t24, a bonding load is applied to the collet 105 (bonding step 218). When bonding is completed at time t25, the collet starts to rise. The predetermined parallel movement altitude is reached at time t26. Thereafter, the collet 105 moves to the pickup unit again for the next chip peeling.

10. Summary The invention made by the present inventor has been specifically described by taking a square silicon chip as an example based on the embodiment. However, the present invention is not limited thereto, and various modifications can be made without departing from the scope of the invention. It goes without saying that it is possible.

  For example, it goes without saying that the present invention is equally applicable to picking up electronic chips on rectangular chips, chips of other shapes, chips other than silicon such as GaAs chips, and other chips.

DESCRIPTION OF SYMBOLS 1 Chip 10 Adhesive member layer 11 Wiring board 100 Chip apparatus peeling (chip processing apparatus)
105 Adsorption collet 125 Rubber chip 300 Die bonding part 400 Chip processing device

Claims (15)

A method of manufacturing a semiconductor integrated circuit device including the following steps:
(A) A chip pick-up unit of a chip processing apparatus with a plurality of chips divided into individual chip regions, with their back surfaces fixed to an adhesive tape, with the two-dimensional arrangement of the original wafer almost unchanged. Supplying to
(B) The surface of the first chip of the plurality of chips is vacuum-sucked to the lower surface of the rubber chip of the suction collet, and the adhesive tape on the back surface of the first chip is vacuumed to the upper surface of the lower substrate. Peeling the adhesive tape from the back surface of the first chip in the adsorbed state;
(C) After the step (b), in a state where the surface of the first chip is adsorbed to the lower surface of the rubber chip of the adsorption collet, the first chip is attached to the die of the chip processing apparatus. Transferring to the bonding part;
(D) After the step (c), with the front surface of the first chip adsorbed to the lower surface of the rubber chip, the back surface side of the first chip is placed on the die of the chip processing apparatus. Landing on the upper surface of the wiring board placed on the bonding part;
(E) After the step (d), by pressing the front surface of the first chip downward with the lower surface of the rubber chip, the first chip is placed on the back surface of the first chip. Fixing to the upper surface of the wiring board via an adhesive member layer between the upper surfaces of the wiring board;
Here, the rubber chip has an elastomer as a main component and has a hardness of 15 or more and less than 55.   In the method for manufacturing a semiconductor integrated circuit device according to the item 1, the hardness is 20 or more and less than 40.   In the method for manufacturing a semiconductor integrated circuit device according to the item 1 or 2, the elastomer is a thermosetting elastomer.   4. The method for manufacturing a semiconductor integrated circuit device according to any one of items 1 to 3, wherein the elastomer is a silicone-based elastomer.   5. In the method of manufacturing a semiconductor integrated circuit device according to any one of items 1 to 4, a vacuum suction system in the suction collet body is provided with a leak hole, and vacuum suction is performed in a leaked state therethrough.   6. The method for manufacturing a semiconductor integrated circuit device according to any one of 1 to 5, wherein the adhesive member layer is a DAF member layer. The method for manufacturing a semiconductor integrated circuit device according to any one of 1 to 6 further includes the following steps:
(E) A step of irradiating UV light from the adhesive tape side of the plurality of chips whose back surfaces are fixed to the adhesive tape before the step (b). A method of manufacturing a semiconductor integrated circuit device including the following steps:
(A) supplying a plurality of chips to a chip pickup unit of a chip processing apparatus;
(B) In a state where the surface of the first chip of the plurality of chips of the chip pickup unit is vacuum-sucked to the lower surface of the rubber chip of the suction collet, the first chip is placed in the die of the chip processing apparatus.・ Transfer process to the bonding part;
(C) After the step (b), with the front surface of the first chip adsorbed to the lower surface of the rubber chip, the back surface side of the first chip is placed on the die of the chip processing apparatus. Landing on the upper surface of the wiring board placed on the bonding part;
(D) After the step (c), by pressing the front surface of the first chip downward with the lower surface of the rubber chip, the first chip is brought into contact with the back surface of the first chip. Fixing to the upper surface of the wiring board via an adhesive member layer between the upper surfaces of the wiring board;
Here, the rubber chip has a vacuum suction hole in the center portion, and an elastomer as a main component, and the hardness thereof is 10 or more and less than 70.     9. The method for manufacturing a semiconductor integrated circuit device according to the item 8, wherein the elastomer is a thermosetting elastomer.   10. The method for manufacturing a semiconductor integrated circuit device according to 8 or 9, wherein the elastomer is a silicone elastomer.   In the method of manufacturing a semiconductor integrated circuit device according to any one of items 8 to 10, a vacuum hole is provided in a vacuum suction system in the suction collet body, and vacuum suction is performed in a leaked state therethrough.   12. The method for manufacturing a semiconductor integrated circuit device according to any one of 8 to 11, wherein the adhesive member layer is a DAF member layer. The method for manufacturing a semiconductor integrated circuit device according to any one of 8 to 12, further comprising the following steps:
(E) A step of irradiating UV light from the adhesive tape side of the plurality of chips whose back surfaces are fixed to the adhesive tape before the step (b).   14. In the method of manufacturing a semiconductor integrated circuit device according to any one of 8 to 13, the adsorption of the rubber chip to the lower surface in the step (c) is mainly based on physical adsorption.   15. In the method for manufacturing a semiconductor integrated circuit device according to any one of 8 to 14, the vacuum suction is turned off in the steps (c) to (d).

Images