JP2012151802A - Semiconductor output circuit - Google Patents

Semiconductor output circuit Download PDF

Info

Publication number
JP2012151802A
JP2012151802A JP2011010838A JP2011010838A JP2012151802A JP 2012151802 A JP2012151802 A JP 2012151802A JP 2011010838 A JP2011010838 A JP 2011010838A JP 2011010838 A JP2011010838 A JP 2011010838A JP 2012151802 A JP2012151802 A JP 2012151802A
Authority
JP
Japan
Prior art keywords
npn transistor
collector
emitter
resistor
output
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2011010838A
Other languages
Japanese (ja)
Inventor
Hiroki Otsuka
弘樹 大塚
Kazunobu Yamada
一信 山田
Masahiro Hioki
政宏 日置
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Asahi Kasei Electronics Co Ltd
Original Assignee
Asahi Kasei Electronics Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Asahi Kasei Electronics Co Ltd filed Critical Asahi Kasei Electronics Co Ltd
Priority to JP2011010838A priority Critical patent/JP2012151802A/en
Publication of JP2012151802A publication Critical patent/JP2012151802A/en
Pending legal-status Critical Current

Links

Images

Landscapes

  • Logic Circuits (AREA)

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor output circuit which generates an output signal in quick response to an input signal and can be reduced in power consumption.SOLUTION: The semiconductor output circuit of the present invention includes a first npn transistor, a second npn transistor, and a third npn transistor which has a base connected to a constant current source, a collector connected to an emitter of the second npn transistor, and an emitter connected to a collector of the first npn transistor.

Description

本発明は、主にバイポーラトランジスタで構成される集積回路の出力段とする半導体出力回路に関する。   The present invention relates to a semiconductor output circuit as an output stage of an integrated circuit mainly composed of bipolar transistors.

バイポーラ型集積回路の従来の出力回路としては、図２に示すような半導体出力回路が知られている（例えば特許文献１参照）。   As a conventional output circuit of a bipolar integrated circuit, a semiconductor output circuit as shown in FIG. 2 is known (see, for example, Patent Document 1).

図２に示す従来の半導体出力回路は、一端が高電位線９０に接続された第１の抵抗８１と、ベースが入力端子８７に接続され、コレクタが前記第１の抵抗８１の他端に接続され、エミッタが低電位線９１に接続される第１のｎｐｎトランジスタ８２と、一端が高電位線９０に接続された第２の抵抗８３と、ベースが前記第１の抵抗８１の他端と前記第１のｎｐｎトランジスタ８２のコレクタの間のノードＮ６０に接続され、コレクタが前記第２の抵抗８３の他端に接続される第２のｎｐｎトランジスタ８５と、ベースが前記第１のｎｐｎトランジスタ８２のベースに接続され、コレクタが前記第２のｎｐｎトランジスタ８５のエミッタに接続され、エミッタが低電位線９１に接続される第３のｎｐｎトランジスタ８４と、ベースが前記第２のｎｐｎトランジスタ８５のエミッタと前記第３のｎｐｎトランジスタ８４のコレクタの間のノードＮ６１に接続され、コレクタが出力端子８８に接続され、エミッタが低電位線９１に接続される出力トランジスタ８６と、を備える。   The conventional semiconductor output circuit shown in FIG. 2 has a first resistor 81 having one end connected to the high potential line 90, a base connected to the input terminal 87, and a collector connected to the other end of the first resistor 81. A first npn transistor 82 whose emitter is connected to the low potential line 91, a second resistor 83 whose one end is connected to the high potential line 90, and whose base is the other end of the first resistor 81 The second npn transistor 85 is connected to the node N60 between the collectors of the first npn transistor 82, the collector is connected to the other end of the second resistor 83, and the base is the first npn transistor 82. A third npn transistor 84 having a collector connected to the base, a collector connected to the emitter of the second npn transistor 85, and an emitter connected to the low potential line 91; and a base connected to the second npn transistor 85. an output transistor 86 connected to a node N61 between the emitter of the pn transistor 85 and the collector of the third npn transistor 84, the collector connected to the output terminal 88, and the emitter connected to the low potential line 91. .

以下、図２の回路の動作について詳しく説明する。
＜入力がＬＯＷの動作＞
図２の回路において、入力端子８７に印加される入力信号がＬＯＷの場合、第１のｎｐｎトランジスタ８２および第３のｎｐｎトランジスタ８４にベース電流が流れない。すると、ノードＮ６０の電位は高電位線９０側に張り付くため、第２のｎｐｎトランジスタ８５はオンとなり、出力トランジスタ８６もオンとなる。よって出力端子８８の電位は低電位線９１側に張り付くため、出力はＬＯＷとなる。 Hereinafter, the operation of the circuit of FIG. 2 will be described in detail.
<Operation when input is LOW>
In the circuit of FIG. 2, when the input signal applied to the input terminal 87 is LOW, the base current does not flow through the first npn transistor 82 and the third npn transistor 84. Then, since the potential of the node N60 sticks to the high potential line 90 side, the second npn transistor 85 is turned on and the output transistor 86 is also turned on. Therefore, since the potential of the output terminal 88 sticks to the low potential line 91 side, the output becomes LOW.

＜入力がＨＩＧＨの動作＞
入力端子８７に印加される入力信号がＨＩＧＨとなり、第１のｎｐｎトランジスタ８２および第３のｎｐｎトランジスタ８４にベース電流が流れる場合、第１および第３のｎｐｎトランジスタはカレントミラー回路を構成しており、同じコレクタ電流を流そうとする。 <Operation when input is HIGH>
When the input signal applied to the input terminal 87 becomes HIGH and the base current flows through the first npn transistor 82 and the third npn transistor 84, the first and third npn transistors constitute a current mirror circuit. Try to pass the same collector current.

しかし、第１のｎｐｎトランジスタ８２がオンし、第２のｎｐｎトランジスタ８５がオフしようとすると、第３のｎｐｎトランジスタ８４はコレクタ電流が減少し、飽和領域で動作する。そのため第３のｎｐｎトランジスタ８４のベースには、第１のｎｐｎトランジスタ８２のベース電流よりも大きい電流が流入し、カレントミラー回路は崩れる。第１のｎｐｎトランジスタ８２はベース電流が減少し、活性領域で動作し、第２のｎｐｎトランジスタ８５はオンする条件となる。   However, when the first npn transistor 82 is turned on and the second npn transistor 85 is turned off, the third npn transistor 84 decreases in collector current and operates in the saturation region. Therefore, a current larger than the base current of the first npn transistor 82 flows into the base of the third npn transistor 84, and the current mirror circuit is destroyed. The first npn transistor 82 has a base current decreased, operates in the active region, and the second npn transistor 85 is turned on.

この条件では、ノードＮ６１の電位は第３のｎｐｎトランジスタ８４の飽和領域でのコレクタ−エミッタ電圧ＶＣＥ３（一般には約０．１Ｖ）となり、出力トランジスタ８６はオフになるので、出力端子８８の電位は高電位線９０側に張り付きＨＩＧＨが出力される。一方で、第２のｎｐｎトランジスタ８５はオンになるので、ノード６０の電位（＝第１のｎｐｎトランジスタのコレクタ−エミッタ間電圧ＶＣＥ１）は、ノード６１の電位に第２のｎｐｎトランジスタ８５のベース−エミッタ間電圧ＶＢＥ２（一般には約０．７Ｖ）を加えた電位となり、第１のｎｐｎトランジスタ８２は活性領域で動作し、第１のｎｐｎトランジスタ８２のベース電流は小さい値で安定する。   Under this condition, the potential of the node N61 is the collector-emitter voltage VCE3 (generally about 0.1 V) in the saturation region of the third npn transistor 84, and the output transistor 86 is turned off, so that the potential of the output terminal 88 is HIGH is output to the high potential line 90 side. On the other hand, since the second npn transistor 85 is turned on, the potential of the node 60 (= the collector-emitter voltage VCE1 of the first npn transistor) becomes the base 61 of the second npn transistor 85 at the potential of the node 61. A potential obtained by adding an emitter-to-emitter voltage VBE2 (generally about 0.7 V) is applied, the first npn transistor 82 operates in the active region, and the base current of the first npn transistor 82 is stabilized at a small value.

特開平８−１９１２３８号公報JP-A-8-191238

しかしながら、図２の回路は、入力がＨＩＧＨのときであっても、第２のｎｐｎトランジスタ８５はオンとなるため、高電位線９０から第２の抵抗８３の経路に電流が流れ続けてしまい、消費電力が増大してしまうという問題があるので、近年の低消費電力化の要求を十分に満たすことができない。   However, in the circuit of FIG. 2, even when the input is HIGH, the second npn transistor 85 is turned on, so that current continues to flow from the high potential line 90 to the path of the second resistor 83. Since there is a problem that the power consumption increases, the recent demand for low power consumption cannot be sufficiently satisfied.

本発明者らは上記課題を解決するために鋭意検討した結果、一端が高電位線に接続された第１の抵抗と、ベースが入力端子に接続され、コレクタが前記第１の抵抗の他端に接続され、エミッタが低電位線に接続される第１のｎｐｎトランジスタと、一端が高電位線に接続された第２の抵抗と、ベースが前記第１の抵抗の他端と前記第１のｎｐｎトランジスタのコレクタの間のノードに接続され、コレクタが前記第２の抵抗の他端に接続される第２のｎｐｎトランジスタと、ベースが定電流源に接続され、コレクタが前記第２のｎｐｎトランジスタのエミッタに接続され、エミッタが前記第１のｎｐｎトランジスタのコレクタに接続される第３のｎｐｎトランジスタと、ベースが前記第２のｎｐｎトランジスタのエミッタと前記第３のｎｐｎトランジスタのコレクタの間のノードに接続され、コレクタが出力端子に接続され、エミッタが低電位線に接続される出力トランジスタと、を備える半導体出力回路により上記課題を解決できることを見出し、本発明を完成させた。   As a result of intensive studies to solve the above problems, the present inventors have found that a first resistor whose one end is connected to a high potential line, a base is connected to an input terminal, and a collector is the other end of the first resistor. A first npn transistor having an emitter connected to the low potential line, a second resistor having one end connected to the high potential line, a base connected to the other end of the first resistor, and the first resistor a second npn transistor connected to a node between collectors of the npn transistor, a collector connected to the other end of the second resistor, a base connected to a constant current source, and a collector connected to the second npn transistor; A third npn transistor having an emitter connected to a collector of the first npn transistor, a base connected to the emitter of the second npn transistor, and the third npn transistor. The present invention has been completed by finding that the above problem can be solved by a semiconductor output circuit including an output transistor having a collector connected to a node between the collectors of the transistors, a collector connected to the output terminal, and an emitter connected to the low potential line. I let you.

本発明によれば、入力信号に対して出力信号が高速に応答し、かつ、半導体出力回路の消費電力を低減させることが可能である。特に入力がＨＩＧＨの時の半導体出力回路の消費電力を低減せしめることが可能である。   According to the present invention, the output signal responds at high speed to the input signal, and the power consumption of the semiconductor output circuit can be reduced. In particular, it is possible to reduce the power consumption of the semiconductor output circuit when the input is HIGH.

本発明の実施形態による半導体出力回路の回路図である。1 is a circuit diagram of a semiconductor output circuit according to an embodiment of the present invention. 従来の半導体出力回路の回路図である。It is a circuit diagram of the conventional semiconductor output circuit.

以下、図面を参照しながら本発明の実施形態について詳細に説明する。
図１は、本発明の実施形態による半導体出力回路の回路図である。図１に示した半導体出力回路は、一端が高電位線１００に接続された第１の抵抗１１０と、ベースが入力端子１０に接続され、コレクタが前記第１の抵抗１１０の他端に接続され、エミッタが低電位線１０１に接続される第１のｎｐｎトランジスタ２１０と、一端が高電位線１００に接続された第２の抵抗１２０と、ベースが前記第１の抵抗１１０の他端と前記第１のｎｐｎトランジスタ２１０のコレクタの間のノードＮ１に接続され、コレクタが前記第２の抵抗１２０の他端に接続される第２のｎｐｎトランジスタ２２０と、ベースが定電流源３００に接続され、コレクタが前記第２のｎｐｎトランジスタ２２０のエミッタに接続され、エミッタが前記第１のｎｐｎトランジスタ２１０のコレクタに接続される第３のｎｐｎトランジスタ２３０と、ベースが前記第２のｎｐｎトランジスタ２２０のエミッタと前記第３のｎｐｎトランジスタ２３０のコレクタの間のノードに接続され、コレクタが出力端子２０に接続され、エミッタが低電位線１０１に接続される出力トランジスタ２４０と、を備える。 Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.
FIG. 1 is a circuit diagram of a semiconductor output circuit according to an embodiment of the present invention. The semiconductor output circuit shown in FIG. 1 has a first resistor 110 having one end connected to the high potential line 100, a base connected to the input terminal 10, and a collector connected to the other end of the first resistor 110. A first npn transistor 210 having an emitter connected to the low potential line 101, a second resistor 120 having one end connected to the high potential line 100, a base connected to the other end of the first resistor 110 and the first resistor. A second npn transistor 220 having a collector connected to the other end of the second resistor 120, a base connected to the constant current source 300, and a collector connected to a node N1 between the collectors of one npn transistor 210; Is connected to the emitter of the second npn transistor 220, and the emitter is connected to the collector of the first npn transistor 210. 0, the base is connected to a node between the emitter of the second npn transistor 220 and the collector of the third npn transistor 230, the collector is connected to the output terminal 20, and the emitter is connected to the low potential line 101. Output transistor 240.

図１の回路の動作について以下に説明する。
＜入力がＬＯＷの動作＞
入力がＬＯＷとなる動作を説明する。なお、説明を簡略化するために、低電位線１０１はグラウンド電位とした。また、定電流源３００は数μＡの低い定電流を流す電流源とした。 The operation of the circuit of FIG. 1 will be described below.
<Operation when input is LOW>
An operation in which the input becomes LOW will be described. In order to simplify the description, the low potential line 101 is set to the ground potential. The constant current source 300 was a current source that passed a constant current as low as several μA.

入力端子１０にはＬＯＷの信号が入力され、第１のｎｐｎトランジスタ２１０はオフとなる。よって、ノードＮ１の電位は高電位線１００側に張りついて第２のｎｐｎトランジスタ２２０はオンとなる。第２のｎｐｎトランジスタ２２０がオンすることにより、出力トランジスタ２４０もオンするので、出力端子にはＬＯＷが出力される。   A LOW signal is input to the input terminal 10 and the first npn transistor 210 is turned off. Therefore, the potential of the node N1 sticks to the high potential line 100 side, and the second npn transistor 220 is turned on. When the second npn transistor 220 is turned on, the output transistor 240 is also turned on, so that LOW is output to the output terminal.

このとき、第３のｎｐｎトランジスタ２３０のコレクタ電圧とエミッタ電圧を比較すると、コレクタ電圧は出力トランジスタ２４０のＶＢＥ（飽和領域でのベース−エミッタ間電圧で、一般に約０．７Ｖ）となり、エミッタ電圧は出力トランジスタ２４０のＶＢＥと第２のｎｐｎトランジスタ２２０のＶＢＥを足した電圧（一般に約１．４Ｖ）となる。この電圧の関係により、定電流源３００から供給される定電流は、第３のｎｐｎトランジスタ２３０のベース−コレクタ間のＰＮダイオードを介して出力トランジスタ２４０のベースに流れる。   At this time, when the collector voltage and the emitter voltage of the third npn transistor 230 are compared, the collector voltage is VBE of the output transistor 240 (base-emitter voltage in the saturation region, generally about 0.7 V), and the emitter voltage is A voltage (generally about 1.4 V) is obtained by adding VBE of the output transistor 240 and VBE of the second npn transistor 220. Due to this voltage relationship, the constant current supplied from the constant current source 300 flows to the base of the output transistor 240 via the PN diode between the base and the collector of the third npn transistor 230.

＜入力がＨＩＧＨの動作＞
入力端子１０にＨＩＧＨの信号が入力されると、第１のｎｐｎトランジスタ２１０は飽和領域でオンとなる。よって、ノードＮ１の電位は飽和領域で動作する第１のｎｐｎトランジスタ２１０のコレクタ−エミッタ間電圧（一般に約０．１Ｖ）となるので、第２のｎｐｎトランジスタ２２０はオフとなる。ここで、第３のｎｐｎトランジスタ２３０は定電流源３００からの定電流によってオンの状態を保つため、第３のｎｐｎトランジスタ２３０および第１のｎｐｎトランジスタ２１０のコレクタ−エミッタ間を介して出力トランジスタ２４０のベースから急速に電流を引き抜くので、出力トランジスタ２４０は入力がＨＩＧＨとなったことにより、高速応答でオフとなり、出力端子２０の電位は高電位線１００側に張り付きＨＩＧＨが出力される。 <Operation when input is HIGH>
When a HIGH signal is input to the input terminal 10, the first npn transistor 210 is turned on in the saturation region. Therefore, the potential of the node N1 becomes the collector-emitter voltage (generally about 0.1 V) of the first npn transistor 210 operating in the saturation region, so that the second npn transistor 220 is turned off. Here, since the third npn transistor 230 is kept on by the constant current from the constant current source 300, the output transistor 240 is interposed between the collector and the emitter of the third npn transistor 230 and the first npn transistor 210. Since the current is rapidly drawn from the base of the output transistor 240, the output transistor 240 is turned off with a high-speed response when the input becomes HIGH, and the potential of the output terminal 20 is stuck to the high potential line 100 side and HIGH is output.

そして、入力端子１０にＨＩＧＨの信号が入力されている間は第２のｎｐｎトランジスタ２２０はオフの状態を保持し続けるため、図２に示した従来の半導体出力回路で消費電力を増大させる原因となっていた高電位線から第２の抵抗の経路に流れる電流が、図１に示した本実施形態の半導体出力回路では流れない。従って、消費電力を低減させることが可能となる。   Since the second npn transistor 220 keeps the OFF state while the HIGH signal is input to the input terminal 10, it is a cause of increasing the power consumption in the conventional semiconductor output circuit shown in FIG. The current flowing from the high potential line to the path of the second resistor does not flow in the semiconductor output circuit of this embodiment shown in FIG. Therefore, power consumption can be reduced.

すなわち、本発明の実施形態の半導体出力回路によれば、入力信号に対して出力信号が高速応答し、かつ、入力信号がＨＩＧＨの間に従来の半導体出力回路と比較して大幅な低消費電力動作が実現可能となる。   That is, according to the semiconductor output circuit of the embodiment of the present invention, the output signal responds at high speed to the input signal, and the power consumption is significantly lower than that of the conventional semiconductor output circuit while the input signal is HIGH. Operation becomes feasible.

１０、８７ 入力端子
２０、８８ 出力端子
１００、９０ 高電位線
１０１、９１ 低電位線
１１０、８１ 第１の抵抗
１２０、８３ 第２の抵抗
１３０ 負荷
２１０、８２ 第１のｎｐｎトランジスタ
２２０、８５ 第２のｎｐｎトランジスタ
２３０、８４ 第３のｎｐｎトランジスタ
２４０、８６ 出力トランジスタ
３００ 定電流源 10, 87 Input terminal 20, 88 Output terminal 100, 90 High potential line 101, 91 Low potential line 110, 81 First resistor 120, 83 Second resistor 130 Load 210, 82 First npn transistor 220, 85 First 2 npn transistors 230 and 84 Third npn transistors 240 and 86 Output transistor 300 Constant current source

Claims (1)

一端が高電位線に接続された第１の抵抗と、
ベースが入力端子に接続され、コレクタが前記第１の抵抗の他端に接続され、エミッタが低電位線に接続される第１のｎｐｎトランジスタと、
一端が高電位線に接続された第２の抵抗と、
ベースが前記第１の抵抗の他端と前記第１のｎｐｎトランジスタのコレクタの間のノードに接続され、コレクタが前記第２の抵抗の他端に接続される第２のｎｐｎトランジスタと、
ベースが定電流源に接続され、コレクタが前記第２のｎｐｎトランジスタのエミッタに接続され、エミッタが前記第１のｎｐｎトランジスタのコレクタに接続される第３のｎｐｎトランジスタと、
ベースが前記第２のｎｐｎトランジスタのエミッタと前記第３のｎｐｎトランジスタのコレクタの間のノードに接続され、コレクタが出力端子に接続され、エミッタが低電位線に接続される出力トランジスタと、
を備える半導体出力回路。 A first resistor having one end connected to the high potential line;
A first npn transistor having a base connected to an input terminal, a collector connected to the other end of the first resistor, and an emitter connected to a low potential line;
A second resistor having one end connected to the high potential line;
A second npn transistor having a base connected to a node between the other end of the first resistor and the collector of the first npn transistor, and a collector connected to the other end of the second resistor;
A third npn transistor having a base connected to a constant current source, a collector connected to the emitter of the second npn transistor, and an emitter connected to the collector of the first npn transistor;
An output transistor having a base connected to a node between the emitter of the second npn transistor and the collector of the third npn transistor, a collector connected to an output terminal, and an emitter connected to a low potential line;
A semiconductor output circuit comprising:
JP2011010838A 2011-01-21 2011-01-21 Semiconductor output circuit Pending JP2012151802A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2011010838A JP2012151802A (en) 2011-01-21 2011-01-21 Semiconductor output circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2011010838A JP2012151802A (en) 2011-01-21 2011-01-21 Semiconductor output circuit

Publications (1)

Publication Number Publication Date
JP2012151802A true JP2012151802A (en) 2012-08-09

Family

ID=46793612

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2011010838A Pending JP2012151802A (en) 2011-01-21 2011-01-21 Semiconductor output circuit

Country Status (1)

Country Link
JP (1) JP2012151802A (en)

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS52155955A (en) * 1976-06-18 1977-12-24 Itt Bipolar monolithic integrated pushhpull power output stage circuit
JPS61118022A (en) * 1984-11-14 1986-06-05 Hitachi Ltd Output circuit
JPH01115216A (en) * 1987-10-29 1989-05-08 Mitsubishi Electric Corp Output circuit
US5394038A (en) * 1991-03-16 1995-02-28 Fujitsu Limited Output circuit comprising bipolar transistors for driving CMOS circuit to reduce power consumption of the output circuit and avoid erroneous operation of the CMOS circuit
JPH08191238A (en) * 1995-01-11 1996-07-23 Omron Corp Semiconductor output circuit
JP3126668U (en) * 2006-08-25 2006-11-02 新日本無線株式会社 Output circuit

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS52155955A (en) * 1976-06-18 1977-12-24 Itt Bipolar monolithic integrated pushhpull power output stage circuit
JPS61118022A (en) * 1984-11-14 1986-06-05 Hitachi Ltd Output circuit
JPH01115216A (en) * 1987-10-29 1989-05-08 Mitsubishi Electric Corp Output circuit
US5394038A (en) * 1991-03-16 1995-02-28 Fujitsu Limited Output circuit comprising bipolar transistors for driving CMOS circuit to reduce power consumption of the output circuit and avoid erroneous operation of the CMOS circuit
JPH08191238A (en) * 1995-01-11 1996-07-23 Omron Corp Semiconductor output circuit
JP3126668U (en) * 2006-08-25 2006-11-02 新日本無線株式会社 Output circuit

Similar Documents

Publication Publication Date Title
CN101976095B (en) High-precision band-gap reference source circuit based on emitter current compensation
US7852154B2 (en) High precision follower device with zero power, zero noise slew enhancement circuit
JP2007034506A (en) Power supply circuit
JP2007305010A (en) Reference voltage generation circuit
JP2015118452A (en) Voltage regulator
US9348352B2 (en) Bandgap reference circuit
US9568933B2 (en) Circuit and method for generating a bandgap reference voltage
JP2006311419A (en) Signal output circuit
JP2006270373A (en) Comparator
JP2012151802A (en) Semiconductor output circuit
JP5712624B2 (en) Reference voltage circuit
US20160070288A1 (en) Voltage generation circuit
JP2016187123A (en) Comparator circuit
JP5925465B2 (en) Constant current circuit
TWI714188B (en) Reference voltage generation circuit
JP5785437B2 (en) Regulated voltage power circuit
JP5538170B2 (en) Constant current circuit
CN106786441B (en) A kind of current-limiting circuit and the electric energy meter comprising the current-limiting circuit
JP2010169562A (en) Window comparator circuit
JPH0216810A (en) Transistor circuit
TWI426369B (en) Voltage stabilizing circuit
JP2006127093A (en) Constant voltage regulator circuit
JP2011053765A (en) Overshoot prevention circuit
JP6395663B2 (en) Power circuit
JP2017022506A (en) Output circuit and semiconductor device

Legal Events

Date Code Title Description
A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20131128

A977 Report on retrieval

Free format text: JAPANESE INTERMEDIATE CODE: A971007

Effective date: 20140418

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20140430

A02 Decision of refusal

Free format text: JAPANESE INTERMEDIATE CODE: A02

Effective date: 20140902