JP5712624B2 - Reference voltage circuit - Google Patents

Description

  The present invention relates to a reference voltage circuit. In particular, the present invention relates to a reference voltage circuit having a function of driving a clamp circuit with a reference voltage output from a constant voltage circuit and clamping a power supply voltage of the constant voltage circuit to a low voltage.

  FIG. 11 is a conceptual diagram of a conventional reference voltage circuit. This reference voltage circuit consists of a constant voltage circuit itself. There are various kinds of constant voltage circuits, but one example is a circuit called a bandgap constant voltage circuit, which has a very small temperature dependency of a reference voltage.

  FIG. 12 is a circuit diagram of a conventional reference voltage circuit 500 using a band gap constant voltage circuit. The reference voltage circuit 500 is a constant voltage circuit 51 itself, which is a band gap constant voltage circuit, and includes an amplifier (operational amplifier) 57, resistors R11, R21, and R22, and diodes D11, D12, D21, and D22. It operates with a low voltage power supply 58. Note that reference numeral 56 in the figure denotes grounding.

  FIG. 13 is a detailed circuit diagram of the amplifier 57 of FIG. The amplifier 57 includes three enhancement type PMOSFETs (which are normally-off type p-channel MOSFETs, hereinafter simply referred to as PMOSFETs) 63, 64, 65, two npn transistors 66, 67, one The bias current source 68 and the phase compensation capacitor Cc are used to output the reference voltage Vref from the output of the amplifier 57. The PMOSFETs 63 and 64 constitute a current mirror circuit.

  In FIG. 12, the output of the amplifier 57 is connected to a circuit 71 in which a resistor R11 and diodes D11 and D12 are connected in series, and a circuit 72 in which resistors R21 and R22 and diodes D21 and D22 are connected in series. A connection point 73 between the resistor R11 and the diode D11 is connected to a + terminal (non-inverting input terminal) of the amplifier 57, and a connection point 74 between the resistor R21 and the resistor R22 is connected to a-terminal (inverting input terminal) of the amplifier 57. These diodes can be replaced by npn transistors having collectors connected to the base, as shown in FIG.

  In this constant voltage circuit 51, the amplifier 57 controls resistors R11, R21, R22, and diodes D11, D12, D21, and so on to control the output voltage so that the potentials of the + terminal and the − terminal are equal (imaginary short). The constant voltage circuit 51 is adjusted by adjusting the specifications of D22 to appropriate values (in one example, R11 = R21 = 150 kΩ, R22 = 12 kΩ, and the junction area of D21 and D22 is five times the junction area of D11 and D12). The reference voltage Vref output from the output terminal 54 is a constant voltage independent of the power supply voltage and temperature.

  Further, in Patent Document 1, a voltage / current conversion as shown in FIG. 15 is made possible by using a low voltage manufacturing process amplifier by providing a clamp circuit (high withstand voltage n-channel MOS transistor) with a high voltage power supply. A circuit is disclosed. This voltage-current conversion circuit includes a high voltage n-channel MOSFET controlled by a clamp voltage, a low voltage manufacturing process amplifier, a low voltage n channel MOSFET driven by the low voltage manufacturing process amplifier, and an electric resistance. With this configuration, the voltage-current conversion circuit can be directly applied to a circuit (for example, an LED display unit circuit) that requires a high breakdown voltage, and the manufacturing cost can be reduced.

JP 2009-213098 A

  Since the reference voltage circuit 500 shown in FIG. 12 operates at a low voltage, the PMOSFETs 63, 64, 65 and the npn transistors 66, 67 constituting the amplifier 57 shown in FIG.

  However, if the reference voltage circuit is directly operated by the high voltage power supply 5, an amplifier 57a having a high breakdown voltage is required as shown by a high breakdown voltage reference voltage circuit 500a in FIG. The high withstand voltage amplifier 57a includes high withstand voltage PMOSFETs 63a, 64a and 65a, high withstand voltage npn transistors 66a and 67a, and a high withstand voltage phase compensation capacitor Cch. When high-voltage components are used in this way, the area when the amplifier 57a is integrated on a semiconductor substrate as a semiconductor device (hereinafter simply referred to as area) increases, and the manufacturing cost of the reference voltage circuit increases.

  If a low voltage power source 58 is generated by connecting a clamp circuit using a resistor and a Zener diode in series to the high voltage power source 5, the low withstand voltage reference voltage circuit 500 can be used as it is. A Zener diode having In addition, since the breakdown voltage of the Zener diode has temperature dependence, the voltage Vcc of the low voltage power supply 58 varies depending on the temperature. If the required number of stages are connected in series instead of the Zener diode, the temperature dependence of the power supply voltage Vcc may be further increased. Since the power supply voltage fluctuation removal performance of the amplifier 57 is finite, when the power supply voltage Vcc fluctuates, the reference voltage Vref output from the reference voltage circuit 500 fluctuates. Furthermore, when the withstand voltage of the amplifier 57 and the minimum operating voltage are close and the clamp voltage range is limited, the design itself becomes difficult.

  In addition, in the voltage-current conversion circuit of Patent Document 1, a “clamp voltage” input to the gate terminal of the high-breakdown-voltage n-channel MOSFET (this is not a normal clamp voltage but an ordinary clamp voltage) A separate circuit is required, and its cost and temperature characteristics become a problem. Further, a source follower circuit for the “clamp voltage” is configured by the high breakdown voltage n-channel MOSFET, and the output voltage of this source follower circuit (this is a clamp voltage in the normal sense) is applied to the source terminal of the high breakdown voltage n channel MOSFET. Since the power supply voltage of the connected low voltage circuit is used, the “clamp voltage” must be higher than the power voltage of the low voltage circuit (“clamp voltage” applied to the gate terminal ≧ the power voltage of the low voltage circuit + high Threshold voltage of the n-channel MOSFET). Therefore, the “clamp voltage” applied to the gate terminal cannot be generated only by the low-voltage circuit connected to the source terminal of the high-voltage n-channel MOSFET, and a voltage higher than the power supply voltage of the low-voltage circuit is generated. It is inevitable to provide some kind of circuit.

  SUMMARY OF THE INVENTION An object of the present invention is to solve the above-mentioned problems and to provide a reference voltage circuit connected to a high voltage power supply (for example, a power supply of 6 V or more), which is higher than a reference voltage generated by the reference voltage circuit and changes in temperature. In contrast, it is an object to provide a reference voltage circuit that uses a high-accuracy clamp voltage with small voltage fluctuation as a power supply voltage and realizes the clamp voltage with a small-scale circuit. It is another object of the present invention to suppress the required number of high voltage elements or the current consumption of the reference voltage circuit.

In order to achieve the above object, according to the first aspect of the present invention, a current supply circuit connected to a high voltage power supply and a pull-up current from the current supply circuit via a power supply terminal are provided. comprising a constant voltage circuit for generating supplied with a reference voltage, and a clamp circuit for clamping a voltage of said power supply terminals, said clamp circuit, p-channel MOS transistor in which the reference voltage is input to the gate terminal, Alternatively, a pnp transistor having the reference voltage input to its base terminal is provided, and the clamp voltage for clamping the voltage of the power supply terminal is electrically connected to the reference voltage output from the constant voltage circuit. The gate-source voltage required for the operation or the base-emitter required for the pnp transistor to conduct And Der Ru reference voltage circuit or the sum of the voltages.

According to the invention described in claim 2 of the claim, in the invention described in claim 1, the constant voltage circuit includes a series circuit of a first resistor and a first nonlinear element, and a second circuit. A reference voltage circuit core in which a series circuit of a resistor, a third resistor, and a second nonlinear element are connected in parallel; a voltage applied to the first nonlinear element; and the second nonlinear element and the third resistor A reference voltage circuit having a differential amplifier that amplifies the difference from the total voltage applied to the output and a buffer circuit that supplies current to the reference voltage circuit core based on the output voltage of the differential amplifier.

According to a third aspect of the present invention, in the second aspect , the gate of the p-channel MOS transistor or the base of the pnp transistor of the clamp circuit is replaced with the reference voltage. And a reference voltage circuit to which the output voltage of the differential amplifier is input.

According to the invention described in claim 4 , the buffer circuit supplies current from the high voltage power source to the reference voltage circuit core in the invention described in claim 3 , and The clamp circuit is a reference voltage circuit that bypasses an excess current obtained by subtracting a current flowing through the differential amplifier from the pull-up current to the reference voltage circuit core.

According to a fifth aspect of the present invention, in the fourth aspect , the pull-up current is a reference voltage that increases or decreases in response to an increase or decrease in current consumption of the reference voltage circuit core. A circuit.

According to a sixth aspect of the present invention, a constant voltage circuit for generating a reference voltage and a clamp circuit are provided, and the constant voltage circuit includes a first resistor and a first nonlinear element in series. A reference voltage circuit core in which a series circuit of a circuit, a second resistor, a third resistor, and a second nonlinear element are connected in parallel; a voltage applied to the first nonlinear element; and the second nonlinear element And a differential amplifier that amplifies the difference between the total voltage applied to the third resistor, and the clamp circuit generates a surplus current obtained by subtracting a current flowing through the differential amplifier from a pull-up current. The reference voltage circuit is configured such that the power supply voltage of the constant voltage circuit is clamped to a clamp voltage higher than the reference voltage by the clamp circuit driven based on the reference voltage.

According to the seventh aspect of the present invention, in the sixth aspect of the present invention, the constant voltage circuit is connected to the reference voltage circuit core based on an output voltage of the differential amplifier. A reference voltage circuit having a buffer circuit for supplying current is used.

  According to the present invention, by providing a clamp circuit, even if the supply voltage is high (in the case of a high voltage power supply), the voltage suppressed to the clamp voltage can be used as all or most of the constant voltage circuit. it can. By using the voltage that determines the clamp voltage as the reference voltage output from the constant voltage circuit, there is no need to provide a special circuit for generating the clamp voltage. As a result, it is possible to provide a low-cost reference voltage circuit with a small circuit scale, that is, a circuit area, in which a clamp voltage higher than the reference voltage and having a small voltage fluctuation is used as a power supply voltage. In particular, when the reference voltage and the power supply voltage of the constant voltage circuit are close, and the number of transistors constituting the clamp circuit is small, the characteristics of the power supply voltage (= clamp voltage) become closer to the characteristics of the reference voltage and Therefore, the voltage fluctuation is small and a highly accurate clamp voltage can be obtained, so that the temperature fluctuation of the reference voltage can be reduced.

  Further, by increasing the accuracy of the clamp voltage, it is possible to minimize the influence of fluctuations in the power supply voltage of the reference voltage circuit on the reference voltage, and it is possible to configure a reference voltage circuit with low current consumption and small fluctuations in the power supply voltage.

  In addition, since all the constant voltage circuits are configured to use the clamp voltage as the power supply voltage, the amplifier of the constant voltage circuit can be configured with low breakdown voltage elements, and the number of required high breakdown voltage elements can be suppressed. The circuit area can be reduced, and the cost of the reference voltage circuit can be reduced.

  In addition, the current consumption of the reference voltage circuit can be suppressed by providing the current of the clamp circuit to the reference voltage circuit core.

1 is a conceptual diagram of a reference voltage circuit 100 of the present invention. 1 is a circuit diagram of a reference voltage circuit 100 according to a first embodiment of the present invention. FIG. 3 is a circuit diagram of the current supply circuit of FIG. 2. FIG. 3 is a circuit diagram of the amplifier of FIG. 2. It is a figure which shows the relationship between the source current of PMOSFET9, and the gate-source voltage. It is a circuit diagram of the reference voltage circuit 200 of 2nd Example of this invention. It is a circuit diagram of the amplifier 7a of FIG. It is a figure which shows the relationship between the emitter current and base-emitter voltage of a two-stage pnp transistor. It is a circuit diagram of the reference voltage circuit 300 of 3rd Example of this invention. It is a circuit diagram of the reference voltage circuit 400 of 4th Example of this invention. It is a conceptual diagram of the conventional reference voltage circuit 500. 1 is a circuit diagram of a conventional reference voltage circuit 500. FIG. FIG. 13 is a detailed circuit diagram of the amplifier of FIG. 12. It is the figure explaining replacement to the pn diode of a pnp transistor. 2 is a circuit configuration diagram disclosed in Patent Document 1. FIG. It is a circuit diagram of a constant voltage circuit with a high breakdown voltage. It is a principal part block diagram of the reference voltage circuit 600 of 5th Example of this invention. It is a part (left side) of the concrete circuit diagram of the reference voltage circuit 600 of 5th Example. It is a part (center) of the concrete circuit diagram of the reference voltage circuit 600 of 5th Example. It is a part (right side) of the specific circuit diagram of the reference voltage circuit 600 of 5th Example. It is a principal part block diagram of the reference voltage circuit 700 of 6th Example of this invention. It is a part (left side) of the concrete circuit diagram of the reference voltage circuit 700 of 6th Example. It is a part (center) of the specific circuit diagram of the reference voltage circuit 700 of 6th Example. It is a part (right side) of the specific circuit diagram of the reference voltage circuit 700 of 6th Example.

  Embodiments will be described in the following examples.

  FIG. 1 is a conceptual diagram of a reference voltage circuit according to the present invention. This reference voltage circuit is a reference voltage circuit that can be driven by a high-voltage power supply, and includes a current supply circuit (current source), a constant voltage circuit, and a clamp circuit.

  2 to 4 show the configuration of the reference voltage circuit 100 according to the first embodiment of the present invention. FIG. 2 is an overall circuit diagram, FIG. 3 is a circuit diagram of the current supply circuit of FIG. FIG. 3 is a circuit diagram of the amplifier of FIG. 2. The reference voltage circuit 100 includes a current supply circuit 3, a constant voltage circuit 1, and a clamp circuit 2 as shown in FIG.

  In FIG. 2, the current supply circuit 3 is connected to the high voltage power supply 5, and the power supply terminal 8 of the constant voltage circuit 1 is connected to the current supply circuit 3. The power supply terminal 8 is also connected to the clamp circuit 2. Reference numeral 6 in the figure denotes ground (ground).

  The constant voltage circuit 1 is the same as the conventional reference voltage circuit 500 (= constant voltage circuit 51) shown in FIG. 12, and the power source is a low terminal voltage of the power supply terminal 8, and the amplifier 7 and resistors R11, R21, R22, and , Diodes D11, D12, D21, and D22. These diodes may use npn transistors as shown in FIG.

  The clamp circuit 2 is composed of one PMOSFET 9, the gate terminal G of the PMOSFET 9 is connected to the output terminal 4 of the constant voltage circuit 1, and the source terminal S of the PMOSFET 9 is connected to the power supply terminal 8.

  In FIG. 3, the current supply circuit 3 is composed of two high voltage PMOSFETs 10 and 11 constituting a current mirror circuit and a J-FET 12 (junction voltage effect transistor) for controlling the value of the pull-up current Ipu. The current supply circuit 3 can be realized by simply connecting a resistor between the high-voltage power supply 5 and the power supply terminal 8, but in the case of the circuit configuration of FIG. 3, Ipu is set by the J-FET 12. This is excellent in that it is a constant current and does not depend on the power supply voltage Vcch of the high-voltage power supply 5. Ipu is equal to the sum of the current Io flowing through the constant voltage circuit 1 and the current I1 flowing through the clamp circuit 2. Here, Ipu needs to be a sufficiently larger value in consideration of the current consumption of the constant voltage circuit 1.

  The configuration of the amplifier 7 shown in FIG. 4 is the same as that of the conventional amplifier 57 driven at a low voltage, and three PMOSFETs 13, 14, 15 and two npn transistors 16, 17 and one bias current source. 18 and a phase compensation capacitor Cc for preventing circuit oscillation. The output of the amplifier 7 is connected to the output terminal 4 of the constant voltage circuit 1 to output the reference voltage Vref. In this configuration, since the voltage gain of the amplifier 7 is increased, the phase compensation capacitor Cc is usually added in this manner in order to prevent circuit oscillation.

  The configuration of the reference voltage circuit 100 shown in FIG. 2 is different from that of the conventional reference voltage circuit 500 shown in FIG. 12 in that a current supply circuit is provided between the high voltage power supply 5 of 10V to 30V and the power supply terminal 8 of the constant voltage circuit 1. 3, the constant voltage circuit 1 and the clamp circuit 2 are connected to the power supply terminal 8, and the pull-up current Ipu is supplied from the current supply circuit 3 to the constant voltage circuit 1 and the clamp circuit 2.

The clamp circuit 2 is a source follower circuit which receives the reference voltage Vref, the voltage of the power supply terminal 8 (power supply voltage Vcc) is, the clamp circuit 2, the level shift voltage Vlsm and the gate-source voltage _{V GS} of PMOSFET9 Clamped to the sum of the reference voltage Vref. Level shift voltage Vlsm is the gate-source voltage _{V GS} when I1 flows through the PMOSFET9 as shown in FIG. This voltage V _GS exceeds the threshold voltage Vgth of the PMOSFET 9 by an overdrive voltage necessary for flowing the current I1.

  In order to obtain the power supply voltage Vcc for operating the constant voltage circuit 1, it is necessary to set the voltage Vcc of the power supply terminal 8 within a predetermined range, and when the difference between the power supply voltage Vcc and the reference voltage Vref is large. Therefore, it is necessary to increase the level shift voltage by increasing the number of stages of transistors constituting the clamp circuit 2 (however, as the number of stages increases, the temperature dependence of the clamp voltage increases due to the temperature characteristics of the transistor. It is preferable to select the number of stages so that the minimum power supply voltage Vcc at which 1 operates is obtained). In the first embodiment, since the amplifier 7 operates normally with the power supply voltage of Vref + Vlsm, the clamp circuit is configured only by the PMOSFET 9.

  Here, the operation of the reference voltage circuit 100 of the present invention will be described. The voltage Vcc is applied from the high voltage power supply Vcch to the power supply terminal 8 of the constant voltage circuit 2 through the current supply circuit 3. This voltage Vcc is also applied to the clamp circuit 2. The constant voltage circuit 1 starts operation, Io flows through the constant voltage circuit 1, and the reference voltage Vref is output from the output terminal 4 of the constant voltage circuit 1. This reference voltage Vref is applied to the gate terminal G of the PMOSFET 9. This reference voltage Vref is determined by the amplifier 7 constituting the constant voltage circuit 1, resistors R11, R21, R22 and diodes D11, D12, D21, D22.

When the reference voltage Vref to the gate terminal G of PMOSFET9 is applied, is applied as the power supply voltage Vcc and the difference between the reference voltage Vref is PMOSFET9 gate terminal G and the source S the gate-source voltage _{V GS} between, conduction PMOSFET9 And I1 flows. Here, the sum of I1 and Io becomes the pull-up current Ipu controlled by the J-FET 12.

When the PMOSFET 9 starts to conduct, the clamp circuit 2 operates as a source follower. As described above, the gate-source voltage V _GS of the PMOSFET 9 is an overdrive for flowing the threshold voltage Vgth of the PMOSFET 9 and I1 = Ipu−I0. Sum of voltage. This sum voltage becomes the level shift voltage Vlsm, and the threshold voltages Vgth, Ipu and I0 of the PMOSFET 9 are constant values, so that the level shift voltage Vlsm also becomes a constant voltage.

  Since the clamp voltage Vs is the sum of the reference voltages Vref and Vlsm, the clamp voltage Vs is also a constant voltage that does not depend on the voltage Vcch of the high voltage power supply 5. The power supply voltage Vcc of the constant voltage circuit 1 is clamped by the clamp voltage Vs and does not depend on the voltage Vcch of the high voltage power supply 5.

  In the reference voltage circuit 100, a high voltage element is required as an element constituting the current supply circuit 3. However, since the constant voltage circuit 1 and the clamp circuit 2 can be composed of low voltage elements, the constant voltage circuit 1 includes a high voltage element. Compared to a reference voltage circuit that can be driven at a high voltage using the circuit, the circuit area can be reduced. For example, when a high voltage element is used in the constant voltage circuit 1, five PMOSFETs 13, 14, 15 and two pnp transistors 16, 17 are used as high voltage elements, and the phase compensation capacitor Cc has a high voltage. Must be converted. On the other hand, in the current supply circuit 3, the two PMOSFETs 10 and 11 and the one J-FET 12 need only be three high breakdown voltage elements, and the circuit area can be halved.

  As described above, by adding the current supply circuit 3 and the clamp circuit 2 to the conventional constant voltage circuit 51, it can be driven by the high voltage power source 5, the voltage fluctuation is small, the circuit area can be reduced, and the manufacturing cost is reduced. Therefore, it is possible to provide the reference voltage circuit 100 capable of achieving the above.

  Next, reference voltage circuits 200 to 400 when the circuit configurations of the constant voltage circuit 1 and the clamp circuit 2 in FIG. 2 are different will be described in the following embodiments.

6 and 7 show the configuration of the reference voltage circuit 200 according to the second embodiment of the present invention. FIG. 6 is an overall circuit diagram, and FIG. 7 is a circuit diagram of the amplifier of FIG.
2 and 4 is that the circuit configuration of the clamp circuit 2a (the gate and the drain of the PMOSFET 9a are short-circuited, a two-stage pnp transistor 19 is connected to the drain, and the gate of the two-stage pnp transistor 19 is a constant voltage) It is connected to the output terminal 4 of the circuit 1a, where the two-stage pnp transistor 19 constitutes an emitter follower circuit), and the circuit configuration of the amplifier 7a (the source configured by the PMOSFET 15 in the amplifier 7) The ground amplification stage is changed to an emitter follower by npn transistors 21 and 22 connected in Darlington, and the phase compensation capacitor Cc is unnecessary.) The operation principle of the constant voltage circuit is the same. Here, the change in the circuit configuration of the clamp circuit 2a is to respond to the increase in the required power supply voltage Vcc accompanying the change in the circuit configuration from the amplifier 7 to the amplifier 7a. 6, even when a large current flows through a load (not shown) connected to the output terminal 4, the voltage fluctuation of the reference voltage Vref can be suppressed smaller than in the case of FIG. 2. .

In the clamp circuit 2a, the level shift voltage Vls level shift when I1 flows through the level shift voltage VLSM (= inter PMOSFET9a gate-source voltage _{V GS)} and two stages of the pnp transistor 19 when I1 flows in PMOSFET9a This is the sum of the voltage Vlsb (= base-emitter voltage V _{BE of the} two-stage pnp transistor).

FIG. 8 is a diagram showing the relationship between the emitter current of the two-stage pnp transistor 19 and the base-emitter voltage.
The base-emitter voltage V _BE of the two-stage pnp transistor 19 is a forward voltage drop generated at the two-stage p _{En B} junction due to I1 flowing through the two-stage pnp transistor 19, and this is the two-stage pnp transistor The level shift voltage Vlsb is obtained by the emitter follower circuit 19.

  Therefore, the clamp voltage Vs includes the reference voltage Vref output from the constant voltage circuit 1a, the gate-source voltage (level shift voltage Vlsm) when I1 flows through the PMOSFET 9a, and the base-emitter voltage of the two-stage pnp transistors. The voltage is determined by (level shift voltage Vlsb). With this clamp voltage Vs, the power supply voltage Vcc of the constant current circuit 1a is clamped and becomes a constant voltage.

  If the constant voltage circuit 1a is directly driven by the high voltage power supply 5 without going through the current supply circuit 3, the two PMOSFETs 13 and 14 and the four pnp transistors 16, 17, 21, All 22 must be high voltage elements. By applying the reference voltage circuit 200 of the present invention, these six elements may be low withstand voltage elements, and the circuit area can be halved.

  FIG. 9 is a circuit diagram of a reference voltage circuit 300 according to the third embodiment of the present invention. The constant voltage circuit 1b includes three PMOSFETs 23, 24, and 25, two NMOSFETs 26 and 27, resistors R41 and R51, and diodes D31, D32, D41, D42, D51, and D52.

  Here, in order to simplify the description, the PMOSFETs 23, 24, and 25 and the NMOSFETs 26 and 27 have the same size. Therefore, an equal current flows through the PMOSFETs 23, 24, and 25 that constitute the mirror circuit. This current value is controlled so that the source potential of the NMOSFETs 26 and 27, that is, the voltage applied to the series connection circuit of D31 and D32 is equal to the voltage applied to the series connection circuit of R41, D41 and D42. Further, the current output from the PMOSFET 25 flows through the series connection circuit of R51, D51, and D52, and generates the reference voltage Vref. Here, the specifications of the resistors R41, R51 and the diodes D31, D32, D41, D42, D51, D52 are appropriate values (in one example, R41 = 12 kΩ, R51 = 150 kΩ, and the junction area between D41 and D42 is D31). , D32, D51, and D52), the reference voltage Vref output from the output terminal 4 of the constant voltage circuit 1b becomes a constant voltage that does not depend on the power supply voltage or temperature.

  Since the constant voltage circuit 1b can sufficiently operate with a power supply voltage of Vref + Vlsm, the clamp circuit 2 corresponding to this is composed of one PMOSFET 9 and is the same as in the case of FIG.

  In this case as well, the clamp circuit 2 clamps the power supply voltage Vcc of the constant voltage power supply 1b to the clamp voltage Vs (= Vref + Vlsm).

FIG. 10 is a circuit diagram of a reference voltage circuit 400 according to the fourth embodiment of the present invention. The constant voltage circuit 1 c is composed of one depletion type NMOSFET (normally on n channel MOSFET) 28 and one enhancement type NMOSFET 29. Here, the depletion type NMOSFET 28 in which the gate and the source are connected and the gate-source voltage V _GS is zero operates as a constant current source, and the enhancement type NMOSFET 29 operates as a load for converting this current into a reference voltage. . A constant voltage having a small temperature dependency can be obtained by adjusting the size so that the temperature dependencies of the two cancel each other.

  Since the constant voltage circuit 1c can sufficiently operate with a power supply voltage of Vref + Vlsm, the clamp circuit 2 corresponding to this is composed of one PMOSFET 9 and is the same as in the case of FIG.

Also in this case, the power supply voltage Vcc of the constant voltage power supply 1c is clamped to the clamp voltage Vs (= Vref + Vlsm) by the clamp circuit 2.
In each of the embodiments described above, the clamp circuit 2 uses the PMOSFET 9, but the PMOSFET 9 may be replaced with a pnp transistor whose emitter terminal is connected to the power supply terminal 8. In that case, the level shift amount Vlsm in the clamp circuit 2 becomes the emitter-base voltage of the pnp transistor. Further, the pnp transistor may be a Darlington transistor, or a diode or a PMOSFET whose gate and drain are short-circuited may be connected between the power supply terminal 8 and the emitter terminal of the pnp transistor.

  For the clamp circuit 2a, the two-stage pnp transistor may be replaced with a PMOSFET. In that case, a plurality of PMOSFETs whose gates and drains are short-circuited may be connected in series instead of one to ensure a total level shift amount. Furthermore, the PMOSFET whose gate and drain are short-circuited may be replaced with a diode.

  FIGS. 17 and 18 to 20 are configuration diagrams of the reference voltage circuit according to the fifth embodiment of the present invention. FIG. 17 is a block diagram of the principal part, and FIGS. Each circuit diagram is shown. The difference between FIGS. 18 to 20 and FIG. 6 is that diodes D11, D12, D21, and D22 are changed to npn transistors Q08, Q09, Q10, and Q11 in which the base terminal and the collector terminal are short-circuited, and are not shown in FIG. The start circuit 32 is shown, a specific circuit of the current supply circuit 31 (current mirror circuit A (37) and JFET 38) is shown, and the clamp circuit 2a is changed to the configuration of the clamp circuit 36. .

  In FIG. 17, the amplifier 7 a of FIG. 6 is divided into a differential amplifier 33 and a buffer circuit 34. Here, the consumption current of the differential amplifier 33 is indicated by Ia, and the consumption current of the buffer circuit 34 is indicated by Ib. In this embodiment, the sum of Ia and Ib corresponds to Io in FIG. Further, the power supply terminal 8a (voltage Vcca) of the differential amplifier 33 shown in FIG. 19 and the power supply terminal 8b (voltage Vccb) of the buffer circuit 34 shown in FIG. 20 are common, and these are the constant voltage circuit of FIG. Corresponds to (a part of) the power supply terminal 8. In FIG. 17, the parts corresponding to the resistors R11, R21, R22 and the diodes D11, D12, D21, D22 of the constant voltage circuit 1a of FIG. 6 are collectively shown as a reference voltage circuit core 35.

  18 to 20 are circuits in which the reference voltage circuit 600 is divided into three, FIG. 18 is a circuit diagram on the left side, FIG. 19 is a circuit diagram on the center, and FIG. 20 is a circuit diagram on the right side. In each figure, symbols (alphabets) attached to the ends of arrows are connected to each other.

  In FIG. 18, the current mirror circuit A37 includes p-channel MOSFETs M01, M02, and M03. Further, the current supply circuit 31 includes M01 and M03 of the current mirror circuit A37 and a JFET 38 (junction field effect transistor), and a startup circuit 32 not shown heretofore is shown.

  In FIG. 19, the differential amplifier 33 includes p-channel MOSFETs M04 and M05, and npn transistors Q03, Q04, and Q05. These M04, M05, Q03, Q04, and Q05 correspond to reference numerals 13, 14, 16, 17, and 18 in FIG.

In FIG. 20, the buffer circuit 34 includes npn transistors Q06 and Q07 connected in a Darlington connection, and corresponds to reference numerals 21 and 22 in FIG.
The reference voltage circuit core 35 is a part that determines the output voltage of the reference voltage circuit 600, and is composed of resistors R11, R21, R22, and Q08, Q09, Q10, Q11 which are npn transistors whose base terminals and collector terminals are short-circuited. Q08, Q09, Q10, and Q11 correspond to D11, D12, D21, and D22 of FIG. 6, respectively.

  The clamp circuit 36 is composed only of M06, which is a p-channel MOSFET in which the gate terminal is connected to the output of the differential amplifier 33. The drain terminal of M06 is connected to the power supply terminals of the constant voltage circuit (that is, the power supply terminals 8a and 8b of the differential amplifier 33 and the buffer circuit 34), and the source terminal of M06 is connected to the ground terminal.

  In FIG. 18, although the gate of JFET 38 is not shown in the figure, the gate is connected to GND and has a constant voltage. Therefore, even if the source-drain voltage of JFET 38 changes, the flowing current is almost constant and functions as a constant current element. ing.

  The function of the starting circuit 32 is to prevent the current from flowing through Q03, Q04, and Q05 constituting the differential amplifier 33 and preventing the reference voltage Vref from being settled. In such a state, since no current flows through Q02, the drain current of M02 lifts the base terminal of Q01 and tries to flow current into Q01. When a current flows through Q01, the current is injected into the base of Q06. As a result, current is supplied to the reference voltage circuit core 35 via Q06 and Q07, and Vref rises. Rises and collector current flows.

When the collector current of Q02 exceeds the drain current of M02, the base potential of Q01 decreases and Q01 is cut off (at this point, Vref is controlled by the differential amplifier 33).
M07, which is an n-channel MOSFET, is provided for the purpose of preventing the collector potential of Q02 from falling and entering the saturation region (when Q02 operates in the saturation region, the base current of Q02 increases, so that Vref To affect). As a result, of the collector current of Q02, the current excluding the drain current of M02 is supplied via M07, and the decrease in the collector potential of Q02 is caused by Vref−Vgs7 (Vgs7: gate necessary for flowing the current through M07). -Saturation of the collector-emitter voltage Vce2 of Q02 can be prevented.

  17 and 18 to 20, the reference voltage circuit core 35 includes a resistor R11 and a series circuit of Q08 and Q09 of npn transistors that are nonlinear elements, and resistors R21 and R22 and Q10 and Q11 of npn transistors that are nonlinear elements. It is constituted by a series circuit. The differential amplifier 33 includes n03 transistors Q03, Q04, Q05 and p-channel MOSFETs M04, M05. The differential amplifier 33 operates such that V1 and V2 of the reference voltage circuit core 35 are equalized (V1 and V2 are virtually short-circuited) through a buffer circuit 34 constituted by emitter followers of Q06 and Q07 which are npn transistors. The output voltage (reference voltage Vref) of the reference voltage circuit is controlled at the point. The reference voltage Vref is determined only by the resistance value of the resistor used for the reference voltage circuit core 35 and the area of the npn transistor. By appropriately adjusting these values, the temperature change of the reference voltage Vref can be reduced.

  Here, the power supply of the differential amplifier 33 and the buffer circuit 34 is supplied from a current supply circuit 31 including a JFET 38 and a current mirror circuit A37 (configured by M01, M02 and M03 which are P-channel MOSFETs) and M06 which is a p-channel MOSFET. It is comprised by the clamp circuit 36 which becomes.

  The clamp circuit 36 extracts the excess surplus current that is not consumed by the differential amplifier 33 and the buffer circuit 34 from the pull-up current Ipu supplied by the current supply circuit 31, thereby reducing the power supply voltage of the differential amplifier 33 (high voltage). Not) Maintain a generally constant value. For this reason, the differential amplifier 33 can be configured without using a high voltage element, and the circuit area can be reduced. Further, even if the voltage Vcch of the high voltage power supply 5 of the reference voltage circuit 600 changes, the voltage Vcca of the power supply terminal 8a of the differential amplifier 33 does not change, so that the dependency of the reference voltage Vref on the power supply voltage (Vcch) can be reduced. .

  The clamp circuit 36 uses the fact that the output voltage Vao of the differential amplifier 33 is higher than the reference voltage Vref by the sum of the base-emitter voltages of the npn transistors Q06 and Q07 constituting the buffer circuit 34. 6, two pnp transistors (19) are reduced compared to the configuration of the clamp circuit 2a of FIG. 6 (in addition to operating the clamp circuit directly using the reference voltage as in this embodiment, the reference voltage Is also included in the scope of the present invention).

  In the reference voltage circuit 600, the pull-up current Ipu is generated by the JFET 38. Since the current Ir required by the reference voltage circuit core 35 has a positive temperature characteristic, the current of the JFET 38 has a negative temperature characteristic, and furthermore, the manufacturing process variation of the JFET 38 is relatively large. The voltage circuit 600 requires attention during design.

  Therefore, in the reference voltage circuit 600, the value of the pull-up current Ipu is set to a value sufficiently larger than the total current consumption (Ia + Ib) of the differential amplifier 33 and the buffer circuit 34 in consideration of a margin due to temperature and process variation. There is a need. On the other hand, the surplus current is discarded to the GND via the clamp circuit 36, so that the current consumption increases. A method for solving this will be described in the sixth embodiment.

  FIGS. 21 and 22 to 24 are block diagrams of the reference voltage circuit according to the sixth embodiment of the present invention. FIG. 21 is a block diagram of the main part of the reference voltage circuit 700, and FIGS. 22 to 24 are reference voltage circuits. A specific circuit diagram of 700 is shown respectively. 22 to 24 are circuits in which the reference voltage circuit 700 is divided into three, FIG. 22 is a circuit diagram on the left side, FIG. 23 is a circuit diagram on the center, and FIG. 24 is a circuit diagram on the right side. In each figure, symbols (alphabets) attached to the ends of arrows are connected to each other.

  The difference between the reference voltage circuit 700 of FIGS. 21 to 24 and the reference voltage circuit 500 of FIGS. 17 to 20 is that the configuration of the clamp circuit 46 and the power supply terminal 8b of the buffer circuit 44 are directly connected to the high voltage power supply 5. And a current mirror circuit B (47b) for generating a pull-up current Ipu according to the current Ir flowing through the reference voltage circuit core 45 is added. The current supply circuit 41 includes a current mirror circuit A (47a), a current mirror circuit B (47b), and a JFET 48.

  In FIG. 24, the clamp circuit 46 is configured only by M11 which is a p-channel MOSFET in which the output Vao of the differential amplifier 43 is connected to the gate terminal, and the drain terminal and the source terminal thereof are the power source 8a of the differential amplifier 43. And the output terminal 4 of the reference voltage circuit.

  As a result, of the pull-up current Ipu, a current that is not consumed by the differential amplifier 43 (surplus current Ipu−Ia = clamp current I1) is supplied to the reference voltage circuit core 45 via M11. At this time, the voltage Vcca at the power supply terminal of the differential amplifier 43 is higher than the output voltage Vao of the differential amplifier 43 by the amount of the gate-source voltage | Vgs11 | of M11 necessary to flow the surplus current Il. Clamped to Vao + | Vgs11 |. Note that the configuration of the clamp circuit 46 shown here is an example, and the differential amplifier 43 can be set to normalize the power supply voltage Vcca of the differential amplifier 43 by flowing the surplus current of the pull-up current Ipu to the reference voltage circuit core 45. Other circuit configurations may be used as long as they are maintained within the operating range.

  The collector terminals of Q06 and Q07 constituting the buffer circuit 44 are directly connected to the high voltage power supply 5, and current is supplied from the high voltage power supply 5 to the reference voltage circuit core 45 via the buffer circuit 43. Yes.

  As a result, of the current Ir required for the reference voltage circuit core 45, the shortage that is not supplied via the clamp circuit 46 is supplied from the buffer circuit 44. Note that the configuration of the buffer circuit 44 shown here is an example, as long as the current Ib supplied from the high voltage power supply 5 to the reference voltage circuit core 45 can be adjusted according to the output voltage Vao of the differential amplifier 43. Other circuit configurations may be used.

  In this reference voltage circuit 700, the pull-up current Ipu needs to be larger than the consumption current Ia of the differential amplifier 43 and smaller than the sum of the current Ir and the current Ia required by the reference voltage circuit core 45. .

  In the present embodiment, it is assumed that the gain of the differential amplifier 43 is sufficiently high and a virtual ground of V1 = V2 is established. In FIG. 24, if R11 = R12, the voltages at both ends of the resistors R11 and R21 are equal, so the current flowing through R11 and the current flowing through R21 are equal to 0.5 Ir. If the emitter area ratio between Q05 and Q11 is 1: 5 (x1 and x5 in FIGS. 23 and 24 indicate that the emitter area ratio between Q05 and Q11 is 1: 5). “Ia = 0.2 × 0.5 × Ir = 0.1Ir”, and Ipu = Ia = 0.1Ir is the lower limit current value at which the differential amplifier 43 operates normally. On the other hand, when Ipu exceeds Ia + Ir = 1.1Ir, the reference voltage Vref cannot be controlled by the differential amplifier 43, and the reference voltage circuit 700 does not operate normally. Therefore, in order for the reference voltage circuit 700 to operate normally, it is necessary to set the pull-up current Ipu so that “0.1Ir <Ipu <1.1Ir” is always satisfied.

  In the present embodiment, a circuit that is proportional to Ipu and Ir is disclosed as a circuit that can easily satisfy the constraints existing between Ipu and Ir even if there is a change in temperature or process. This will be described below.

First, in FIG. 22, the startup circuit 42 has the same configuration as the startup circuit 32 of FIG. 8, but the connection partner of the drain terminal of M07 is different.
In the reference voltage circuit 700 of FIGS. 22 to 24, the current mirror circuit B (47b) composed of p-channel MOSFETs M08, M09, and M10 has the drain terminal of M07 connected to the gate terminal and the drain terminal. The current received at M08 and proportional to the current is output from the drain terminals of M09 and M10. The drain terminal of M10 is connected to the input terminal of the current mirror circuit A (47a) (the terminal where the drain terminal of M01 and the gate terminals of M01, M02, and M03 are connected) and operates as a constant current source. The current is preferentially supplied to the JFET 48. Therefore, when the drain current of M07 increases and the drain current of M10 increases, the drain current of M03 decreases.

  Here, if the mirror ratio of each p-channel MOSFET in the current mirror circuits A and B (47a, 47b) is set appropriately, the current of the current mirror circuit A (47a) finally becomes 0, and the collector of Q02 It is possible to stabilize the state where all currents are supplied to the current mirror circuit B (47b) via M07. At this time, since the sum of the drain current of M02 of the current mirror circuit A (47a) and the drain current of M09 of the current mirror circuit B (47b) is the pull-up current Ipu, the former is 0 and the latter is proportional to Ir. Current (in this embodiment, since the emitter area ratio of Q02 and Q09 is 1: 1, 0.5Ir), Ipu is proportional to Ir.

  Further, the mirror ratio of each p-channel MOSFET of the current mirror circuits A and B (47a and 47b) and the relationship between Ir and Ipu will be described. Here, the mirror ratio of M02 and M03 to M01 is a2 and a3, and the mirror ratio of M09 and M10 to M08 is a9 and a10. A constant current flowing through the JFET 48 is assumed to be I00.

  First, in order for M07 to conduct and current to be supplied to M08, it is necessary to design so as to satisfy “a3 · I00 <0.5Ir”. However, a3 is set large enough not to cause a start-up failure. When the current is supplied to M08, the current supplied to the current mirror circuit A (47a) via M10 decreases, and as a result, the drain current of M03 decreases, so that the current flowing through M08 further increases. To go. Here, if a10 is set so that a10 · 0.5Ir ≧ Ioo, the current supplied to the current mirror circuit A (47a) is settled to be zero. At this time, all of the collector current Ic2 of Q02 (= 0.5Ir in this embodiment) is supplied to M08, and “Ipu = a09 · Ic2”. The value of a09 is set so that Ipu falls within a predetermined range (in this embodiment, “0.1Ir <Ipu <1.1Ir”). As for a02, it is preferable to set “a02 = a09 / a10” so that the current flowing through the current mirror circuit B (47b) does not increase to reduce Ipu. This is due to the following reason.

That is, when the current flowing through the transistor M08 is I8, the following equation is established for the current Ipu.
Ipu = a09 · I8 + a02 (I00−a10 · I8)
= A02 · I00 + (a09-a02 · a10) I8
Thus, if a02 = a09 / a10, the current Ipu is not affected by I8.

  In the reference voltage circuit 700 of FIGS. 22 to 24, the current of the clamp circuit 46 flows to the reference voltage circuit core 45 instead of GND, so that the consumption current is smaller than that of the reference voltage circuit 600 of FIGS. can do. Further, by using a circuit that increases / decreases the pull-up current Ipu in accordance with the increase / decrease of the consumption current Ir of the reference voltage circuit core 45, constraints on Ipu and Ir that occur in the reference voltage circuit 700 of FIGS. It is easy to satisfy.

  For reference, if the currents flowing through the transistors M01 to M03 and M08 to M10 are I1 to I3 and I8 to I10, respectively, the following equations are established. However, since the currents I1 to I3 and I8 to I10 flow only in one direction, there are constraints such as I1 ≧ 0, I2 ≧ 0, I3 ≧ 0, I8 ≧ 0, I9 ≧ 0, and I10 ≧ 0. It is necessary to set the value to zero in the region where does not flow in the forward direction.

I3 + I8 = KIr (current flowing in Q02, K = 0.5)
I1 + I10 = I00
I2 = a2 · I1
I3 = a3 · I1
I9 = a9 · I8
I10 = a10 · I8
From these equations, the following equations hold.

I1 = (I00-a10 · KIr) / (1-a3 · a10)
I8 = (KIr-a3 · I00) / (1-a3 · a10)
Ipu = I2 + I9
= A2 · I1 + a9 · I8
= {(A2-a3 * a9) I00 + (a9-a2 * a10) KIr} / (1-a3 * a10)

1, 1a, 1b, 1c Constant voltage circuit 2, 2a Clamp circuit 3 Current supply circuit 4 Output terminal 5 High voltage power supply 6 Ground (ground)
7, 7a Amplifier 8 Power supply terminal 8a Power supply terminal of differential amplifier 8b Power supply terminal of buffer circuit 9, 9a PMOSFET
10,11 High voltage PMOSFET
12 J-FET
13, 14, 15, 23, 24, 25 PMOSFET
16, 17 npn transistor 18 Bias current source 19 Two-stage pnp transistor 21, 22 pnp transistor 26, 27, 29 NMOSFET
28 Depletion type NMOSFET
31, 41 Current supply circuit 32, 42 Start-up circuit 33, 43 Differential amplifier 34, 44 Buffer circuit 35, 45 Reference voltage circuit core 36, 46 Clamp circuit 37, 47a Current mirror circuit A
38,48 JFET (junction field effect transistor)
47b Current mirror circuit B
100, 200, 300, 400, 600, 700 Reference voltage circuit (reference voltage circuit of the present invention)
Cc Phase compensation capacitor Ipu Pull-up current Vcch Power supply voltage of high voltage power supply Vcc Power supply voltage of constant voltage circuit Vref Reference voltage Vs Clamp voltage Vls Level shift voltage Vlsm Level shift voltage (PMOSFET)
Vlsb level shift voltage (two-stage pnp transistor)
R11, R21, R22, R41, R51 resistors D11, D12, D21, D22, D31, D32, D41, D42,
D51, D52 Diode M01-M06, M08-M11 p-channel MOSFET
M07 n-channel MOSFET
Q01 to Q11 npn transistor I00 Current flowing in JFET Vcca Voltage of power supply terminal of differential amplifier Vccb Voltage of power supply terminal of buffer circuit Vao Output voltage of differential amplifier

Claims (7)

A current supply circuit connected to a high voltage power supply;
A constant voltage circuit that generates a reference voltage by supplying a pull-up current from the current supply circuit via a power supply terminal;
A clamp circuit for clamping a voltage of said power supply terminals,
Comprising
The clamp circuit includes a p-channel MOS transistor to which the reference voltage is input to its gate terminal, or a pnp transistor to which the reference voltage is input to its base terminal, and a clamp voltage at which the voltage of the power supply terminal is clamped Is a reference voltage output from the constant voltage circuit and a gate-source voltage required for the p-channel MOS transistor to be conductive, or a base-emitter voltage required for the pnp transistor to be conductive. reference voltage circuit, characterized in der Rukoto than the sum of. The constant voltage circuit includes a reference voltage circuit core in which a series circuit of a first resistor and a first nonlinear element, and a series circuit of a second resistor, a third resistor, and a second nonlinear element are connected in parallel. A differential amplifier that amplifies a difference between a voltage applied to the first nonlinear element and a total voltage applied to the second nonlinear element and the third resistor, and an output voltage of the differential amplifier, The reference voltage circuit according to claim 1, further comprising a buffer circuit that supplies a current to the reference voltage circuit core. 3. The reference voltage circuit according to claim 2 , wherein an output voltage of the differential amplifier is input to the gate of the p-channel MOS transistor or the base of the pnp transistor of the clamp circuit instead of the reference voltage. . The buffer circuit supplies a current from the high-voltage power source to the reference voltage circuit core, and the clamp circuit generates a surplus current obtained by subtracting a current flowing through the differential amplifier from the pull-up current. The reference voltage circuit according to claim 3 , wherein the reference voltage circuit is bypassed to the core. The reference voltage circuit according to claim 4 , wherein the pull-up current increases or decreases in accordance with an increase or decrease in current consumption of the reference voltage circuit core. Comprising a constant voltage circuit and a clamp circuit for generating a reference voltage;
The constant voltage circuit includes a reference voltage circuit core in which a series circuit of a first resistor and a first nonlinear element, and a series circuit of a second resistor, a third resistor, and a second nonlinear element are connected in parallel. A differential amplifier that amplifies a difference between a voltage applied to the first nonlinear element and a total voltage applied to the second nonlinear element and the third resistor;
The clamp circuit bypasses a surplus current obtained by subtracting a current flowing through the differential amplifier from a pull-up current to the reference voltage circuit core,
The reference voltage circuit, wherein a power supply voltage of the constant voltage circuit is clamped to a clamp voltage higher than the reference voltage by the clamp circuit driven based on the reference voltage. The reference voltage circuit according to claim 6 , wherein the constant voltage circuit includes a buffer circuit that supplies a current to the reference voltage circuit core based on an output voltage of the differential amplifier.