JPH01115216A - Output circuit - Google Patents

Abstract

PURPOSE:To decrease a constant current supplied from a constant current source to the control electrode of an output transistor and to obtain an efficient output circuit with a low power consumption by providing a current mirror circuit to give a current in accordance with an output current to the control electrode of the output transistor. CONSTITUTION:When a prescribed current is supplied to the base of a transistor(Tr) Q1 from an input terminal 1, the Tr Q1 is turned on, a constant current I0 of a constant current source 2 is caused to flow in a GND, and since the constant current I0 is hardly caused to flow in an output Tr Q2, the Tr Q2 is turned off At this time, since a Tr Q3 is also turned off, a current mirror circuit 5 is not operated. On the other hand, when the current from the terminal 1 is cut, the Tr Q3 is turned on, and a collector current is outputted to the collector of the Tr Q2. At this time, it is necessary to supply a prescribed base current to the base of the Tr Q3 in order to obtain a prescribed collector current. Since this base current is the sum of the collector current of a Tr Q5 of the current mirror circuit 5 and the constant current I0, the constant current I0 can be minimized, and as a result, a circuit voltage when the Tr Q2 is an OFF state can be decreased.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an output circuit used in an output stage of an electronic circuit.

[Conventional technology]

FIG. 3 is a circuit diagram showing a conventional output circuit.

In the figure, Ql is an NPN transistor whose base is connected to input terminal 1 and whose collector is connected to power supply V via constant current source 2.

0, and their emitters are grounded. Q2 is an output transistor consisting of an NPN transistor,
The base is connected to the collector of the NPN transistor Q2, the collector is connected to the output terminal 3, and the emitter is grounded.

Next, the operation will be explained. Connect NPN transistor Q1 to the base of NPN transistor Q1 from input terminal 1.
When sufficient current is supplied to cause the ONL constant current source 2 to flow, the NPN transistor Q1 receives the constant current I from the ONL constant current source 2. is GN
Since almost no current is supplied to the base of the NPN transistor Q2, the output transistor Q2 is
It is in the FF state.

Next, when the current supplied from input terminal 1 to the base of NPN transistor Q1 is cut, NPN transistor Q1 is turned off, so output 1 to transistor Q2
A constant current I from a constant current source 2 is applied to the base of the constant current source 2. is supplied,
Output transistor Q2 is turned on. In this case, the collector current I of the output transistor Q2. 2 is, assuming that the common emitter current amplification factor of the output transistor Q2 is h.
G [2 1=h i ...(1) C2
It becomes FE O. This collector current of 1°2 is output to the output terminal 3.

[Problem that the invention seeks to solve]

Since the conventional output circuit is configured as described above, the constant current IO from the constant current source 2 always flows through the output circuit regardless of whether the output transistor Q2 is ON or OFF, resulting in high power consumption and low efficiency. The problem was that it was bad.

This invention was made to solve the above-mentioned problems, and aims to reduce the constant current of a constant current source, reduce power consumption, and obtain an efficient output circuit.

[Means for solving problems]

The output circuit according to the present invention includes a constant current source that supplies a constant current to a control electrode of an output transistor, and a constant current source that is turned on according to an input signal.
/OFFt,, when ON, the constant current from the constant current source is G
a first transistor that leads to ND and turns off the output transistor;
In an output circuit having a transistor, the output transistor and a second transistor constituting a first current mirror circuit, and a current flowing through the second transistor as a reference current, and a current flowing through the second transistor according to the output current of the output transistor. The configuration includes a second current mirror circuit that applies current to the limiting a electrode of the output transistor.

[Effect]

Since the second current mirror circuit in this invention applies a current corresponding to the output current to the control electrode of the output transistor, the constant current applied from the constant current source to the control 1m pole of the output transistor is small and generalized.

(Embodiment) FIG. 1 is a circuit diagram showing an output circuit which is an embodiment of the present invention. In the figure, the difference from the conventional one is that an NPN transistor Q3 and a current mirror circuit 5 are further provided.

The NPN transistor Q3 constitutes a current mirror circuit 4 with the output transistor Q2, and the base is connected to the output transistor Q2.
and the collector of the NPNi transistor Q1, the collector is connected to the current mirror circuit 5, and the emitter is grounded. It is assumed that the emitter area ratio of the output transistor Q2 and the NPN transistor Q3 is set to n:1, for example.

The current mirror circuit 5 transmits a current corresponding to the output current of the output terminal 3 to the output transistor Q2 and the NPN transistor Q3.
It consists of PNPt transistors Q and C5.

PNP transistor Q4 is a reference transistor,
The base is its own collector, the emitter is the electric IfAv c
c, the ``rectors'' are connected to the ``rectors of the N P N transistors Q3, respectively. The PNP transistor Q5 has a base connected to the base of the PNP transistor Q4, an emitter connected to the power supply VCC, and a rectifier connected to the NPNi-transistor Q.
3 bases, respectively. It is assumed that the emitter area ratio of the PNP transistors Q5 and C6 is set to 1:m. The other configurations are the same as the conventional example.

Next, the operation will be explained. Turn on NPN transistor Q1 from input terminal 1 to the base of NPN transistor Q1.
When a sufficient current is supplied to cause the output transistor to turn off, the output transistor Q2 is turned off as in the conventional case. At this time, the NPN transistor Q3 is also turned off, so the current mirror circuit 5! l] Don't make it.

On the other hand, when the current supplied from the input terminal 1 to the base of the NPN transistor Q1 is cut, the output transistor Q2 becomes ONL, as in the conventional case.
Collector current IC2 is output to the collector of No.2. At this time, the output transistor Q2 and the NPN transistor Q
3 constitutes a current mirror circuit 4, so if the emitter current of the output transistor Q2 is E2, the emitter current of the NPN transistor Q is (1,/n) ・'
It becomes E2.

Also, since the PNP transistors Q and C5 constitute the current mirror circuit 5, the emitter current of the PNP transistor Q5 is m of the emitter current of the PNP transistor Q4.
It will be doubled. Emitter current of PNP transistor Q and N
Since the emitter current of the PN transistor Q3 is almost equal, one current of the PNP transistor Q5 is m/n times the emitter current of the output transistor Q2, that is, (m/n)・IF5, and a current almost equal to this is m/n times the emitter current of the output transistor Q2. P
It is supplied from the collector of the NP transistor Q5 to the base of the output transistor Q2.

Therefore, the desired output current I. 2 (#IE2), if the current required to be supplied to the base of the output transistor Q2 is IB2, then 1 = I + (m
/n)-I[2.(2)B2 0 The current value I of the constant current source 2 is set so that B2 0 holds true. All you have to do is set . ■ In the conventional circuit. has to be set equal to IB2, resulting in a relatively large current value, but in this example, from equation (2), 1 = t (m/n) "IF5 -
(3) B2, and a relatively small current value is sufficient. Therefore, compared to the conventional circuit current when the output transistor Q2 is OFF (m/
n)·'E2 can be reduced.

FIG. 2 is a circuit diagram showing an output circuit in which a current limiting circuit 6 is further added to the embodiment shown in FIG. The current limiting circuit 6 is N
PN transistor Q3-yaPNP i-transistor Q4→PNP transistor Q5→NPN transistor Q
This is to prevent the base current of the output transistor Q2 from increasing excessively due to positive feedback through the path No. 3, thereby preventing the switching speed from slowing down due to saturation of the transistors Q2 and Q3. It is inserted between the current mirror circuits 4 and 5, and the NPN
It is composed of a transistor Q6 and a resistor R. N
The base of the PN transistor Q6 is connected to its own emitter via a resistor R, and also to the collector of the NPN transistor Q3, and the collector is connected to the power supply ■. Connected to 0.

In this output circuit, the base of NPN transistor Q6
If the emitter voltage is ■, the resistance E6 of the resistor R is R, and the output of the current mirror circuit 5 is P
Collector current I of NP transistor Q5. 5 is m・(■
B: It will not be higher than 6/R).
If a current larger than this flows into the current limiting circuit 6, the voltage drop across the resistor 1 becomes VBE6 or more, so the NPN transistor Q6 turns ONL, and the current flows into the PNP transistor Q4, which is the reference transistor of the current mirror circuit 5. This is because the current will stop flowing and the current mirror circuit 5 will no longer operate. The current value to be limited is determined by adjusting the resistor R in consideration of the size of the transistor Q2. By adopting such a configuration, it is possible to prevent the switching speed from becoming slow. .

In the above embodiment, a resistor is inserted between the output transistor Q2 and the NPN transistor Q3 and the ground, and a resistor is inserted between the emitters of the PNP transistors Q4 and Q5 and the power supply. A resistor may be inserted between 0 and 0 to change the current ratio, and in this case, the same effect as in the above embodiment can be obtained.

〔Effect of the invention〕

As described above, according to the present invention, since the second current mirror circuit provides a current corresponding to the output current to the control electrode of the output transistor, a constant current is supplied from the constant current source to the control electrode of the output transistor. can be made smaller by that amount, and as a result, the circuit current when the output transistor is off can be reduced, reducing power consumption.
This has the effect of providing an efficient output circuit.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing one embodiment of the invention, FIG. 2 is a circuit diagram showing another embodiment of the invention, and FIG. 3 is a circuit diagram showing a conventional output circuit. In the figure, 1 is an input terminal, 3 is an output terminal, 4 and 5 are current mirror circuits, Q2 is an output transistor, and Q3 is an NP
It is an NP transistor. Note that the same reference numerals in each figure indicate the same or corresponding parts. Agent Oiwa Masuo Figure 1 1-----λ Power Standing King 3-111 Earth! 1 Island) 4.5-11 Den Umaru Mirror Repayment Q2--Ichito Katora, ・Tadari Q3-1-NPN1 Wonzu' Star Figure 2 Figure 3 Procedural Amendment (Spontaneous) 2. Title of the Invention Person making the output circuit correction Representative Moriya Shiki 4, Agent 5, Correction partner Φ [Brief description of drawings column] of the specification 6. Contents of the amendment (1) Mei IB, page 10, No. 14 “Q3 is NPN
"P transistor" is corrected to "Q3 is an NPN transistor". that's all

Claims (1)

[Claims] (1) A constant current source that supplies a constant current to the control electrode of the output transistor, and a constant current source that is turned ON/OFF according to an input signal and that, when turned on, leads the constant current from the constant current source to GND to turn off the output transistor. a second transistor that constitutes a first current mirror circuit with the output transistor, and a current flowing through the second transistor as a reference current;
An output circuit comprising: a second current mirror circuit that applies a current corresponding to the output current of the output transistor to a control electrode of the output transistor.